URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/rtl/RTL_VB
- from Rev 19 to Rev 23
- ↔ Reverse comparison
Rev 19 → Rev 23
/rx_spw.v
45,7 → 45,7
output rx_got_null, |
output rx_got_nchar, |
output rx_got_time_code, |
output rx_got_fct, |
output reg rx_got_fct, |
|
output reg [8:0] rx_data_flag, |
output reg rx_buffer_write, |
88,6 → 88,7
reg last_was_timec; |
|
reg [3:0] control; |
reg [3:0] control_r; |
reg [9:0] data; |
reg [9:0] timecode; |
|
94,19 → 95,23
reg [3:0] control_l_r; |
reg [9:0] data_l_r; |
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reg [9:0] dta_timec; |
|
reg parity_error; |
wire check_c_d; |
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reg rx_data_take; |
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reg first_time; |
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//CLOCK RECOVERY |
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0; |
assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0; |
assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0; |
|
assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0; |
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0; |
assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0; |
//assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0; |
|
assign rx_got_bit = (posedge_clk)?1'b1:1'b0; |
|
128,6 → 133,8
bit_d_5 <= 1'b0; |
bit_d_7 <= 1'b0; |
bit_d_9 <= 1'b0; |
|
first_time <= 1'b0; |
end |
else |
begin |
139,7 → 146,7
bit_d_5 <= bit_d_3; |
bit_d_7 <= bit_d_5; |
bit_d_9 <= bit_d_7; |
|
first_time <= 1'b1; |
end |
|
end |
157,17 → 164,9
bit_d_4 <= 1'b0; |
bit_d_6 <= 1'b0; |
bit_d_8 <= 1'b0; |
|
is_control <= 1'b0; |
is_data <= 1'b0; |
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counter_neg <= 5'd0; |
|
end |
else |
begin |
|
|
bit_c_0 <= rx_din; |
bit_c_2 <= bit_c_0; |
|
176,7 → 175,48
bit_d_4 <= bit_d_2; |
bit_d_6 <= bit_d_4; |
bit_d_8 <= bit_d_6; |
|
end |
end |
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always@(*) |
begin |
rx_got_fct = 1'b0; |
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if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d) |
begin |
rx_got_fct = 1'b1; |
end |
end |
|
always@(*) |
begin |
dta_timec = 10'd0; |
control_r = 4'd0; |
|
if(counter_neg == 5'd2) |
begin |
control_r = {bit_c_3,bit_c_2,bit_c_1,bit_c_0}; |
end |
else if(counter_neg == 5'd5) |
begin |
dta_timec = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7}; |
end |
end |
|
always@(posedge negedge_clk or negedge rx_resetn) |
begin |
|
if(!rx_resetn) |
begin |
is_control <= 1'b0; |
is_data <= 1'b0; |
|
counter_neg <= 5'd0; |
end |
else |
begin |
|
if(counter_neg == 5'd1) |
begin |
if(bit_c_0) |
223,6 → 263,7
end |
end |
|
|
always@(*) |
begin |
|
284,9 → 325,9
|
if(!rx_resetn) |
begin |
control <= 4'd0; |
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control_l_r <= 4'd0; |
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control <= 4'd0; |
data <= 10'd0; |
data_l_r <= 10'd0; |
rx_data_flag <= 9'd0; |
312,12 → 353,12
rx_buffer_write <= rx_data_take; |
rx_data_flag <= data[8:0]; |
|
rx_time_out <= timecode; |
rx_time_out <= timecode[7:0]; |
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if((control[2:0] != 3'd7 & is_data) == 1'b1) |
if((control_r[2:0] != 3'd7 & is_data) == 1'b1) |
begin |
|
data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7}; |
data <= dta_timec; |
data_l_r <= data; |
|
rx_data_take <= 1'b1; |
330,10 → 371,10
last_was_data <= last_is_data ; |
last_was_timec <= last_is_timec; |
end |
else if((control[2:0] == 3'd7 & is_data) == 1'b1) |
else if((control_r[2:0] == 3'd7 && is_data) == 1'b1) |
begin |
|
timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7}; |
timecode <= dta_timec; |
rx_tick_out <= 1'b1; |
rx_data_take <= 1'b0; |
|
344,18 → 385,18
last_was_data <= last_is_data ; |
last_was_timec <= last_is_timec; |
end |
else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12) |
else if(control_r == 4'd6 || control_r == 4'd13 || control_r == 4'd5 || control_r == 4'd15 || control_r == 4'd7 || control_r == 4'd4 || control_r == 4'd12) |
begin |
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0}; |
control <= control_r; |
control_l_r <= control[3:0]; |
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if((control[2:0] == 3'd6 & is_control) == 1'b1 ) |
if((control_r[2:0] == 3'd6 & is_control) == 1'b1 ) |
begin |
data <= 10'b0100000001; |
rx_data_take <= 1'b1; |
end |
else if( (control[2:0] == 3'd5 & is_control) == 1'b1 ) |
else if( (control_r[2:0] == 3'd5 & is_control) == 1'b1 ) |
begin |
data <= 10'b0100000000; |
rx_data_take <= 1'b1; |
/tx_spw.v
582,10 → 582,10
begin |
if(!enable_tx) |
begin |
null_s <= 8'h74; |
fct_s <= 4'h4; |
eop_s <= 4'h5; |
eep_s <= 4'h6; |
null_s <= 8'b01110100; |
fct_s <= 4'b0100; |
eop_s <= 4'b0101; |
eep_s <= 4'b0110; |
timecode_s <= 14'b01110000000000; |
|
fct_flag <= 3'd7; |
655,7 → 655,7
if(first_time) |
begin |
first_time <= 1'b0; |
hold_null <= 1'b1; |
hold_null <= 1'b1; |
global_counter_transfer <= global_counter_transfer + 4'd1; |
end |
else if(global_counter_transfer != 4'd7) |