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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

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    /spacewiresystemc/trunk
    from Rev 24 to Rev 25
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Rev 24 → Rev 25

/rtl/RTL_VB/fsm_spw.v
129,7 → 129,7
begin
next_state_fsm = error_reset;
end
else if((!link_disable) && (link_start |(auto_start && rx_got_null)))
else if((!link_disable) & (link_start |(auto_start && rx_got_null)))
begin
next_state_fsm = started;
end
138,11 → 138,11
started:
begin
 
if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
begin
next_state_fsm = error_reset;
end
else if(rx_got_null && rx_got_bit)
else if(rx_got_null & rx_got_bit)
begin
next_state_fsm = connecting;
end
151,7 → 151,7
connecting:
begin
 
if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
begin
next_state_fsm = error_reset;
end
208,6 → 208,7
begin
end
endcase
end
end
 
220,8 → 221,13
end
else
begin
if(state_fsm == error_wait | state_fsm == started | state_fsm == connecting)
 
if(next_state_fsm == connecting && state_fsm == started)
begin
after128us <= 12'd0;
end
else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
begin
if(after128us < 12'd1279)
after128us <= after128us + 12'd1;
else
268,16 → 274,23
end
else
begin
if(rx_got_bit)
if(state_fsm != run)
begin
after850ns <= 12'd0;
end
else
begin
if(after850ns < 12'd85 && state_fsm == run)
after850ns <= after850ns + 12'd1;
if(rx_got_bit)
begin
after850ns <= 12'd0;
end
else
after850ns <= 12'd0;
begin
if(after850ns < 12'd85 && state_fsm == run)
after850ns <= after850ns + 12'd1;
else
after850ns <= 12'd0;
end
end
end
 
/rtl/RTL_VB/rx_spw.v
39,23 → 39,25
 
input rx_resetn,
 
output rx_error,
output reg rx_error,
 
output rx_got_bit,
output rx_got_null,
output rx_got_nchar,
output rx_got_time_code,
output reg rx_got_null,
output reg rx_got_nchar,
output reg rx_got_time_code,
output reg rx_got_fct,
output reg rx_got_fct_fsm,
 
output reg [8:0] rx_data_flag,
output reg rx_buffer_write,
 
output reg [7:0] rx_time_out,
output [7:0] rx_time_out,
output reg rx_tick_out
);
 
 
reg [4:0] counter_neg;
reg control_bit_found;
 
wire posedge_clk;
wire negedge_clk;
64,6 → 66,7
reg bit_c_1;//P
reg bit_c_2;//N
reg bit_c_3;//P
reg bit_c_ex;//P
 
reg bit_d_0;//N
reg bit_d_1;//P
97,28 → 100,24
 
reg [9:0] dta_timec;
 
reg parity_error;
wire check_c_d;
 
reg rx_data_take;
reg rx_data_take_0;
 
reg first_time;
 
wire ready_control;
wire ready_data;
//CLOCK RECOVERY
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
 
assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
 
assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
//assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
 
assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
 
assign rx_error = parity_error;
assign rx_time_out = timecode[7:0];
 
assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
assign ready_control = is_control;
assign ready_data = (counter_neg == 5'd5)?is_data:1'b0;
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
125,27 → 124,20
 
if(!rx_resetn)
begin
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
 
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
 
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
first_time <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
 
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
first_time <= 1'b1;
end
 
156,54 → 148,57
 
if(!rx_resetn)
begin
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
 
bit_d_0 <= 1'b0;
bit_d_2 <= 1'b0;
bit_d_4 <= 1'b0;
bit_d_6 <= 1'b0;
bit_d_8 <= 1'b0;
 
end
else
begin
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
 
bit_d_0 <= rx_din;
bit_d_2 <= bit_d_0;
bit_d_4 <= bit_d_2;
bit_d_6 <= bit_d_4;
bit_d_8 <= bit_d_6;
end
end
 
always@(*)
always@(posedge posedge_clk or negedge rx_resetn)
begin
rx_got_fct = 1'b0;
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)
 
if(!rx_resetn)
begin
rx_got_fct = 1'b1;
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
bit_c_ex <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
bit_c_ex <= bit_c_3;
end
 
end
 
always@(*)
always@(posedge negedge_clk or negedge rx_resetn)
begin
dta_timec = 10'd0;
control_r = 4'd0;
 
if(counter_neg == 5'd2)
if(!rx_resetn)
begin
control_r = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
end
else if(counter_neg == 5'd5)
else
begin
dta_timec = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
end
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
211,192 → 206,322
begin
is_control <= 1'b0;
is_data <= 1'b0;
 
control_bit_found <= 1'b0;
counter_neg <= 5'd0;
end
else
begin
if(counter_neg == 5'd1)
if(counter_neg == 5'd0)
begin
if(bit_c_0)
begin
is_control <= 1'b1;
is_data <= 1'b0;
end
else
begin
is_control <= 1'b0;
is_data <= 1'b1;
end
 
control_bit_found <= rx_din;
is_control <= 1'b0;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
 
end
else if(counter_neg == 5'd1 && control_bit_found)
begin
is_control <= 1'b1;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
end
else if(counter_neg == 5'd1 && !control_bit_found)
begin
is_control <= 1'b0;
is_data <= 1'b1;
counter_neg <= counter_neg + 5'd1;
end
else
begin
 
if(is_control)
begin
 
if(counter_neg == 5'd2)
begin
control_bit_found <= rx_din;
counter_neg <= 5'd1;
is_control <= 1'b0;
is_data <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
else if(is_data)
begin
if(counter_neg == 5'd5)
begin
control_bit_found <= rx_din;
 
counter_neg <= 5'd1;
is_data <= 1'b0;
is_control <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
else
begin
counter_neg <= counter_neg + 5'd1;
end
end
 
end
end
 
 
always@(*)
begin
 
parity_error = 1'b0;
rx_got_fct = 1'b0;
 
if(last_is_control)
if(negedge_clk)
begin
if(last_was_control)
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && ready_control)
begin
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
begin
parity_error = 1'b1;
end
rx_got_fct = 1'b1;
end
else if(last_was_timec)
end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
rx_error <= 1'b0;
end
else
begin
if(last_is_control)
begin
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
if(last_was_control)
begin
parity_error = 1'b1;
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
begin
rx_error <= 1'b1;
end
end
else if(last_was_timec)
begin
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
begin
rx_error <= 1'b1;
end
end
else if(last_was_data)
begin
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
begin
rx_error <= 1'b1;
end
end
end
else if(last_was_data)
else if(last_is_data)
begin
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
if(last_was_control)
begin
parity_error = 1'b1;
if(!(data[8]^control[1]^control[0]) != data[9])
begin
rx_error <= 1'b1;
end
end
else if(last_was_timec)
begin
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
begin
rx_error <= 1'b1;
end
end
else if(last_was_data)
begin
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
begin
rx_error <= 1'b1;
end
end
end
 
end
else if(last_is_data)
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
if(last_was_control)
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
else
begin
if(control[2:0] != 3'd7 && last_is_data )
begin
if(!(data[8]^control[1]^control[0]) != data[9])
begin
parity_error = 1'b1;
end
rx_got_nchar <= 1'b1;
end
else if(last_was_timec)
else if(control[2:0] == 3'd7 && last_is_data)
begin
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
begin
parity_error = 1'b1;
end
rx_got_time_code <= 1'b1;
end
else if(last_was_data)
else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
begin
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
begin
parity_error = 1'b1;
end
rx_got_null <= 1'b1;
end
else
begin
rx_got_null <= rx_got_null;
rx_got_time_code <= rx_got_time_code;
rx_got_nchar <= rx_got_nchar;
end
end
end
 
always@(posedge check_c_d or negedge rx_resetn )
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_fct_fsm <= 1'b0;
rx_buffer_write <= 1'b0;
rx_data_take_0 <= 1'b0;
end
else
begin
rx_data_take_0 <= rx_data_take;
rx_buffer_write <= rx_data_take_0;
 
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
rx_got_fct_fsm <= 1'b1;
else
rx_got_fct_fsm <= rx_got_fct_fsm;
end
end
 
always@(posedge ready_control or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_r <= 4'd0;
end
else
begin
if(counter_neg == 5'd2)
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
else if(counter_neg == 5'd1 && control == 4'd7)
control_r <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
else
control_r <= control_r;
end
end
 
control_l_r <= 4'd0;
control <= 4'd0;
data <= 10'd0;
data_l_r <= 10'd0;
rx_data_flag <= 9'd0;
rx_buffer_write <= 1'b0;
rx_data_take <= 1'b0;
 
timecode <= 10'd0;
rx_time_out <= 8'd0;
rx_tick_out <= 1'b0;
always@(posedge ready_data or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec <= 10'd0;
end
else
begin
if(counter_neg == 5'd5)
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
else
dta_timec <= dta_timec;
end
end
 
last_is_control <=1'b0;
last_is_data <=1'b0;
last_is_timec <=1'b0;
always@(posedge posedge_clk or negedge rx_resetn )
begin
 
last_was_control <=1'b0;
last_was_data <=1'b0;
last_was_timec <=1'b0;
if(!rx_resetn)
begin
 
control_l_r <= 4'd0;
control <= 4'd0;
data <= 10'd0;
data_l_r <= 10'd0;
rx_data_flag <= 9'd0;
rx_data_take <= 1'b0;
 
 
timecode <= 10'd0;
rx_tick_out <= 1'b0;
 
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
 
last_was_control <= 1'b0;
last_was_data <= 1'b0;
last_was_timec <= 1'b0;
end
else
begin
 
rx_buffer_write <= rx_data_take;
rx_data_flag <= data[8:0];
rx_time_out <= timecode[7:0];
if(ready_control)
begin
control <= control_r;
control_l_r <= control;
 
if((control_r[2:0] != 3'd7 & is_data) == 1'b1)
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
else if(ready_data)
begin
 
data <= dta_timec;
if(control[2:0] != 3'd7)
begin
rx_data_flag <= dta_timec[8:0];
data <= dta_timec;
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
else if(control[2:0] == 3'd7)
begin
timecode <= dta_timec;
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
end
else if(last_is_timec)
begin
 
data_l_r <= data;
rx_data_take <= 1'b1;
rx_tick_out <= 1'b0;
 
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
//meta_hold_setup <= 1'b0;
end
else if((control_r[2:0] == 3'd7 && is_data) == 1'b1)
else if(last_is_data)
begin
 
timecode <= dta_timec;
rx_tick_out <= 1'b1;
rx_data_take <= 1'b0;
 
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
//meta_hold_setup <= 1'b0;
end
else if(control_r == 4'd6 || control_r == 4'd13 || control_r == 4'd5 || control_r == 4'd15 || control_r == 4'd7 || control_r == 4'd4 || control_r == 4'd12)
else if(last_is_control)
begin
//if(control == 4'd6 || control == 4'd13 || control == 4'd5 || control == 4'd15 || control == 4'd7 || control == 4'd4 || control == 4'd12)
 
control <= control_r;
control_l_r <= control[3:0];
 
if((control_r[2:0] == 3'd6 & is_control) == 1'b1 )
if((control[2:0] == 3'd6) == 1'b1 )
begin
data <= 10'b0100000001;
rx_data_take <= 1'b1;
end
else if( (control_r[2:0] == 3'd5 & is_control) == 1'b1 )
else if((control[2:0] == 3'd5) == 1'b1 )
begin
data <= 10'b0100000000;
rx_data_take <= 1'b1;
408,13 → 533,9
 
rx_tick_out <= 1'b0;
 
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
//meta_hold_setup <= 1'b0;
end
end
end
 
/rtl/RTL_VB/top_spw_ultra_light.v
84,7 → 84,9
wire send_null_tx;
wire send_fct_tx;
 
wire got_fct_flag_fsm;
 
 
FSM_SPW FSM(
.pclk(pclk),
.resetn(resetn),
99,7 → 101,7
.rx_got_null(got_null_rx),
.rx_got_nchar(got_nchar_rx),
.rx_got_time_code(got_time_code_rx),
.rx_got_fct(got_fct_rx),
.rx_got_fct(got_fct_flag_fsm),
.rx_resetn(resetn_rx),
 
.enable_tx(enable_tx),
114,7 → 116,6
RX_SPW RX(
.rx_din(top_din),
.rx_sin(top_sin),
 
.rx_resetn(resetn_rx),
 
.rx_error(error_rx),
123,6 → 124,7
.rx_got_nchar(got_nchar_rx),
.rx_got_time_code(got_time_code_rx),
.rx_got_fct(got_fct_rx),
.rx_got_fct_fsm(got_fct_flag_fsm),
 
.rx_data_flag(datarx_flag),
.rx_buffer_write(buffer_write),
/rtl/RTL_VB/tx_spw.v
70,13 → 70,22
DATA = 6'b010000,
TIMEC = 6'b100000;
 
 
localparam [7:0] null_s = 8'b01110100;
localparam [2:0] fct_s = 3'b100;
localparam [3:0] eop_s = 4'b0101;
localparam [3:0] eep_s = 4'b0110;
localparam [13:0] timecode_ss = 14'b01110000000000;
 
 
 
reg [2:0] state_tx;
reg [2:0] next_state_tx;
 
reg [7:0] null_s;
reg [3:0] fct_s;
reg [3:0] eop_s;
reg [3:0] eep_s;
//reg [7:0] null_s;
//reg [2:0] fct_s;
//reg [3:0] eop_s;
//reg [3:0] eep_s;
reg [13:0] timecode_s;
 
reg [5:0] last_type;
578,16 → 587,12
 
end
 
always@(posedge pclk_tx)
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
null_s <= 8'b01110100;
fct_s <= 4'b0100;
eop_s <= 4'b0101;
eep_s <= 4'b0110;
timecode_s <= 14'b01110000000000;
 
timecode_s <= 14'b01110000000000;
fct_flag <= 3'd7;
 
first_time <= 1'b1;
618,6 → 623,13
else
begin
//null_s <= null_s;
//fct_s <= fct_s;
//eop_s <= eop_s;
//eep_s <= eep_s;
//timecode_s <= timecode_s;
//fct_flag <= fct_flag;
 
state_tx <= next_state_tx;
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
627,6 → 639,11
 
ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
//hold_null <= 1'b0;
hold_fct <= 1'b0;
hold_data <= 1'b0;
hold_time_code <= 1'b0;
 
//
if(gotfct_tx && !block_sum)
begin
666,6 → 683,7
else
begin
hold_null <= 1'b0;
last_type <= NULL;
global_counter_transfer <= 4'd0;
end
end
675,6 → 693,12
ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
 
hold_null <= 1'b0;
//hold_fct <= 1'b0;
hold_data <= 1'b0;
hold_time_code <= 1'b0;
 
 
if(gotfct_tx && !block_sum)
begin
fct_counter_receive <= fct_counter;
710,11 → 734,16
hold_fct <= 1'b0;
global_counter_transfer <= 4'd0;
fct_flag <= fct_flag - 3'd1;
last_type <=FCT;
end
end
else if(enable_time_code)
begin
hold_null <= 1'b0;
hold_fct <= 1'b0;
hold_data <= 1'b0;
//hold_time_code <= 1'b0;
ready_tx_data <= 1'b0;
 
if(gotfct_tx && !block_sum)
750,12 → 779,13
if(global_counter_transfer < 4'd13)
begin
global_counter_transfer <= global_counter_transfer + 4'd1;
timecode_s <= {timecode_s[13:10],2'd2,timecode_tx_i[7:0]};
timecode_s <= {timecode_ss[13:10],2'd2,timecode_tx_i[7:0]};
end
else
begin
last_timein_control_flag_tx <= timecode_tx_i;
global_counter_transfer <= 4'd0;
last_type <= TIMEC;
end
end
else if(enable_n_char)
762,7 → 792,11
begin
ready_tx_timecode <= 1'b0;
 
hold_null <= 1'b0;
hold_fct <= 1'b0;
//hold_data <= 1'b0;
hold_time_code <= 1'b0;
//
if(send_fct_now && !block_sum_fct_send)
begin
811,6 → 845,7
hold_data <= 1'b0;
global_counter_transfer <= 4'd0;
fct_counter_receive <= fct_counter_receive - 6'd1;
last_type <= DATA;
end
 
end
850,6 → 885,7
hold_data <= 1'b0;
global_counter_transfer <= 4'd0;
fct_counter_receive <= fct_counter_receive - 6'd1;
last_type <=EOP;
end
end
 

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