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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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/spacewiresystemc/trunk
- from Rev 26 to Rev 27
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Rev 26 → Rev 27
/rtl/DEBUG_VERILOG/write_axi.v
0,0 → 1,54
//+FHDR------------------------------------------------------------------------ |
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved |
//GLADIC Open Source RTL |
//----------------------------------------------------------------------------- |
//FILE NAME : |
//DEPARTMENT : IC Design / Verification |
//AUTHOR : Felipe Fernandes da Costa |
//AUTHOR’S EMAIL : |
//----------------------------------------------------------------------------- |
//RELEASE HISTORY |
//VERSION DATE AUTHOR DESCRIPTION |
//1.0 YYYY-MM-DD name |
//----------------------------------------------------------------------------- |
//KEYWORDS : General file searching keywords, leave blank if none. |
//----------------------------------------------------------------------------- |
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008 |
//----------------------------------------------------------------------------- |
//PARAMETERS |
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS |
//e.g.DATA_WIDTH [32,16] : width of the data : 32: |
//----------------------------------------------------------------------------- |
//REUSE ISSUES |
//Reset Strategy : |
//Clock Domains : |
//Critical Timing : |
//Test Features : |
//Asynchronous I/F : |
//Scan Methodology : |
//Instantiations : |
//Synthesizable (y/n) : |
//Other : |
//-FHDR------------------------------------------------------------------------ |
module write_axi( |
input clock_recovery, |
input reset_n, |
input [13:0] data_rec, |
output reg [13:0] data_stand |
); |
|
|
always@(posedge clock_recovery or negedge reset_n ) |
begin |
|
if(!reset_n) |
begin |
data_stand <= 14'd0; |
end |
else |
begin |
data_stand <= data_rec; |
end |
end |
|
endmodule |