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Rev 32 → Rev 33

/rtl/RTL_VB/fifo_rx.v
0,0 → 1,199
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module fifo_rx
#(
parameter integer DWIDTH = 9,
parameter integer AWIDTH = 6
)
 
(
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in,
output reg f_full,f_empty,
output reg open_slot_fct,
output reg overflow_credit_error,
output reg [DWIDTH-1:0] data_out,
output reg [AWIDTH-1:0] counter
);
 
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
 
reg block_read;
reg block_write;
 
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
 
reg [AWIDTH-1:0] credit_counter;
 
//Write pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
block_write <= 1'b0;
overflow_credit_error<=1'b0;
end
else
begin
if(block_write)
begin
if(!wr_en)
block_write <= 1'b0;
end
else if (wr_en && !f_full)
begin
block_write <= 1'b1;
mem[wr_ptr]<=data_in;
wr_ptr <= wr;
end
 
if(wr_en && credit_counter > 6'd55)
begin
overflow_credit_error<=1'b1;
end
end
end
 
//FULL - EMPTY COUNTER
 
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty <= 1'b1;
counter <= {(AWIDTH){1'b0}};
credit_counter <= 6'd55;
end
else
begin
 
if (wr_en && !f_full && !block_write)
begin
if(rd_en && !f_empty && !block_read)
begin
counter <= counter;
end
else
begin
counter <= counter + 6'd1;
end
 
credit_counter <= credit_counter - 6'd1;
end
else if(rd_en && !f_empty && !block_read)
begin
if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
credit_counter <= credit_counter + 6'd8;
 
counter <= counter - 6'd1;
end
 
 
 
 
if(counter == 6'd63)
begin
f_full <= 1'b1;
end
else
begin
f_full <= 1'b0;
end
 
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
 
end
end
 
//Read pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
open_slot_fct<= 1'b0;
block_read <= 1'b0;
end
else
begin
 
if(rd_ptr == 6'd8 || rd_ptr == 6'd16 || rd_ptr == 6'd24 || rd_ptr == 6'd32 || rd_ptr == 6'd40 || rd_ptr == 6'd48 || rd_ptr == 6'd56 || rd_ptr == 6'd63)
begin
open_slot_fct<= 1'b1;
end
else
begin
open_slot_fct<= 1'b0;
end
if(block_read == 1)
begin
if(!rd_en)
block_read<= 1'b0;
 
data_out <= mem[rd_ptr];
end
else
if(rd_en && !f_empty)
begin
rd_ptr <= rd;
block_read<= 1'b1;
end
else
begin
data_out <= mem[rd_ptr];
end
end
end
 
//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule
/rtl/RTL_VB/fifo_tx.v
0,0 → 1,177
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
parameter integer DWIDTH = 9,
parameter integer AWIDTH = 6
)
 
(
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in,
output reg f_full,write_tx,f_empty,
output reg [DWIDTH-1:0] data_out,
output reg [AWIDTH-1:0] counter
);
 
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
 
reg block_read;
reg block_write;
 
wire [AWIDTH-1:0] wr;
wire [AWIDTH-1:0] rd;
 
//Write pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
wr_ptr <= {(AWIDTH){1'b0}};
block_write <= 1'b0;
end
else if(block_write)
begin
if(!wr_en)
block_write <= 1'b0;
end
else if (wr_en && !f_full)
begin
block_write <= 1'b1;
mem[wr_ptr]<=data_in;
wr_ptr <= wr;
end
end
 
//FULL - EMPTY COUNTER
 
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty<= 1'b1;
counter <= {(AWIDTH){1'b0}};
end
else
begin
 
if (wr_en && !f_full && !block_write)
begin
if(rd_en && !f_empty && !block_read)
begin
counter <= counter;
end
else
begin
counter <= counter + 6'd1;
end
end
else if(rd_en && !f_empty && !block_read)
begin
counter <= counter - 6'd1;
end
 
if(counter == 6'd63)
begin
f_full <= 1'b1;
end
else
begin
f_full <= 1'b0;
end
 
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
 
end
end
 
//Read pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
write_tx <= 1'b0;
block_read <= 1'b0;
end
else
begin
 
if(block_read == 1)
begin
if(!rd_en)
block_read<= 1'b0;
 
data_out <= mem[rd_ptr];
end
else if(rd_en && !f_empty)
begin
rd_ptr <= rd;
block_read<= 1'b1;
end
else
begin
data_out <= mem[rd_ptr];
end
 
if(rd_en == 1'b1)
begin
write_tx<= 1'b0;
end
else if(counter > 6'd0)
begin
write_tx<= 1'b1;
end
else
write_tx<= write_tx;
 
end
end
 
//assign f_empty = ((wr_ptr - rd_ptr) == 6'd0)?1'b1:1'b0;
assign wr = (wr_en && !f_full)?wr_ptr + 6'd1:wr_ptr + 6'd0;
assign rd = (rd_en && !f_empty)?rd_ptr+ 6'd1:rd_ptr + 6'd0;
 
endmodule
/rtl/RTL_VB/fsm_spw.v
50,12 → 50,12
input rx_got_nchar,
input rx_got_time_code,
input rx_got_fct,
output rx_resetn,
output reg rx_resetn,
 
//tx status control
output enable_tx,
output send_null_tx,
output send_fct_tx,
output reg enable_tx,
output reg send_null_tx,
output reg send_fct_tx,
 
output [5:0] fsm_state
 
75,19 → 75,9
reg [11:0] after64us;
reg [11:0] after850ns;
 
//
assign enable_tx = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1;
reg got_bit_internal;
 
//
assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;
 
//
assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
 
//
assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
 
//
assign fsm_state = state_fsm;
 
always@(*)
129,7 → 119,7
begin
next_state_fsm = error_reset;
end
else if((!link_disable) & (link_start |(auto_start && rx_got_null)))
else if(((!link_disable) & (link_start |(auto_start & rx_got_null)))==1'b1)
begin
next_state_fsm = started;
end
142,7 → 132,7
begin
next_state_fsm = error_reset;
end
else if(rx_got_null & rx_got_bit)
else if((rx_got_null & rx_got_bit)== 1'b1)
begin
next_state_fsm = connecting;
end
177,11 → 167,17
endcase
end
 
always@(posedge pclk)
always@(posedge pclk or negedge resetn)
begin
if(!resetn)
begin
state_fsm <= error_reset;
 
rx_resetn <= 1'b0;
 
enable_tx<= 1'b0;
send_null_tx<= 1'b0;
send_fct_tx<= 1'b0;
end
else
begin
191,21 → 187,49
case(state_fsm)
error_reset:
begin
enable_tx<= 1'b0;
send_null_tx<= 1'b0;
send_fct_tx<= 1'b0;
if(after64us == 12'd639)
rx_resetn <= 1'b1;
else
rx_resetn <= 1'b0;
end
error_wait:
begin
rx_resetn <= 1'b1;
enable_tx<= 1'b0;
send_null_tx<= 1'b0;
send_fct_tx<= 1'b0;
end
ready:
begin
rx_resetn <= 1'b1;
enable_tx<= 1'b1;
send_null_tx<= 1'b0;
send_fct_tx<= 1'b0;
end
started:
begin
rx_resetn <= 1'b1;
enable_tx<= 1'b1;
send_null_tx<= 1'b1;
send_fct_tx<= 1'b0;
end
connecting:
begin
rx_resetn <= 1'b1;
enable_tx<= 1'b1;
send_null_tx<= 1'b1;
send_fct_tx<= 1'b1;
end
run:
begin
rx_resetn <= 1'b1;
enable_tx<= 1'b1;
send_null_tx<= 1'b1;
send_fct_tx<= 1'b1;
end
endcase
215,7 → 239,7
always@(posedge pclk)
begin
 
if(!resetn)
if(!resetn || state_fsm == error_reset)
begin
after128us <= 12'd0;
end
267,9 → 291,24
 
always@(posedge pclk)
begin
 
if(!resetn)
begin
got_bit_internal <= 1'b0;
end
else
begin
if(rx_got_bit)
got_bit_internal <= 1'b1;
else
got_bit_internal <= 1'b0;
end
end
 
always@(posedge pclk)
begin
 
if(!resetn | got_bit_internal)
begin
after850ns <= 12'd0;
end
else
280,17 → 319,11
end
else
begin
if(rx_got_bit)
begin
if(after850ns < 12'd85 && state_fsm == run)
after850ns <= after850ns + 12'd1;
else
after850ns <= 12'd0;
end
else
begin
if(after850ns < 12'd85 && state_fsm == run)
after850ns <= after850ns + 12'd1;
else
after850ns <= 12'd0;
end
 
end
end
 
/rtl/RTL_VB/rx_spw.v
41,7 → 41,7
 
output reg rx_error,
 
output rx_got_bit,
output reg rx_got_bit,
output reg rx_got_null,
output reg rx_got_nchar,
output reg rx_got_time_code,
56,8 → 56,9
);
 
 
reg [4:0] counter_neg;
reg [5:0] counter_neg;
reg control_bit_found;
reg data_bit_found;
 
wire posedge_clk;
wire negedge_clk;
66,7 → 67,6
reg bit_c_1;//P
reg bit_c_2;//N
reg bit_c_3;//P
reg bit_c_ex;//P
 
reg bit_d_0;//N
reg bit_d_1;//P
80,7 → 80,7
reg bit_d_9;//P
 
reg is_control;
reg is_data;
//reg is_data;
 
reg last_is_control;
reg last_is_data;
92,6 → 92,7
 
reg [3:0] control;
reg [3:0] control_r;
reg [3:0] control_p_r;
reg [9:0] data;
reg [9:0] timecode;
 
99,26 → 100,84
reg [9:0] data_l_r;
 
reg [9:0] dta_timec;
reg [9:0] dta_timec_p;
 
reg rx_data_take;
reg rx_data_take_0;
 
reg first_time;
reg ready_control;
reg ready_data;
 
wire ready_control;
wire ready_data;
reg ready_control_p;
reg ready_data_p;
 
reg ready_control_p_r;
reg ready_data_p_r;
 
reg posedge_p;
//CLOCK RECOVERY
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
assign posedge_clk = posedge_p;
assign negedge_clk = !posedge_p;
 
assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
 
assign rx_time_out = timecode[7:0];
 
assign ready_control = is_control;
assign ready_data = (counter_neg == 5'd5)?is_data:1'b0;
always@(*)
begin
 
rx_got_bit = 1'b0;
 
if(rx_din | rx_sin)
begin
rx_got_bit = 1'b1;
end
end
 
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
 
if(counter_neg[5:0] == 6'd4 && !posedge_p)
begin
ready_control = 1'b1;
end
else if(counter_neg[5:0] == 6'd32 && !posedge_p)
begin
ready_data = 1'b1;
end
end
 
 
always@(*)
begin
ready_control_p = 1'b0;
ready_data_p = 1'b0;
 
if(counter_neg[5:0] == 6'd4 && posedge_p)
begin
ready_control_p = 1'b1;
end
else if(counter_neg[5:0] == 6'd32 && posedge_p)
begin
ready_data_p = 1'b1;
end
end
 
always@(*)
begin
posedge_p = 1'b0;
 
if((rx_din ^ rx_sin) == 1'b1)
begin
posedge_p = 1'b1;
end
else
begin
posedge_p = 1'b0;
end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
129,7 → 188,6
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
first_time <= 1'b0;
end
else
begin
138,7 → 196,6
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
first_time <= 1'b1;
end
 
end
172,13 → 229,11
begin
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
bit_c_ex <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
bit_c_ex <= bit_c_3;
end
 
end
198,85 → 253,24
end
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
is_control <= 1'b0;
is_data <= 1'b0;
control_bit_found <= 1'b0;
counter_neg <= 5'd0;
rx_got_fct <= 1'b0;
end
else
begin
if(counter_neg == 5'd0)
begin
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
begin
control_bit_found <= rx_din;
is_control <= 1'b0;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
rx_got_fct <= 1'b1;
end
else if(counter_neg == 5'd1 && control_bit_found)
begin
is_control <= 1'b1;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
end
else if(counter_neg == 5'd1 && !control_bit_found)
begin
is_control <= 1'b0;
is_data <= 1'b1;
counter_neg <= counter_neg + 5'd1;
end
else
begin
 
if(is_control)
begin
 
if(counter_neg == 5'd2)
begin
control_bit_found <= rx_din;
counter_neg <= 5'd1;
is_control <= 1'b0;
is_data <= 1'b0;
end
end
else if(is_data)
begin
if(counter_neg == 5'd5)
begin
control_bit_found <= rx_din;
 
counter_neg <= 5'd1;
is_data <= 1'b0;
is_control <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
end
 
end
end
 
always@(*)
begin
 
rx_got_fct = 1'b0;
 
if(negedge_clk)
begin
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && ready_control)
begin
rx_got_fct = 1'b1;
rx_got_fct <= 1'b0;
end
end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
289,53 → 283,77
end
else
begin
if(last_is_control)
if(last_is_control == 1'b1)
begin
if(last_was_control)
if(last_was_control == 1'b1)
begin
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
else if(last_was_timec)
else if(last_was_timec == 1'b1)
begin
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
else if(last_was_data)
else if(last_was_data == 1'b1)
begin
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
end
else if(last_is_data)
else if(last_is_data == 1'b1)
begin
if(last_was_control)
if(last_was_control == 1'b1)
begin
if(!(data[8]^control[1]^control[0]) != data[9])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
else if(last_was_timec)
else if(last_was_timec == 1'b1)
begin
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
else if(last_was_data)
else if(last_was_data == 1'b1)
begin
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
begin
rx_error <= 1'b1;
end
else
begin
rx_error <= 1'b0;
end
end
end
 
353,23 → 371,23
end
else
begin
if(control[2:0] != 3'd7 && last_is_data )
if(last_is_data == 1'b1 )
begin
rx_got_nchar <= 1'b1;
end
else if(control[2:0] == 3'd7 && last_is_data)
else if(last_is_timec == 1'b1)
begin
rx_got_time_code <= 1'b1;
end
else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
else if(last_is_control == 1'b1)
begin
rx_got_null <= 1'b1;
end
else
begin
rx_got_null <= rx_got_null;
rx_got_time_code <= rx_got_time_code;
rx_got_nchar <= rx_got_nchar;
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
end
end
378,9 → 396,12
begin
if(!rx_resetn)
begin
rx_got_fct_fsm <= 1'b0;
rx_got_fct_fsm <= 1'b0;
rx_buffer_write <= 1'b0;
rx_data_take_0 <= 1'b0;
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
 
end
else
begin
387,7 → 408,28
rx_data_take_0 <= rx_data_take;
rx_buffer_write <= rx_data_take_0;
 
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
 
if(ready_control || ready_control_p)
begin
if(is_control)
ready_control_p_r <= 1'b1;
end
else
begin
ready_control_p_r <= 1'b0;
end
 
if(ready_data || ready_data_p)
begin
if(!is_control)
ready_data_p_r <= 1'b1;
end
else
begin
ready_data_p_r <= 1'b0;
end
 
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
rx_got_fct_fsm <= 1'b1;
else
rx_got_fct_fsm <= rx_got_fct_fsm;
402,16 → 444,26
end
else
begin
if(counter_neg == 5'd2)
//if(is_control)
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
else if(counter_neg == 5'd1 && control == 4'd7)
control_r <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
else
control_r <= control_r;
end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_p_r <= 4'd0;
end
else
begin
//if(is_control)
control_p_r <= control_r;
end
end
 
 
 
always@(posedge ready_data or negedge rx_resetn )
begin
if(!rx_resetn)
420,13 → 472,92
end
else
begin
if(counter_neg == 5'd5)
//if(!is_control)
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
else
dta_timec <= dta_timec;
end
end
 
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec_p <= 10'd0;
end
else
begin
//if(!is_control)
dta_timec_p <= dta_timec;
end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
is_control <= 1'b0;
control_bit_found <= 1'b0;
counter_neg[5:0] <= 6'd1;
end
else
begin
 
control_bit_found <= rx_din;
 
case(counter_neg)
6'd1:
begin
counter_neg[5:0] <= 6'd2;
end
6'd2:
begin
if(control_bit_found == 1'b1)
begin
is_control <= 1'b1;
end
else
begin
is_control <= 1'b0;
end
 
counter_neg[5:0] <= 6'd4;
end
6'd4:
begin
if(is_control == 1'b1)
begin
counter_neg[5:0] <= 6'd2;
is_control <= 1'b0;
end
else
begin
counter_neg[5:0] <= 6'd8;
end
end
6'd8:
begin
counter_neg[5:0] <= 6'd16;
end
6'd16:
begin
counter_neg[5:0] <= 6'd32;
end
6'd32:
begin
is_control <= 1'b0;
counter_neg[5:0] <= 6'd2;
end
default:
begin
is_control <= is_control;
counter_neg[5:0] <= counter_neg[5:0];
end
endcase
 
end
end
 
always@(posedge posedge_clk or negedge rx_resetn )
begin
 
456,9 → 587,9
else
begin
 
if(ready_control)
if(ready_control_p_r)
begin
control <= control_r;
control <= control_p_r;
control_l_r <= control;
 
last_is_control <= 1'b1;
468,13 → 599,14
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
else if(ready_data)
else if(ready_data_p_r)
begin
 
if(control[2:0] != 3'd7)
begin
rx_data_flag <= dta_timec[8:0];
data <= dta_timec;
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
data <= dta_timec_p;
data_l_r <= data;
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
493,37 → 625,28
last_was_timec <= last_is_timec;
end
end
else if(last_is_timec)
else if(last_is_timec == 1'b1)
begin
 
data_l_r <= data;
rx_data_take <= 1'b1;
rx_tick_out <= 1'b0;
 
//meta_hold_setup <= 1'b0;
rx_data_take <= 1'b0;
rx_tick_out <= 1'b1;
end
else if(last_is_data)
else if(last_is_data == 1'b1)
begin
 
rx_tick_out <= 1'b1;
rx_data_take <= 1'b0;
//meta_hold_setup <= 1'b0;
rx_tick_out <= 1'b0;
rx_data_take <= 1'b1;
end
else if(last_is_control)
else if(last_is_control == 1'b1)
begin
//if(control == 4'd6 || control == 4'd13 || control == 4'd5 || control == 4'd15 || control == 4'd7 || control == 4'd4 || control == 4'd12)
 
if((control[2:0] == 3'd6) == 1'b1 )
if(control[2:0] == 3'd6)
begin
data <= 10'b0100000001;
rx_data_flag <= 9'd257;
rx_data_take <= 1'b1;
end
else if((control[2:0] == 3'd5) == 1'b1 )
else if(control[2:0] == 3'd5)
begin
data <= 10'b0100000000;
rx_data_flag <= 9'd256;
rx_data_take <= 1'b1;
end
else
532,10 → 655,7
end
 
rx_tick_out <= 1'b0;
 
//meta_hold_setup <= 1'b0;
end
end
end
 
/rtl/RTL_VB/spw_ulight_con_top_x.v
0,0 → 1,132
module spw_ulight_con_top_x(
input ppll_100_MHZ,
input ppllclk,
input reset_spw_n_b,
input top_sin,
input top_din,
input top_auto_start,
input top_link_start,
input top_link_disable,
 
input top_tx_write,
input [8:0] top_tx_data,
 
input top_tx_tick,
input [7:0] top_tx_time,
 
input read_rx_fifo_en,
 
output [8:0] datarx_flag,
 
output tick_out,
output [7:0] time_out,
 
output top_dout,
output top_sout,
 
output f_full,
output f_empty,
output f_full_rx,
output f_empty_rx,
output top_tx_ready_tick,
 
output [5:0]top_fsm,
 
output [5:0]counter_fifo_tx,
output [5:0]counter_fifo_rx
//output [13:0] data_info
);
 
wire [8:0] datarx_flag_axi;
wire [8:0] datarx_flag_w;
wire buffer_write_w;
wire [7:0] time_out_axi;
wire [13:0] monitor_x_axi;
wire [13:0] data_x;
wire rx_buffer_write_mon_x;
 
wire credit_error_rx_w,top_send_fct_now_w;
wire top_tx_write_w,top_tx_ready_w;
wire [8:0] top_tx_data_w;
wire tx_reset_n;
 
assign tx_reset_n = (top_fsm != 6'd16 | !reset_spw_n_b)?1'b0:1'b1;
 
//assign time_out = time_out_w;
assign datarx_flag = datarx_flag_axi;
//assign data_info = data_x;
top_spw_ultra_light SPW(
 
.pclk(ppll_100_MHZ),
.ppllclk(ppllclk),
.resetn(reset_spw_n_b),
 
.top_sin(top_sin),
.top_din(top_din),
 
.top_auto_start(top_auto_start),
.top_link_start(top_link_start),
.top_link_disable(top_link_disable),
 
.top_tx_write(top_tx_write_w),
.top_tx_data(top_tx_data_w),
 
.top_tx_tick(top_tx_tick),
.top_tx_time(top_tx_time),
 
.credit_error_rx(credit_error_rx_w),
.top_send_fct_now(top_send_fct_now_w),
 
.datarx_flag(datarx_flag_w),
.buffer_write(buffer_write_w),
 
.time_out(time_out),
.tick_out(tick_out),
 
.top_dout(top_dout),
.top_sout(top_sout),
 
.top_tx_ready(top_tx_ready_w),
.top_tx_ready_tick(top_tx_ready_tick),
 
.top_fsm(top_fsm)
);
 
 
fifo_rx rx_data(
.clock(ppll_100_MHZ),
.reset(tx_reset_n),
.wr_en(buffer_write_w),
.rd_en(read_rx_fifo_en),
.data_in(datarx_flag_w),
.f_full(f_full_rx),
.f_empty(f_empty_rx),
.open_slot_fct(top_send_fct_now_w),
.overflow_credit_error(credit_error_rx_w),
.data_out(datarx_flag_axi),
.counter(counter_fifo_rx)
);
fifo_tx tx_data(
.clock(ppll_100_MHZ),
.reset(tx_reset_n),
.wr_en(top_tx_write),
.rd_en(top_tx_ready_w),
.data_in(top_tx_data),
.f_full(f_full),
.f_empty(f_empty),
.write_tx(top_tx_write_w),
.data_out(top_tx_data_w),
.counter(counter_fifo_tx)
);
endmodule
/rtl/RTL_VB/top_spw_ultra_light.v
150,8 → 150,8
.gotfct_tx(got_fct_rx),
.send_fct_now(top_send_fct_now),
.tx_dout(top_dout),
.tx_sout(top_sout),
.tx_dout_e(top_dout),
.tx_sout_e(top_sout),
 
.ready_tx_data(top_tx_ready),
.ready_tx_timecode(top_tx_ready_tick)
/rtl/RTL_VB/tx_spw.v
50,8 → 50,8
input gotfct_tx,
input send_fct_now,
//
output reg tx_dout,
output reg tx_sout,
output reg tx_dout_e,
output reg tx_sout_e,
//
output reg ready_tx_data,
output reg ready_tx_timecode
113,322 → 113,358
reg last_tx_dout;
reg last_tx_sout;
 
reg tx_dout;
reg tx_sout;
 
reg tx_dout_null;
reg tx_dout_fct;
reg tx_dout_timecode;
reg tx_dout_data;
 
reg block_sum;
reg block_sum_fct_send;
 
reg [3:0] global_counter_transfer;
 
always@(*)
begin
tx_dout_null = 1'b0;
 
if(enable_null)
begin
if(first_time && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = null_s[7];
end
else if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^fct_s[0]^fct_s[1]);
end
else if(last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^eop_s[0]^eop_s[1]);
end
else if(last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^eep_s[0]^eep_s[1]);
end
else if(last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_null = !(null_s[6]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_null = null_s[6];
end
else if(global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_null = null_s[5];
end
else if(global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_null = null_s[4];
end
else if(global_counter_transfer[3:0] == 4'd4)
begin
tx_dout_null = null_s[3];
end
else if(global_counter_transfer[3:0] == 4'd5)
begin
tx_dout_null = null_s[2];
end
else if(global_counter_transfer[3:0] == 4'd6)
begin
tx_dout_null = null_s[1];
end
else if(global_counter_transfer[3:0] == 4'd7)
begin
tx_dout_null = null_s[0];
end
end
end
 
 
always@(*)
begin
tx_dout = 1'b0;
 
if(!enable_tx)
begin
tx_dout = 1'b0;
end
else if( enable_null & first_time & global_counter_transfer == 4'd0)
begin
tx_dout = null_s[7];
end
else if( enable_null & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^null_s[0]^null_s[1]);
end
else if( enable_null & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^fct_s[0]^fct_s[1]);
end
else if( enable_null & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^eop_s[0]^eop_s[1]);
end
else if( enable_null & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^eep_s[0]^eep_s[1]);
end
else if( enable_null & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_null & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(null_s[6]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_null & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = null_s[6];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = null_s[5];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = null_s[4];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd4)
begin
tx_dout = null_s[3];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd5)
begin
tx_dout = null_s[2];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd6)
begin
tx_dout = null_s[1];
end
else if( enable_null & !first_time & global_counter_transfer == 4'd7)
begin
tx_dout = null_s[0];
end
else if( enable_fct & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^null_s[0]^null_s[1]);
end
else if( enable_fct & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^fct_s[0]^fct_s[1]);
end
else if( enable_fct & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^eop_s[0]^eop_s[1]);
end
else if( enable_fct & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^eep_s[0]^eep_s[1]);
end
else if ( enable_fct & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_fct & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(fct_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_fct & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = fct_s[2];
end
else if( enable_fct & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = fct_s[1];
end
else if( enable_fct & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = fct_s[0];
end
else if( enable_time_code & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^null_s[0]^null_s[1]);
end
else if( enable_time_code & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^fct_s[0]^fct_s[1]);
end
else if ( enable_time_code & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^eop_s[0]^eop_s[1]);
end
else if( enable_time_code & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^eep_s[0]^eep_s[1]);
end
else if( enable_time_code & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_time_code & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(timecode_s[12]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = timecode_s[12];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = timecode_s[11];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = timecode_s[10];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd4)
begin
tx_dout = timecode_s[9];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd5)
begin
tx_dout = timecode_s[8];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd6)
begin
tx_dout = timecode_s[0];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd7)
begin
tx_dout = timecode_s[1];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd8)
begin
tx_dout = timecode_s[2];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd9)
begin
tx_dout = timecode_s[3];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd10)
begin
tx_dout = timecode_s[4];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd11)
begin
tx_dout = timecode_s[5];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd12)
begin
tx_dout = timecode_s[6];
end
else if( enable_time_code & !first_time & global_counter_transfer == 4'd13)
begin
tx_dout = timecode_s[7];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^null_s[0]^null_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^fct_s[0]^fct_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^eop_s[0]^eop_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^eep_s[0]^eep_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_n_char & !data_tx_i[8] & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(data_tx_i[8]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^null_s[0]^null_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^fct_s[0]^fct_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^eop_s[0]^eop_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^eep_s[0]^eep_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(eop_s[3]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = eop_s[2];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = eop_s[1];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b00 & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = eop_s[0];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == NULL & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^null_s[0]^null_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == FCT & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^fct_s[0]^fct_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == EOP & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^eop_s[0]^eop_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == EEP & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^eep_s[0]^eep_s[1]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == DATA & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( enable_n_char & !data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & last_type == TIMEC & global_counter_transfer == 4'd0)
begin
tx_dout = !(eep_s[3]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( enable_n_char & !data_tx_i[8] & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = data_tx_i[8];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = data_tx_i[0];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = data_tx_i[1];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd4)
begin
tx_dout = data_tx_i[2];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd5)
begin
tx_dout = data_tx_i[3];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd6)
begin
tx_dout = data_tx_i[4];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd7)
begin
tx_dout = data_tx_i[5];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd8)
begin
tx_dout = data_tx_i[6];
end
else if( enable_n_char & !data_tx_i[8] & !first_time & global_counter_transfer == 4'd9)
begin
tx_dout = data_tx_i[7];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd1)
begin
tx_dout = eep_s[2];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd2)
begin
tx_dout = eep_s[1];
end
else if( enable_n_char & data_tx_i[8] & data_tx_i[1:0] == 2'b01 & !first_time & global_counter_transfer == 4'd3)
begin
tx_dout = eep_s[0];
end
tx_dout_fct = 1'b0;
if(enable_fct)
begin
 
if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^fct_s[0]^fct_s[1]);
end
else if(last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^eop_s[0]^eop_s[1]);
end
else if(last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^eep_s[0]^eep_s[1]);
end
else if (last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_fct = !(fct_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_fct = fct_s[2];
end
else if(global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_fct = fct_s[1];
end
else if(global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_fct = fct_s[0];
end
 
end
end
 
always@(*)
begin
tx_dout_timecode = 1'b0;
 
if(enable_time_code)
begin
if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^fct_s[0]^fct_s[1]);
end
else if (last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^eop_s[0]^eop_s[1]);
end
else if( last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^eep_s[0]^eep_s[1]);
end
else if( last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_timecode = !(timecode_s[12]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_timecode = timecode_s[12];
end
else if( global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_timecode = timecode_s[11];
end
else if( global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_timecode = timecode_s[10];
end
else if( global_counter_transfer[3:0] == 4'd4)
begin
tx_dout_timecode = timecode_s[9];
end
else if( global_counter_transfer[3:0] == 4'd5)
begin
tx_dout_timecode = timecode_s[8];
end
else if( global_counter_transfer[3:0] == 4'd6)
begin
tx_dout_timecode = timecode_s[0];
end
else if( global_counter_transfer[3:0] == 4'd7)
begin
tx_dout_timecode = timecode_s[1];
end
else if( global_counter_transfer[3:0] == 4'd8)
begin
tx_dout_timecode = timecode_s[2];
end
else if(global_counter_transfer[3:0] == 4'd9)
begin
tx_dout_timecode = timecode_s[3];
end
else if(global_counter_transfer[3:0] == 4'd10)
begin
tx_dout_timecode = timecode_s[4];
end
else if(global_counter_transfer[3:0] == 4'd11)
begin
tx_dout_timecode = timecode_s[5];
end
else if( global_counter_transfer[3:0] == 4'd12)
begin
tx_dout_timecode = timecode_s[6];
end
else if(global_counter_transfer[3:0] == 4'd13)
begin
tx_dout_timecode = timecode_s[7];
end
end
end
 
always@(*)
begin
tx_dout_data = 1'b0;
 
if(enable_n_char)
begin
if(!data_tx_i[8] && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^null_s[0]^null_s[1]);
end
else if(!data_tx_i[8] && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^fct_s[0]^fct_s[1]);
end
else if(!data_tx_i[8] && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^eop_s[0]^eop_s[1]);
end
else if(!data_tx_i[8] && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^eep_s[0]^eep_s[1]);
end
else if(!data_tx_i[8] && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(!data_tx_i[8] && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(data_tx_i[8]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^null_s[0]^null_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^fct_s[0]^fct_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^eop_s[0]^eop_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^eep_s[0]^eep_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eop_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^null_s[0]^null_s[1]);
end
else if(data_tx_i[8] & data_tx_i[1:0] == 2'b01 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^fct_s[0]^fct_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^eop_s[0]^eop_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^eep_s[0]^eep_s[1]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout_data = !(eep_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_data = data_tx_i[8];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_data = data_tx_i[0];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_data = data_tx_i[1];
end
else if( !data_tx_i[8] && global_counter_transfer[3:0] == 4'd4)
begin
tx_dout_data = data_tx_i[2];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd5)
begin
tx_dout_data = data_tx_i[3];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd6)
begin
tx_dout_data = data_tx_i[4];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd7)
begin
tx_dout_data = data_tx_i[5];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd8)
begin
tx_dout_data = data_tx_i[6];
end
else if(!data_tx_i[8] && global_counter_transfer[3:0] == 4'd9)
begin
tx_dout_data = data_tx_i[7];
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_data = eep_s[2];
end
else if( data_tx_i[8] && data_tx_i[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_data = eep_s[1];
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_data = eep_s[0];
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout_data = eop_s[2];
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout_data = eop_s[1];
end
else if(data_tx_i[8] && data_tx_i[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout_data = eop_s[0];
end
end
end
//strobe
always@(*)
439,15 → 475,14
begin
tx_sout = 1'b0;
end
else if((enable_null | enable_fct | enable_n_char | enable_time_code) && tx_dout == last_tx_dout)
else if((enable_null | enable_fct | enable_n_char | enable_time_code) & tx_dout == last_tx_dout)
begin
tx_sout = !last_tx_sout;
end
else if((enable_null | enable_fct | enable_n_char | enable_time_code) && tx_dout != last_tx_dout)
else if((enable_null | enable_fct | enable_n_char | enable_time_code) & tx_dout != last_tx_dout)
begin
tx_sout = last_tx_sout;
end
end
end
 
always@(*)
587,11 → 622,68
 
end
 
 
always@(*)
begin
 
tx_dout = 1'b0;
 
if(enable_null)
begin
tx_dout = tx_dout_null;
end
else if(enable_fct)
begin
tx_dout = tx_dout_fct;
end
else if(enable_time_code)
begin
tx_dout = tx_dout_timecode;
end
else if(enable_n_char)
begin
tx_dout = tx_dout_data;
end
end
 
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
tx_dout_e <= 1'b0;
tx_sout_e <= 1'b0;
end
else
begin
if(enable_null)
begin
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
end
else if(enable_fct)
begin
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
end
else if(enable_time_code)
begin
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
end
else if(enable_n_char)
begin
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
end
end
end
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
 
timecode_s <= 14'b01110000000000;
fct_flag <= 3'd7;
 
617,18 → 709,12
 
last_tx_dout <= 1'b0;
last_tx_sout <= 1'b0;
 
state_tx <= tx_spw_start;
 
end
else
begin
//null_s <= null_s;
//fct_s <= fct_s;
//eop_s <= eop_s;
//eep_s <= eep_s;
//timecode_s <= timecode_s;
//fct_flag <= fct_flag;
 
state_tx <= next_state_tx;
last_tx_dout <= tx_dout;
689,7 → 775,6
end
else if(enable_fct)
begin
 
ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
 
739,6 → 824,7
end
else if(enable_time_code)
begin
 
hold_null <= 1'b0;
hold_fct <= 1'b0;
hold_data <= 1'b0;
790,7 → 876,6
end
else if(enable_n_char)
begin
ready_tx_timecode <= 1'b0;
hold_null <= 1'b0;
hold_fct <= 1'b0;

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