URL
https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk
Subversion Repositories sparc64soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/sparc64soc/trunk
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/os2wb/l1dir.v
172,7 → 172,7
assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)}; |
assign inval_vect0[111:94]=0; |
|
assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)}; |
/*assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)}; |
assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)}; |
assign inval_vect1[31:8]=0; |
assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)}; |
183,8 → 183,21
assign inval_vect1[87:64]=0; |
assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)}; |
assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)}; |
assign inval_vect1[111:94]=0;*/ |
|
assign inval_vect1[3:0]=0; |
assign inval_vect1[7:4]=0; |
assign inval_vect1[31:8]=0; |
assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5]==0)}; |
assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5]==0)}; |
assign inval_vect1[55:38]=0; |
assign inval_vect1[59:56]=0; |
assign inval_vect1[63:60]=0; |
assign inval_vect1[87:64]=0; |
assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5]==1)}; |
assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5]==1)}; |
assign inval_vect1[111:94]=0; |
|
|
assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0]; |
assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0]; |
assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) || |
/os2wb/os2wb_dual.v
577,9 → 577,9
if(pcx_packet_d[117]) // Flush |
begin |
cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer |
cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer |
cpx_two_packet<=1; |
cpu2<=!cpu; // Flush should be sent to both cores |
//cpx_packet_2<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer |
//cpx_two_packet<=1; |
//cpu2<=!cpu; // Flush should be sent to both cores |
end |
else // Tread-to-thread interrupt |
begin |
750,7 → 750,7
5'b00101://STRSTORE |
begin |
cpx_packet_1[143:140]<=4'b0110; // Type |
cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],inval_vect0}; |
cpx_packet_1[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0}; |
wb_cycle<=0; |
state<=`CPX_READY_1; |
end |
758,7 → 758,7
begin |
cpx_packet_1[143:140]<=4'b0000; // Load return for first packet |
cpx_packet_2[143:140]<=4'b0100; // Store ACK for second packet |
cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],inval_vect0}; |
cpx_packet_2[127:0]<={5'b0,pcx_packet_d[64+5:64+4],2'b0,cpu,pcx_packet_d[64+11:64+6],inval_vect0}; |
cpx_packet_1[127:0]<={wb_data_i,wb_data_i}; |
state<=`PCX_REQ_STEP2; |
end |
1054,7 → 1054,7
if(cpu2 && othercpuhit[1]) |
begin |
cpx_ready<=1; |
cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b000,pcx_packet_d[64+11:64+6],inval_vect1};; |
cpx_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b000,pcx_packet_d[64+11:64+6],inval_vect1};; |
end |
else |
begin |
1070,7 → 1070,7
if(!cpu2 && othercpuhit[1]) |
begin |
cpx1_ready<=1; |
cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5:64+4],3'b001,pcx_packet_d[64+11:64+6],inval_vect1};; |
cpx1_packet<={1'b1,4'b0011,12'b0,5'b0,pcx_packet_d[64+5],1'b1,3'b001,pcx_packet_d[64+11:64+6],inval_vect1};; |
end |
else |
begin |