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URL https://opencores.org/ocsvn/spi2ram/spi2ram/trunk

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    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/trunk/tb2.v
0,0 → 1,319
module top_module ();
reg clk=0;
reg spi_sck,spi_cs,spi_mosi,spi_clk ;
wire spi_miso;
wire[16:0] nvram_addr;
wire nvram_en;
wire nvram_g;
wire nvram_w;
 
reg sys_clk;
reg sys_rstn;
reg [7:0] rDin;
 
parameter clockperiod = 10;
parameter clockperiod1 = 8;
initial
begin
rDin = 0;
sys_rstn = 0;
sys_clk = 0;
#15
sys_rstn = 1;
end
 
initial
begin
spi_sck = 1'b0;
//repeat(1000) spi_sck = #(clockperiod/2)~spi_sck;
end
 
initial `probe_start; // Start the timing diagram
// A testbench
initial begin
#80;
spi_cs = 1'b0;
#20;spi_cs = 1'b1;
#20;spi_cs = 1'b0;
datasend(8'h03);
datasend(8'h01);
datasend(8'h55);
rDin = 8'h11;
datasend(8'ha1);
rDin = 8'h33;
datasend(8'hdd);
rDin = 8'h22;
datasend(8'h11);
rDin = 8'h77;
datasend(8'h22);
rDin = 8'h99;
datasend(8'h44);
spi_cs = 1'b1;
#20;
$finish; // Quit the simulation
end
 
task datasend(input [7:0] senddata);
begin
#5; spi_sck = 1'b0;
spi_mosi = senddata[7];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[6];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[5];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[4];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[3];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[2];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[1];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
spi_mosi = senddata[0];
#5; spi_sck = 1'b1;
#5; spi_sck = 1'b0;
#5;
end
endtask
spi_slave_nvram spi_slave_nvram_sim (
.spi_sck(spi_sck),
.spi_cs(spi_cs),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
 
.sAddress(sAddress) ,
.sCSn(sCSn),
.sOEn(sOEn),
.sWRn(sWRn),
.sDqDir(sDqDir),
.sDqOut(sDqOut),
.sDqIn(rDin)
);
`probe(spi_sck); // Probe signal "clk"
`probe(spi_mosi); // Probe signal "clk"
`probe(sys_rstn); // Probe signal "clk"
`probe(spi_cs); // Probe signal "clk"
`probe(spi_miso); // Probe signal "clk"
endmodule
 
module spi_slave_nvram
(
//spi interface
input spi_sck,
input spi_cs,
input spi_mosi,
output spi_miso,
//nvram interface
output [16:0] sAddress ,
output sCSn,
output sOEn,
output sWRn,
output sDqDir,
output [7:0] sDqOut,
input [7:0] sDqIn
);
reg [7:0] rINBUF;
reg [7:0] rOUTBUF;
assign spi_miso = rOUTBUF[7];
 
reg [5:0] rCnt;
reg rCntOV;
wire sCnt8;
//assign sCnt8 = (~|(rCnt[2:0])) & (|rCnt[5:3]);
assign sCnt8 = (~|(rCnt[2:0])) & ((|rCnt[5:3]) | rCntOV);
assign sCSn = sOEn & sWRn;
assign sOEn = ~sRamOE;
assign sWRn = ~sRamWR;
assign sDqDir = sRamWR;
 
always@(posedge spi_sck , posedge spi_cs )begin
if(spi_cs)begin
rINBUF <= 'b0;
rCnt <= 'b0;
end
else
begin
rINBUF <= {rINBUF[6:0], spi_mosi};
rCnt <= rCnt + 1'b1;
end
end
reg [7:0] rCmd;
reg [7:0] rState;
reg [16:0] rAddress;
reg rReadFlag1,rReadFlag2;
assign sAddress = (rReadFlag1 ) ? {rAddress[16:8],rINBUF}:rAddress;
reg rDoutEn;
wire sRamOE;
assign sRamOE = sCnt8 & spi_sck & (rReadFlag1 | rReadFlag2);
reg rWriteFlag1;
wire sRamWR;
assign sRamWR = sCnt8 & spi_sck & rWriteFlag1;
reg [7:0] rRamWrBuf;
assign sDqOut = sRamWR?rINBUF:8'h00;
reg rCmdGotFlag;
 
always@( negedge spi_sck , posedge spi_cs ) begin
if(spi_cs)begin
rWriteFlag1<= 'b0;
rReadFlag1<= 'b0;
rReadFlag2<= 'b0;
rDoutEn <= 0;
rAddress<= 'b0;
rCmdGotFlag <= 0;
rCntOV <= 1'b0;
end
else
if(sCnt8)begin
if(!rCmdGotFlag)begin
rCmdGotFlag <= 1'b1;
rCntOV <= 1'b1;
rCmd <= rINBUF;
if(rINBUF == 8'h9f) rOUTBUF <= 8'haa;
if(rINBUF == 8'h05) rOUTBUF <= rState;
if(rINBUF == 8'h04) rState[1] <= 1'b0;
if(rINBUF == 8'h06) rState[1] <= 1'b1;
end
else begin
case(rCmd)
8'h01:begin
if( rCnt[5:3] == 3'b010) rState <= rINBUF;
end
8'h02:begin
if( rWriteFlag1 == 'b0 )begin
case( rCnt[5:3])
3'b010: begin
rAddress[16] <= rINBUF[0];
end
3'b011: begin
rAddress[15:8] <= rINBUF;
end
3'b100: begin
rAddress[7:0] <= rINBUF;
rWriteFlag1 <= 1'b1;
end
endcase
end
else begin
rRamWrBuf <= rINBUF;
rAddress <= rAddress + 1'b1;
end
end
8'h03:begin
if( rReadFlag2 == 'b0 )begin
case( rCnt[5:3])
3'b010: begin
rAddress[16] <= rINBUF[0];
//rOUTBUF <= 8'h00;
rReadFlag1<= 'b0;
rReadFlag2<= 'b0;
end
3'b011: begin
rAddress[15:8] <= rINBUF;
//rOUTBUF <= 8'h00;
rReadFlag1<= 'b1;
rReadFlag2<= 'b0;
end
3'b100: begin
rAddress[16:0] <= {rAddress[16:8], rINBUF} + 1'b1;
rOUTBUF <= sDqIn;
rReadFlag1<= 'b0;
rReadFlag2 <= 'b1;
end
endcase
end
else begin
rOUTBUF <= sDqIn;
rAddress <= rAddress + 1'b1;
end
end
8'h04:begin
end
8'h05:begin
if( rCnt[5:3] == 3'b010) rOUTBUF <= rState;
end
8'h06:begin
end
8'h9f:begin
case( rCnt[5:3])
3'b010: begin
rOUTBUF <= 8'h11;
end
3'b011: begin
rOUTBUF <= 8'h22;
end
3'b100: begin
rOUTBUF <= 8'h33;
end
endcase
end
default:begin
end
endcase
end
end
else begin
rOUTBUF <= {rOUTBUF[6:0],1'b0};
end
end
`probe(rCnt);
`probe(rCmd);
`probe(spi_sck);
`probe(rINBUF);
`probe(rOUTBUF);
`probe(sCnt8);
`probe(rState);
`probe(sAddress);
`probe(rAddress);
`probe(rReadFlag1);
`probe(rReadFlag2);
`probe(sRamOE);
`probe(sRamWR);
`probe(rRamWrBuf);
`probe(sCSn);
`probe(sOEn);
`probe( sWRn);
`probe(sDqOut);
`probe(sDqIn);
endmodule

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