URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/
- from Rev 20 to Rev 19
- ↔ Reverse comparison
Rev 20 → Rev 19
/spi_master_slave/trunk/rtl/spi_loopback_test.vhd
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/spi_master_slave/trunk/syn/spi_master_atlys_top.par
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/spi_master_slave/trunk/syn/spi_master_atlys_top.pcf
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/spi_master_slave/trunk/syn/spi_master_atlys_top.xst
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/spi_master_slave/trunk/syn/spi_master_atlys_top.drc
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/spi_master_slave/trunk/syn/spi_master_atlys_top.twr
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/spi_master_slave/trunk/syn/spi_master_atlys_top.syr
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/spi_master_slave/trunk/syn/spi_ms_atlys.gise
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/spi_master_slave/trunk/syn/spi_master_atlys_top_envsettings.html
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/spi_master_slave/trunk/syn/spi_ms_atlys.xise
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/spi_master_slave/trunk/syn/spi_master_summary.html
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/spi_master_slave/trunk/syn/spi_master_atlys_top_guide.ncd
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/spi_master_slave/trunk/syn/fuseRelaunch.cmd
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/spi_master_slave/trunk/syn/spi_master_atlys_top_summary.html
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/spi_master_slave/trunk/syn/fuse.xmsgs
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/spi_master_slave/trunk/syn/sim_master_slave_ct.pdf
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spi_master_slave/trunk/syn/sim_master_slave_ct.pdf
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Index: spi_master_slave/trunk/syn/readme.txt
===================================================================
--- spi_master_slave/trunk/syn/readme.txt (revision 20)
+++ spi_master_slave/trunk/syn/readme.txt (revision 19)
@@ -11,27 +11,28 @@
The files are:
-------------
-spi_master.vhd vhdl model for the spi_master interface
-spi_slave.vhd vhdl model for the spi_slave interface
-grp_debouncer.vhd vhdl model for the switch debouncer
-spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board
-spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd'
-spi_master_atlys.xise ISE 13.1 project file
-spi_master_atlys.ucf pin lock constraints for the Atlys board
-spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests
-spi_master_envsettings.html synthesis env settings, with the tools setup used
-ATLYS_0x.SET Tek MSO2014 settings files with the debug pin names
-spi_master_atlys_top_bit.zip bitgen file to program the Atlys board
+spi_master.vhd vhdl model for the spi_master interface
+spi_slave.vhd vhdl model for the spi_slave interface
+grp_debouncer.vhd vhdl model for the switch debouncer
+spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board
+spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd'
+spi_master_atlys.xise ISE 13.1 project file
+spi_master_atlys.ucf pin lock constraints for the Atlys board
+spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests
+spi_master_envsettings.html synthesis env settings, with the tools setup used
+ATLYS_01.SET Tek MSO2014 settings files with the debug pin names
+ATLYS_02.SET
+ATLYS_03.SET
+spi_master_atlys_top_bit.zip bitgen file to program the Atlys board
-If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org
+If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
http://opencores.org/project,spi_master_slave,bugtracker
-If you find this core useful, please let me know: jdoin@opencores.org
In any case, thank you very much for testing this core.
@@ -39,3 +40,4 @@
Jonny Doin
jdoin@opencores.org
+
/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd
51,8 → 51,6
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
s_do_o : out std_logic_vector (7 downto 0); |
m_do_o : out std_logic_vector (7 downto 0); |
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state |
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
71,8 → 69,8
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
constant CPOL : std_logic := '0'; |
constant CPHA : std_logic := '0'; |
constant CPOL : std_logic := '1'; |
constant CPHA : std_logic := '1'; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
91,7 → 89,7
st_wait_spi_di_req_3, st_wait_spi_ack_3); |
|
type fsm_slave_write_state_type is |
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, st_wait_spi_do_valid_1, |
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, |
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end); |
|
type fsm_slave_read_state_type is |
156,9 → 154,6
signal spi_do_s : std_logic_vector (N-1 downto 0); |
signal spi_wr_ack_s : std_logic; |
signal spi_rx_bit_s : std_logic; |
-- spi debug data -- |
signal spi_state_m : std_logic_vector (3 downto 0); |
signal spi_state_s : std_logic_vector (3 downto 0); |
-- slave data output regs -- |
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
193,9 → 188,8
wren_i => spi_wren_reg_m, |
wr_ack_o => spi_wr_ack_m, |
do_valid_o => spi_do_valid_m, |
do_o => spi_do_m, |
do_o => spi_do_m |
------------ debug pins ------------ |
state_dbg_o => spi_state_m -- debug: internal state register |
); |
|
-- spi slave port: data and control signals driven by the slave fsm |
212,14 → 206,13
wren_i => spi_wren_reg_s, |
wr_ack_o => spi_wr_ack_s, |
do_valid_o => spi_do_valid_s, |
do_o => spi_do_s, |
do_o => spi_do_s |
------------ debug pins ------------ |
state_dbg_o => spi_state_s -- debug: internal state register |
); |
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 200) -- debounce 8 inputs with 200 us settling time |
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => sw_i, -- noisy input data |
228,7 → 221,7
|
-- debounce for the input pushbuttons, with new data strobe output |
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 200) -- debounce 6 inputs with 200 us settling time |
generic map (N => 6, CNT_VAL => 20000) -- debounce 6 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => btn_i, -- noisy input data |
364,7 → 357,7
-- master port fsm state and combinatorial logic |
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, |
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg, |
new_button, clear) is |
new_button) is |
begin |
spi_rst_next <= spi_rst_reg; |
spi_di_next_m <= spi_di_reg_m; |
392,7 → 385,7
m_wr_st_next <= st_send_spi_data_sw; |
elsif new_button = '1' then |
btn_next <= btn_data; -- load new button data (end the mismatch condition) |
if clear = '0' then |
if btn_data(btUP) = '0' then |
if btn_data(btDOWN) = '1' then |
m_wr_st_next <= st_send_spi_data_sw; |
elsif btn_data(btLEFT) = '1' then |
460,7 → 453,7
end process fsm_m_wr_combi_proc; |
|
-- slave port fsm state and combinatorial logic |
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s, |
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, |
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is |
begin |
spi_wren_next_s <= spi_wren_reg_s; |
480,9 → 473,9
|
when st_wait_spi_di_req_2 => |
if spi_di_req_s = '1' then |
-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss) |
-- spi_wren_next_s <= '1'; |
s_wr_st_next <= st_wait_spi_do_valid_1; |
spi_di_next_s <= X"D2"; |
spi_wren_next_s <= '1'; |
s_wr_st_next <= st_wait_spi_ack_2; |
end if; |
|
when st_wait_spi_ack_2 => -- the actual write happens on this state |
491,11 → 484,6
s_wr_st_next <= st_wait_spi_di_req_3; |
end if; |
|
when st_wait_spi_do_valid_1 => |
if spi_do_valid_s = '1' then |
s_wr_st_next <= st_wait_spi_di_req_3; |
end if; |
|
when st_wait_spi_di_req_3 => |
if spi_di_req_s = '1' then |
spi_di_next_s <= X"D3"; |
607,17 → 595,11
dbg(10) <= spi_wr_ack_m; |
dbg(9) <= spi_di_req_m; |
dbg(8) <= spi_do_valid_m; |
-- dbg(11 downto 8) <= spi_state_s; |
-- slave signals mapped on dbg |
dbg(7) <= spi_wren_reg_s; |
dbg(6) <= spi_wr_ack_s; |
dbg(5) <= spi_di_req_s; |
dbg(4) <= spi_do_valid_s; |
-- specific ports to test on testbench |
s_do_o <= spi_do_s; |
m_do_o <= spi_do_m; |
m_state_o <= spi_state_m; -- master spi fsm state |
s_state_o <= spi_state_s; -- slave spi fsm state |
|
end behavioral; |
|
/spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
101,8 → 101,6
sw_i => sw_data, |
btn_i => btn_data, |
led_o => leds, |
m_do_o => m_do_reg, |
s_do_o => s_do_reg, |
m_state_o => master_state, |
s_state_o => slave_state, |
dbg_o => dbg |
113,7 → 111,6
wr_ack_m <= dbg(10); |
di_req_m <= dbg(9); |
do_valid_m <= dbg(8); |
|
-- slave signals mapped on dbg |
wren_s <= dbg(7); |
wr_ack_s <= dbg(6); |
139,18 → 136,14
begin |
wait for 100 ns; -- wait until global set/reset completes |
|
btn_data(btUP) <= '1'; |
btn_data(btRESET) <= '1'; |
wait for 1 us; |
btn_data(btUP) <= '0'; |
sw_data <= X"81"; |
wait for 5 us; |
sw_data <= X"C1"; |
wait for 5 us; |
sw_data <= X"C9"; |
wait for 5 us; |
sw_data <= X"55"; |
wait for 5 us; |
assert false report "End Simulation" severity failure; -- stop simulation |
btn_data(btRESET) <= '0'; |
wait for 900 ns; |
|
sw_data <= X"5A"; |
|
wait; -- will wait forever |
end process tb; |
-- End Test Bench |
END; |
/spi_master_slave/trunk/syn/spi_master_atlys_top_bit.zip
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/spi_master_slave/trunk/syn/spi_test_ct.wcfg
3,7 → 3,7
<wave_state> |
</wave_state> |
<db_ref_list> |
<db_ref path="D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto"> |
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto"> |
<top_modules> |
<top_module name="numeric_std" /> |
<top_module name="std_logic_1164" /> |
16,7 → 16,7
</top_modules> |
</db_ref> |
</db_ref_list> |
<WVObjectSize size="21" /> |
<WVObjectSize size="22" /> |
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">dbg[11:0]</obj_property> |
<obj_property name="ObjectShortName">dbg[11:0]</obj_property> |
48,6 → 48,10
<obj_property name="ElementShortName">spi_mosi</obj_property> |
<obj_property name="ObjectShortName">spi_mosi</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/dbg[3]" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">[3]</obj_property> |
<obj_property name="ObjectShortName">dbg[3]</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_miso</obj_property> |
<obj_property name="ObjectShortName">spi_miso</obj_property> |
/spi_master_slave/trunk/syn/spi_master_envsettings.html
16,51 → 16,44
<tr> |
<td>PATHEXT</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>Path</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Flash Magic</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Flash Magic</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_FOR_ALTIUM_OVERRIDE</td> |
<td> </td> |
<td><font color=gray> </font></td> |
<td><font color=gray>< not set ></font></td> |
<td><font color=gray>< not set ></font></td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
357,28 → 350,28
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td><font color=gray>-dd</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>_ngo</font></td> |
<td><font color=gray>None</font></td> |
<td>-dd</td> |
<td> </td> |
<td>_ngo</td> |
<td>None</td> |
</tr> |
<tr> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
</tr> |
<tr> |
<td><font color=gray>-uc</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys.ucf</font></td> |
<td><font color=gray>None</font></td> |
<td>-uc</td> |
<td> </td> |
<td>spi_master_atlys.ucf</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Map Property Settings"></A> |
393,144 → 386,102
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td><font color=gray>-detail</font></td> |
<td><font color=gray>Generate Detailed MAP Report</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
<td>-detail</td> |
<td>Generate Detailed MAP Report</td> |
<td>TRUE</td> |
<td>TRUE</td> |
</tr> |
<tr> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>high</font></td> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>high</td> |
</tr> |
<tr> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray>Placer Extra Effort Map</font></td> |
<td><font color=gray>NORMAL</font></td> |
<td><font color=gray> </font></td> |
<td>-xe</td> |
<td>Placer Extra Effort Map</td> |
<td>NORMAL</td> |
<td> </td> |
</tr> |
<tr> |
<td><font color=gray>-xt</font></td> |
<td><font color=gray>Extra Cost Tables</font></td> |
<td><font color=gray>0</font></td> |
<td><font color=gray>0</font></td> |
<td>-xt</td> |
<td>Extra Cost Tables</td> |
<td>0</td> |
<td>0</td> |
</tr> |
<tr> |
<td><font color=gray>-global_opt</font></td> |
<td><font color=gray>Global Optimization map</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>FALSE</font></td> |
<td>-global_opt</td> |
<td>Global Optimization map</td> |
<td>TRUE</td> |
<td>FALSE</td> |
</tr> |
<tr> |
<td><font color=gray>-ir</font></td> |
<td><font color=gray>Use RLOC Constraints</font></td> |
<td><font color=gray>OFF</font></td> |
<td><font color=gray>OFF</font></td> |
<td>-ir</td> |
<td>Use RLOC Constraints</td> |
<td>OFF</td> |
<td>OFF</td> |
</tr> |
<tr> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>2</font></td> |
<td><font color=gray>0</font></td> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>2</td> |
<td>0</td> |
</tr> |
<tr> |
<td><font color=gray>-t</font></td> |
<td><font color=gray>Starting Placer Cost Table (1-100) Map</font></td> |
<td><font color=gray>1</font></td> |
<td><font color=gray>0</font></td> |
<td>-t</td> |
<td>Starting Placer Cost Table (1-100) Map</td> |
<td>1</td> |
<td>0</td> |
</tr> |
<tr> |
<td><font color=gray>-r</font></td> |
<td><font color=gray>Register Ordering</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>4</font></td> |
<td>-r</td> |
<td>Register Ordering</td> |
<td>4</td> |
<td>4</td> |
</tr> |
<tr> |
<td><font color=gray>-equivalent_register_removal</font></td> |
<td><font color=gray>Equivalent Register Removal</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
<td>-equivalent_register_removal</td> |
<td>Equivalent Register Removal</td> |
<td>TRUE</td> |
<td>TRUE</td> |
</tr> |
<tr> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td><font color=gray>-lc</font></td> |
<td><font color=gray>LUT Combining</font></td> |
<td><font color=gray>area</font></td> |
<td><font color=gray>off</font></td> |
<td>-lc</td> |
<td>LUT Combining</td> |
<td>area</td> |
<td>off</td> |
</tr> |
<tr> |
<td><font color=gray>-o</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys_top_map.ncd</font></td> |
<td><font color=gray>None</font></td> |
<td>-o</td> |
<td> </td> |
<td>spi_master_atlys_top_map.ncd</td> |
<td>None</td> |
</tr> |
<tr> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
<tr> |
<td><font color=gray>-pr</font></td> |
<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td> |
<td><font color=gray>off</font></td> |
<td><font color=gray>off</font></td> |
<td>-pr</td> |
<td>Pack I/O Registers/Latches into IOBs</td> |
<td>off</td> |
<td>off</td> |
</tr> |
<tr> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>n</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray> </font></td> |
</tr> |
<tr> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>std</font></td> |
</tr> |
<tr> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
545,31 → 496,31
</tr> |
<tr> |
<td>CPU Architecture/Speed</td> |
<td>Intel(R) Xeon(R) CPU E5620 @ 2.40GHz/2394 MHz</td> |
<td><font color=gray>Intel(R) Xeon(R) CPU E5620 @ 2.40GHz/2394 MHz</font></td> |
<td><font color=gray>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</font></td> |
<td><font color=gray>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</font></td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>Host</td> |
<td>EELE313</td> |
<td><font color=gray>EELE313</font></td> |
<td><font color=gray>Develop-W7</font></td> |
<td><font color=gray>Develop-W7</font></td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>OS Name</td> |
<td>Microsoft Windows 7 , 64-bit</td> |
<td><font color=gray>Microsoft Windows 7 , 64-bit</font></td> |
<td><font color=gray>Microsoft Windows 7 , 32-bit</font></td> |
<td><font color=gray>Microsoft Windows 7 , 32-bit</font></td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>OS Release</td> |
<td>Service Pack 1 (build 7601)</td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td><font color=gray>< data not available ></font></td> |
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</BODY> </HTML> |
/spi_master_slave/trunk/syn/spi_master_atlys.xise
0,0 → 1,379
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="grp_debouncer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="spi_master_atlys.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="spi_master_atlys_test.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map" xil_pn:value="Area" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
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<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
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<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
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<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spi_master_atlys_top_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="spi_master_atlys_top_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spi_master_atlys_top_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spi_master_atlys_top_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="12000 ns" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="12 us" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="spi_master_atlys" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-07T09:55:20" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C5BE631B69F48AB8C2F24035AF7A13B" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings> |
<binding xil_pn:location="/spi_master_atlys_top" xil_pn:name="spi_master_atlys.ucf"/> |
</bindings> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
/spi_master_slave/trunk/syn/spi_master_atlys.ucf
206,14 → 206,14
# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET |
|
# PMOD Connector |
NET "m_state_o<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N |
NET "m_state_o<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P |
NET "m_state_o<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N |
NET "m_state_o<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P |
# NET "s_state_o<0>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N |
# NET "s_state_o<1>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P |
# NET "s_state_o<2>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N |
# NET "s_state_o<3>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P |
# NET "spi_ssel_o" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N |
# NET "spi_sck_o" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P |
# NET "spi_mosi_o" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N |
# NET "dbg_o<0>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P |
# NET "dbg_o<1>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N |
# NET "dbg_o<2>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P |
# NET "dbg_o<3>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N |
# NET "dbg_o<4>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P |
|
# onboard VHDCI |
# Channnel 1 connects to P signals, Channel 2 to N signals |
/spi_master_slave/trunk/syn/usage_statistics_webtalk.html
17,7 → 17,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">31</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD> |
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD> |
</TR> |
29,7 → 29,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD> |
<TD><xtag-property name="Date Generated">2011-08-10T22:59:16</xtag-property></TD> |
<TD><xtag-property name="Date Generated">2011-07-18T02:50:20</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD> |
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD> |
</TR> |
84,21 → 84,22
<xtag-group><xtag-group-name name="Counters=5">Counters=5</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit up counter=3</xtag-item1></LI> |
<LI><xtag-item1>8-bit up counter=2</xtag-item1></LI> |
<LI><xtag-item1>14-bit up counter=1</xtag-item1></LI> |
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FSMs=3">FSMs=3</xtag-group-name> |
<xtag-group><xtag-group-name name="FSMs=1">FSMs=1</xtag-group-name> |
</xtag-group> |
<xtag-group><xtag-group-name name="Multiplexers=46">Multiplexers=46</xtag-group-name> |
<xtag-group><xtag-group-name name="Multiplexers=42">Multiplexers=42</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=20</xtag-item1></LI> |
<LI><xtag-item1>4-bit 2-to-1 multiplexer=12</xtag-item1></LI> |
<LI><xtag-item1>8-bit 2-to-1 multiplexer=14</xtag-item1></LI> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=21</xtag-item1></LI> |
<LI><xtag-item1>4-bit 2-to-1 multiplexer=13</xtag-item1></LI> |
<LI><xtag-item1>8-bit 2-to-1 multiplexer=8</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="Registers=205">Registers=205</xtag-group-name> |
<xtag-group><xtag-group-name name="Registers=171">Registers=171</xtag-group-name> |
<UL> |
<LI><xtag-item1>Flip-Flops=205</xtag-item1></LI> |
<LI><xtag-item1>Flip-Flops=171</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
107,36 → 108,37
<TD> |
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>AGG_BONDED_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=43</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=91</xtag-item1></LI> |
<LI><xtag-item1>NUM_BONDED_IOB=63</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=96</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=49</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=80</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=225</xtag-item1></LI> |
<LI><xtag-item1>AGG_BONDED_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=70</xtag-item1></LI> |
<LI><xtag-item1>NUM_BONDED_IOB=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=76</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=41</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=78</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=195</xtag-item1></LI> |
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=43</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=13</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=75</xtag-item1></LI> |
<LI><xtag-item1>NUM_IOB_FF=9</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=32</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=27</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=48</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=6</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=6</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=26</xtag-item1></LI> |
<LI><xtag-item1>NUM_OLOGIC2=9</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEL=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEM=1</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=82</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=25</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=198</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_F7MUX=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=209</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=15</xtag-item1></LI> |
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=59</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=61</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=20</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=177</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=171</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_SRL_O6ONLY=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=51</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
143,38 → 145,39
<TD> |
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>NumNets_Active=365</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Active=311</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=4</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=23</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=76</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=13</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=39</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=326</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=73</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=75</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=8</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=561</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=313</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=298</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=44</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=11</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=67</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=15</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=35</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=253</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=53</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=78</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=10</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=417</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=268</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=257</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=24</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=15</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=210</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=694</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=616</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=101</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=431</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=178</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=530</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED2=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=423</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=90</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=350</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=25</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=22</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
181,11 → 184,11
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBM=33</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBS=30</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=18</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=20</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBM=20</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBS=19</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=4</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=17</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=8</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
196,22 → 199,23
<UL> |
<LI><xtag-item2>BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=4</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=42</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=8</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=30</xtag-item2></LI> |
<LI><xtag-item2>HARD0=2</xtag-item2></LI> |
<LI><xtag-item2>IOB=63</xtag-item2></LI> |
<LI><xtag-item2>IOB=39</xtag-item2></LI> |
<LI><xtag-item2>IOB_IMUX=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_INBUF=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_OUTBUF=48</xtag-item2></LI> |
<LI><xtag-item2>LUT5=64</xtag-item2></LI> |
<LI><xtag-item2>LUT6=128</xtag-item2></LI> |
<LI><xtag-item2>LUT_OR_MEM6=4</xtag-item2></LI> |
<LI><xtag-item2>PAD=63</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=167</xtag-item2></LI> |
<LI><xtag-item2>SELMUX2_1=4</xtag-item2></LI> |
<LI><xtag-item2>IOB_OUTBUF=24</xtag-item2></LI> |
<LI><xtag-item2>LUT5=65</xtag-item2></LI> |
<LI><xtag-item2>LUT6=108</xtag-item2></LI> |
<LI><xtag-item2>LUT_OR_MEM6=2</xtag-item2></LI> |
<LI><xtag-item2>OLOGIC2=9</xtag-item2></LI> |
<LI><xtag-item2>OLOGIC2_OUTFF=9</xtag-item2></LI> |
<LI><xtag-item2>PAD=39</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=141</xtag-item2></LI> |
<LI><xtag-item2>SLICEL=8</xtag-item2></LI> |
<LI><xtag-item2>SLICEM=1</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=82</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=61</xtag-item2></LI> |
</UL> |
</xtag-group> |
</TD> |
223,33 → 227,52
<TD> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:42] [CK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:42]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:36] [SYNC:6]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:26] [CK_INV:4]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:28] [SYNC:2]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name> |
<UL> |
<LI><xtag-item3>DRIVEATTRBOX=[12:48]</xtag-item3></LI> |
<LI><xtag-item3>SLEW=[SLOW:48]</xtag-item3></LI> |
<LI><xtag-item3>SUSPEND=[3STATE:48]</xtag-item3></LI> |
<LI><xtag-item3>DRIVEATTRBOX=[12:24]</xtag-item3></LI> |
<LI><xtag-item3>SLEW=[SLOW:24]</xtag-item3></LI> |
<LI><xtag-item3>SUSPEND=[3STATE:24]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> |
<UL> |
<LI><xtag-item3>LUT_OR_MEM=[LUT:1]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>LUT_OR_MEM=[RAM:4]</xtag-item3></LI> |
<LI><xtag-item3>RAMMODE=[SRL16:4]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:2] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>LUT_OR_MEM=[RAM:2]</xtag-item3></LI> |
<LI><xtag-item3>RAMMODE=[SRL16:2]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:9]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK0=[CK0_INV:0] [CK0:9]</xtag-item3></LI> |
<LI><xtag-item3>OUTFFTYPE=[FF:9]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT_OQ=[0:9]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:166] [CK_INV:1]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:167]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:164] [SRINIT1:3]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:159] [SYNC:8]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:125] [CK_INV:16]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:141]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:139] [SRINIT1:2]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:121] [SYNC:20]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
256,7 → 279,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:3] [CLK_INV:1]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:5] [CLK_INV:0]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> |
266,7 → 289,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:71] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:46] [CLK_INV:6]</xtag-item3></LI> |
</UL> |
</xtag-group> |
</TD> |
290,30 → 313,30
</xtag-group> |
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name> |
<UL> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CO3=2</xtag-item1></LI> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CO3=6</xtag-item1></LI> |
<LI><xtag-item1>CYINIT=2</xtag-item1></LI> |
<LI><xtag-item1>DI0=4</xtag-item1></LI> |
<LI><xtag-item1>DI1=4</xtag-item1></LI> |
<LI><xtag-item1>DI2=4</xtag-item1></LI> |
<LI><xtag-item1>DI3=2</xtag-item1></LI> |
<LI><xtag-item1>O0=4</xtag-item1></LI> |
<LI><xtag-item1>O1=4</xtag-item1></LI> |
<LI><xtag-item1>O2=4</xtag-item1></LI> |
<LI><xtag-item1>O3=4</xtag-item1></LI> |
<LI><xtag-item1>S0=4</xtag-item1></LI> |
<LI><xtag-item1>S1=4</xtag-item1></LI> |
<LI><xtag-item1>S2=4</xtag-item1></LI> |
<LI><xtag-item1>S3=4</xtag-item1></LI> |
<LI><xtag-item1>DI0=8</xtag-item1></LI> |
<LI><xtag-item1>DI1=7</xtag-item1></LI> |
<LI><xtag-item1>DI2=7</xtag-item1></LI> |
<LI><xtag-item1>DI3=6</xtag-item1></LI> |
<LI><xtag-item1>O0=8</xtag-item1></LI> |
<LI><xtag-item1>O1=8</xtag-item1></LI> |
<LI><xtag-item1>O2=7</xtag-item1></LI> |
<LI><xtag-item1>O3=7</xtag-item1></LI> |
<LI><xtag-item1>S0=8</xtag-item1></LI> |
<LI><xtag-item1>S1=8</xtag-item1></LI> |
<LI><xtag-item1>S2=7</xtag-item1></LI> |
<LI><xtag-item1>S3=7</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=20</xtag-item1></LI> |
<LI><xtag-item1>CK=42</xtag-item1></LI> |
<LI><xtag-item1>D=42</xtag-item1></LI> |
<LI><xtag-item1>Q=42</xtag-item1></LI> |
<LI><xtag-item1>SR=7</xtag-item1></LI> |
<LI><xtag-item1>CE=14</xtag-item1></LI> |
<LI><xtag-item1>CK=30</xtag-item1></LI> |
<LI><xtag-item1>D=30</xtag-item1></LI> |
<LI><xtag-item1>Q=30</xtag-item1></LI> |
<LI><xtag-item1>SR=4</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name> |
324,8 → 347,8
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name> |
<UL> |
<LI><xtag-item1>I=15</xtag-item1></LI> |
<LI><xtag-item1>O=48</xtag-item1></LI> |
<LI><xtag-item1>PAD=63</xtag-item1></LI> |
<LI><xtag-item1>O=24</xtag-item1></LI> |
<LI><xtag-item1>PAD=39</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name> |
342,106 → 365,125
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name> |
<UL> |
<LI><xtag-item1>IN=48</xtag-item1></LI> |
<LI><xtag-item1>OUT=48</xtag-item1></LI> |
<LI><xtag-item1>IN=24</xtag-item1></LI> |
<LI><xtag-item1>OUT=24</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=17</xtag-item1></LI> |
<LI><xtag-item1>A2=29</xtag-item1></LI> |
<LI><xtag-item1>A3=31</xtag-item1></LI> |
<LI><xtag-item1>A4=30</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>O5=64</xtag-item1></LI> |
<LI><xtag-item1>A1=15</xtag-item1></LI> |
<LI><xtag-item1>A2=23</xtag-item1></LI> |
<LI><xtag-item1>A3=14</xtag-item1></LI> |
<LI><xtag-item1>A4=16</xtag-item1></LI> |
<LI><xtag-item1>A5=19</xtag-item1></LI> |
<LI><xtag-item1>O5=65</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=34</xtag-item1></LI> |
<LI><xtag-item1>A2=66</xtag-item1></LI> |
<LI><xtag-item1>A3=97</xtag-item1></LI> |
<LI><xtag-item1>A4=108</xtag-item1></LI> |
<LI><xtag-item1>A5=126</xtag-item1></LI> |
<LI><xtag-item1>A6=128</xtag-item1></LI> |
<LI><xtag-item1>O6=128</xtag-item1></LI> |
<LI><xtag-item1>A1=39</xtag-item1></LI> |
<LI><xtag-item1>A2=58</xtag-item1></LI> |
<LI><xtag-item1>A3=69</xtag-item1></LI> |
<LI><xtag-item1>A4=90</xtag-item1></LI> |
<LI><xtag-item1>A5=91</xtag-item1></LI> |
<LI><xtag-item1>A6=107</xtag-item1></LI> |
<LI><xtag-item1>O6=108</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> |
<UL> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=1</xtag-item1></LI> |
<LI><xtag-item1>O5=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=4</xtag-item1></LI> |
<LI><xtag-item1>A2=4</xtag-item1></LI> |
<LI><xtag-item1>A3=4</xtag-item1></LI> |
<LI><xtag-item1>A4=4</xtag-item1></LI> |
<LI><xtag-item1>A5=4</xtag-item1></LI> |
<LI><xtag-item1>A6=4</xtag-item1></LI> |
<LI><xtag-item1>CLK=4</xtag-item1></LI> |
<LI><xtag-item1>DI2=4</xtag-item1></LI> |
<LI><xtag-item1>O6=4</xtag-item1></LI> |
<LI><xtag-item1>WE=4</xtag-item1></LI> |
<LI><xtag-item1>A1=2</xtag-item1></LI> |
<LI><xtag-item1>A2=2</xtag-item1></LI> |
<LI><xtag-item1>A3=2</xtag-item1></LI> |
<LI><xtag-item1>A4=2</xtag-item1></LI> |
<LI><xtag-item1>A5=2</xtag-item1></LI> |
<LI><xtag-item1>A6=2</xtag-item1></LI> |
<LI><xtag-item1>CLK=2</xtag-item1></LI> |
<LI><xtag-item1>DI2=2</xtag-item1></LI> |
<LI><xtag-item1>O6=2</xtag-item1></LI> |
<LI><xtag-item1>WE=2</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name> |
<UL> |
<LI><xtag-item1>CLK0=9</xtag-item1></LI> |
<LI><xtag-item1>D1=9</xtag-item1></LI> |
<LI><xtag-item1>OQ=9</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name> |
<UL> |
<LI><xtag-item1>CK0=9</xtag-item1></LI> |
<LI><xtag-item1>D1=9</xtag-item1></LI> |
<LI><xtag-item1>Q=9</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name> |
<UL> |
<LI><xtag-item1>PAD=63</xtag-item1></LI> |
<LI><xtag-item1>PAD=39</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=92</xtag-item1></LI> |
<LI><xtag-item1>CK=167</xtag-item1></LI> |
<LI><xtag-item1>D=167</xtag-item1></LI> |
<LI><xtag-item1>Q=167</xtag-item1></LI> |
<LI><xtag-item1>SR=11</xtag-item1></LI> |
<LI><xtag-item1>CE=69</xtag-item1></LI> |
<LI><xtag-item1>CK=141</xtag-item1></LI> |
<LI><xtag-item1>D=141</xtag-item1></LI> |
<LI><xtag-item1>Q=141</xtag-item1></LI> |
<LI><xtag-item1>SR=23</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name> |
<UL> |
<LI><xtag-item1>0=4</xtag-item1></LI> |
<LI><xtag-item1>1=4</xtag-item1></LI> |
<LI><xtag-item1>OUT=4</xtag-item1></LI> |
<LI><xtag-item1>S0=4</xtag-item1></LI> |
<LI><xtag-item1>0=2</xtag-item1></LI> |
<LI><xtag-item1>1=2</xtag-item1></LI> |
<LI><xtag-item1>OUT=2</xtag-item1></LI> |
<LI><xtag-item1>S0=2</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=1</xtag-item1></LI> |
<LI><xtag-item1>A2=1</xtag-item1></LI> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A4=3</xtag-item1></LI> |
<LI><xtag-item1>A5=5</xtag-item1></LI> |
<LI><xtag-item1>A6=5</xtag-item1></LI> |
<LI><xtag-item1>AMUX=4</xtag-item1></LI> |
<LI><xtag-item1>AQ=2</xtag-item1></LI> |
<LI><xtag-item1>A6=8</xtag-item1></LI> |
<LI><xtag-item1>AMUX=5</xtag-item1></LI> |
<LI><xtag-item1>AQ=4</xtag-item1></LI> |
<LI><xtag-item1>AX=1</xtag-item1></LI> |
<LI><xtag-item1>B5=4</xtag-item1></LI> |
<LI><xtag-item1>B6=4</xtag-item1></LI> |
<LI><xtag-item1>B4=4</xtag-item1></LI> |
<LI><xtag-item1>B5=3</xtag-item1></LI> |
<LI><xtag-item1>B6=8</xtag-item1></LI> |
<LI><xtag-item1>BMUX=4</xtag-item1></LI> |
<LI><xtag-item1>BQ=1</xtag-item1></LI> |
<LI><xtag-item1>BQ=5</xtag-item1></LI> |
<LI><xtag-item1>BX=1</xtag-item1></LI> |
<LI><xtag-item1>C1=1</xtag-item1></LI> |
<LI><xtag-item1>C2=4</xtag-item1></LI> |
<LI><xtag-item1>C3=4</xtag-item1></LI> |
<LI><xtag-item1>C4=4</xtag-item1></LI> |
<LI><xtag-item1>C5=8</xtag-item1></LI> |
<LI><xtag-item1>C6=8</xtag-item1></LI> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CLK=4</xtag-item1></LI> |
<LI><xtag-item1>CMUX=5</xtag-item1></LI> |
<LI><xtag-item1>COUT=2</xtag-item1></LI> |
<LI><xtag-item1>CQ=3</xtag-item1></LI> |
<LI><xtag-item1>CX=4</xtag-item1></LI> |
<LI><xtag-item1>D1=3</xtag-item1></LI> |
<LI><xtag-item1>D2=3</xtag-item1></LI> |
<LI><xtag-item1>D3=4</xtag-item1></LI> |
<LI><xtag-item1>D4=4</xtag-item1></LI> |
<LI><xtag-item1>D5=6</xtag-item1></LI> |
<LI><xtag-item1>D6=8</xtag-item1></LI> |
<LI><xtag-item1>DMUX=4</xtag-item1></LI> |
<LI><xtag-item1>DQ=1</xtag-item1></LI> |
<LI><xtag-item1>C5=3</xtag-item1></LI> |
<LI><xtag-item1>C6=7</xtag-item1></LI> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CLK=5</xtag-item1></LI> |
<LI><xtag-item1>CMUX=3</xtag-item1></LI> |
<LI><xtag-item1>COUT=6</xtag-item1></LI> |
<LI><xtag-item1>CQ=5</xtag-item1></LI> |
<LI><xtag-item1>CX=1</xtag-item1></LI> |
<LI><xtag-item1>D=1</xtag-item1></LI> |
<LI><xtag-item1>D1=1</xtag-item1></LI> |
<LI><xtag-item1>D2=1</xtag-item1></LI> |
<LI><xtag-item1>D3=1</xtag-item1></LI> |
<LI><xtag-item1>D4=5</xtag-item1></LI> |
<LI><xtag-item1>D5=4</xtag-item1></LI> |
<LI><xtag-item1>D6=7</xtag-item1></LI> |
<LI><xtag-item1>DMUX=3</xtag-item1></LI> |
<LI><xtag-item1>DQ=5</xtag-item1></LI> |
<LI><xtag-item1>DX=1</xtag-item1></LI> |
<LI><xtag-item1>SR=4</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
448,22 → 490,6
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=1</xtag-item1></LI> |
<LI><xtag-item1>A2=1</xtag-item1></LI> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=1</xtag-item1></LI> |
<LI><xtag-item1>A6=1</xtag-item1></LI> |
<LI><xtag-item1>AI=1</xtag-item1></LI> |
<LI><xtag-item1>AQ=1</xtag-item1></LI> |
<LI><xtag-item1>B1=1</xtag-item1></LI> |
<LI><xtag-item1>B2=1</xtag-item1></LI> |
<LI><xtag-item1>B3=1</xtag-item1></LI> |
<LI><xtag-item1>B4=1</xtag-item1></LI> |
<LI><xtag-item1>B5=1</xtag-item1></LI> |
<LI><xtag-item1>B6=1</xtag-item1></LI> |
<LI><xtag-item1>BI=1</xtag-item1></LI> |
<LI><xtag-item1>BQ=1</xtag-item1></LI> |
<LI><xtag-item1>C1=1</xtag-item1></LI> |
<LI><xtag-item1>C2=1</xtag-item1></LI> |
<LI><xtag-item1>C3=1</xtag-item1></LI> |
486,49 → 512,49
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item1>A=16</xtag-item1></LI> |
<LI><xtag-item1>A=20</xtag-item1></LI> |
<LI><xtag-item1>A1=16</xtag-item1></LI> |
<LI><xtag-item1>A2=26</xtag-item1></LI> |
<LI><xtag-item1>A3=32</xtag-item1></LI> |
<LI><xtag-item1>A4=34</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>A6=32</xtag-item1></LI> |
<LI><xtag-item1>AMUX=13</xtag-item1></LI> |
<LI><xtag-item1>AQ=46</xtag-item1></LI> |
<LI><xtag-item1>AX=28</xtag-item1></LI> |
<LI><xtag-item1>B=10</xtag-item1></LI> |
<LI><xtag-item1>B1=8</xtag-item1></LI> |
<LI><xtag-item1>B2=14</xtag-item1></LI> |
<LI><xtag-item1>B3=19</xtag-item1></LI> |
<LI><xtag-item1>B4=23</xtag-item1></LI> |
<LI><xtag-item1>B5=24</xtag-item1></LI> |
<LI><xtag-item1>B6=22</xtag-item1></LI> |
<LI><xtag-item1>BMUX=8</xtag-item1></LI> |
<LI><xtag-item1>BQ=36</xtag-item1></LI> |
<LI><xtag-item1>BX=24</xtag-item1></LI> |
<LI><xtag-item1>C=9</xtag-item1></LI> |
<LI><xtag-item1>C1=9</xtag-item1></LI> |
<LI><xtag-item1>A2=19</xtag-item1></LI> |
<LI><xtag-item1>A3=24</xtag-item1></LI> |
<LI><xtag-item1>A4=26</xtag-item1></LI> |
<LI><xtag-item1>A5=27</xtag-item1></LI> |
<LI><xtag-item1>A6=27</xtag-item1></LI> |
<LI><xtag-item1>AMUX=11</xtag-item1></LI> |
<LI><xtag-item1>AQ=32</xtag-item1></LI> |
<LI><xtag-item1>AX=24</xtag-item1></LI> |
<LI><xtag-item1>B=7</xtag-item1></LI> |
<LI><xtag-item1>B1=10</xtag-item1></LI> |
<LI><xtag-item1>B2=17</xtag-item1></LI> |
<LI><xtag-item1>B3=17</xtag-item1></LI> |
<LI><xtag-item1>B4=18</xtag-item1></LI> |
<LI><xtag-item1>B5=17</xtag-item1></LI> |
<LI><xtag-item1>B6=17</xtag-item1></LI> |
<LI><xtag-item1>BMUX=7</xtag-item1></LI> |
<LI><xtag-item1>BQ=32</xtag-item1></LI> |
<LI><xtag-item1>BX=22</xtag-item1></LI> |
<LI><xtag-item1>C=8</xtag-item1></LI> |
<LI><xtag-item1>C1=6</xtag-item1></LI> |
<LI><xtag-item1>C2=12</xtag-item1></LI> |
<LI><xtag-item1>C3=18</xtag-item1></LI> |
<LI><xtag-item1>C4=20</xtag-item1></LI> |
<LI><xtag-item1>C5=23</xtag-item1></LI> |
<LI><xtag-item1>C6=21</xtag-item1></LI> |
<LI><xtag-item1>CE=29</xtag-item1></LI> |
<LI><xtag-item1>CLK=71</xtag-item1></LI> |
<LI><xtag-item1>CMUX=8</xtag-item1></LI> |
<LI><xtag-item1>CQ=35</xtag-item1></LI> |
<LI><xtag-item1>C3=14</xtag-item1></LI> |
<LI><xtag-item1>C4=15</xtag-item1></LI> |
<LI><xtag-item1>C5=16</xtag-item1></LI> |
<LI><xtag-item1>C6=15</xtag-item1></LI> |
<LI><xtag-item1>CE=25</xtag-item1></LI> |
<LI><xtag-item1>CLK=52</xtag-item1></LI> |
<LI><xtag-item1>CMUX=9</xtag-item1></LI> |
<LI><xtag-item1>CQ=27</xtag-item1></LI> |
<LI><xtag-item1>CX=19</xtag-item1></LI> |
<LI><xtag-item1>D=14</xtag-item1></LI> |
<LI><xtag-item1>D1=13</xtag-item1></LI> |
<LI><xtag-item1>D2=21</xtag-item1></LI> |
<LI><xtag-item1>D3=25</xtag-item1></LI> |
<LI><xtag-item1>D4=28</xtag-item1></LI> |
<LI><xtag-item1>D5=30</xtag-item1></LI> |
<LI><xtag-item1>D6=28</xtag-item1></LI> |
<LI><xtag-item1>DMUX=21</xtag-item1></LI> |
<LI><xtag-item1>DQ=39</xtag-item1></LI> |
<LI><xtag-item1>DX=24</xtag-item1></LI> |
<LI><xtag-item1>SR=10</xtag-item1></LI> |
<LI><xtag-item1>D=11</xtag-item1></LI> |
<LI><xtag-item1>D1=11</xtag-item1></LI> |
<LI><xtag-item1>D2=15</xtag-item1></LI> |
<LI><xtag-item1>D3=16</xtag-item1></LI> |
<LI><xtag-item1>D4=19</xtag-item1></LI> |
<LI><xtag-item1>D5=19</xtag-item1></LI> |
<LI><xtag-item1>D6=18</xtag-item1></LI> |
<LI><xtag-item1>DMUX=10</xtag-item1></LI> |
<LI><xtag-item1>DQ=29</xtag-item1></LI> |
<LI><xtag-item1>DX=22</xtag-item1></LI> |
<LI><xtag-item1>SR=6</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
541,10 → 567,185
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
</xtag-section></UL></TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR> |
570,8 → 771,8
</tr> |
<tr> |
<td><xtag-program-name>bitgen</xtag-program-name></td> |
<td><xtag-total-run-started>178</xtag-total-run-started></td> |
<td><xtag-total-run-finished>178</xtag-total-run-finished></td> |
<td><xtag-total-run-started>137</xtag-total-run-started></td> |
<td><xtag-total-run-finished>137</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
630,8 → 831,8
</tr> |
<tr> |
<td><xtag-program-name>map</xtag-program-name></td> |
<td><xtag-total-run-started>506</xtag-total-run-started></td> |
<td><xtag-total-run-finished>490</xtag-total-run-finished></td> |
<td><xtag-total-run-started>444</xtag-total-run-started></td> |
<td><xtag-total-run-finished>429</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
640,8 → 841,8
</tr> |
<tr> |
<td><xtag-program-name>netgen</xtag-program-name></td> |
<td><xtag-total-run-started>489</xtag-total-run-started></td> |
<td><xtag-total-run-finished>481</xtag-total-run-finished></td> |
<td><xtag-total-run-started>459</xtag-total-run-started></td> |
<td><xtag-total-run-finished>451</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
660,8 → 861,8
</tr> |
<tr> |
<td><xtag-program-name>ngdbuild</xtag-program-name></td> |
<td><xtag-total-run-started>550</xtag-total-run-started></td> |
<td><xtag-total-run-finished>550</xtag-total-run-finished></td> |
<td><xtag-total-run-started>476</xtag-total-run-started></td> |
<td><xtag-total-run-finished>476</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
670,8 → 871,8
</tr> |
<tr> |
<td><xtag-program-name>par</xtag-program-name></td> |
<td><xtag-total-run-started>522</xtag-total-run-started></td> |
<td><xtag-total-run-finished>464</xtag-total-run-finished></td> |
<td><xtag-total-run-started>462</xtag-total-run-started></td> |
<td><xtag-total-run-finished>407</xtag-total-run-finished></td> |
<td><xtag-total-error>14</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
690,8 → 891,8
</tr> |
<tr> |
<td><xtag-program-name>trce</xtag-program-name></td> |
<td><xtag-total-run-started>491</xtag-total-run-started></td> |
<td><xtag-total-run-finished>491</xtag-total-run-finished></td> |
<td><xtag-total-run-started>433</xtag-total-run-started></td> |
<td><xtag-total-run-finished>433</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
720,8 → 921,8
</tr> |
<tr> |
<td><xtag-program-name>xst</xtag-program-name></td> |
<td><xtag-total-run-started>848</xtag-total-run-started></td> |
<td><xtag-total-run-finished>843</xtag-total-run-finished></td> |
<td><xtag-total-run-started>754</xtag-total-run-started></td> |
<td><xtag-total-run-finished>749</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
769,11 → 970,8
<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_MapLUTCombining_spartan6</xtag-process-property-name>=<xtag-process-property-value>Area</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_ProjectDescription</xtag-process-property-name>=<xtag-process-property-value>Testbed for the spi master/slave cores for continuous transmission mode</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_SelectedInstanceHierarchicalPath</xtag-process-property-name>=<xtag-process-property-value>/testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_SynthExtractRAM</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
|
795,16 → 993,10
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2011-07-07T09:55:20</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>2C5BE631B69F48AB8C2F24035AF7A13B</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>31</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_behav</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_par</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_translate</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimSourceNode</xtag-process-property-name>=<xtag-process-property-value>inst_spi_master_atlys_top</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_xilxBitgStart_Clk_DriveDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_xilxMapReportDetail</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
813,9 → 1005,6
</TR><TR><TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_ISimSimulationRun_behav_tb</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRun_translate_tb</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_MapExtraEffort_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_xilxMapEnableMultiThreading</xtag-process-property-name>=<xtag-process-property-value>2</xtag-process-property-value></TD> |
|
823,21 → 1012,16
<TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx45</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRunTime_behav_tb</xtag-process-property-name>=<xtag-process-property-value>30000 ns</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_ISimSimulationRunTime_par_tb</xtag-process-property-name>=<xtag-process-property-value>12000 ns</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRunTime_translate_tb</xtag-process-property-name>=<xtag-process-property-value>12 us</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_parEnableMultiThreading_spartan6</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD> |
</TR><TR><TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_parEnableMultiThreading_spartan6</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD> |
<TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD> |
|
</TR><TR><TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>5</xtag-source-property-value></TD> |
</TR><TR><TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD> |
<TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>4</xtag-source-property-value></TD> |
</TR></xtag-section></TABLE> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> |
<xtag-section name="UnisimStatistics"> |
845,68 → 1029,68
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>83</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>65</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>111</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>10</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>74</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>18</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>17</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>55</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>12</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>47</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>48</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>19</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>46</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>30</xtag-preunisim-param-value></TD> |
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>83</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>111</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>10</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>74</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>17</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>55</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>12</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>47</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>48</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>19</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>46</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>30</xtag-postunisim-param-value></TD> |
</xtag-section></TABLE> |
<BR></BODY></HTML> |
/spi_master_slave/trunk/bench/spi_master_atlys_test.vhd
0,0 → 1,149
-- TestBench Template |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity testbench is |
end testbench; |
|
architecture behavior of testbench is |
|
--============================================================================================= |
-- Constants |
--============================================================================================= |
-- clock period |
constant CLK_PERIOD : time := 10 ns; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
constant btUP : integer := 1; |
constant btLEFT : integer := 2; |
constant btDOWN : integer := 3; |
constant btRIGHT : integer := 4; |
constant btCENTER : integer := 5; |
|
--============================================================================================= |
-- COMPONENT DECLARATIONS |
--============================================================================================= |
component spi_master_atlys_top |
port( |
gclk_i : in std_logic; |
sw_i : in std_logic_vector(7 downto 0); |
btn_i : in std_logic_vector(5 downto 0); |
spi_ssel_o : out std_logic; |
spi_sck_o : out std_logic; |
spi_mosi_o : out std_logic; |
spi_miso_o : out std_logic; |
led_o : out std_logic_vector(7 downto 0); |
s_do_o : out std_logic_vector (7 downto 0); |
m_do_o : out std_logic_vector (7 downto 0); |
m_state_o : out std_logic_vector (3 downto 0); |
s_state_o : out std_logic_vector (3 downto 0); |
dbg_o : out std_logic_vector(11 downto 0) |
); |
end component; |
|
--============================================================================================= |
-- Signals for state machine control |
--============================================================================================= |
|
--============================================================================================= |
-- Signals for internal operation |
--============================================================================================= |
--- clock signals --- |
signal sysclk : std_logic := '0'; -- 100MHz clock |
--- switch debouncer signals --- |
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data |
--- pushbutton debouncer signals --- |
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons |
--- spi port signals --- |
signal spi_ssel : std_logic; |
signal spi_sck : std_logic; |
signal spi_mosi : std_logic; |
signal spi_miso : std_logic; |
-- debug output signals |
signal leds : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (11 downto 0) := (others => '0'); |
-- debug ports -- |
signal s_do_reg : std_logic_vector (7 downto 0); |
signal m_do_reg : std_logic_vector (7 downto 0); |
-- master signals mapped on dbg |
signal wren_m : std_logic; |
signal wr_ack_m : std_logic; |
signal di_req_m : std_logic; |
signal do_valid_m : std_logic; |
signal master_state : std_logic_vector (3 downto 0); |
-- slave signals mapped on dbg |
signal wren_s : std_logic; |
signal wr_ack_s : std_logic; |
signal di_req_s : std_logic; |
signal do_valid_s : std_logic; |
signal slave_state : std_logic_vector (3 downto 0); |
begin |
|
--============================================================================================= |
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST |
--============================================================================================= |
-- spi_master_atlys_top: |
-- receives the 100 MHz clock from the board clock oscillator |
-- receives the 8 slide switches and 5 pushbuttons as test stimuli |
-- connects to 4 spi signals |
-- connects to 8 board LEDs |
-- connects to 12 debug pins |
inst_spi_master_atlys_top: spi_master_atlys_top |
port map( |
gclk_i => sysclk, |
spi_ssel_o => spi_ssel, |
spi_sck_o => spi_sck, |
spi_mosi_o => spi_mosi, |
spi_miso_o => spi_miso, |
sw_i => sw_data, |
btn_i => btn_data, |
led_o => leds, |
m_state_o => master_state, |
s_state_o => slave_state, |
dbg_o => dbg |
); |
|
-- master signals mapped on dbg |
wren_m <= dbg(11); |
wr_ack_m <= dbg(10); |
di_req_m <= dbg(9); |
do_valid_m <= dbg(8); |
-- slave signals mapped on dbg |
wren_s <= dbg(7); |
wr_ack_s <= dbg(6); |
di_req_s <= dbg(5); |
do_valid_s <= dbg(4); |
|
|
--============================================================================================= |
-- CLOCK GENERATION |
--============================================================================================= |
gclk_proc: process is |
begin |
loop |
sysclk <= not sysclk; |
wait for CLK_PERIOD / 2; |
end loop; |
end process gclk_proc; |
|
--============================================================================================= |
-- TEST BENCH STIMULI |
--============================================================================================= |
tb : process |
begin |
wait for 100 ns; -- wait until global set/reset completes |
|
btn_data(btRESET) <= '1'; |
wait for 1 us; |
btn_data(btRESET) <= '0'; |
wait for 900 ns; |
|
sw_data <= X"5A"; |
|
wait; -- will wait forever |
end process tb; |
-- End Test Bench |
END; |
/spi_master_slave/trunk/bench/spi_test_ct.wcfg
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?> |
<wave_config> |
<wave_state> |
</wave_state> |
<db_ref_list> |
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto"> |
<top_modules> |
<top_module name="numeric_std" /> |
<top_module name="std_logic_1164" /> |
<top_module name="testbench" /> |
<top_module name="textio" /> |
<top_module name="vcomponents" /> |
<top_module name="vital_primitives" /> |
<top_module name="vital_timing" /> |
<top_module name="vpackage" /> |
</top_modules> |
</db_ref> |
</db_ref_list> |
<WVObjectSize size="22" /> |
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">dbg[11:0]</obj_property> |
<obj_property name="ObjectShortName">dbg[11:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/sysclk" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">sysclk</obj_property> |
<obj_property name="ObjectShortName">sysclk</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/sw_data" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">sw_data[7:0]</obj_property> |
<obj_property name="ObjectShortName">sw_data[7:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/btn_data" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">btn_data[5:0]</obj_property> |
<obj_property name="ObjectShortName">btn_data[5:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_ssel" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_ssel</obj_property> |
<obj_property name="ObjectShortName">spi_ssel</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_sck" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_sck</obj_property> |
<obj_property name="ObjectShortName">spi_sck</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_mosi" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_mosi</obj_property> |
<obj_property name="ObjectShortName">spi_mosi</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/dbg[3]" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">[3]</obj_property> |
<obj_property name="ObjectShortName">dbg[3]</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_miso</obj_property> |
<obj_property name="ObjectShortName">spi_miso</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/wren_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_m</obj_property> |
<obj_property name="ObjectShortName">wren_m</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/wr_ack_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wr_ack_m</obj_property> |
<obj_property name="ObjectShortName">wr_ack_m</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/di_req_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">di_req_m</obj_property> |
<obj_property name="ObjectShortName">di_req_m</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/do_valid_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_valid_m</obj_property> |
<obj_property name="ObjectShortName">do_valid_m</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/m_do_reg" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">m_do_reg[7:0]</obj_property> |
<obj_property name="ObjectShortName">m_do_reg[7:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/master_state" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">master_state[3:0]</obj_property> |
<obj_property name="ObjectShortName">master_state[3:0]</obj_property> |
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/wren_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_s</obj_property> |
<obj_property name="ObjectShortName">wren_s</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/wr_ack_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wr_ack_s</obj_property> |
<obj_property name="ObjectShortName">wr_ack_s</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/di_req_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">di_req_s</obj_property> |
<obj_property name="ObjectShortName">di_req_s</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/do_valid_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_valid_s</obj_property> |
<obj_property name="ObjectShortName">do_valid_s</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/s_do_reg" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">s_do_reg[7:0]</obj_property> |
<obj_property name="ObjectShortName">s_do_reg[7:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/leds" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">leds[7:0]</obj_property> |
<obj_property name="ObjectShortName">leds[7:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/slave_state" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">slave_state[3:0]</obj_property> |
<obj_property name="ObjectShortName">slave_state[3:0]</obj_property> |
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> |
</wvobject> |
</wave_config> |
/spi_master_slave/trunk/bench/readme.txt
0,0 → 1,9
spi_master_slave simulation testbench |
===================================== |
|
This is the basic simulation testbench file for the spi_master.vhd and spi_slave.vhd. |
The simulation environment used for the development was Xilinx ISIM from the ISE 13.1 webpack. |
|
The .wcfg file is the ISIM waveform configuration file, with all the buses already configured for |
hexadecimal number format and signal groupings that make sense. |
|
/spi_master_slave/trunk/bench/spi_loopback_test.vhd
0,0 → 1,305
-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Jonny Doin |
-- |
-- Create Date: 22:59:18 04/25/2011 |
-- Design Name: spi_master_slave |
-- Module Name: spi_master_slave/spi_loopback_test.vhd |
-- Project Name: SPI_interface |
-- Target Device: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested |
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave' |
-- module, simulating the internal working of each design. |
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for |
-- both modules, and also a different clock domain for each parallel interface. |
-- Different values for PREFETCH for each interface can be tested, to model the best value |
-- for the pipelined memory / bus that is attached to the di/do ports. |
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with |
-- 8 words of data to be sent, synchronous to each clock and flow control signals. |
-- |
-- |
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave' |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.10 - Implemented FIFO simulation for each interface. |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
|
library work; |
use work.all; |
|
ENTITY spi_loopback_test IS |
GENERIC ( |
N : positive := 32; -- 32bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 2 -- prefetch lookahead cycles |
); |
END spi_loopback_test; |
|
ARCHITECTURE behavior OF spi_loopback_test IS |
|
--========================================================= |
-- Component declaration for the Unit Under Test (UUT) |
--========================================================= |
|
COMPONENT spi_loopback |
PORT( |
m_clk_i : IN std_logic; |
m_rst_i : IN std_logic; |
m_spi_miso_i : IN std_logic; |
m_di_i : IN std_logic_vector(31 downto 0); |
m_wren_i : IN std_logic; |
s_clk_i : IN std_logic; |
s_spi_ssel_i : IN std_logic; |
s_spi_sck_i : IN std_logic; |
s_spi_mosi_i : IN std_logic; |
s_di_i : IN std_logic_vector(31 downto 0); |
s_wren_i : IN std_logic; |
m_spi_ssel_o : OUT std_logic; |
m_spi_sck_o : OUT std_logic; |
m_spi_mosi_o : OUT std_logic; |
m_di_req_o : OUT std_logic; |
m_do_valid_o : OUT std_logic; |
m_do_o : OUT std_logic_vector(31 downto 0); |
m_do_transfer_o : OUT std_logic; |
m_wren_o : OUT std_logic; |
m_wren_ack_o : OUT std_logic; |
m_rx_bit_reg_o : OUT std_logic; |
m_state_dbg_o : OUT std_logic_vector(5 downto 0); |
m_core_clk_o : OUT std_logic; |
m_core_n_clk_o : OUT std_logic; |
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0); |
s_spi_miso_o : OUT std_logic; |
s_di_req_o : OUT std_logic; |
s_do_valid_o : OUT std_logic; |
s_do_o : OUT std_logic_vector(31 downto 0); |
s_do_transfer_o : OUT std_logic; |
s_wren_o : OUT std_logic; |
s_wren_ack_o : OUT std_logic; |
s_rx_bit_reg_o : OUT std_logic; |
s_state_dbg_o : OUT std_logic_vector(5 downto 0) |
); |
END COMPONENT; |
|
--========================================================= |
-- constants |
--========================================================= |
constant fifo_memory_size : integer := 16; |
|
--========================================================= |
-- types |
--========================================================= |
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0); |
|
--========================================================= |
-- signals to connect the instances |
--========================================================= |
-- internal clk and rst |
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck. |
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck. |
signal rst : std_logic := 'U'; |
-- spi bus wires |
signal spi_sck : std_logic; |
signal spi_ssel : std_logic; |
signal spi_miso : std_logic; |
signal spi_mosi : std_logic; |
-- master parallel interface |
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U'); |
signal do_valid_m : std_logic; |
signal do_transfer_m : std_logic; |
signal di_req_m : std_logic; |
signal wren_m : std_logic := '0'; |
signal wren_o_m : std_logic := 'U'; |
signal wren_ack_o_m : std_logic := 'U'; |
signal rx_bit_reg_m : std_logic; |
signal state_m : std_logic_vector (5 downto 0); |
signal core_clk_o_m : std_logic; |
signal core_n_clk_o_m : std_logic; |
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- slave parallel interface |
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_s : std_logic_vector (N-1 downto 0); |
signal do_valid_s : std_logic; |
signal do_transfer_s : std_logic; |
signal di_req_s : std_logic; |
signal wren_s : std_logic := '0'; |
signal wren_o_s : std_logic := 'U'; |
signal wren_ack_o_s : std_logic := 'U'; |
signal rx_bit_reg_s : std_logic; |
signal state_s : std_logic_vector (5 downto 0); |
-- signal sh_reg_s : std_logic_vector (N-1 downto 0); |
|
--========================================================= |
-- Clock period definitions |
--========================================================= |
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock |
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock |
|
BEGIN |
|
--========================================================= |
-- Component instantiation for the Unit Under Test (UUT) |
--========================================================= |
|
Inst_spi_loopback: spi_loopback |
port map( |
----------------MASTER----------------------- |
m_clk_i => m_clk, |
m_rst_i => rst, |
m_spi_ssel_o => spi_ssel, |
m_spi_sck_o => spi_sck, |
m_spi_mosi_o => spi_mosi, |
m_spi_miso_i => spi_miso, |
m_di_req_o => di_req_m, |
m_di_i => di_m, |
m_wren_i => wren_m, |
m_do_valid_o => do_valid_m, |
m_do_o => do_m, |
----- debug ----- |
m_do_transfer_o => do_transfer_m, |
m_wren_o => wren_o_m, |
m_wren_ack_o => wren_ack_o_m, |
m_rx_bit_reg_o => rx_bit_reg_m, |
m_state_dbg_o => state_m, |
m_core_clk_o => core_clk_o_m, |
m_core_n_clk_o => core_n_clk_o_m, |
m_sh_reg_dbg_o => sh_reg_m, |
----------------SLAVE----------------------- |
s_clk_i => s_clk, |
s_spi_ssel_i => spi_ssel, |
s_spi_sck_i => spi_sck, |
s_spi_mosi_i => spi_mosi, |
s_spi_miso_o => spi_miso, |
s_di_req_o => di_req_s, |
s_di_i => di_s, |
s_wren_i => wren_s, |
s_do_valid_o => do_valid_s, |
s_do_o => do_s, |
----- debug ----- |
s_do_transfer_o => do_transfer_s, |
s_wren_o => wren_o_s, |
s_wren_ack_o => wren_ack_o_s, |
s_rx_bit_reg_o => rx_bit_reg_s, |
s_state_dbg_o => state_s |
-- s_sh_reg_dbg_o => sh_reg_s |
); |
|
--========================================================= |
-- Clock generator processes |
--========================================================= |
m_clk_process : process |
begin |
m_clk <= '0'; |
wait for m_clk_period/2; |
m_clk <= '1'; |
wait for m_clk_period/2; |
end process m_clk_process; |
|
s_clk_process : process |
begin |
s_clk <= '0'; |
wait for s_clk_period/2; |
s_clk <= '1'; |
wait for s_clk_period/2; |
end process s_clk_process; |
|
--========================================================= |
-- rst_i process |
--========================================================= |
rst <= '0', '1' after 20 ns, '0' after 100 ns; |
|
--========================================================= |
-- Master interface process |
--========================================================= |
master_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789", |
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until m_clk'event and m_clk = '1'; |
di_m <= (others => '0'); |
wren_m <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
wait until di_req_m = '1'; -- wait shift register request for data |
-- load next fifo contents into shift register |
for cnt in 0 to (fifo_memory_size/2)-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '1'; -- write data into spi master |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '0'; -- remove write enable signal |
wait until di_req_m = '1'; -- wait shift register request for data |
end loop; |
wait until spi_ssel = '1'; |
wait for 2000 ns; |
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '1'; -- write data into spi master |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '0'; -- remove write enable signal |
wait until di_req_m = '1'; -- wait shift register request for data |
end loop; |
wait; |
end process master_tx_fifo_proc; |
|
|
--========================================================= |
-- Slave interface process |
--========================================================= |
slave_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394", |
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until s_clk'event and s_clk = '1'; |
di_s <= (others => '0'); |
wren_s <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
wait until di_req_s = '1'; -- wait shift register request for data |
-- load next fifo contents into shift register |
for cnt in 0 to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '1'; -- write data into shift register |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '0'; -- remove write enable signal |
wait until di_req_s = '1'; -- wait shift register request for data |
end loop; |
wait; |
end process slave_tx_fifo_proc; |
|
END ARCHITECTURE behavior; |
/spi_master_slave/trunk/bench/spi_loopback_test_dbg.wcfg
0,0 → 1,157
<?xml version="1.0" encoding="UTF-8"?> |
<wave_config> |
<wave_state> |
</wave_state> |
<db_ref_list> |
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_master_slave/spi_loopback_test_isim_par.wdb" id="1" type="auto"> |
<top_modules> |
<top_module name="numeric_std" /> |
<top_module name="spi_loopback_test" /> |
<top_module name="std_logic_1164" /> |
<top_module name="textio" /> |
<top_module name="vcomponents" /> |
<top_module name="vital_primitives" /> |
<top_module name="vital_timing" /> |
<top_module name="vpackage" /> |
</top_modules> |
</db_ref> |
</db_ref_list> |
<WVObjectSize size="32" /> |
<wvobject fp_name="/spi_loopback_test/cpol" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">cpol</obj_property> |
<obj_property name="ObjectShortName">cpol</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/cpha" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">cpha</obj_property> |
<obj_property name="ObjectShortName">cpha</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/core_clk_o_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">core_clk_o_m</obj_property> |
<obj_property name="ObjectShortName">core_clk_o_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/core_n_clk_o_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">core_n_clk_o_m</obj_property> |
<obj_property name="ObjectShortName">core_n_clk_o_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/m_clk" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">m_clk</obj_property> |
<obj_property name="ObjectShortName">m_clk</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/rst" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">rst</obj_property> |
<obj_property name="ObjectShortName">rst</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/spi_ssel" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_ssel</obj_property> |
<obj_property name="ObjectShortName">spi_ssel</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/spi_sck" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_sck</obj_property> |
<obj_property name="ObjectShortName">spi_sck</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/spi_mosi" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_mosi</obj_property> |
<obj_property name="ObjectShortName">spi_mosi</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/rx_bit_reg_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">rx_bit_reg_s</obj_property> |
<obj_property name="ObjectShortName">rx_bit_reg_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/spi_miso" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_miso</obj_property> |
<obj_property name="ObjectShortName">spi_miso</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/rx_bit_reg_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">rx_bit_reg_m</obj_property> |
<obj_property name="ObjectShortName">rx_bit_reg_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/sh_reg_m" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">sh_reg_m[31:0]</obj_property> |
<obj_property name="ObjectShortName">sh_reg_m[31:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_m" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">do_m[31:0]</obj_property> |
<obj_property name="ObjectShortName">do_m[31:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_transfer_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_transfer_m</obj_property> |
<obj_property name="ObjectShortName">do_transfer_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_valid_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_valid_m</obj_property> |
<obj_property name="ObjectShortName">do_valid_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/di_req_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">di_req_m</obj_property> |
<obj_property name="ObjectShortName">di_req_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/di_m" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">di_m[31:0]</obj_property> |
<obj_property name="ObjectShortName">di_m[31:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_m</obj_property> |
<obj_property name="ObjectShortName">wren_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_o_m" type="logic" db_ref_id="1"> |
<obj_property name="DisplayName">label</obj_property> |
<obj_property name="ElementShortName">wren_o_m</obj_property> |
<obj_property name="ObjectShortName">wren_o_m</obj_property> |
<obj_property name="label">wren_o_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_ack_o_m" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_ack_o_m</obj_property> |
<obj_property name="ObjectShortName">wren_ack_o_m</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/state_m" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">state_m[5:0]</obj_property> |
<obj_property name="ObjectShortName">state_m[5:0]</obj_property> |
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/s_clk" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">s_clk</obj_property> |
<obj_property name="ObjectShortName">s_clk</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_s" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">do_s[31:0]</obj_property> |
<obj_property name="ObjectShortName">do_s[31:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_transfer_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_transfer_s</obj_property> |
<obj_property name="ObjectShortName">do_transfer_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/do_valid_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">do_valid_s</obj_property> |
<obj_property name="ObjectShortName">do_valid_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/di_req_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">di_req_s</obj_property> |
<obj_property name="ObjectShortName">di_req_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/di_s" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">di_s[31:0]</obj_property> |
<obj_property name="ObjectShortName">di_s[31:0]</obj_property> |
<obj_property name="Radix">HEXRADIX</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_s</obj_property> |
<obj_property name="ObjectShortName">wren_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_o_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_o_s</obj_property> |
<obj_property name="ObjectShortName">wren_o_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/wren_ack_o_s" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">wren_ack_o_s</obj_property> |
<obj_property name="ObjectShortName">wren_ack_o_s</obj_property> |
</wvobject> |
<wvobject fp_name="/spi_loopback_test/state_s" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">state_s[5:0]</obj_property> |
<obj_property name="ObjectShortName">state_s[5:0]</obj_property> |
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> |
</wvobject> |
</wave_config> |