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https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/spi_master_slave/trunk/rtl
- from Rev 13 to Rev 12
- ↔ Reverse comparison
Rev 13 → Rev 12
/grp_debouncer.vhd
File deleted
/spi_slave.vhd
115,10 → 115,6
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core. |
-- Simulated in iSim with the master core for continuous transmission mode. |
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit. |
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
125,11 → 121,12
-- TODO |
-- ==== |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_unsigned.all; |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity spi_slave is |
Generic ( |
153,7 → 150,7
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
rx_bit_next_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
end spi_slave; |
168,7 → 165,7
-- synthesis tool will remove the receive logic from the generated circuitry. |
--================================================================================================================ |
|
architecture rtl of spi_slave is |
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge |
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge |
183,25 → 180,25
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
------------------------------------------------------------------------------------------ |
-- internal state signals for register and combinatorial stages |
-- internal state signals for register and combinational stages |
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state |
-- shifter signals for register and combinatorial stages |
signal sh_next : std_logic_vector (N-1 downto 0); |
signal sh_reg : std_logic_vector (N-1 downto 0); |
-- shifter signals for register and combinational stages |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- mosi and miso connections |
signal rx_bit_next : std_logic; |
signal tx_bit_next : std_logic; |
signal tx_bit_reg : std_logic; |
-- buffered di_i data signals for register and combinatorial stages |
signal rx_bit_next : std_logic := '0'; |
signal tx_bit_next : std_logic := '0'; |
signal tx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinational stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
-- internal wren_i stretcher for fsm combinatorial stage |
-- internal wren_i stretcher for fsm combinational stage |
signal wren : std_logic; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinatorial stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0); |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal signal to flag transfer to do_buffer_reg |
signal do_transfer_next : std_logic := '0'; |
signal do_transfer_reg : std_logic := '0'; |
294,7 → 291,7
end process in_transfer_proc; |
|
--============================================================================================= |
-- REGISTER TRANSFER PROCESSES |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers change on spi SHIFT_EDGE |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
320,9 → 317,9
end process core_reg_proc; |
|
--============================================================================================= |
-- COMBINATORIAL LOGIC PROCESSES |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
-- state and datapath combinational logic |
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, |
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is |
begin |
335,16 → 332,15
di_req_next <= di_req_reg; -- data input request |
state_next <= state_reg; -- fsm control state |
case state_reg is |
|
when (N) => |
-- stretch do_valid |
wr_ack_next <= '0'; -- acknowledge data in transfer |
-- acknowledge write enable |
wr_ack_next <= '1'; -- acknowledge data in transfer |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
|
when (N-1) downto (PREFETCH+3) => |
-- send bit out and shif bit in |
do_transfer_next <= '0'; -- reset transfer signal |
354,7 → 350,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
|
when (PREFETCH+2) downto 3 => |
-- raise data prefetch request |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
363,7 → 358,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
|
when 2 => |
-- transfer parallel data on next state |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
374,7 → 368,6
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle |
do_buffer_next <= sh_next; -- get next data directly into rx buffer |
state_next <= state_reg - 1; -- update next state at each sck pulse |
|
when 1 => |
-- restart from state 'N' if more sck pulses come |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
381,6 → 374,7
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
if wren = '1' then -- load tx register if valid data present at di_reg |
wr_ack_next <= '1'; -- acknowledge data in transfer |
state_next <= N; -- next state is top bit of new data |
389,53 → 383,44
sh_next <= (others => '0'); -- load null data (output '0' if no load) |
state_next <= 0; -- next state is idle state |
end if; |
|
when 0 => |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
-- idle state: start and end of transmission |
if CPHA = '1' then |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
else |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= not wr_ack_reg; -- will request data if shifter empty |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
end if; |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
state_next <= N; -- next state is top bit of new data |
|
when others => |
state_next <= 0; -- safe state |
|
end case; |
end process core_combi_proc; |
|
--============================================================================================= |
-- OUTPUT LOGIC PROCESSES |
-- RTL OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
|
----------------------------------------------------------------------------------------------- |
-- MISO driver process: copy next tx bit at reset |
----------------------------------------------------------------------------------------------- |
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit |
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic. |
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is |
begin |
if spi_ssel_i = '1' then |
spi_miso_o <= tx_bit_next; -- copy next => reg at reset |
else |
spi_miso_o <= tx_bit_reg; |
end if; |
end process spi_miso_o_proc; |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
--============================================================================================= |
-- these signals are useful for verification, and can be deleted after debug. |
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug |
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; |
wren_o_proc: wren_o <= wren; |
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
end architecture rtl; |
end architecture RTL; |
|
/spi_master.vhd
13,7 → 13,6
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation. |
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial |
-- 'sclk_i' clock. |
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line. |
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two |
-- clock domains. |
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. |
144,8 → 143,6
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm. |
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
196,7 → 193,7
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
core_clk_o : out std_logic; |
core_n_clk_o : out std_logic; |
core_ce_o : out std_logic; |
209,7 → 206,7
-- this architecture is a pipelined register-transfer description. |
-- all signals are clocked at the rising edge of the system clock 'sclk_i'. |
--================================================================================================================ |
architecture rtl of spi_master is |
architecture RTL of spi_master is |
-- core clocks, generated from 'sclk_i': initialized to differential values |
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic |
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic |
237,14 → 234,14
signal state_next : natural range N+1 downto 0 := 0; |
signal state_reg : natural range N+1 downto 0 := 0; |
-- shifter signals for register and combinatorial stages |
signal sh_next : std_logic_vector (N-1 downto 0); |
signal sh_reg : std_logic_vector (N-1 downto 0); |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinatorial stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinatorial stage |
signal wren : std_logic; |
signal wren : std_logic := '0'; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
-- internal SSEL enable control signals |
254,8 → 251,8
signal sck_ena_next : std_logic; |
signal sck_ena_reg : std_logic; |
-- buffered do_o data signals for register and combinatorial stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0); |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal signal to flag transfer to do_buffer_reg |
signal do_transfer_next : std_logic := '0'; |
signal do_transfer_reg : std_logic := '0'; |
312,7 → 309,7
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, |
-- based on the configuration of CPOL and CPHA. |
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI |
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew. |
-- modes, by a single high-speed global clock, preserving clock resources. |
----------------------------------------------------------------------------------------------- |
-- generate the 2x spi base clock enable from the serial high-speed input clock |
spi_2x_ce_gen_proc: process (sclk_i) is |
360,6 → 357,7
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
|
----------------------------------------------------------------------------------------------- |
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA |
-- always sample data at the half-cycle of the fsm update cell |
383,8 → 381,7
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
----------------------------------------------------------------------------------------------- |
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock |
|
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
|
--============================================================================================= |
391,6 → 388,10
-- REGISTERED INPUTS |
--============================================================================================= |
-- rx bit flop: capture rx bit after SAMPLE edge of sck |
-- |
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO |
-- REDUCED DEMAND ON MISO SETUP TIME. |
-- |
rx_bit_proc : process (sclk_i, spi_miso_i) is |
begin |
if sclk_i'event and sclk_i = '1' then |
449,7 → 450,7
end process in_transfer_proc; |
|
--============================================================================================= |
-- REGISTER TRANSFER PROCESSES |
-- RTL REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers: synchronous to the spi base reference clock |
core_reg_proc : process (sclk_i) is |
482,7 → 483,7
end process core_reg_proc; |
|
--============================================================================================= |
-- COMBINATORIAL LOGIC PROCESSES |
-- RTL combinatorial LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg, |
495,12 → 496,10
do_transfer_next <= do_transfer_reg; -- output data flag |
wr_ack_next <= wr_ack_reg; -- write acknowledge |
di_req_next <= di_req_reg; -- prefetch data request |
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference |
state_next <= state_reg; -- next state |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
case state_reg is |
when (N+1) => -- this state is to enable SSEL before SCK |
-- slave select |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL |
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
507,8 → 506,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N) => -- deassert 'di_rdy' |
-- stretch do_valid |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
515,8 → 512,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer' |
-- send bit out and shif bit in |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- reset transfer signal |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
524,8 → 519,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid' |
-- raise data prefetch request |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
532,8 → 525,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 1 => -- transfer rx data to do_buffer and restart if wren |
-- load next word or end transmission |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
549,17 → 540,15
state_next <= state_reg - 1; -- update next state at each sck pulse |
end if; |
when 0 => |
-- idle state: start and end of transmission |
di_req_next <= '1'; -- will request data if shifter empty |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
if wren = '1' then -- load tx register if valid data present at di_i |
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead) |
ssel_ena_next <= '1'; -- enable interface SSEL |
state_next <= N+1; -- start from idle: let one cycle for SSEL settling |
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead) |
sh_next <= di_reg; -- load bits from di_reg into shifter |
wr_ack_next <= '1'; -- acknowledge data in transfer |
else |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= 0; -- when idle, keep this state |
599,9 → 588,9
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
--============================================================================================= |
-- these signals are useful for verification, and can be deleted after debug. |
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; |
612,5 → 601,5
sck_ena_o_proc: sck_ena_o <= sck_ena_reg; |
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce; |
|
end architecture rtl; |
end architecture RTL; |
|