URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- from Rev 10 to Rev 9
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Rev 10 → Rev 9
/trunk/syn/ATLYS_02.SET
File deleted
\ No newline at end of file
/trunk/syn/spi_slave.vhd
File deleted
/trunk/syn/readme.txt
1,10 → 1,11
SPI_MASTER_ATLYS |
================ |
|
This is a ISE 13.1 project to test the spi_master.vhd, spi_slave.vhd and grp_debouncer.vhd models in silicon. |
This is a ISE 13.1 project to test the spi_master.vhd model in silicon. |
|
The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies. |
|
See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested. |
The circuit verifies both master and slave cores, with transmit and receive streams operating full-duplex at 50MHz of SPI clock. |
|
This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license. |
|
25,8 → 26,7
|
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
http://opencores.org/project,spi_master_slave,bugtracker |
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker. |
|
In any case, thank you very much for testing this core. |
|
/trunk/syn/spi_master.vhd
133,11 → 133,11
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock. |
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, |
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
-- > verify the receive interface in silicon, and determine the top usable frequency. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library ieee; |
146,8 → 146,6
use ieee.std_logic_unsigned.all; |
|
--================================================================================================================ |
-- SYNTHESIS CONSIDERATIONS |
-- ======================== |
-- There are several output ports that are used to simulate and verify the core operation. |
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing |
-- circuitry. |
195,7 → 193,7
-- this architecture is a pipelined register-transfer description. |
-- all signals are clocked at the rising edge of the system clock 'sclk_i'. |
--================================================================================================================ |
architecture RTL of spi_master is |
architecture rtl of spi_master is |
-- core clocks, generated from 'sclk_i': initialized to differential values |
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic |
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic |
377,13 → 375,13
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO |
-- REDUCED DEMAND ON MISO SETUP TIME. |
-- |
rx_bit_proc : process (sclk_i, spi_miso_i) is |
rx_bit_proc : process (sclk_i) is |
begin |
-- if sclk_i'event and sclk_i = '1' then |
-- if samp_ce = '1' then |
if sclk_i'event and sclk_i = '1' then |
if samp_ce = '1' then |
rx_bit_reg <= spi_miso_i; |
-- end if; |
-- end if; |
end if; |
end if; |
end process rx_bit_proc; |
|
--============================================================================================= |
564,5 → 562,5
core_ce_o_proc: core_ce_o <= core_ce; |
core_n_ce_o_proc: core_n_ce_o <= core_n_ce; |
|
end architecture RTL; |
end architecture rtl; |
|
/trunk/syn/grp_debouncer.vhd
3,7 → 3,7
-- |
-- Create Date: 09:56:30 07/06/2011 |
-- Module Name: grp_debouncer - RTL |
-- Project Name: basic functions |
-- Project Name: generic functions |
-- Target Devices: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: |
84,26 → 84,26
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- -------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/syn/spi_master_atlys_top_bit.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/syn/spi_master_atlys_top.vhd
8,15 → 8,13
-- Target Devices: Spartan-6 LX45 |
-- Tool versions: ISE 13.1 |
-- Description: |
-- This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores. |
-- This is a test project for the Atlys board, to test the spi_master and grp_debounce cores. |
-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock. |
-- |
-- See the "spi_master_atlys.ucf" file for pin assignments. |
-- See the "spi_master_atlys.ucf" file for pin assignments. |
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used |
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical |
-- digital pod port. |
-- The board switches are used to set the SPI_MASTER transmit data, and the SPI_SLAVE receive data drives the switch LEDs. |
-- The pushbuttons drive the slave transmit data, and the master received data drives the parallel debug port. |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
34,7 → 32,7
---------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_arith.all; |
|
entity spi_master_atlys_top is |
Port ( |
44,7 → 42,6
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
52,11 → 49,8
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
dbg_o : out std_logic_vector (7 downto 0); -- 10 generic debug pins |
dbg_o : out std_logic_vector (9 downto 0); -- 10 generic debug pins |
--- spi debug pins --- |
spi_rx_bit_m_o : out std_logic; -- master rx bit feedback |
spi_rx_bit_s_o : out std_logic; -- slave rx bit feedback |
spi_do_valid_o : out std_logic; -- spi data valid |
spi_di_req_o : out std_logic; -- spi data request |
spi_wren_o : out std_logic; -- spi write enable |
spi_wren_ack_o : out std_logic -- spi write enable ack |
70,9 → 64,9
--============================================================================================= |
-- clock divider count values from gclk_i (100MHz board clock) |
-- these constants shall not be zero |
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz |
constant FSM_CE_DIV : integer := 1; |
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock |
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
constant SAMP_CE_DIV : integer := 1; |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
|
88,133 → 82,86
-- Type definitions |
--============================================================================================= |
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch, |
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish ); |
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish ); |
|
--============================================================================================= |
-- Signals for state machine control |
--============================================================================================= |
signal state_reg : fsm_state_type := st_reset; |
signal state_next : fsm_state_type := st_reset; |
signal state_reg : fsm_state_type := st_reset; |
signal state_next : fsm_state_type := st_reset; |
|
--============================================================================================= |
-- Signals for internal operation |
--============================================================================================= |
--- clock enable signals --- |
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs |
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic |
--- switch debouncer signals --- |
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data |
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data |
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data |
signal new_switch : std_logic := '0'; -- detector for new switch data |
--- pushbutton debouncer signals --- |
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons |
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data |
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data |
signal new_button : std_logic := '0'; -- detector for new button data |
--- spi port signals --- |
-- spi bus wires |
signal spi_ssel : std_logic; |
signal spi_sck : std_logic; |
signal spi_mosi : std_logic; |
signal spi_miso : std_logic; |
-- spi master port control signals |
signal spi_rst_reg : std_logic := '1'; |
signal spi_rst_next : std_logic := '1'; |
signal spi_ssel_reg : std_logic; |
signal spi_wren_reg_m : std_logic := '0'; |
signal spi_wren_next_m : std_logic := '0'; |
-- spi master port flow control flags |
signal spi_di_req_m : std_logic; |
signal spi_do_valid_m : std_logic; |
-- spi master port parallel data bus |
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_do_m : std_logic_vector (N-1 downto 0); |
-- spi master port debug flags |
signal spi_rx_bit_m : std_logic; |
signal spi_wr_ack_m : std_logic; |
-- spi slave port control signals |
signal spi_wren_reg_s : std_logic := '1'; |
signal spi_wren_next_s : std_logic := '0'; |
-- spi slave port flow control flags |
signal spi_di_req_s : std_logic; |
signal spi_do_valid_s : std_logic; |
-- spi slave port parallel data bus |
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (7 => '1', 6 => '0', 5 => '1', others => '0'); |
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_do_s : std_logic_vector (N-1 downto 0); |
-- spi slave port debug flags |
signal spi_rx_bit_s : std_logic; |
signal spi_wr_ack_s : std_logic; |
-- clock signals |
signal core_clk : std_logic := '0'; -- core clock, direct copy of board clock |
signal spi_2x_clk : std_logic := '0'; -- spi_2x clock, 50% clock divided-down from board clock |
-- clock enable signals |
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs |
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic |
-- switch debouncer signals |
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data |
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data |
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data |
signal new_switch : std_logic := '0'; -- detector for new switch data |
-- pushbutton debouncer signals |
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons |
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data |
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data |
signal new_button : std_logic := '0'; -- detector for new button data |
-- spi port signals |
signal spi_ssel : std_logic; |
signal spi_sck : std_logic; |
signal spi_mosi : std_logic; |
signal spi_di_req : std_logic; |
signal spi_ssel_reg : std_logic; |
signal spi_wr_ack : std_logic; |
signal spi_rst_reg : std_logic := '1'; |
signal spi_rst_next : std_logic := '1'; |
signal spi_di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_di_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_wren_reg : std_logic := '0'; |
signal spi_wren_next : std_logic := '0'; |
-- other signals |
signal clear : std_logic := '0'; |
-- debug output signals |
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (7 downto 0) := (others => '0'); |
signal clear : std_logic := '0'; |
-- output signals |
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered led outputs |
signal dbg : std_logic_vector (9 downto 0) := (others => '0'); -- we have 10 debug pins available |
begin |
|
--============================================================================================= |
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST |
-- Component instantiation for the SPI port |
--============================================================================================= |
-- spi master port: |
-- receives parallel data from the slide switches, transmits to slave port. |
-- receives serial data from slave port, sends to 8bit parallel debug port. |
Inst_spi_master_port: entity work.spi_master(rtl) |
-- spi_port is the spi output port |
Inst_spi_port: entity work.spi_master(rtl) |
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV) |
port map( |
sclk_i => gclk_i, -- system clock is used for serial and parallel ports |
pclk_i => gclk_i, |
sclk_i => core_clk, -- system clock is used for serial and parallel ports |
pclk_i => core_clk, |
rst_i => spi_rst_reg, |
spi_ssel_o => spi_ssel, |
spi_sck_o => spi_sck, |
spi_mosi_o => spi_mosi, |
spi_miso_i => spi_miso, |
di_req_o => spi_di_req_m, |
di_i => spi_di_reg_m, |
do_valid_o => spi_do_valid_m, |
do_o => spi_do_m, |
rx_bit_reg_o => spi_rx_bit_m, |
wren_i => spi_wren_reg_m, |
di_req_o => spi_di_req, |
di_i => spi_di_reg, |
wren_i => spi_wren_reg, |
wren_o => spi_wren_o, |
wren_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port |
wren_ack_o => spi_wr_ack, -- monitor wren ack from inside spi port |
core_ce_o => dbg(8), -- monitor the internal core clock enable lines |
core_n_ce_o => dbg(9) |
); |
|
dbg(7 downto 0) <= spi_do_m(7 downto 0); -- connect master received data to 8bit debug port |
spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port |
|
-- spi slave port |
-- receives parallel data from the pushbuttons, transmits to master port. |
-- receives serial data from master port, sends to the 8 LEDs. |
Inst_spi_slave_port: entity work.spi_slave(rtl) |
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3) |
port map( |
clk_i => gclk_i, |
spi_ssel_i => spi_ssel, -- generated by the spi master |
spi_sck_i => spi_sck, -- generated by the spi master |
spi_mosi_i => spi_mosi, |
spi_miso_o => spi_miso, |
di_req_o => spi_di_req_s, |
di_i => spi_di_reg_s, |
wren_i => spi_wren_reg_s, |
rx_bit_reg_o => spi_rx_bit_s, |
do_valid_o => spi_do_valid_s, |
do_o => spi_do_s |
); |
|
spi_di_reg_s(7 downto 5) <= B"101"; -- get the slave transmit data from pushbuttons |
spi_di_reg_s(4 downto 0) <= btn_data(5 downto 1); |
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data |
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port |
|
spi_di_req_o <= spi_di_req; -- monitor data request |
spi_wren_ack_o <= spi_wr_ack; |
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 10000) -- debounce 8 inputs with 100 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
clk_i => core_clk, -- system clock |
data_i => sw_i, -- noisy input data |
data_o => sw_data -- registered stable output data |
-- strb_o => dbg(0) -- monitor the debounced data strobe |
data_o => sw_data, -- registered stable output data |
strb_o => dbg(0) -- monitor the debounced data strobe |
); |
|
-- debounce for the input pushbuttons, with new data strobe output |
221,26 → 168,31
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 50000) -- debounce 6 inputs with 500 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
clk_i => core_clk, -- system clock |
data_i => btn_i, -- noisy input data |
data_o => btn_data -- registered stable output data |
-- strb_o => dbg(3) -- monitor the debounced data strobe |
data_o => btn_data, -- registered stable output data |
strb_o => dbg(3) -- monitor the debounced data strobe |
); |
|
dbg1_proc: dbg(1) <= new_switch; -- monitor new_switch signal |
dbg2_proc: dbg(2) <= sw_i(0); -- monitor raw input (rightmost switch) |
dbg4_proc: dbg(4) <= new_button; -- monitor new_button signal |
dbg5_proc: dbg(5) <= btn_i(5); -- monitor raw input (center btn) |
|
--============================================================================================= |
-- CONSTANTS CONSTRAINTS CHECKING |
--============================================================================================= |
-- clock dividers shall not be zero |
assert FSM_CE_DIV > 0 |
report "Constant 'FSM_CE_DIV' should not be zero" |
assert FSM_CE_DIV > 0 |
report "Constant 'FSM_CE_DIV' should not be zero" |
severity FAILURE; |
-- minimum prefetch lookahead check |
assert SPI_2X_CLK_DIV > 0 |
report "Constant 'SPI_2X_CLK_DIV' should not be zero" |
assert SPI_2X_CLK_DIV > 0 |
report "Constant 'SPI_2X_CLK_DIV' should not be zero" |
severity FAILURE; |
-- maximum prefetch lookahead check |
assert SAMP_CE_DIV > 0 |
report "Constant 'SAMP_CE_DIV' should not be zero" |
assert SAMP_CE_DIV > 0 |
report "Constant 'SAMP_CE_DIV' should not be zero" |
severity FAILURE; |
|
--============================================================================================= |
251,6 → 203,8
-- spi 2x base clock, |
-- fsm clock, |
----------------------------------------------------------------------------------------------- |
-- generate the core clock from the 100MHz board input clock |
core_clock_gen_proc: core_clk <= gclk_i; |
-- generate the sampling clock enable from the 100MHz board input clock |
samp_ce_gen_proc: process (gclk_i) is |
variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0; |
279,29 → 233,44
end if; |
end if; |
end process fsm_ce_gen_proc; |
-- generate the spi base clock from the 100MHz board input clock |
-- spi_2x_clk_div_proc: spi_2x_clk <= gclk_i; -- generate 50MHz SPI SCK |
|
spi_2x_clk_div_proc: process (gclk_i) is |
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0:= 0; |
begin |
if gclk_i'event and gclk_i = '1' then |
if clk_cnt = SPI_2X_CLK_DIV-1 then |
spi_2x_clk <= not spi_2x_clk; |
clk_cnt := 0; |
else |
clk_cnt := clk_cnt + 1; |
end if; |
end if; |
end process spi_2x_clk_div_proc; |
|
--============================================================================================= |
-- INPUTS LOGIC |
--============================================================================================= |
-- registered inputs |
samp_inputs_proc: process (gclk_i) is |
samp_inputs_proc: process (core_clk) is |
begin |
if gclk_i'event and gclk_i = '1' then |
if core_clk'event and core_clk = '1' then |
if samp_ce = '1' then |
clear <= btn_data(btUP); -- clear is button UP |
leds_reg <= spi_do_s; -- update LEDs with spi_slave received data |
-- clear <= btn_data(btRESET); -- sample reset input |
leds_reg <= sw_data; -- update LEDs with debounced switches |
end if; |
end if; |
end process samp_inputs_proc; |
|
--============================================================================================= |
-- REGISTER TRANSFER PROCESSES |
-- FSM REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers: synchronous to the spi base reference clock |
fsm_reg_proc : process (gclk_i) is |
fsm_reg_proc : process (core_clk) is |
begin |
-- FFD registers clocked on rising edge and cleared on sync 'clear' |
if gclk_i'event and gclk_i = '1' then |
if core_clk'event and core_clk = '1' then |
if clear = '1' then -- sync reset |
state_reg <= st_reset; -- only provide local reset for the state register |
else |
311,12 → 280,10
end if; |
end if; |
-- FFD registers clocked on rising edge, with no reset |
if gclk_i'event and gclk_i = '1' then |
if core_clk'event and core_clk = '1' then |
if fsm_ce = '1' then |
spi_wren_reg_m <= spi_wren_next_m; |
spi_di_reg_m <= spi_di_next_m; |
-- spi_wren_reg_s <= spi_wren_next_s; |
-- spi_di_reg_s <= spi_di_next_s; |
spi_wren_reg <= spi_wren_next; |
spi_di_reg <= spi_di_next; |
spi_rst_reg <= spi_rst_next; |
spi_ssel_reg <= spi_ssel; |
sw_reg <= sw_next; |
326,23 → 293,21
end process fsm_reg_proc; |
|
--============================================================================================= |
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES |
-- FSM COMBINATORIAL NEXT-STATE LOGIC PROCESSES |
--============================================================================================= |
-- edge detector for new switch data |
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference |
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference |
-- edge detector for new button data |
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference |
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference |
-- fsm state and combinatorial logic |
-- the sequencer will wait for a new switch combination, and send the switch data to the spi port |
fsm_combi_proc: process ( state_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, -- spi_di_reg_s, |
spi_wren_reg_s, spi_ssel_reg, spi_rst_reg, sw_data, |
sw_reg, new_switch, btn_data, btn_reg, new_button) is |
fsm_combi_proc: process ( state_reg, spi_wren_reg, spi_di_reg, spi_di_req, spi_wr_ack, |
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, |
btn_data, btn_reg, new_button) is |
begin |
spi_di_next <= spi_di_reg; |
spi_rst_next <= spi_rst_reg; |
spi_di_next_m <= spi_di_reg_m; |
spi_wren_next_m <= spi_wren_reg_m; |
-- spi_di_next_s <= spi_di_reg_s; |
-- spi_wren_next_s <= spi_wren_reg_s; |
spi_wren_next <= spi_wren_reg; |
sw_next <= sw_reg; |
btn_next <= btn_reg; |
state_next <= state_reg; |
349,10 → 314,8
case state_reg is |
when st_reset => |
spi_rst_next <= '1'; -- place spi interface on reset |
spi_di_next_m <= (others => '0'); -- clear spi data port |
spi_di_next_s <= (others => '0'); -- clear spi data port |
spi_wren_next_m <= '0'; -- deassert write enable |
spi_wren_next_s <= '0'; -- deassert write enable |
spi_di_next <= (others => '0'); -- clear spi data port |
spi_wren_next <= '0'; -- deassert write enable |
state_next <= st_wait_spi_idle; |
|
when st_wait_spi_idle => |
367,20 → 330,20
state_next <= st_send_spi_data; |
elsif new_button = '1' then |
btn_next <= btn_data; -- load new button data (end the mismatch condition) |
if btn_data /= B"000001" then |
if btn_data /= (5 downto 0 => '0') then |
state_next <= st_send_spi_data; |
end if; |
end if; |
|
when st_send_spi_data => |
spi_di_next_m <= sw_reg; -- load switch register to the spi port |
spi_wren_next_m <= '1'; -- write data on next clock |
spi_di_next <= sw_reg; -- load switch register to the spi port |
spi_wren_next <= '1'; -- write data on next clock |
state_next <= st_wait_spi_ack; |
|
when st_wait_spi_ack => -- the actual write happens on this state |
spi_di_next_m <= sw_reg; -- load switch register to the spi port |
if spi_wr_ack_m = '1' then -- wait acknowledge |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
spi_di_next <= sw_reg; -- load switch register to the spi port |
if spi_wr_ack = '1' then -- wait acknowledge |
spi_wren_next <= '0'; -- remove write strobe on next clock |
state_next <= st_wait_spi_finish; |
end if; |
|
398,20 → 361,17
-- OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- connect the spi output wires |
spi_ssel_o_proc: spi_ssel_o <= spi_ssel; |
spi_sck_o_proc: spi_sck_o <= spi_sck; |
spi_mosi_o_proc: spi_mosi_o <= spi_mosi; |
spi_miso_o_proc: spi_miso_o <= spi_miso; |
spi_do_valid_o_proc: spi_do_valid_o <= spi_do_valid_m; |
spi_di_req_o_proc: spi_di_req_o <= spi_di_req_m; |
spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m; |
led_o_proc: led_o <= leds_reg; -- connect leds_reg signal to LED outputs |
spi_ssel_o_proc: spi_ssel_o <= spi_ssel; |
spi_sck_o_proc: spi_sck_o <= spi_sck; |
spi_mosi_o_proc: spi_mosi_o <= spi_mosi; |
-- connect leds_reg signal to LED outputs |
leds_out_proc: led_o <= leds_reg; |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
--============================================================================================= |
-- connect the debug vector outputs |
dbg_o_proc: dbg_o <= dbg; |
|
dbg_o_proc: dbg_o <= dbg; |
|
end behavioral; |
|
/trunk/syn/spi_master_atlys.xise
17,23 → 17,19
<files> |
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="grp_debouncer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="spi_master_atlys.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
</files> |
|
<properties> |
/trunk/syn/spi_master_scope_photos.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/syn/spi_master_atlys.ucf
219,8 → 219,8
# Channnel 1 connects to P signals, Channel 2 to N signals |
NET "spi_ssel_o" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P, MSO D15 |
NET "spi_mosi_o" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P, MSO D13 |
NET "spi_di_req_o" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11 |
NET "spi_rx_bit_s_o" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9 |
NET "spi_wren_o" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11 |
NET "dbg_o<9>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9 |
NET "dbg_o<7>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P, MSO D7 |
NET "dbg_o<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P, MSO D5 |
NET "dbg_o<3>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P, MSO D3 |
239,9 → 239,9
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P |
|
NET "spi_sck_o" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N, MSO D14 |
NET "spi_miso_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12 |
NET "spi_rx_bit_m_o" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10 |
NET "spi_do_valid_o" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8 |
NET "spi_di_req_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12 |
NET "spi_wren_ack_o" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10 |
NET "dbg_o<8>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8 |
NET "dbg_o<6>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N, MSO D6 |
NET "dbg_o<4>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N, MSO D4 |
NET "dbg_o<2>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N, MSO D2 |
/trunk/rtl/readme.txt
34,8 → 34,7
|
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
http://opencores.org/project,spi_master_slave,bugtracker. |
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker. |
|
|
In any case, thank you for testing and using this core. |
44,3 → 43,6
Jonny Doin |
jdoin@opencores.org |
|
|
|
|
/trunk/rtl/spi_master.vhd
133,11 → 133,11
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock. |
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, |
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
-- > verify the receive interface in silicon, and determine the top usable frequency. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library ieee; |
146,8 → 146,6
use ieee.std_logic_unsigned.all; |
|
--================================================================================================================ |
-- SYNTHESIS CONSIDERATIONS |
-- ======================== |
-- There are several output ports that are used to simulate and verify the core operation. |
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing |
-- circuitry. |
195,7 → 193,7
-- this architecture is a pipelined register-transfer description. |
-- all signals are clocked at the rising edge of the system clock 'sclk_i'. |
--================================================================================================================ |
architecture RTL of spi_master is |
architecture rtl of spi_master is |
-- core clocks, generated from 'sclk_i': initialized to differential values |
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic |
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic |
377,13 → 375,13
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO |
-- REDUCED DEMAND ON MISO SETUP TIME. |
-- |
rx_bit_proc : process (sclk_i, spi_miso_i) is |
rx_bit_proc : process (sclk_i) is |
begin |
-- if sclk_i'event and sclk_i = '1' then |
-- if samp_ce = '1' then |
if sclk_i'event and sclk_i = '1' then |
if samp_ce = '1' then |
rx_bit_reg <= spi_miso_i; |
-- end if; |
-- end if; |
end if; |
end if; |
end process rx_bit_proc; |
|
--============================================================================================= |
564,5 → 562,5
core_ce_o_proc: core_ce_o <= core_ce; |
core_n_ce_o_proc: core_n_ce_o <= core_n_ce; |
|
end architecture RTL; |
end architecture rtl; |
|
/trunk/rtl/spi_loopback.vhd
19,12 → 19,22
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
library work; |
use work.all; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--use IEEE.NUMERIC_STD.ALL; |
|
-- Uncomment the following library declaration if instantiating |
-- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
|
entity spi_loopback is |
Generic ( |
N : positive := 32; -- 32bit serial word length is default |
/trunk/rtl/spi_slave.vhd
12,8 → 12,6
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard. |
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'. |
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line. |
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two |
-- clock domains. |
-- |
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. |
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch |
106,8 → 104,6
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
126,7 → 122,7
N : positive := 32; -- 32bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 3); -- prefetch lookahead cycles |
PREFETCH : positive := 2); -- prefetch lookahead cycles |
Port ( |
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers) |
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line |
143,21 → 139,16
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
state_dbg_o : out std_logic_vector (5 downto 0) -- debug: internal state register |
-- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
end spi_slave; |
|
--================================================================================================================ |
-- SYNTHESIS CONSIDERATIONS |
-- ======================== |
-- There are several output ports that are used to simulate and verify the core operation. |
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing |
-- circuitry. |
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the |
-- synthesis tool will remove the receive logic from the generated circuitry. |
-- this architecture is a pipelined register-transfer description. |
-- the spi bus and core registers are synchronous to the 'spi_sck_i' clock. |
-- the parallel write/read interface is synchronous to the 'clk_i' clock. |
--================================================================================================================ |
|
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA); |
380,6 → 371,6
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
-- sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
end architecture RTL; |
|