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https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/spi_master_slave
- from Rev 12 to Rev 11
- ↔ Reverse comparison
Rev 12 → Rev 11
/trunk/rtl/spi_master.vhd
1,5 → 1,5
----------------------------------------------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author: Jonny Doin, jdoin@opencores.org |
-- |
-- Create Date: 12:18:12 04/25/2011 |
-- Module Name: SPI_MASTER - RTL |
124,7 → 124,7
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wren_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit. |
-- (minor bug) : removed fsm registers from (not rst_i) chip enable. |
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed). |
138,11 → 138,6
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end. |
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'. |
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz. |
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches. |
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz. |
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
184,14 → 179,12
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit) |
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit) |
--- debug ports: can be removed or left unconnected for the application circuit --- |
sck_ena_o : out std_logic; -- debug: internal sck enable signal |
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
core_clk_o : out std_logic; |
215,10 → 208,10
-- spi bus clock, generated from the CPOL selected core clock polarity |
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable |
signal spi_clk : std_logic := '0'; -- spi bus output clock |
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize) |
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck |
-- core fsm clock enables |
signal fsm_ce : std_logic := '1'; -- fsm clock enable |
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable |
signal ena_sck_ce : std_logic := '1'; -- SCK clock enable |
signal samp_ce : std_logic := '1'; -- data sampling clock enable |
-- |
-- GLOBAL RESET: |
242,14 → 235,14
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinatorial stage |
signal wren : std_logic := '0'; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
-- internal SSEL enable control signals |
signal ssel_ena_next : std_logic := '0'; |
signal ssel_ena_reg : std_logic := '0'; |
signal ena_ssel_next : std_logic := '0'; |
signal ena_ssel_reg : std_logic := '0'; |
-- internal SCK enable control signals |
signal sck_ena_next : std_logic; |
signal sck_ena_reg : std_logic; |
signal ena_sck_next : std_logic := '0'; |
signal ena_sck_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinatorial stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
343,46 → 336,45
end if; |
end if; |
end process core_clock_gen_proc; |
|
--============================================================================================= |
-- GENERATE BLOCKS |
--============================================================================================= |
----------------------------------------------------------------------------------------------- |
-- spi clk generator: generate spi_clk from core_clk depending on CPOL |
spi_sck_cpol_0_proc: if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
|
spi_sck_cpol_1_proc: if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
|
spi_sck_cpol_0_proc : |
if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
spi_sck_cpol_1_proc : |
if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
----------------------------------------------------------------------------------------------- |
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA |
-- always sample data at the half-cycle of the fsm update cell |
samp_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
|
samp_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
samp_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
samp_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
----------------------------------------------------------------------------------------------- |
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA |
fsm_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
|
fsm_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
fsm_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
fsm_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
|
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
ena_sck_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
|
--============================================================================================= |
-- REGISTERED INPUTS |
431,7 → 423,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is |
in_transfer_proc: process ( pclk_i, wren_i, wren_ack_reg ) is |
begin |
-- registered data input, input register with clock enable |
if pclk_i'event and pclk_i = '1' then |
443,7 → 435,7
if pclk_i'event and pclk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
467,19 → 459,20
if sclk_i'event and sclk_i = '1' then |
if fsm_ce = '1' then |
sh_reg <= sh_next; -- shift register |
ssel_ena_reg <= ssel_ena_next; -- spi select enable |
ena_ssel_reg <= ena_ssel_next; -- spi select enable |
ena_sck_reg <= ena_sck_next; -- spi clock enable |
do_buffer_reg <= do_buffer_next; -- registered output data buffer |
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer |
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end if; |
-- FF registers clocked one-half cycle earlier than the fsm state |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_ce = '1' then |
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic |
end if; |
end if; |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_ce = '1' then |
-- ena_sck_reg <= ena_sck_next; -- spi clock enable |
-- end if; |
-- end if; |
end process core_reg_proc; |
|
--============================================================================================= |
486,44 → 479,33
-- RTL combinatorial LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg, |
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren ) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line |
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line |
ena_ssel_next <= ena_ssel_reg; -- controls the slave select line |
ena_sck_next <= ena_sck_reg; -- controls the clock enable of spi sck line |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wr_ack_next <= wr_ack_reg; -- write acknowledge |
di_req_next <= di_req_reg; -- prefetch data request |
state_next <= state_reg; -- next state |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N+1) => -- this state is to enable SSEL before SCK |
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL |
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
ena_ssel_next <= '1'; -- tx in progress: will assert SSEL |
ena_sck_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
when (N) => -- deassert 'di_rdy' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- reset transfer signal |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid' |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 1 => -- transfer rx data to do_buffer and restart if wren |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
532,25 → 514,22
if wren = '1' then -- load tx register if valid data present at di_i |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
sck_ena_next <= '1'; -- SCK enabled |
wr_ack_next <= '1'; -- acknowledge data in transfer |
ena_sck_next <= '1'; -- SCK enabled |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
end if; |
when 0 => |
di_req_next <= '1'; -- will request data if shifter empty |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
if wren = '1' then -- load tx register if valid data present at di_i |
ssel_ena_next <= '1'; -- enable interface SSEL |
ena_ssel_next <= '1'; -- enable interface SSEL |
state_next <= N+1; -- start from idle: let one cycle for SSEL settling |
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead) |
sh_next <= di_reg; -- load bits from di_reg into shifter |
wr_ack_next <= '1'; -- acknowledge data in transfer |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
ena_ssel_next <= '0'; -- deassert SSEL: interface is idle |
state_next <= 0; -- when idle, keep this state |
end if; |
when others => |
562,25 → 541,30
-- OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line |
do_o_proc: do_o <= do_buffer_reg; -- parallel data out |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid |
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge |
spi_ssel_o_proc: spi_ssel_o <= not ena_ssel_reg; -- drive active-low slave select line |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
----------------------------------------------------------------------------------------------- |
-- SCK out logic: pipeline phase compensation for the SCK line |
----------------------------------------------------------------------------------------------- |
-- This is a MUX with an output register. |
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore |
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. |
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is |
-- This is a MUX with an output register. The register gives us a pipeline delay for the SCK line, |
-- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay. |
spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is |
begin |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_reg = '1' then |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_reg = '1' then |
-- spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
-- else |
-- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
-- end if; |
-- end if; |
if ena_sck_reg = '1' then |
if sclk_i'event and sclk_i = '1' then |
spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
spi_sck_o <= spi_clk_reg; -- connect register to output |
end process spi_sck_o_gen_proc; |
590,16 → 574,15
--============================================================================================= |
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
core_clk_o_proc: core_clk_o <= core_clk; |
core_n_clk_o_proc: core_n_clk_o <= core_n_clk; |
core_ce_o_proc: core_ce_o <= core_ce; |
core_n_ce_o_proc: core_n_ce_o <= core_n_ce; |
sck_ena_o_proc: sck_ena_o <= sck_ena_reg; |
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce; |
|
end architecture RTL; |
|
/trunk/rtl/spi_slave.vhd
105,16 → 105,9
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs: |
-- - redesigned core clocking to address all CPOL and CPHA configurations. |
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite |
-- clock phases from SHIFT_EDGE. |
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
143,13 → 136,13
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) |
wren_i : in std_logic := 'X'; -- user data write enable |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) |
--- debug ports: can be removed for the application circuit --- |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
rx_bit_next_o : out std_logic; -- debug: internal rx bit |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
167,10 → 160,10
|
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge |
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge |
|
------------------------------------------------------------------------------------------ |
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA); |
constant SAMPLE_LEVEL : std_logic := SAMPLE_EDGE; |
constant SHIFT_EDGE : std_logic := (CPOL xor CPHA); |
-- |
-- GLOBAL RESET: |
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit |
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and |
179,23 → 172,21
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
------------------------------------------------------------------------------------------ |
-- |
-- internal state signals for register and combinational stages |
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_next : natural range N+1 downto 0 := 0; |
signal state_reg : natural range N+1 downto 0 := 0; |
-- shifter signals for register and combinational stages |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- mosi and miso connections |
signal rx_bit_next : std_logic := '0'; |
signal tx_bit_next : std_logic := '0'; |
signal tx_bit_reg : std_logic := '0'; |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinational stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinational stage |
signal wren : std_logic; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
signal wren : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
203,8 → 194,7
signal do_transfer_next : std_logic := '0'; |
signal do_transfer_reg : std_logic := '0'; |
-- internal input data request signal |
signal di_req_next : std_logic := '0'; |
signal di_req_reg : std_logic := '0'; |
signal di_req : std_logic := '0'; |
-- cross-clock do_valid_o logic |
signal do_valid_next : std_logic := '0'; |
signal do_valid_A : std_logic := '0'; |
233,14 → 223,36
severity FAILURE; |
|
--============================================================================================= |
-- GENERATE BLOCKS |
-- REGISTERED INPUTS |
--============================================================================================= |
-- rx bit flop: capture rx bit after SAMPLE edge of sck |
rx_bit_proc : process (spi_sck_i, spi_mosi_i) is |
begin |
if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then |
rx_bit_reg <= spi_mosi_i; |
end if; |
end process rx_bit_proc; |
|
--============================================================================================= |
-- DATA INPUTS |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- connect rx bit input |
rx_bit_proc : rx_bit_next <= spi_mosi_i; |
-- fsm state and data registers change on spi SHIFT clock |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC |
248,7 → 260,7
-- do_valid_o and di_req_o strobe output logic |
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a |
-- fixed-length delayed pulse for the output flags, at the parallel clock domain |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg, |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req, |
do_valid_A, do_valid_B, do_valid_D, |
di_req_o_A, di_req_o_B, di_req_o_D) is |
begin |
260,8 → 272,8
do_valid_D <= do_valid_C; |
do_valid_o_reg <= do_valid_next; -- registered output pulse |
-------------------------------- |
-- di_req_reg -> di_req_o_reg |
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long |
-- di_req -> di_req_o_reg |
di_req_o_A <= di_req; -- the input signal must be at least 2 clocks long |
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs |
di_req_o_C <= di_req_o_B; |
di_req_o_D <= di_req_o_C; |
272,7 → 284,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is |
in_transfer_proc: process (clk_i, wren_i, wren_ack_reg) is |
begin |
-- registered data input, input register with clock enable |
if clk_i'event and clk_i = '1' then |
284,7 → 296,7
if clk_i'event and clk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
291,115 → 303,63
end process in_transfer_proc; |
|
--============================================================================================= |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers change on spi SHIFT_EDGE |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization |
end if; |
-- FFD registers clocked on CHANGE edge |
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then |
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinational logic |
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, |
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren, wren_ack_reg) is |
begin |
-- all output signals are assigned to (avoid latches) |
sh_next <= sh_reg; -- shift register |
tx_bit_next <= tx_bit_reg; -- MISO driver |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wr_ack_next <= wr_ack_reg; -- write enable acknowledge |
di_req_next <= di_req_reg; -- data input request |
state_next <= state_reg; -- fsm control state |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req <= '0'; -- prefetch data request: deassert when shifting data |
spi_miso_o <= sh_reg(N-1); -- output serial data from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N) => |
-- acknowledge write enable |
wr_ack_next <= '1'; -- acknowledge data in transfer |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (N-1) downto (PREFETCH+3) => |
-- send bit out and shif bit in |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 3 => |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (PREFETCH+2) downto 2 => |
-- raise data prefetch request |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 2 => |
-- transfer parallel data on next state |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle |
do_buffer_next <= sh_next; -- get next data directly into rx buffer |
state_next <= state_reg - 1; -- update next state at each sck pulse |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when 1 => |
-- restart from state 'N' if more sck pulses come |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
do_transfer_next <= '1'; -- signal transfer to do_buffer |
state_next <= N; -- next state is top bit of new data |
if wren = '1' then -- load tx register if valid data present at di_reg |
wr_ack_next <= '1'; -- acknowledge data in transfer |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
sh_next <= (others => '0'); -- load null data (output '0' if no load) |
state_next <= 0; -- next state is idle state |
end if; |
when 0 => |
-- idle state: start and end of transmission |
if CPHA = '1' then |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
di_req <= not wren_ack_reg; -- will request data if shifter empty |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
spi_miso_o <= di_reg(N-1); -- shift out first tx bit from the MSb |
if CPHA = '0' then |
-- initial state for CPHA=0, when slave interface is first selected or idle |
state_next <= N-1; -- next state is top bit of new data |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= not wr_ack_reg; -- will request data if shifter empty |
-- initial state for CPHA=1, when slave interface is first selected or idle |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
end if; |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
state_next <= N; -- next state is top bit of new data |
end if; |
when others => |
state_next <= 0; -- safe state |
state_next <= 0; -- state 0 is safe state |
end case; |
end process core_combi_proc; |
|
407,11 → 367,9
-- RTL OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
419,8 → 377,9
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
end architecture RTL; |
|
/trunk/syn/ATLYS_03.SET
File deleted
\ No newline at end of file
/trunk/syn/spi_master_atlys_test.vhd
File deleted
/trunk/syn/spi_master_envsettings.html
18,7 → 18,7
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>< data not available ></font></td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
</tr> |
<tr> |
<td>Path</td> |
25,7 → 25,7
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
</tr> |
<tr> |
<td>XILINX</td> |
32,7 → 32,7
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
39,7 → 39,7
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
46,7 → 46,7
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
53,7 → 53,7
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
482,6 → 482,48
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td> </td> |
<td>n</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td> </td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>4</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>std</td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
499,7 → 541,7
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
</tr> |
<tr> |
<td>Host</td> |
506,7 → 548,7
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Develop-W7</td> |
</tr> |
<tr> |
<td>OS Name</td> |
513,7 → 555,7
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Microsoft Windows 7 , 32-bit</td> |
</tr> |
<tr> |
<td>OS Release</td> |
520,7 → 562,7
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Service Pack 1 (build 7601)</td> |
</tr> |
</TABLE> |
</BODY> </HTML> |
/trunk/syn/spi_master_atlys_top_bit.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/syn/spi_master_atlys_top.vhd
1,5 → 1,5
---------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Engineer: Jonny Doin |
-- |
-- Create Date: 01:21:32 06/30/2011 |
-- Design Name: |
27,7 → 27,7
-- external monitoring pins to the VHDCI ports. |
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, |
-- 6.25MHz, 1MHz and 500kHz |
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug. |
-- 2011/07/18 v1.12.0105 [JD] spi_master.vhd changed to fix CPHA='1' clock glitch. |
-- |
-- |
---------------------------------------------------------------------------------- |
37,20 → 37,27
|
entity spi_master_atlys_top is |
Port ( |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
--- SPI interface --- |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
--- SPI interface --- |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
dbg_o : out std_logic_vector (7 downto 0); -- 10 generic debug pins |
--- spi debug pins --- |
spi_rx_bit_m_o : out std_logic; -- master rx bit feedback |
spi_rx_bit_s_o : out std_logic; -- slave rx bit feedback |
spi_do_valid_o : out std_logic; -- spi data valid |
spi_di_req_o : out std_logic -- spi data request |
-- spi_wren_o : out std_logic; -- spi write enable |
-- spi_wren_ack_o : out std_logic -- spi write enable ack |
); |
end spi_master_atlys_top; |
|
66,8 → 73,8
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
constant CPOL : std_logic := '1'; |
constant CPHA : std_logic := '1'; |
constant CPOL : std_logic := '0'; |
constant CPHA : std_logic := '0'; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
81,7 → 88,7
-- Type definitions |
--============================================================================================= |
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch, |
st_send_spi_data, st_wait_spi_ack ); |
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish ); |
|
--============================================================================================= |
-- Signals for state machine control |
127,26 → 134,24
-- spi master port debug flags |
signal spi_rx_bit_m : std_logic; |
signal spi_wr_ack_m : std_logic; |
signal state_dbg_m : std_logic_vector (5 downto 0); |
-- spi slave port control signals |
signal spi_wren_reg_s : std_logic := '1'; |
signal spi_wren_next_s : std_logic := '1'; |
signal spi_wren_next_s : std_logic := '0'; |
-- spi slave port flow control flags |
signal spi_di_req_s : std_logic; |
signal spi_do_valid_s : std_logic; |
-- spi slave port parallel data bus |
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (7 => '1', 6 => '0', 5 => '1', others => '0'); |
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_do_s : std_logic_vector (N-1 downto 0); |
-- spi slave port debug flags |
signal spi_rx_bit_s : std_logic; |
signal spi_wr_ack_s : std_logic; |
signal state_dbg_s : std_logic_vector (5 downto 0); |
-- other signals |
signal clear : std_logic := '0'; |
-- debug output signals |
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (11 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (7 downto 0) := (others => '0'); |
begin |
|
--============================================================================================= |
167,20 → 172,16
spi_miso_i => spi_miso, |
di_req_o => spi_di_req_m, |
di_i => spi_di_reg_m, |
wren_i => spi_wren_reg_m, |
do_valid_o => spi_do_valid_m, |
do_o => spi_do_m, |
------------ debug pins ------------ |
-- rx_bit_reg_o => spi_rx_bit_m, |
-- state_dbg_o => state_dbg_m, -- monitor internal master state register |
-- sck_ena_o => sck_ena_m, -- monitor internal sck_ena register |
rx_bit_reg_o => spi_rx_bit_m, |
wren_i => spi_wren_reg_m, |
-- wren_o => spi_wren_o, |
wr_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port |
wren_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port |
); |
|
-- state_dbg_o(3 downto 0) <= state_dbg_m(3 downto 0); -- connect master state debug port |
-- sck_ena_o <= sck_ena_m; -- sck_ena debug port |
-- spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port |
dbg(7 downto 0) <= spi_do_m(7 downto 0); -- connect master received data to 8bit debug port |
spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port |
|
-- spi slave port |
-- receives parallel data from the pushbuttons, transmits to master port. |
196,48 → 197,37
di_req_o => spi_di_req_s, |
di_i => spi_di_reg_s, |
wren_i => spi_wren_reg_s, |
rx_bit_reg_o => spi_rx_bit_s, |
do_valid_o => spi_do_valid_s, |
do_o => spi_do_s, |
------------ debug pins ------------ |
state_dbg_o => state_dbg_s, -- monitor internal state register |
rx_bit_next_o => spi_rx_bit_s, |
wr_ack_o => dbg(5), |
do_transfer_o => dbg(4) |
do_o => spi_do_s |
); |
|
-- connect debug port pins to slave instance interface signals |
dbg(7) <= spi_rx_bit_s; |
dbg(6) <= spi_wren_reg_s; |
dbg(3) <= spi_do_valid_s; |
dbg(2) <= spi_di_req_s; |
dbg(1) <= '0'; |
dbg(0) <= '0'; |
|
dbg(11 downto 8) <= state_dbg_s(3 downto 0);-- connect state register |
|
spi_di_reg_s(7) <= btn_data(btLEFT); -- get the slave transmit data from pushbuttons |
spi_di_reg_s(6) <= btn_data(btCENTER); |
spi_di_reg_s(5 downto 1) <= B"10101"; |
spi_di_reg_s(0) <= btn_data(btRIGHT); |
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data |
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port |
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time |
generic map (N => 8, CNT_VAL => 10000) -- debounce 8 inputs with 100 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => sw_i, -- noisy input data |
data_o => sw_data -- registered stable output data |
); |
-- strb_o => dbg(0) -- monitor the debounced data strobe |
); |
|
-- debounce for the input pushbuttons, with new data strobe output |
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 20000) -- debounce 6 inputs with 200 us settling time |
generic map (N => 6, CNT_VAL => 50000) -- debounce 6 inputs with 500 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => btn_i, -- noisy input data |
data_o => btn_data -- registered stable output data |
); |
-- strb_o => dbg(3) -- monitor the debounced data strobe |
); |
|
--============================================================================================= |
-- CONSTANTS CONSTRAINTS CHECKING |
327,6 → 317,8
if fsm_ce = '1' then |
spi_wren_reg_m <= spi_wren_next_m; |
spi_di_reg_m <= spi_di_next_m; |
-- spi_wren_reg_s <= spi_wren_next_s; |
-- spi_di_reg_s <= spi_di_next_s; |
spi_rst_reg <= spi_rst_next; |
spi_ssel_reg <= spi_ssel; |
sw_reg <= sw_next; |
351,6 → 343,8
spi_rst_next <= spi_rst_reg; |
spi_di_next_m <= spi_di_reg_m; |
spi_wren_next_m <= spi_wren_reg_m; |
-- spi_di_next_s <= spi_di_reg_s; |
-- spi_wren_next_s <= spi_wren_reg_s; |
sw_next <= sw_reg; |
btn_next <= btn_reg; |
state_next <= state_reg; |
364,7 → 358,6
state_next <= st_wait_spi_idle; |
|
when st_wait_spi_idle => |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
if spi_ssel_reg = '1' then |
spi_rst_next <= '0'; -- remove reset when interface is idle |
state_next <= st_wait_new_switch; |
388,9 → 381,16
|
when st_wait_spi_ack => -- the actual write happens on this state |
spi_di_next_m <= sw_reg; -- load switch register to the spi port |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
state_next <= st_wait_spi_idle; |
if spi_wr_ack_m = '1' then -- wait acknowledge |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
state_next <= st_wait_spi_finish; |
end if; |
|
when st_wait_spi_finish => |
if spi_ssel_reg = '1' then |
state_next <= st_wait_new_switch; |
end if; |
|
when others => |
state_next <= st_reset; -- state st_reset is safe state |
end case; |
404,8 → 404,10
spi_sck_o_proc: spi_sck_o <= spi_sck; |
spi_mosi_o_proc: spi_mosi_o <= spi_mosi; |
spi_miso_o_proc: spi_miso_o <= spi_miso; |
-- connect leds_reg signal to LED outputs |
led_o_proc: led_o <= leds_reg; |
spi_do_valid_o_proc: spi_do_valid_o <= spi_do_valid_m; |
spi_di_req_o_proc: spi_di_req_o <= spi_di_req_m; |
-- spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m; |
led_o_proc: led_o <= leds_reg; -- connect leds_reg signal to LED outputs |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
/trunk/syn/spi_master.vhd
1,5 → 1,5
----------------------------------------------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author: Jonny Doin, jdoin@opencores.org |
-- |
-- Create Date: 12:18:12 04/25/2011 |
-- Module Name: SPI_MASTER - RTL |
124,7 → 124,7
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wren_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit. |
-- (minor bug) : removed fsm registers from (not rst_i) chip enable. |
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed). |
138,11 → 138,6
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end. |
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'. |
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz. |
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches. |
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz. |
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
184,14 → 179,12
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit) |
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit) |
--- debug ports: can be removed or left unconnected for the application circuit --- |
sck_ena_o : out std_logic; -- debug: internal sck enable signal |
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
core_clk_o : out std_logic; |
215,10 → 208,10
-- spi bus clock, generated from the CPOL selected core clock polarity |
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable |
signal spi_clk : std_logic := '0'; -- spi bus output clock |
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize) |
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck |
-- core fsm clock enables |
signal fsm_ce : std_logic := '1'; -- fsm clock enable |
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable |
signal ena_sck_ce : std_logic := '1'; -- SCK clock enable |
signal samp_ce : std_logic := '1'; -- data sampling clock enable |
-- |
-- GLOBAL RESET: |
242,14 → 235,14
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinatorial stage |
signal wren : std_logic := '0'; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
-- internal SSEL enable control signals |
signal ssel_ena_next : std_logic := '0'; |
signal ssel_ena_reg : std_logic := '0'; |
signal ena_ssel_next : std_logic := '0'; |
signal ena_ssel_reg : std_logic := '0'; |
-- internal SCK enable control signals |
signal sck_ena_next : std_logic; |
signal sck_ena_reg : std_logic; |
signal ena_sck_next : std_logic := '0'; |
signal ena_sck_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinatorial stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
343,46 → 336,45
end if; |
end if; |
end process core_clock_gen_proc; |
|
--============================================================================================= |
-- GENERATE BLOCKS |
--============================================================================================= |
----------------------------------------------------------------------------------------------- |
-- spi clk generator: generate spi_clk from core_clk depending on CPOL |
spi_sck_cpol_0_proc: if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
|
spi_sck_cpol_1_proc: if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
|
spi_sck_cpol_0_proc : |
if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
spi_sck_cpol_1_proc : |
if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
----------------------------------------------------------------------------------------------- |
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA |
-- always sample data at the half-cycle of the fsm update cell |
samp_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
|
samp_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
samp_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
samp_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
----------------------------------------------------------------------------------------------- |
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA |
fsm_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
|
fsm_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
fsm_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
fsm_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
|
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
ena_sck_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
|
--============================================================================================= |
-- REGISTERED INPUTS |
431,7 → 423,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is |
in_transfer_proc: process ( pclk_i, wren_i, wren_ack_reg ) is |
begin |
-- registered data input, input register with clock enable |
if pclk_i'event and pclk_i = '1' then |
443,7 → 435,7
if pclk_i'event and pclk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
467,19 → 459,20
if sclk_i'event and sclk_i = '1' then |
if fsm_ce = '1' then |
sh_reg <= sh_next; -- shift register |
ssel_ena_reg <= ssel_ena_next; -- spi select enable |
ena_ssel_reg <= ena_ssel_next; -- spi select enable |
ena_sck_reg <= ena_sck_next; -- spi clock enable |
do_buffer_reg <= do_buffer_next; -- registered output data buffer |
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer |
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end if; |
-- FF registers clocked one-half cycle earlier than the fsm state |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_ce = '1' then |
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic |
end if; |
end if; |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_ce = '1' then |
-- ena_sck_reg <= ena_sck_next; -- spi clock enable |
-- end if; |
-- end if; |
end process core_reg_proc; |
|
--============================================================================================= |
486,44 → 479,33
-- RTL combinatorial LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg, |
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren ) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line |
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line |
ena_ssel_next <= ena_ssel_reg; -- controls the slave select line |
ena_sck_next <= ena_sck_reg; -- controls the clock enable of spi sck line |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wr_ack_next <= wr_ack_reg; -- write acknowledge |
di_req_next <= di_req_reg; -- prefetch data request |
state_next <= state_reg; -- next state |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N+1) => -- this state is to enable SSEL before SCK |
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL |
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
ena_ssel_next <= '1'; -- tx in progress: will assert SSEL |
ena_sck_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
when (N) => -- deassert 'di_rdy' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- reset transfer signal |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid' |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 1 => -- transfer rx data to do_buffer and restart if wren |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
532,25 → 514,22
if wren = '1' then -- load tx register if valid data present at di_i |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
sck_ena_next <= '1'; -- SCK enabled |
wr_ack_next <= '1'; -- acknowledge data in transfer |
ena_sck_next <= '1'; -- SCK enabled |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
end if; |
when 0 => |
di_req_next <= '1'; -- will request data if shifter empty |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
if wren = '1' then -- load tx register if valid data present at di_i |
ssel_ena_next <= '1'; -- enable interface SSEL |
ena_ssel_next <= '1'; -- enable interface SSEL |
state_next <= N+1; -- start from idle: let one cycle for SSEL settling |
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead) |
sh_next <= di_reg; -- load bits from di_reg into shifter |
wr_ack_next <= '1'; -- acknowledge data in transfer |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
ena_ssel_next <= '0'; -- deassert SSEL: interface is idle |
state_next <= 0; -- when idle, keep this state |
end if; |
when others => |
562,25 → 541,30
-- OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line |
do_o_proc: do_o <= do_buffer_reg; -- parallel data out |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid |
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge |
spi_ssel_o_proc: spi_ssel_o <= not ena_ssel_reg; -- drive active-low slave select line |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
----------------------------------------------------------------------------------------------- |
-- SCK out logic: pipeline phase compensation for the SCK line |
----------------------------------------------------------------------------------------------- |
-- This is a MUX with an output register. |
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore |
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. |
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is |
-- This is a MUX with an output register. The register gives us a pipeline delay for the SCK line, |
-- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay. |
spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is |
begin |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_reg = '1' then |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_reg = '1' then |
-- spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
-- else |
-- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
-- end if; |
-- end if; |
if ena_sck_reg = '1' then |
if sclk_i'event and sclk_i = '1' then |
spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
spi_sck_o <= spi_clk_reg; -- connect register to output |
end process spi_sck_o_gen_proc; |
590,16 → 574,15
--============================================================================================= |
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
core_clk_o_proc: core_clk_o <= core_clk; |
core_n_clk_o_proc: core_n_clk_o <= core_n_clk; |
core_ce_o_proc: core_ce_o <= core_ce; |
core_n_ce_o_proc: core_n_ce_o <= core_n_ce; |
sck_ena_o_proc: sck_ena_o <= sck_ena_reg; |
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce; |
|
end architecture RTL; |
|
/trunk/syn/spi_master_scope_photos.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/syn/spi_slave.vhd
105,16 → 105,9
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs: |
-- - redesigned core clocking to address all CPOL and CPHA configurations. |
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite |
-- clock phases from SHIFT_EDGE. |
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
143,13 → 136,13
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) |
wren_i : in std_logic := 'X'; -- user data write enable |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) |
--- debug ports: can be removed for the application circuit --- |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
rx_bit_next_o : out std_logic; -- debug: internal rx bit |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
167,10 → 160,10
|
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge |
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge |
|
------------------------------------------------------------------------------------------ |
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA); |
constant SAMPLE_LEVEL : std_logic := SAMPLE_EDGE; |
constant SHIFT_EDGE : std_logic := (CPOL xor CPHA); |
-- |
-- GLOBAL RESET: |
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit |
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and |
179,23 → 172,21
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
------------------------------------------------------------------------------------------ |
-- |
-- internal state signals for register and combinational stages |
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_next : natural range N+1 downto 0 := 0; |
signal state_reg : natural range N+1 downto 0 := 0; |
-- shifter signals for register and combinational stages |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- mosi and miso connections |
signal rx_bit_next : std_logic := '0'; |
signal tx_bit_next : std_logic := '0'; |
signal tx_bit_reg : std_logic := '0'; |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinational stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinational stage |
signal wren : std_logic; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
signal wren : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
203,8 → 194,7
signal do_transfer_next : std_logic := '0'; |
signal do_transfer_reg : std_logic := '0'; |
-- internal input data request signal |
signal di_req_next : std_logic := '0'; |
signal di_req_reg : std_logic := '0'; |
signal di_req : std_logic := '0'; |
-- cross-clock do_valid_o logic |
signal do_valid_next : std_logic := '0'; |
signal do_valid_A : std_logic := '0'; |
233,14 → 223,36
severity FAILURE; |
|
--============================================================================================= |
-- GENERATE BLOCKS |
-- REGISTERED INPUTS |
--============================================================================================= |
-- rx bit flop: capture rx bit after SAMPLE edge of sck |
rx_bit_proc : process (spi_sck_i, spi_mosi_i) is |
begin |
if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then |
rx_bit_reg <= spi_mosi_i; |
end if; |
end process rx_bit_proc; |
|
--============================================================================================= |
-- DATA INPUTS |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- connect rx bit input |
rx_bit_proc : rx_bit_next <= spi_mosi_i; |
-- fsm state and data registers change on spi SHIFT clock |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC |
248,7 → 260,7
-- do_valid_o and di_req_o strobe output logic |
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a |
-- fixed-length delayed pulse for the output flags, at the parallel clock domain |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg, |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req, |
do_valid_A, do_valid_B, do_valid_D, |
di_req_o_A, di_req_o_B, di_req_o_D) is |
begin |
260,8 → 272,8
do_valid_D <= do_valid_C; |
do_valid_o_reg <= do_valid_next; -- registered output pulse |
-------------------------------- |
-- di_req_reg -> di_req_o_reg |
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long |
-- di_req -> di_req_o_reg |
di_req_o_A <= di_req; -- the input signal must be at least 2 clocks long |
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs |
di_req_o_C <= di_req_o_B; |
di_req_o_D <= di_req_o_C; |
272,7 → 284,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is |
in_transfer_proc: process (clk_i, wren_i, wren_ack_reg) is |
begin |
-- registered data input, input register with clock enable |
if clk_i'event and clk_i = '1' then |
284,7 → 296,7
if clk_i'event and clk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
291,115 → 303,63
end process in_transfer_proc; |
|
--============================================================================================= |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers change on spi SHIFT_EDGE |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization |
end if; |
-- FFD registers clocked on CHANGE edge |
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then |
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinational logic |
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, |
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren, wren_ack_reg) is |
begin |
-- all output signals are assigned to (avoid latches) |
sh_next <= sh_reg; -- shift register |
tx_bit_next <= tx_bit_reg; -- MISO driver |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wr_ack_next <= wr_ack_reg; -- write enable acknowledge |
di_req_next <= di_req_reg; -- data input request |
state_next <= state_reg; -- fsm control state |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req <= '0'; -- prefetch data request: deassert when shifting data |
spi_miso_o <= sh_reg(N-1); -- output serial data from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N) => |
-- acknowledge write enable |
wr_ack_next <= '1'; -- acknowledge data in transfer |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (N-1) downto (PREFETCH+3) => |
-- send bit out and shif bit in |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 3 => |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (PREFETCH+2) downto 2 => |
-- raise data prefetch request |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 2 => |
-- transfer parallel data on next state |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle |
do_buffer_next <= sh_next; -- get next data directly into rx buffer |
state_next <= state_reg - 1; -- update next state at each sck pulse |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when 1 => |
-- restart from state 'N' if more sck pulses come |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
do_transfer_next <= '1'; -- signal transfer to do_buffer |
state_next <= N; -- next state is top bit of new data |
if wren = '1' then -- load tx register if valid data present at di_reg |
wr_ack_next <= '1'; -- acknowledge data in transfer |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
sh_next <= (others => '0'); -- load null data (output '0' if no load) |
state_next <= 0; -- next state is idle state |
end if; |
when 0 => |
-- idle state: start and end of transmission |
if CPHA = '1' then |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
di_req <= not wren_ack_reg; -- will request data if shifter empty |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
spi_miso_o <= di_reg(N-1); -- shift out first tx bit from the MSb |
if CPHA = '0' then |
-- initial state for CPHA=0, when slave interface is first selected or idle |
state_next <= N-1; -- next state is top bit of new data |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= not wr_ack_reg; -- will request data if shifter empty |
-- initial state for CPHA=1, when slave interface is first selected or idle |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
end if; |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
state_next <= N; -- next state is top bit of new data |
end if; |
when others => |
state_next <= 0; -- safe state |
state_next <= 0; -- state 0 is safe state |
end case; |
end process core_combi_proc; |
|
407,11 → 367,9
-- RTL OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
419,8 → 377,9
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
end architecture RTL; |
|
/trunk/syn/spi_master_atlys.xise
16,12 → 16,15
|
<files> |
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="grp_debouncer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="spi_master_atlys.ucf" xil_pn:type="FILE_UCF"> |
28,14 → 31,9
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="spi_master_atlys_test.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> |
</file> |
</files> |
|
<properties> |
95,7 → 93,6
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
129,7 → 126,7
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
143,9 → 140,8
<property xil_pn:name="Global Optimization map" xil_pn:value="Area" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_master_atlys_top|behavioral" xil_pn:valueState="non-default"/> |
275,12 → 271,11
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
289,15 → 284,15
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="12000 ns" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="12 us" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
345,15 → 340,15
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="spi_master_atlys" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-07T09:55:20" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C5BE631B69F48AB8C2F24035AF7A13B" xil_pn:valueState="non-default"/> |
/trunk/syn/readme.txt
12,17 → 12,13
------------- |
|
spi_master.vhd vhdl model for the spi_master interface |
spi_slave.vhd vhdl model for the spi_slave interface |
grp_debouncer.vhd vhdl model for the switch debouncer |
spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board |
spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd' |
spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys |
spi_master_atlys.xise ISE 13.1 project file |
spi_master_atlys.ucf pin lock constraints for the Atlys board |
spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests |
spi_master_envsettings.html synthesis env settings, with the tools setup used |
ATLYS_01.SET Tek MSO2014 settings files with the debug pin names |
ATLYS_02.SET |
ATLYS_03.SET |
ATLYS_01.SET Tek MSO2014 settings file with the debug pin names |
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board |
|
|
/trunk/syn/grp_debouncer.vhd
1,5 → 1,5
----------------------------------------------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author: Jonny Doin, jdoin@opencores.org |
-- |
-- Create Date: 09:56:30 07/06/2011 |
-- Module Name: grp_debouncer - RTL |
80,13 → 80,12
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
115,7 → 114,6
-- TODO |
-- ==== |
-- |
-- The circuit can easily be extended to have a signature of which inputs changed at the data out port. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library ieee; |
/trunk/syn/spi_master_atlys.ucf
216,41 → 216,36
# NET "dbg_o<4>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P |
|
# onboard VHDCI |
# Channnel 1 connects to P signals, Channel 2 to N signals |
|
# 16bit debug outputs for MSO2014 digital signals, in 2 pod connectors |
# D15-D8 connector pod |
NET "spi_ssel_o" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P, MSO D15 |
NET "spi_sck_o" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N, MSO D14 |
NET "spi_mosi_o" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P, MSO D13 |
NET "spi_miso_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12 |
NET "dbg_o<11>" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11 |
NET "dbg_o<10>" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10 |
NET "dbg_o<9>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9 |
NET "dbg_o<8>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8 |
# D7-D0 connector pod |
NET "dbg_o<7>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P, MSO D7 |
NET "dbg_o<6>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N, MSO D6 |
NET "dbg_o<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P, MSO D5 |
NET "dbg_o<4>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N, MSO D4 |
NET "dbg_o<3>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P, MSO D3 |
NET "dbg_o<2>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N, MSO D2 |
NET "dbg_o<1>" LOC = "M10"; # Bank = 2, Pin name = *IO_L22P, Sch name = EXP-IO8_P, MSO D1 |
NET "dbg_o<0>" LOC = "N9"; # Bank = 2, Pin name = *IO_L22N, Sch name = EXP-IO8_N, MSO D0 |
|
# NET "VHDCIIO1<8>" LOC = "U11"; # Bank = 2, Pin name = IO_L23P, Sch name = EXP-IO9_P |
# NET "VHDCIIO1<9>" LOC = "R10"; # Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = EXP-IO10_P |
# NET "VHDCIIO1<10>" LOC = "U10"; # Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = EXP-IO11_P |
# NET "VHDCIIO1<11>" LOC = "R8"; # Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = EXP-IO12_P |
# NET "VHDCIIO1<12>" LOC = "M8"; # Bank = 2, Pin name = *IO_L40P, Sch name = EXP-IO13_P |
# NET "VHDCIIO1<13>" LOC = "U8"; # Bank = 2, Pin name = IO_L41P, Sch name = EXP-IO14_P |
# NET "VHDCIIO1<14>" LOC = "U7"; # Bank = 2, Pin name = IO_L43P, Sch name = EXP-IO15_P |
# NET "VHDCIIO1<15>" LOC = "N7"; # Bank = 2, Pin name = *IO_L44P, Sch name = EXP-IO16_P |
# NET "VHDCIIO1<16>" LOC = "T6"; # Bank = 2, Pin name = IO_L45P, Sch name = EXP-IO17_P |
# NET "VHDCIIO1<17>" LOC = "R7"; # Bank = 2, Pin name = IO_L46P, Sch name = EXP-IO18_P |
# NET "VHDCIIO1<18>" LOC = "N6"; # Bank = 2, Pin name = *IO_L47P, Sch name = EXP-IO19_P |
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P |
|
# Channnel 1 connects to P signals, Channel 2 to N signals |
NET "spi_ssel_o" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P, MSO D15 |
NET "spi_mosi_o" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P, MSO D13 |
NET "spi_di_req_o" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11 |
NET "spi_rx_bit_s_o" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9 |
NET "dbg_o<7>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P, MSO D7 |
NET "dbg_o<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P, MSO D5 |
NET "dbg_o<3>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P, MSO D3 |
NET "dbg_o<1>" LOC = "M10"; # Bank = 2, Pin name = *IO_L22P, Sch name = EXP-IO8_P, MSO D1 |
# NET "VHDCIIO1<8>" LOC = "U11"; # Bank = 2, Pin name = IO_L23P, Sch name = EXP-IO9_P |
# NET "VHDCIIO1<9>" LOC = "R10"; # Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = EXP-IO10_P |
# NET "VHDCIIO1<10>" LOC = "U10"; # Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = EXP-IO11_P |
# NET "VHDCIIO1<11>" LOC = "R8"; # Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = EXP-IO12_P |
# NET "VHDCIIO1<12>" LOC = "M8"; # Bank = 2, Pin name = *IO_L40P, Sch name = EXP-IO13_P |
# NET "VHDCIIO1<13>" LOC = "U8"; # Bank = 2, Pin name = IO_L41P, Sch name = EXP-IO14_P |
# NET "VHDCIIO1<14>" LOC = "U7"; # Bank = 2, Pin name = IO_L43P, Sch name = EXP-IO15_P |
# NET "VHDCIIO1<15>" LOC = "N7"; # Bank = 2, Pin name = *IO_L44P, Sch name = EXP-IO16_P |
# NET "VHDCIIO1<16>" LOC = "T6"; # Bank = 2, Pin name = IO_L45P, Sch name = EXP-IO17_P |
# NET "VHDCIIO1<17>" LOC = "R7"; # Bank = 2, Pin name = IO_L46P, Sch name = EXP-IO18_P |
# NET "VHDCIIO1<18>" LOC = "N6"; # Bank = 2, Pin name = *IO_L47P, Sch name = EXP-IO19_P |
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P |
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NET "spi_sck_o" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N, MSO D14 |
NET "spi_miso_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12 |
NET "spi_rx_bit_m_o" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10 |
NET "spi_do_valid_o" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8 |
NET "dbg_o<6>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N, MSO D6 |
NET "dbg_o<4>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N, MSO D4 |
NET "dbg_o<2>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N, MSO D2 |
NET "dbg_o<0>" LOC = "N9"; # Bank = 2, Pin name = *IO_L22N, Sch name = EXP-IO8_N, MSO D0 |
# NET "VHDCIIO2<8>" LOC = "V11"; # Bank = 2, Pin name = IO_L23N, Sch name = EXP-IO9_N |
# NET "VHDCIIO2<9>" LOC = "T10"; # Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = EXP-IO10_N |
# NET "VHDCIIO2<10>" LOC = "V10"; # Bank = 2, Pin name = IO_L30N_GCLK0_USERCCLK, Sch name = EXP-IO11_N |