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URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

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    /spi_master_slave
    from Rev 13 to Rev 12
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Rev 13 → Rev 12

/trunk/rtl/grp_debouncer.vhd File deleted
/trunk/rtl/spi_slave.vhd
115,10 → 115,6
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
--
-----------------------------------------------------------------------------------------------------------------------
125,11 → 121,12
-- TODO
-- ====
--
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity spi_slave is
Generic (
153,7 → 150,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
168,7 → 165,7
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture rtl of spi_slave is
architecture RTL of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
183,25 → 180,25
-- By using GSR for the initialization, and reducing RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinatorial stages
-- internal state signals for register and combinational stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- shifter signals for register and combinational stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- mosi and miso connections
signal rx_bit_next : std_logic;
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic;
-- buffered di_i data signals for register and combinatorial stages
signal rx_bit_next : std_logic := '0';
signal tx_bit_next : std_logic := '0';
signal tx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinational stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
-- internal wren_i stretcher for fsm combinational stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- buffered do_o data signals for register and combinational stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
294,7 → 291,7
end process in_transfer_proc;
 
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
-- RTL CORE REGISTER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
320,9 → 317,9
end process core_reg_proc;
 
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
-- RTL COMBINATIONAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
-- state and datapath combinational logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
335,16 → 332,15
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) =>
-- stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
-- acknowledge write enable
wr_ack_next <= '1'; -- acknowledge data in transfer
do_transfer_next <= '0'; -- reset transfer signal
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) =>
-- send bit out and shif bit in
do_transfer_next <= '0'; -- reset transfer signal
354,7 → 350,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 =>
-- raise data prefetch request
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
363,7 → 358,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 =>
-- transfer parallel data on next state
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
374,7 → 368,6
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 =>
-- restart from state 'N' if more sck pulses come
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
381,6 → 374,7
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
state_next <= N; -- next state is top bit of new data
389,53 → 383,44
sh_next <= (others => '0'); -- load null data (output '0' if no load)
state_next <= 0; -- next state is idle state
end if;
when 0 =>
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
-- idle state: start and end of transmission
if CPHA = '1' then
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
else
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= not wr_ack_reg; -- will request data if shifter empty
sh_next <= di_reg; -- load parallel data from di_reg into shifter
end if;
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
 
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
-- RTL OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
 
-----------------------------------------------------------------------------------------------
-- MISO driver process: copy next tx bit at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
begin
if spi_ssel_i = '1' then
spi_miso_o <= tx_bit_next; -- copy next => reg at reset
else
spi_miso_o <= tx_bit_reg;
end if;
end process spi_miso_o_proc;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
-- these signals are useful for verification, and can be deleted or commented-out after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture rtl;
end architecture RTL;
 
/trunk/rtl/spi_master.vhd
13,7 → 13,6
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
144,8 → 143,6
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
196,7 → 193,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
209,7 → 206,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
237,14 → 234,14
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wren : std_logic := '0';
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
254,8 → 251,8
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
312,7 → 309,7
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-- modes, by a single high-speed global clock, preserving clock resources.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
360,6 → 357,7
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
383,8 → 381,7
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
 
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
391,6 → 388,10
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
--
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
449,7 → 450,7
end process in_transfer_proc;
 
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
-- RTL REGISTER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
482,7 → 483,7
end process core_reg_proc;
 
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
-- RTL combinatorial LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
495,12 → 496,10
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
-- slave select
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
507,8 → 506,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy'
-- stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
515,8 → 512,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
-- send bit out and shif bit in
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
524,8 → 519,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
-- raise data prefetch request
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
532,8 → 525,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if wren
-- load next word or end transmission
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
549,17 → 540,15
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 =>
-- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
599,9 → 588,9
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
-- these signals are useful for verification, and can be deleted or commented-out after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
612,5 → 601,5
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
 
end architecture rtl;
end architecture RTL;
 
/trunk/syn/ATLYS_04.SET File deleted \ No newline at end of file
/trunk/syn/spi_test_ct.wcfg File deleted
/trunk/syn/spi_master_atlys_test.vhd
36,10 → 36,6
spi_mosi_o : out std_logic;
spi_miso_o : out std_logic;
led_o : out std_logic_vector(7 downto 0);
s_do_o : out std_logic_vector (7 downto 0);
m_do_o : out std_logic_vector (7 downto 0);
m_state_o : out std_logic_vector (3 downto 0);
s_state_o : out std_logic_vector (3 downto 0);
dbg_o : out std_logic_vector(11 downto 0)
);
end component;
65,21 → 61,9
-- debug output signals
signal leds : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
-- debug ports --
signal s_do_reg : std_logic_vector (7 downto 0);
signal m_do_reg : std_logic_vector (7 downto 0);
-- master signals mapped on dbg
signal wren_m : std_logic;
signal wr_ack_m : std_logic;
signal di_req_m : std_logic;
signal do_valid_m : std_logic;
signal master_state : std_logic_vector (3 downto 0);
-- slave signals mapped on dbg
signal wren_s : std_logic;
signal wr_ack_s : std_logic;
signal di_req_s : std_logic;
signal do_valid_s : std_logic;
signal slave_state : std_logic_vector (3 downto 0);
-- debug ports
signal spi_do_s : std_logic_vector (7 downto 0) := (others => '0');
signal spi_state_s : std_logic_vector (3 downto 0) := (others => '0');
begin
 
--=============================================================================================
101,22 → 85,11
sw_i => sw_data,
btn_i => btn_data,
led_o => leds,
m_state_o => master_state,
s_state_o => slave_state,
dbg_o => dbg
);
 
-- master signals mapped on dbg
wren_m <= dbg(11);
wr_ack_m <= dbg(10);
di_req_m <= dbg(9);
do_valid_m <= dbg(8);
-- slave signals mapped on dbg
wren_s <= dbg(7);
wr_ack_s <= dbg(6);
di_req_s <= dbg(5);
do_valid_s <= dbg(4);
spi_do_s <= dbg(7 downto 0);
spi_state_s <= dbg(11 downto 8);
 
--=============================================================================================
-- CLOCK GENERATION
136,12 → 109,8
begin
wait for 100 ns; -- wait until global set/reset completes
 
btn_data(btRESET) <= '1';
wait for 1 us;
btn_data(btRESET) <= '0';
wait for 900 ns;
sw_data <= X"5A";
btn_data(btRIGHT) <= '1';
wait; -- will wait forever
end process tb;
/trunk/syn/spi_master_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/syn/spi_master_atlys_top.vhd
28,7 → 28,6
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
--
--
----------------------------------------------------------------------------------
51,8 → 50,6
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
--- debug outputs ---
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
);
end spi_master_atlys_top;
83,28 → 80,14
--=============================================================================================
-- Type definitions
--=============================================================================================
type fsm_master_write_state_type is
(st_reset, st_wait_spi_idle, st_wait_new_switch, st_send_spi_data_sw, st_wait_spi_ack_sw,
st_send_spi_data_1, st_wait_spi_ack_1, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3);
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch,
st_send_spi_data, st_wait_spi_ack );
 
type fsm_slave_write_state_type is
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end);
 
type fsm_slave_read_state_type is
(st_reset, st_wait_spi_do_valid_1, st_wait_spi_n_do_valid_1, st_wait_spi_do_valid_2,
st_wait_spi_n_do_valid_2, st_wait_spi_do_valid_3, st_wait_spi_n_do_valid_3);
 
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
signal m_wr_st_reg : fsm_master_write_state_type := st_reset;
signal m_wr_st_next : fsm_master_write_state_type := st_reset;
signal s_wr_st_reg : fsm_slave_write_state_type := st_reset;
signal s_wr_st_next : fsm_slave_write_state_type := st_reset;
signal s_rd_st_reg : fsm_slave_read_state_type := st_reset;
signal s_rd_st_next : fsm_slave_read_state_type := st_reset;
signal state_reg : fsm_state_type := st_reset;
signal state_next : fsm_state_type := st_reset;
 
--=============================================================================================
-- Signals for internal operation
141,7 → 124,10
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_m : std_logic_vector (N-1 downto 0);
-- spi master port debug flags
signal spi_rx_bit_m : std_logic;
signal spi_wr_ack_m : std_logic;
signal state_dbg_m : std_logic_vector (5 downto 0);
-- spi slave port control signals
signal spi_wren_reg_s : std_logic := '1';
signal spi_wren_next_s : std_logic := '1';
152,20 → 138,14
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_s : std_logic_vector (N-1 downto 0);
-- spi slave port debug flags
signal spi_rx_bit_s : std_logic;
signal spi_wr_ack_s : std_logic;
signal spi_rx_bit_s : std_logic;
-- slave data output regs --
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal state_dbg_s : std_logic_vector (5 downto 0);
-- other signals
signal clear : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0);
signal leds_next : std_logic_vector (7 downto 0) := (others => '0');
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
begin
 
172,7 → 152,9
--=============================================================================================
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi master port: data and control signals driven by the master fsm
-- spi master port:
-- receives parallel data from the slide switches, transmits to slave port.
-- receives serial data from slave port, sends to 8bit parallel debug port.
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
182,34 → 164,63
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso, -- driven by the spi slave
spi_miso_i => spi_miso,
di_req_o => spi_di_req_m,
di_i => spi_di_reg_m,
wren_i => spi_wren_reg_m,
wr_ack_o => spi_wr_ack_m,
do_valid_o => spi_do_valid_m,
do_o => spi_do_m
do_o => spi_do_m,
------------ debug pins ------------
-- rx_bit_reg_o => spi_rx_bit_m,
-- state_dbg_o => state_dbg_m, -- monitor internal master state register
-- sck_ena_o => sck_ena_m, -- monitor internal sck_ena register
-- wren_o => spi_wren_o,
wr_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port
);
 
-- spi slave port: data and control signals driven by the slave fsm
-- state_dbg_o(3 downto 0) <= state_dbg_m(3 downto 0); -- connect master state debug port
-- sck_ena_o <= sck_ena_m; -- sck_ena debug port
-- spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port
 
-- spi slave port
-- receives parallel data from the pushbuttons, transmits to master port.
-- receives serial data from master port, sends to the 8 LEDs.
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3)
port map(
clk_i => gclk_i,
spi_ssel_i => spi_ssel, -- driven by the spi master
spi_sck_i => spi_sck, -- driven by the spi master
spi_mosi_i => spi_mosi, -- driven by the spi master
spi_ssel_i => spi_ssel, -- generated by the spi master
spi_sck_i => spi_sck, -- generated by the spi master
spi_mosi_i => spi_mosi,
spi_miso_o => spi_miso,
di_req_o => spi_di_req_s,
di_i => spi_di_reg_s,
wren_i => spi_wren_reg_s,
wr_ack_o => spi_wr_ack_s,
do_valid_o => spi_do_valid_s,
do_o => spi_do_s
do_o => spi_do_s,
------------ debug pins ------------
state_dbg_o => state_dbg_s, -- monitor internal state register
rx_bit_next_o => spi_rx_bit_s,
wr_ack_o => dbg(5),
do_transfer_o => dbg(4)
);
 
-- connect debug port pins to slave instance interface signals
dbg(7) <= spi_rx_bit_s;
dbg(6) <= spi_wren_reg_s;
dbg(3) <= spi_do_valid_s;
dbg(2) <= spi_di_req_s;
dbg(1) <= '0';
dbg(0) <= '0';
 
dbg(11 downto 8) <= state_dbg_s(3 downto 0);-- connect state register
spi_di_reg_s(7) <= btn_data(btLEFT); -- get the slave transmit data from pushbuttons
spi_di_reg_s(6) <= btn_data(btCENTER);
spi_di_reg_s(5 downto 1) <= B"10101";
spi_di_reg_s(0) <= btn_data(btRIGHT);
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data
 
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time
247,11 → 258,10
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- All registers are clocked directly from the 100MHz system clock.
-- The clock generation block derives 2 clock enable signals, divided down from the 100MHz input
-- clock.
-- input sample clock enable,
-- fsm clock enable,
-- The clock generation block derives 3 internal clocks, divided down from the 100MHz input clock
-- core clock,
-- spi 2x base clock,
-- fsm clock,
-----------------------------------------------------------------------------------------------
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (gclk_i) is
259,7 → 269,7
begin
if gclk_i'event and gclk_i = '1' then
if clk_cnt = SAMP_CE_DIV-1 then
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
samp_ce <= '1';
clk_cnt := 0;
else
samp_ce <= '0';
273,7 → 283,7
begin
if gclk_i'event and gclk_i = '1' then
if clk_cnt = FSM_CE_DIV-1 then
fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
fsm_ce <= '1';
clk_cnt := 0;
else
fsm_ce <= '0';
291,7 → 301,7
if gclk_i'event and gclk_i = '1' then
if samp_ce = '1' then
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= leds_next; -- update LEDs with spi_slave received data
leds_reg <= spi_do_s; -- update LEDs with spi_slave received data
end if;
end if;
end process samp_inputs_proc;
299,35 → 309,22
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the system clock
-- fsm state and data registers: synchronous to the spi base reference clock
fsm_reg_proc : process (gclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if gclk_i'event and gclk_i = '1' then
if clear = '1' then -- sync reset
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
if clear = '1' then -- sync reset
state_reg <= st_reset; -- only provide local reset for the state register
else
if fsm_ce = '1' then
m_wr_st_reg <= m_wr_st_next; -- master write state register update
state_reg <= state_next; -- state register
end if;
end if;
end if;
-- FFD registers clocked on rising edge and cleared on ssel = '1'
if gclk_i'event and gclk_i = '1' then
if spi_ssel = '1' then -- sync reset
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
s_rd_st_reg <= st_reset;
else
if fsm_ce = '1' then
s_wr_st_reg <= s_wr_st_next; -- slave write state register update
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if gclk_i'event and gclk_i = '1' then
if fsm_ce = '1' then
--------- master write fsm signals -----------
spi_wren_reg_m <= spi_wren_next_m;
spi_di_reg_m <= spi_di_next_m;
spi_rst_reg <= spi_rst_next;
334,13 → 331,6
spi_ssel_reg <= spi_ssel;
sw_reg <= sw_next;
btn_reg <= btn_next;
--------- slave write fsm signals -----------
spi_wren_reg_s <= spi_wren_next_s;
spi_di_reg_s <= spi_di_next_s;
--------- slave read fsm signals -----------
s_do_1_reg <= s_do_1_next;
s_do_2_reg <= s_do_2_next;
s_do_3_reg <= s_do_3_next;
end if;
end if;
end process fsm_reg_proc;
349,15 → 339,14
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
--=============================================================================================
-- edge detector for new switch data
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for edge
 
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference
-- edge detector for new button data
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for edge
 
-- master port fsm state and combinatorial logic
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
new_button) is
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference
-- fsm state and combinatorial logic
-- the sequencer will wait for a new switch combination, and send the switch data to the spi port
fsm_combi_proc: process ( state_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, -- spi_di_reg_s,
spi_wren_reg_s, spi_ssel_reg, spi_rst_reg, sw_data,
sw_reg, new_switch, btn_data, btn_reg, new_button) is
begin
spi_rst_next <= spi_rst_reg;
spi_di_next_m <= spi_di_reg_m;
364,214 → 353,49
spi_wren_next_m <= spi_wren_reg_m;
sw_next <= sw_reg;
btn_next <= btn_reg;
m_wr_st_next <= m_wr_st_reg;
case m_wr_st_reg is
state_next <= state_reg;
case state_reg is
when st_reset =>
spi_rst_next <= '1'; -- place spi interface on reset
spi_di_next_m <= (others => '0'); -- clear spi data port
spi_di_next_s <= (others => '0'); -- clear spi data port
spi_wren_next_m <= '0'; -- deassert write enable
m_wr_st_next <= st_wait_spi_idle;
spi_wren_next_s <= '0'; -- deassert write enable
state_next <= st_wait_spi_idle;
when st_wait_spi_idle =>
spi_wren_next_m <= '0'; -- remove write strobe on next clock
if spi_ssel_reg = '1' then
spi_rst_next <= '0'; -- remove reset when interface is idle
m_wr_st_next <= st_wait_new_switch;
state_next <= st_wait_new_switch;
end if;
 
when st_wait_new_switch =>
if new_switch = '1' then -- wait for new stable switch data
sw_next <= sw_data; -- load new switch data (end the mismatch condition)
m_wr_st_next <= st_send_spi_data_sw;
state_next <= st_send_spi_data;
elsif new_button = '1' then
btn_next <= btn_data; -- load new button data (end the mismatch condition)
if btn_data(btUP) = '0' then
if btn_data(btDOWN) = '1' then
m_wr_st_next <= st_send_spi_data_sw;
elsif btn_data(btLEFT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btCENTER) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btRIGHT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
end if;
if btn_data /= B"000001" then
state_next <= st_send_spi_data;
end if;
end if;
when st_send_spi_data_sw =>
when st_send_spi_data =>
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_sw;
state_next <= st_wait_spi_ack;
 
when st_wait_spi_ack_sw => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_send_spi_data_1 =>
spi_di_next_m <= X"A1"; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_1;
 
when st_wait_spi_ack_1 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A2";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack => -- the actual write happens on this state
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '0'; -- remove write strobe on next clock
state_next <= st_wait_spi_idle;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A3";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_3;
end if;
 
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_idle; -- wait transmission end
end if;
when others =>
m_wr_st_next <= st_reset; -- state st_reset is safe state
state_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_m_wr_combi_proc;
end process fsm_combi_proc;
 
-- slave port fsm state and combinatorial logic
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s,
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
begin
spi_wren_next_s <= spi_wren_reg_s;
spi_di_next_s <= spi_di_reg_s;
s_wr_st_next <= s_wr_st_reg;
case s_wr_st_reg is
when st_reset =>
spi_di_next_s <= X"D1"; -- write first data word
spi_wren_next_s <= '1'; -- set write enable
s_wr_st_next <= st_wait_spi_start;
when st_wait_spi_start =>
if spi_ssel_reg = '0' then -- wait for slave select
spi_wren_next_s <= '0'; -- remove write enable
s_wr_st_next <= st_wait_spi_di_req_2;
end if;
 
when st_wait_spi_di_req_2 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D2";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D3";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_3;
end if;
 
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_end; -- wait transmission end
end if;
when st_wait_spi_end => -- wait interface to be deselected
if spi_ssel_reg = '1' then
s_wr_st_next <= st_reset; -- wait transmission start
end if;
when others =>
s_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_wr_combi_proc;
 
-- slave port fsm state and combinatorial logic
fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
s_do_1_next <= s_do_1_reg;
s_do_2_next <= s_do_2_reg;
s_do_3_next <= s_do_3_reg;
s_rd_st_next <= s_rd_st_reg;
case s_rd_st_reg is
when st_reset =>
s_rd_st_next <= st_wait_spi_do_valid_1;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_1_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_1;
end if;
 
when st_wait_spi_n_do_valid_1 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_2;
end if;
when st_wait_spi_do_valid_2 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_2_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_2;
end if;
 
when st_wait_spi_n_do_valid_2 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_3;
end if;
when st_wait_spi_do_valid_3 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_3_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_3;
end if;
when st_wait_spi_n_do_valid_3 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_reset;
end if;
 
when others =>
s_rd_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_rd_combi_proc;
 
leds_combi_proc: process (btn_data, leds_reg, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
leds_next <= leds_reg;
if btn_data(btRIGHT) = '1' then
leds_next <= s_do_3_reg;
elsif btn_data(btCENTER) = '1' then
leds_next <= s_do_2_reg;
elsif btn_data(btLEFT) = '1' then
leds_next <= s_do_1_reg;
elsif btn_data(btDOWN) = '1' then
leds_next <= s_do_1_reg;
end if;
end process leds_combi_proc;
 
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
581,7 → 405,7
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
spi_miso_o_proc: spi_miso_o <= spi_miso;
-- connect leds_reg signal to LED outputs
led_o_proc: led_o <= leds_reg;
led_o_proc: led_o <= leds_reg;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
588,18 → 412,6
--=============================================================================================
-- connect the debug vector outputs
dbg_o_proc: dbg_o <= dbg;
-- connect debug port pins to spi ports instances interface signals
-- master signals mapped on dbg
dbg(11) <= spi_wren_reg_m;
dbg(10) <= spi_wr_ack_m;
dbg(9) <= spi_di_req_m;
dbg(8) <= spi_do_valid_m;
-- slave signals mapped on dbg
dbg(7) <= spi_wren_reg_s;
dbg(6) <= spi_wr_ack_s;
dbg(5) <= spi_di_req_s;
dbg(4) <= spi_do_valid_s;
 
end behavioral;
 
/trunk/syn/spi_slave.vhd
115,10 → 115,6
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
--
-----------------------------------------------------------------------------------------------------------------------
125,11 → 121,12
-- TODO
-- ====
--
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity spi_slave is
Generic (
153,7 → 150,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
168,7 → 165,7
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture rtl of spi_slave is
architecture RTL of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
183,25 → 180,25
-- By using GSR for the initialization, and reducing RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinatorial stages
-- internal state signals for register and combinational stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- shifter signals for register and combinational stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- mosi and miso connections
signal rx_bit_next : std_logic;
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic;
-- buffered di_i data signals for register and combinatorial stages
signal rx_bit_next : std_logic := '0';
signal tx_bit_next : std_logic := '0';
signal tx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinational stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
-- internal wren_i stretcher for fsm combinational stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- buffered do_o data signals for register and combinational stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
294,7 → 291,7
end process in_transfer_proc;
 
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
-- RTL CORE REGISTER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
320,9 → 317,9
end process core_reg_proc;
 
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
-- RTL COMBINATIONAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
-- state and datapath combinational logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
335,16 → 332,15
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) =>
-- stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
-- acknowledge write enable
wr_ack_next <= '1'; -- acknowledge data in transfer
do_transfer_next <= '0'; -- reset transfer signal
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) =>
-- send bit out and shif bit in
do_transfer_next <= '0'; -- reset transfer signal
354,7 → 350,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 =>
-- raise data prefetch request
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
363,7 → 358,6
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 =>
-- transfer parallel data on next state
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
374,7 → 368,6
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 =>
-- restart from state 'N' if more sck pulses come
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
381,6 → 374,7
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
state_next <= N; -- next state is top bit of new data
389,53 → 383,44
sh_next <= (others => '0'); -- load null data (output '0' if no load)
state_next <= 0; -- next state is idle state
end if;
when 0 =>
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
-- idle state: start and end of transmission
if CPHA = '1' then
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
else
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= not wr_ack_reg; -- will request data if shifter empty
sh_next <= di_reg; -- load parallel data from di_reg into shifter
end if;
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
 
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
-- RTL OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
 
-----------------------------------------------------------------------------------------------
-- MISO driver process: copy next tx bit at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
begin
if spi_ssel_i = '1' then
spi_miso_o <= tx_bit_next; -- copy next => reg at reset
else
spi_miso_o <= tx_bit_reg;
end if;
end process spi_miso_o_proc;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
-- these signals are useful for verification, and can be deleted or commented-out after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture rtl;
end architecture RTL;
 
/trunk/syn/spi_master.vhd
13,7 → 13,6
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
144,8 → 143,6
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
196,7 → 193,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
209,7 → 206,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
237,14 → 234,14
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wren : std_logic := '0';
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
254,8 → 251,8
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
312,7 → 309,7
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-- modes, by a single high-speed global clock, preserving clock resources.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
360,6 → 357,7
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
383,8 → 381,7
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
 
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
391,6 → 388,10
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
--
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
449,7 → 450,7
end process in_transfer_proc;
 
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
-- RTL REGISTER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
482,7 → 483,7
end process core_reg_proc;
 
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
-- RTL combinatorial LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
495,12 → 496,10
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
-- slave select
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
507,8 → 506,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy'
-- stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
515,8 → 512,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
-- send bit out and shif bit in
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
524,8 → 519,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
-- raise data prefetch request
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
532,8 → 525,6
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if wren
-- load next word or end transmission
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
549,17 → 540,15
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 =>
-- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
599,9 → 588,9
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
-- these signals are useful for verification, and can be deleted or commented-out after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
612,5 → 601,5
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
 
end architecture rtl;
end architecture RTL;
 
/trunk/syn/spi_master_scope_photos.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/bench/spi_master_atlys_test.vhd File deleted
/trunk/bench/spi_test_ct.wcfg File deleted

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