URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/spi_master_slave
- from Rev 23 to Rev 22
- ↔ Reverse comparison
Rev 23 → Rev 22
/trunk/license/lgpl.txt
File deleted
/trunk/rtl/spi_slave.vhd
73,26 → 73,26
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/rtl/spi_master.vhd
90,10 → 90,10
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
108,7 → 108,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/rtl/grp_debouncer.vhd
40,23 → 40,21
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+---------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______ |
-- ------ ------ | ------ | N ____ \---| \ | fd | |
-- | \---/---)) \ |AND |-----| |----[strb_o] |
-- | ))XOR |-----|___/ | | |
-- \-------------------------/---))___/ | | |
-- N | | |
-- |> | |
-- ------ |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- |
-- |
-- PIPELINE LOGIC |
77,12 → 75,12
-- RESOURCES USED |
-- ============== |
-- |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers. |
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. |
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
90,8 → 88,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
106,13 → 104,12
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
141,8 → 138,6
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors |
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output |
signal dat_strb : std_logic := '0'; -- data transfer strobe |
signal strb_reg : std_logic := '0'; -- registered strobe |
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
174,14 → 169,11
-- input pipeline logic |
pipeline_proc: process (clk_i) is |
begin |
-- edge detection pipeline |
if clk_i'event and clk_i = '1' then |
-- edge detection pipeline |
reg_A <= data_i; |
reg_B <= reg_A; |
-- new data strobe pipeline delay |
strb_reg <= strb_next; |
end if; |
-- output data pipeline |
if clk_i'event and clk_i = '1' then |
if dat_strb = '1' then |
reg_out <= reg_B; |
190,14 → 182,14
end process pipeline_proc; |
-- edge detector |
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0'; |
-- lookahead new data strobe |
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
|
--============================================================================================= |
-- OUTPUT LOGIC |
--============================================================================================= |
-- new data strobe detection |
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
-- connect output ports |
data_o_proc: data_o <= reg_out; |
strb_o_proc: strb_o <= strb_reg; |
|
end rtl; |
|
/trunk/rtl/readme.txt
31,13 → 31,7
|
Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board. |
|
LICENSING |
--------- |
|
This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. |
|
|
|
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
/trunk/syn/spi_master.vhd
90,10 → 90,10
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
108,7 → 108,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/syn/spi_slave.vhd
73,26 → 73,26
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/syn/readme.txt
24,13 → 24,7
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board |
|
|
LICENSING |
--------- |
|
This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. |
|
|
|
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
/trunk/syn/grp_debouncer.vhd
40,23 → 40,21
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+---------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______ |
-- ------ ------ | ------ | N ____ \---| \ | fd | |
-- | \---/---)) \ |AND |-----| |----[strb_o] |
-- | ))XOR |-----|___/ | | |
-- \-------------------------/---))___/ | | |
-- N | | |
-- |> | |
-- ------ |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- |
-- |
-- PIPELINE LOGIC |
77,12 → 75,12
-- RESOURCES USED |
-- ============== |
-- |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers. |
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. |
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
90,8 → 88,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
106,13 → 104,12
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
141,8 → 138,6
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors |
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output |
signal dat_strb : std_logic := '0'; -- data transfer strobe |
signal strb_reg : std_logic := '0'; -- registered strobe |
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
174,14 → 169,11
-- input pipeline logic |
pipeline_proc: process (clk_i) is |
begin |
-- edge detection pipeline |
if clk_i'event and clk_i = '1' then |
-- edge detection pipeline |
reg_A <= data_i; |
reg_B <= reg_A; |
-- new data strobe pipeline delay |
strb_reg <= strb_next; |
end if; |
-- output data pipeline |
if clk_i'event and clk_i = '1' then |
if dat_strb = '1' then |
reg_out <= reg_B; |
190,14 → 182,14
end process pipeline_proc; |
-- edge detector |
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0'; |
-- lookahead new data strobe |
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
|
--============================================================================================= |
-- OUTPUT LOGIC |
--============================================================================================= |
-- new data strobe detection |
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
-- connect output ports |
data_o_proc: data_o <= reg_out; |
strb_o_proc: strb_o <= strb_reg; |
|
end rtl; |
|