URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/spi_master_slave/trunk/syn
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/spi_master_atlys_test.vhd
0,0 → 1,118
-- TestBench Template |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity testbench is |
end testbench; |
|
architecture behavior of testbench is |
|
--============================================================================================= |
-- Constants |
--============================================================================================= |
-- clock period |
constant CLK_PERIOD : time := 10 ns; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
constant btUP : integer := 1; |
constant btLEFT : integer := 2; |
constant btDOWN : integer := 3; |
constant btRIGHT : integer := 4; |
constant btCENTER : integer := 5; |
|
--============================================================================================= |
-- COMPONENT DECLARATIONS |
--============================================================================================= |
component spi_master_atlys_top |
port( |
gclk_i : in std_logic; |
sw_i : in std_logic_vector(7 downto 0); |
btn_i : in std_logic_vector(5 downto 0); |
spi_ssel_o : out std_logic; |
spi_sck_o : out std_logic; |
spi_mosi_o : out std_logic; |
spi_miso_o : out std_logic; |
led_o : out std_logic_vector(7 downto 0); |
dbg_o : out std_logic_vector(11 downto 0) |
); |
end component; |
|
--============================================================================================= |
-- Signals for state machine control |
--============================================================================================= |
|
--============================================================================================= |
-- Signals for internal operation |
--============================================================================================= |
--- clock signals --- |
signal sysclk : std_logic := '0'; -- 100MHz clock |
--- switch debouncer signals --- |
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data |
--- pushbutton debouncer signals --- |
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons |
--- spi port signals --- |
signal spi_ssel : std_logic; |
signal spi_sck : std_logic; |
signal spi_mosi : std_logic; |
signal spi_miso : std_logic; |
-- debug output signals |
signal leds : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (11 downto 0) := (others => '0'); |
-- debug ports |
signal spi_do_s : std_logic_vector (7 downto 0) := (others => '0'); |
signal spi_state_s : std_logic_vector (3 downto 0) := (others => '0'); |
begin |
|
--============================================================================================= |
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST |
--============================================================================================= |
-- spi_master_atlys_top: |
-- receives the 100 MHz clock from the board clock oscillator |
-- receives the 8 slide switches and 5 pushbuttons as test stimuli |
-- connects to 4 spi signals |
-- connects to 8 board LEDs |
-- connects to 12 debug pins |
inst_spi_master_atlys_top: spi_master_atlys_top |
port map( |
gclk_i => sysclk, |
spi_ssel_o => spi_ssel, |
spi_sck_o => spi_sck, |
spi_mosi_o => spi_mosi, |
spi_miso_o => spi_miso, |
sw_i => sw_data, |
btn_i => btn_data, |
led_o => leds, |
dbg_o => dbg |
); |
|
spi_do_s <= dbg(7 downto 0); |
spi_state_s <= dbg(11 downto 8); |
|
--============================================================================================= |
-- CLOCK GENERATION |
--============================================================================================= |
gclk_proc: process is |
begin |
loop |
sysclk <= not sysclk; |
wait for CLK_PERIOD / 2; |
end loop; |
end process gclk_proc; |
|
--============================================================================================= |
-- TEST BENCH STIMULI |
--============================================================================================= |
tb : process |
begin |
wait for 100 ns; -- wait until global set/reset completes |
|
sw_data <= X"5A"; |
btn_data(btRIGHT) <= '1'; |
|
wait; -- will wait forever |
end process tb; |
-- End Test Bench |
END; |
/spi_master_envsettings.html
18,7 → 18,7
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>Path</td> |
25,7 → 25,7
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX</td> |
32,7 → 32,7
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
39,7 → 39,7
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
46,7 → 46,7
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
53,7 → 53,7
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
482,48 → 482,6
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td> </td> |
<td>n</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td> </td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>4</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>std</td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
541,7 → 499,7
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>Host</td> |
548,7 → 506,7
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>OS Name</td> |
555,7 → 513,7
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
<tr> |
<td>OS Release</td> |
562,7 → 520,7
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td><font color=gray>< data not available ></font></td> |
</tr> |
</TABLE> |
</BODY> </HTML> |
/spi_master_atlys_top_bit.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spi_master_atlys_top.vhd
1,5 → 1,5
---------------------------------------------------------------------------------- |
-- Engineer: Jonny Doin |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Create Date: 01:21:32 06/30/2011 |
-- Design Name: |
27,7 → 27,7
-- external monitoring pins to the VHDCI ports. |
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz, |
-- 6.25MHz, 1MHz and 500kHz |
-- 2011/07/18 v1.12.0105 [JD] spi_master.vhd changed to fix CPHA='1' clock glitch. |
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug. |
-- |
-- |
---------------------------------------------------------------------------------- |
37,27 → 37,20
|
entity spi_master_atlys_top is |
Port ( |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
--- SPI interface --- |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
--- SPI interface --- |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
dbg_o : out std_logic_vector (7 downto 0); -- 10 generic debug pins |
--- spi debug pins --- |
spi_rx_bit_m_o : out std_logic; -- master rx bit feedback |
spi_rx_bit_s_o : out std_logic; -- slave rx bit feedback |
spi_do_valid_o : out std_logic; -- spi data valid |
spi_di_req_o : out std_logic -- spi data request |
-- spi_wren_o : out std_logic; -- spi write enable |
-- spi_wren_ack_o : out std_logic -- spi write enable ack |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
); |
end spi_master_atlys_top; |
|
73,8 → 66,8
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
constant CPOL : std_logic := '0'; |
constant CPHA : std_logic := '0'; |
constant CPOL : std_logic := '1'; |
constant CPHA : std_logic := '1'; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
88,7 → 81,7
-- Type definitions |
--============================================================================================= |
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch, |
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish ); |
st_send_spi_data, st_wait_spi_ack ); |
|
--============================================================================================= |
-- Signals for state machine control |
134,24 → 127,26
-- spi master port debug flags |
signal spi_rx_bit_m : std_logic; |
signal spi_wr_ack_m : std_logic; |
signal state_dbg_m : std_logic_vector (5 downto 0); |
-- spi slave port control signals |
signal spi_wren_reg_s : std_logic := '1'; |
signal spi_wren_next_s : std_logic := '0'; |
signal spi_wren_next_s : std_logic := '1'; |
-- spi slave port flow control flags |
signal spi_di_req_s : std_logic; |
signal spi_do_valid_s : std_logic; |
-- spi slave port parallel data bus |
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (7 => '1', 6 => '0', 5 => '1', others => '0'); |
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal spi_do_s : std_logic_vector (N-1 downto 0); |
-- spi slave port debug flags |
signal spi_rx_bit_s : std_logic; |
signal spi_wr_ack_s : std_logic; |
signal state_dbg_s : std_logic_vector (5 downto 0); |
-- other signals |
signal clear : std_logic := '0'; |
-- debug output signals |
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (7 downto 0) := (others => '0'); |
signal dbg : std_logic_vector (11 downto 0) := (others => '0'); |
begin |
|
--============================================================================================= |
172,16 → 167,20
spi_miso_i => spi_miso, |
di_req_o => spi_di_req_m, |
di_i => spi_di_reg_m, |
wren_i => spi_wren_reg_m, |
do_valid_o => spi_do_valid_m, |
do_o => spi_do_m, |
rx_bit_reg_o => spi_rx_bit_m, |
wren_i => spi_wren_reg_m, |
------------ debug pins ------------ |
-- rx_bit_reg_o => spi_rx_bit_m, |
-- state_dbg_o => state_dbg_m, -- monitor internal master state register |
-- sck_ena_o => sck_ena_m, -- monitor internal sck_ena register |
-- wren_o => spi_wren_o, |
wren_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port |
wr_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port |
); |
|
dbg(7 downto 0) <= spi_do_m(7 downto 0); -- connect master received data to 8bit debug port |
spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port |
-- state_dbg_o(3 downto 0) <= state_dbg_m(3 downto 0); -- connect master state debug port |
-- sck_ena_o <= sck_ena_m; -- sck_ena debug port |
-- spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port |
|
-- spi slave port |
-- receives parallel data from the pushbuttons, transmits to master port. |
197,37 → 196,48
di_req_o => spi_di_req_s, |
di_i => spi_di_reg_s, |
wren_i => spi_wren_reg_s, |
rx_bit_reg_o => spi_rx_bit_s, |
do_valid_o => spi_do_valid_s, |
do_o => spi_do_s |
do_o => spi_do_s, |
------------ debug pins ------------ |
state_dbg_o => state_dbg_s, -- monitor internal state register |
rx_bit_next_o => spi_rx_bit_s, |
wr_ack_o => dbg(5), |
do_transfer_o => dbg(4) |
); |
|
-- connect debug port pins to slave instance interface signals |
dbg(7) <= spi_rx_bit_s; |
dbg(6) <= spi_wren_reg_s; |
dbg(3) <= spi_do_valid_s; |
dbg(2) <= spi_di_req_s; |
dbg(1) <= '0'; |
dbg(0) <= '0'; |
|
dbg(11 downto 8) <= state_dbg_s(3 downto 0);-- connect state register |
|
spi_di_reg_s(7) <= btn_data(btLEFT); -- get the slave transmit data from pushbuttons |
spi_di_reg_s(6) <= btn_data(btCENTER); |
spi_di_reg_s(5 downto 1) <= B"10101"; |
spi_di_reg_s(0) <= btn_data(btRIGHT); |
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data |
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port |
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 10000) -- debounce 8 inputs with 100 us settling time |
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => sw_i, -- noisy input data |
data_o => sw_data -- registered stable output data |
-- strb_o => dbg(0) -- monitor the debounced data strobe |
); |
); |
|
-- debounce for the input pushbuttons, with new data strobe output |
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 50000) -- debounce 6 inputs with 500 us settling time |
generic map (N => 6, CNT_VAL => 20000) -- debounce 6 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => btn_i, -- noisy input data |
data_o => btn_data -- registered stable output data |
-- strb_o => dbg(3) -- monitor the debounced data strobe |
); |
); |
|
--============================================================================================= |
-- CONSTANTS CONSTRAINTS CHECKING |
317,8 → 327,6
if fsm_ce = '1' then |
spi_wren_reg_m <= spi_wren_next_m; |
spi_di_reg_m <= spi_di_next_m; |
-- spi_wren_reg_s <= spi_wren_next_s; |
-- spi_di_reg_s <= spi_di_next_s; |
spi_rst_reg <= spi_rst_next; |
spi_ssel_reg <= spi_ssel; |
sw_reg <= sw_next; |
343,8 → 351,6
spi_rst_next <= spi_rst_reg; |
spi_di_next_m <= spi_di_reg_m; |
spi_wren_next_m <= spi_wren_reg_m; |
-- spi_di_next_s <= spi_di_reg_s; |
-- spi_wren_next_s <= spi_wren_reg_s; |
sw_next <= sw_reg; |
btn_next <= btn_reg; |
state_next <= state_reg; |
358,6 → 364,7
state_next <= st_wait_spi_idle; |
|
when st_wait_spi_idle => |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
if spi_ssel_reg = '1' then |
spi_rst_next <= '0'; -- remove reset when interface is idle |
state_next <= st_wait_new_switch; |
381,16 → 388,9
|
when st_wait_spi_ack => -- the actual write happens on this state |
spi_di_next_m <= sw_reg; -- load switch register to the spi port |
if spi_wr_ack_m = '1' then -- wait acknowledge |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
state_next <= st_wait_spi_finish; |
end if; |
spi_wren_next_m <= '0'; -- remove write strobe on next clock |
state_next <= st_wait_spi_idle; |
|
when st_wait_spi_finish => |
if spi_ssel_reg = '1' then |
state_next <= st_wait_new_switch; |
end if; |
|
when others => |
state_next <= st_reset; -- state st_reset is safe state |
end case; |
404,10 → 404,8
spi_sck_o_proc: spi_sck_o <= spi_sck; |
spi_mosi_o_proc: spi_mosi_o <= spi_mosi; |
spi_miso_o_proc: spi_miso_o <= spi_miso; |
spi_do_valid_o_proc: spi_do_valid_o <= spi_do_valid_m; |
spi_di_req_o_proc: spi_di_req_o <= spi_di_req_m; |
-- spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m; |
led_o_proc: led_o <= leds_reg; -- connect leds_reg signal to LED outputs |
-- connect leds_reg signal to LED outputs |
led_o_proc: led_o <= leds_reg; |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
/spi_slave.vhd
105,9 → 105,16
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. |
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. |
-- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs: |
-- - redesigned core clocking to address all CPOL and CPHA configurations. |
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite |
-- clock phases from SHIFT_EDGE. |
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
136,13 → 143,13
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) |
wren_i : in std_logic := 'X'; -- user data write enable |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) |
--- debug ports: can be removed for the application circuit --- |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
rx_bit_next_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
160,10 → 167,10
|
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA); |
constant SAMPLE_LEVEL : std_logic := SAMPLE_EDGE; |
constant SHIFT_EDGE : std_logic := (CPOL xor CPHA); |
-- |
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge |
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge |
|
------------------------------------------------------------------------------------------ |
-- GLOBAL RESET: |
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit |
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and |
172,21 → 179,23
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
-- |
------------------------------------------------------------------------------------------ |
-- internal state signals for register and combinational stages |
signal state_next : natural range N+1 downto 0 := 0; |
signal state_reg : natural range N+1 downto 0 := 0; |
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state |
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state |
-- shifter signals for register and combinational stages |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
-- mosi and miso connections |
signal rx_bit_next : std_logic := '0'; |
signal tx_bit_next : std_logic := '0'; |
signal tx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinational stages |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal di_reg : std_logic_vector (N-1 downto 0); |
-- internal wren_i stretcher for fsm combinational stage |
signal wren : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
signal wren : std_logic; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
194,7 → 203,8
signal do_transfer_next : std_logic := '0'; |
signal do_transfer_reg : std_logic := '0'; |
-- internal input data request signal |
signal di_req : std_logic := '0'; |
signal di_req_next : std_logic := '0'; |
signal di_req_reg : std_logic := '0'; |
-- cross-clock do_valid_o logic |
signal do_valid_next : std_logic := '0'; |
signal do_valid_A : std_logic := '0'; |
223,36 → 233,14
severity FAILURE; |
|
--============================================================================================= |
-- REGISTERED INPUTS |
-- GENERATE BLOCKS |
--============================================================================================= |
-- rx bit flop: capture rx bit after SAMPLE edge of sck |
rx_bit_proc : process (spi_sck_i, spi_mosi_i) is |
begin |
if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then |
rx_bit_reg <= spi_mosi_i; |
end if; |
end process rx_bit_proc; |
|
--============================================================================================= |
-- RTL CORE REGISTER PROCESSES |
-- DATA INPUTS |
--============================================================================================= |
-- fsm state and data registers change on spi SHIFT clock |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end process core_reg_proc; |
-- connect rx bit input |
rx_bit_proc : rx_bit_next <= spi_mosi_i; |
|
--============================================================================================= |
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC |
260,7 → 248,7
-- do_valid_o and di_req_o strobe output logic |
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a |
-- fixed-length delayed pulse for the output flags, at the parallel clock domain |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req, |
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg, |
do_valid_A, do_valid_B, do_valid_D, |
di_req_o_A, di_req_o_B, di_req_o_D) is |
begin |
272,8 → 260,8
do_valid_D <= do_valid_C; |
do_valid_o_reg <= do_valid_next; -- registered output pulse |
-------------------------------- |
-- di_req -> di_req_o_reg |
di_req_o_A <= di_req; -- the input signal must be at least 2 clocks long |
-- di_req_reg -> di_req_o_reg |
di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long |
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs |
di_req_o_C <= di_req_o_B; |
di_req_o_D <= di_req_o_C; |
284,7 → 272,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process (clk_i, wren_i, wren_ack_reg) is |
in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is |
begin |
-- registered data input, input register with clock enable |
if clk_i'event and clk_i = '1' then |
296,7 → 284,7
if clk_i'event and clk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
303,63 → 291,115
end process in_transfer_proc; |
|
--============================================================================================= |
-- RTL CORE REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers change on spi SHIFT_EDGE |
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag |
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization |
end if; |
-- FFD registers clocked on CHANGE edge |
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then |
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinational logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren, wren_ack_reg) is |
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, |
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
-- all output signals are assigned to (avoid latches) |
sh_next <= sh_reg; -- shift register |
tx_bit_next <= tx_bit_reg; -- MISO driver |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req <= '0'; -- prefetch data request: deassert when shifting data |
spi_miso_o <= sh_reg(N-1); -- output serial data from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
wr_ack_next <= wr_ack_reg; -- write enable acknowledge |
di_req_next <= di_req_reg; -- data input request |
state_next <= state_reg; -- fsm control state |
case state_reg is |
when (N) => |
-- acknowledge write enable |
wr_ack_next <= '1'; -- acknowledge data in transfer |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N-1) downto (PREFETCH+3) => |
-- send bit out and shif bit in |
do_transfer_next <= '0'; -- reset transfer signal |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (PREFETCH+2) downto 2 => |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 3 => |
-- raise data prefetch request |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 2 => |
-- transfer parallel data on next state |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
tx_bit_next <= sh_reg(N-1); -- output next MSbit |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle |
do_buffer_next <= sh_next; -- get next data directly into rx buffer |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 1 => |
-- restart from state 'N' if more sck pulses come |
di_req <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
do_transfer_next <= '1'; -- signal transfer to do_buffer |
state_next <= N; -- next state is top bit of new data |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
if wren = '1' then -- load tx register if valid data present at di_reg |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
wren_ack_next <= '1'; -- acknowledge data in transfer |
wr_ack_next <= '1'; -- acknowledge data in transfer |
state_next <= N; -- next state is top bit of new data |
else |
wr_ack_next <= '0'; -- remove data load ack for all but the load stages |
sh_next <= (others => '0'); -- load null data (output '0' if no load) |
state_next <= 0; -- next state is idle state |
end if; |
when 0 => |
di_req <= not wren_ack_reg; -- will request data if shifter empty |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
spi_miso_o <= di_reg(N-1); -- shift out first tx bit from the MSb |
if CPHA = '0' then |
-- initial state for CPHA=0, when slave interface is first selected or idle |
state_next <= N-1; -- next state is top bit of new data |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
-- idle state: start and end of transmission |
if CPHA = '1' then |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
wren_ack_next <= '1'; -- acknowledge data in transfer |
else |
-- initial state for CPHA=1, when slave interface is first selected or idle |
state_next <= N; -- next state is top bit of new data |
wr_ack_next <= '1'; -- acknowledge data in transfer |
di_req_next <= not wr_ack_reg; -- will request data if shifter empty |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
end if; |
end if; |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data |
state_next <= N; -- next state is top bit of new data |
when others => |
state_next <= 0; -- state 0 is safe state |
state_next <= 0; -- safe state |
end case; |
end process core_combi_proc; |
|
367,9 → 407,11
-- RTL OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
377,9 → 419,8
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; |
wren_o_proc: wren_o <= wren; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
end architecture RTL; |
|
/spi_master.vhd
1,5 → 1,5
----------------------------------------------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org |
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Create Date: 12:18:12 04/25/2011 |
-- Module Name: SPI_MASTER - RTL |
124,7 → 124,7
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce |
-- synthesis LUT overhead in Spartan-6 architecture. |
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wren_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets. |
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit. |
-- (minor bug) : removed fsm registers from (not rst_i) chip enable. |
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed). |
138,6 → 138,11
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end. |
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'. |
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz. |
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches. |
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz. |
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions |
-- for each state, to avoid reported inference problems in some synthesis engines. |
-- Streamlined port names and indentation blocks. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
179,12 → 184,14
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit) |
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle |
wr_ack_o : out std_logic; -- write acknowledge |
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit) |
--- debug ports: can be removed or left unconnected for the application circuit --- |
sck_ena_o : out std_logic; -- debug: internal sck enable signal |
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
rx_bit_reg_o : out std_logic; -- debug: internal rx bit |
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
core_clk_o : out std_logic; |
208,10 → 215,10
-- spi bus clock, generated from the CPOL selected core clock polarity |
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable |
signal spi_clk : std_logic := '0'; -- spi bus output clock |
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck |
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize) |
-- core fsm clock enables |
signal fsm_ce : std_logic := '1'; -- fsm clock enable |
signal ena_sck_ce : std_logic := '1'; -- SCK clock enable |
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable |
signal samp_ce : std_logic := '1'; -- data sampling clock enable |
-- |
-- GLOBAL RESET: |
235,14 → 242,14
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal wren_i stretcher for fsm combinatorial stage |
signal wren : std_logic := '0'; |
signal wren_ack_next : std_logic := '0'; |
signal wren_ack_reg : std_logic := '0'; |
signal wr_ack_next : std_logic := '0'; |
signal wr_ack_reg : std_logic := '0'; |
-- internal SSEL enable control signals |
signal ena_ssel_next : std_logic := '0'; |
signal ena_ssel_reg : std_logic := '0'; |
signal ssel_ena_next : std_logic := '0'; |
signal ssel_ena_reg : std_logic := '0'; |
-- internal SCK enable control signals |
signal ena_sck_next : std_logic := '0'; |
signal ena_sck_reg : std_logic := '0'; |
signal sck_ena_next : std_logic; |
signal sck_ena_reg : std_logic; |
-- buffered do_o data signals for register and combinatorial stages |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
336,45 → 343,46
end if; |
end if; |
end process core_clock_gen_proc; |
----------------------------------------------------------------------------------------------- |
|
--============================================================================================= |
-- GENERATE BLOCKS |
--============================================================================================= |
-- spi clk generator: generate spi_clk from core_clk depending on CPOL |
spi_sck_cpol_0_proc : |
if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
spi_sck_cpol_1_proc : |
if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
spi_sck_cpol_0_proc: if CPOL = '0' generate |
begin |
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
|
spi_sck_cpol_1_proc: if CPOL = '1' generate |
begin |
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
|
----------------------------------------------------------------------------------------------- |
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA |
-- always sample data at the half-cycle of the fsm update cell |
samp_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
samp_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
samp_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
samp_ce <= core_ce; |
end generate; |
|
samp_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
samp_ce <= core_n_ce; |
end generate; |
----------------------------------------------------------------------------------------------- |
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA |
fsm_ce_cpha_0_proc : |
if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
fsm_ce_cpha_1_proc : |
if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
fsm_ce_cpha_0_proc: if CPHA = '0' generate |
begin |
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable |
end generate; |
|
fsm_ce_cpha_1_proc: if CPHA = '1' generate |
begin |
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable |
end generate; |
|
ena_sck_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle |
|
--============================================================================================= |
-- REGISTERED INPUTS |
423,7 → 431,7
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; |
end process out_transfer_proc; |
-- parallel load input registers: data register and write enable |
in_transfer_proc: process ( pclk_i, wren_i, wren_ack_reg ) is |
in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is |
begin |
-- registered data input, input register with clock enable |
if pclk_i'event and pclk_i = '1' then |
435,7 → 443,7
if pclk_i'event and pclk_i = '1' then |
if wren_i = '1' then -- wren_i is the sync preset for wren |
wren <= '1'; |
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren |
elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren |
wren <= '0'; |
end if; |
end if; |
459,20 → 467,19
if sclk_i'event and sclk_i = '1' then |
if fsm_ce = '1' then |
sh_reg <= sh_next; -- shift register |
ena_ssel_reg <= ena_ssel_next; -- spi select enable |
ena_sck_reg <= ena_sck_next; -- spi clock enable |
ssel_ena_reg <= ssel_ena_next; -- spi select enable |
do_buffer_reg <= do_buffer_next; -- registered output data buffer |
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer |
di_req_reg <= di_req_next; -- input data request |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization |
end if; |
end if; |
-- FF registers clocked one-half cycle earlier than the fsm state |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_ce = '1' then |
-- ena_sck_reg <= ena_sck_next; -- spi clock enable |
-- end if; |
-- end if; |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_ce = '1' then |
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic |
end if; |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
479,33 → 486,44
-- RTL combinatorial LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg, |
do_transfer_reg, di_reg, wren ) is |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg, |
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
ena_ssel_next <= ena_ssel_reg; -- controls the slave select line |
ena_sck_next <= ena_sck_reg; -- controls the clock enable of spi sck line |
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line |
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line |
do_buffer_next <= do_buffer_reg; -- output data buffer |
do_transfer_next <= do_transfer_reg; -- output data flag |
wren_ack_next <= '0'; -- remove data load ack for all but the load stages |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= wr_ack_reg; -- write acknowledge |
di_req_next <= di_req_reg; -- prefetch data request |
state_next <= state_reg; -- next state |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N+1) => -- this state is to enable SSEL before SCK |
ena_ssel_next <= '1'; -- tx in progress: will assert SSEL |
ena_sck_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL |
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N) => -- deassert 'di_rdy' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer' |
di_req_next <= '0'; -- prefetch data request: deassert when shifting data |
do_transfer_next <= '0'; -- reset transfer signal |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid' |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
when 1 => -- transfer rx data to do_buffer and restart if wren |
di_req_next <= '1'; -- request data in advance to allow for pipeline delays |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
514,22 → 532,25
if wren = '1' then -- load tx register if valid data present at di_i |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
ena_sck_next <= '1'; -- SCK enabled |
wren_ack_next <= '1'; -- acknowledge data in transfer |
sck_ena_next <= '1'; -- SCK enabled |
wr_ack_next <= '1'; -- acknowledge data in transfer |
else |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= state_reg - 1; -- update next state at each sck pulse |
end if; |
when 0 => |
di_req_next <= '1'; -- will request data if shifter empty |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send |
if wren = '1' then -- load tx register if valid data present at di_i |
ena_ssel_next <= '1'; -- enable interface SSEL |
ssel_ena_next <= '1'; -- enable interface SSEL |
state_next <= N+1; -- start from idle: let one cycle for SSEL settling |
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead) |
sh_next <= di_reg; -- load bits from di_reg into shifter |
wren_ack_next <= '1'; -- acknowledge data in transfer |
wr_ack_next <= '1'; -- acknowledge data in transfer |
else |
ena_ssel_next <= '0'; -- deassert SSEL: interface is idle |
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle |
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages |
state_next <= 0; -- when idle, keep this state |
end if; |
when others => |
541,30 → 562,25
-- OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
spi_ssel_o_proc: spi_ssel_o <= not ena_ssel_reg; -- drive active-low slave select line |
do_o_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output |
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output |
spi_ssel_o_proc: spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line |
do_o_proc: do_o <= do_buffer_reg; -- parallel data out |
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- data out valid |
di_req_o_proc: di_req_o <= di_req_o_reg; -- input data request for next cycle |
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- write acknowledge |
----------------------------------------------------------------------------------------------- |
-- SCK out logic: pipeline phase compensation for the SCK line |
----------------------------------------------------------------------------------------------- |
-- This is a MUX with an output register. The register gives us a pipeline delay for the SCK line, |
-- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay. |
spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is |
-- This is a MUX with an output register. |
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore |
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. |
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is |
begin |
-- if sclk_i'event and sclk_i = '1' then |
-- if ena_sck_reg = '1' then |
-- spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
-- else |
-- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
-- end if; |
-- end if; |
if ena_sck_reg = '1' then |
if sclk_i'event and sclk_i = '1' then |
if sclk_i'event and sclk_i = '1' then |
if sck_ena_reg = '1' then |
spi_clk_reg <= spi_clk; -- copy the selected clock polarity |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
else |
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity |
end if; |
spi_sck_o <= spi_clk_reg; -- connect register to output |
end process spi_sck_o_gen_proc; |
574,15 → 590,16
--============================================================================================= |
-- these signals are useful for verification, and can be deleted or commented-out after debug. |
do_transfer_proc: do_transfer_o <= do_transfer_reg; |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); |
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg; |
wren_o_proc: wren_o <= wren; |
wren_ack_o_proc: wren_ack_o <= wren_ack_reg; |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; |
core_clk_o_proc: core_clk_o <= core_clk; |
core_n_clk_o_proc: core_n_clk_o <= core_n_clk; |
core_ce_o_proc: core_ce_o <= core_ce; |
core_n_ce_o_proc: core_n_ce_o <= core_n_ce; |
sck_ena_o_proc: sck_ena_o <= sck_ena_reg; |
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce; |
|
end architecture RTL; |
|
/ATLYS_03.SET
0,0 → 1,617
+¯âÓ~|ŽòØ™æÝÂTÞ…
+ ¦?T}¨~éÚrˆÊÐí•‚‡4„…¨´BLíá<0)ÚQÜóžvœÛê?j›ÔD†õá+ûÞò•h˜¬Ö×6¹’FĹUØr lƒŽ--‚öí7 סŠ}Êîhp‚Jc%“U]²Äþ^*™*¦ê&²õn¹®'’M¸¥È%§D0O¨G4là%¯U·M„ænéˆ £rö<Ýø‘m4]àM=å(wçp8lVCóxÕMÏŠ2Q(Ë&=|üd[¦§É‚°:SELECT:DALL 0 |
:ACQUIRE:STOPAFTER RUNSTOP |
:ACQUIRE:STATE 1 |
:ACQUIRE:MODE SAMPLE |
:ACQUIRE:NUMENV INFINITE |
:ACQUIRE:NUMAVG 128 |
:ACQUIRE:MAGNIVU 0 |
:HEADER 0 |
:LOCK NONE |
:VERBOSE 1 |
:MESSAGE:SHOW "" |
:MESSAGE:BOX 92,39,92,49 |
:MESSAGE:STATE 0 |
:ALIAS:STATE 0 |
:DISPLAY:COLOR:PALETTE NORMAL |
:DISPLAY:STYLE:DOTSONLY 0 |
:DISPLAY:PERSISTENCE 0.0E+0 |
:DISPLAY:CLOCK TIMEONLY |
:DISPLAY:FORMAT YT |
:DISPLAY:GRATICULE FULL |
:DISPLAY:INTENSITY:WAVEFORM 40 |
:DISPLAY:INTENSITY:GRATICULE 20 |
:DISPLAY:INTENSITY:BACKLIGHT MEDIUM |
:DISPLAY:INTENSITY:GLITCH 0 |
:DISPLAY:GLITCH 0 |
:DISPLAY:DIGITAL:HEIGHT MEDIUM |
:FILTERVU:FREQUENCY 100000000 |
:HARDCOPY:INKSAVER 1 |
:HARDCOPY:LAYOUT LANDSCAPE |
:HARDCOPY:PREVIEW 0 |
:PICTBRIDGE:PAPERSIZE DEFLT |
:PICTBRIDGE:IMAGESIZE DEFLT |
:PICTBRIDGE:PAPERTYPE DEFLT |
:PICTBRIDGE:PRINTQUAL DEFLT |
:PICTBRIDGE:DATEPRINT DEFLT |
:PICTBRIDGE:IDPRINT OFF |
:SAVE:IMAGE:LAYOUT LANDSCAPE |
:SAVE:IMAGE:FILEFORMAT BMP |
:SAVE:IMAGE:INKSAVER 0 |
:SAVE:WAVEFORM:FILEFORMAT SPREADSHEET |
:SAVE:WAVEFORM:GATING NONE |
:SAVE:WAVEFORM:SPREADSHEET:RESOLUTION FULL |
:SAVE:ASSIGN:TYPE IMAGE |
:D0:THRESHOLD 1.2600 |
:D1:THRESHOLD 1.2600 |
:D2:THRESHOLD 1.2600 |
:D3:THRESHOLD 1.2600 |
:D4:THRESHOLD 1.2600 |
:D5:THRESHOLD 1.2600 |
:D6:THRESHOLD 1.2600 |
:D7:THRESHOLD 1.2600 |
:D8:THRESHOLD 1.2600 |
:D9:THRESHOLD 1.2600 |
:D10:THRESHOLD 1.2600 |
:D11:THRESHOLD 1.2600 |
:D12:THRESHOLD 1.2600 |
:D13:THRESHOLD 1.2600 |
:D14:THRESHOLD 1.2600 |
:D15:THRESHOLD 1.2600 |
:D0:POSITION 60.0000E-3 |
:D1:POSITION 60.0000E-3 |
:D2:POSITION -2.9400 |
:D3:POSITION -2.4400 |
:D4:POSITION -1.9400 |
:D5:POSITION -1.4400 |
:D6:POSITION -940.0000E-3 |
:D7:POSITION -440.0000E-3 |
:D8:POSITION 60.0000E-3 |
:D9:POSITION 60.0000E-3 |
:D10:POSITION 60.0000E-3 |
:D11:POSITION 60.0000E-3 |
:D12:POSITION 1.0600 |
:D13:POSITION 1.5600 |
:D14:POSITION 2.0600 |
:D15:POSITION 2.5600 |
:D0:LABEL "" |
:D1:LABEL "" |
:D2:LABEL "di_req" |
:D3:LABEL "do_valid" |
:D4:LABEL "do_transfer" |
:D5:LABEL "wr_ack" |
:D6:LABEL "wren_reg" |
:D7:LABEL "rx_bit" |
:D8:LABEL "" |
:D9:LABEL "" |
:D10:LABEL "" |
:D11:LABEL "" |
:D12:LABEL "MISO" |
:D13:LABEL "MOSI" |
:D14:LABEL "SCK" |
:D15:LABEL "SSEL" |
:HORIZONTAL:POSITION 50.0000 |
:HORIZONTAL:SCALE 40.0000E-9 |
:HORIZONTAL:RECORDLENGTH 1000000 |
:HORIZONTAL:DELAY:MODE 1 |
:HORIZONTAL:DELAY:TIME 80.0000E-9 |
:SELECT:CH1 0 |
:SELECT:CH2 0 |
:SELECT:CH3 0 |
:SELECT:CH4 0 |
:SELECT:MATH 0 |
:SELECT:REF1 0 |
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:SELECT:D0 0 |
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:SELECT:D4 1 |
:SELECT:D5 1 |
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:SELECT:D7 1 |
:SELECT:D8 0 |
:SELECT:D9 0 |
:SELECT:D10 0 |
:SELECT:D11 0 |
:SELECT:D12 1 |
:SELECT:D13 1 |
:SELECT:D14 1 |
:SELECT:D15 1 |
:SELECT:BUS1 0 |
:SELECT:BUS2 1 |
:SELECT:CONTROL D7 |
:CH1:AMPSVIAVOLTS:ENABLE 0 |
:CH2:AMPSVIAVOLTS:ENABLE 0 |
:CH3:AMPSVIAVOLTS:ENABLE 0 |
:CH4:AMPSVIAVOLTS:ENABLE 0 |
:CH1:AMPSVIAVOLTS:FACTOR 10.0000 |
:CH2:AMPSVIAVOLTS:FACTOR 10.0000 |
:CH3:AMPSVIAVOLTS:FACTOR 10.0000 |
:CH4:AMPSVIAVOLTS:FACTOR 10.0000 |
:CH1:PROBE:GAIN 100.0000E-3 |
:CH2:PROBE:GAIN 100.0000E-3 |
:CH3:PROBE:GAIN 100.0000E-3 |
:CH4:PROBE:GAIN 100.0000E-3 |
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:CH1:BANDWIDTH 100.0000E+6 |
:CH2:BANDWIDTH 100.0000E+6 |
:CH3:BANDWIDTH 100.0000E+6 |
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:CH1:COUPLING DC |
:CH2:COUPLING DC |
:CH3:COUPLING DC |
:CH4:COUPLING DC |
:CH1:DESKEW 0.0E+0 |
:CH2:DESKEW 0.0E+0 |
:CH3:DESKEW 0.0E+0 |
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:CH2:TERMINATION 1.0000E+6 |
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:CH4:TERMINATION 1.0000E+6 |
:CH1:LABEL "\x0eACK" |
:CH2:LABEL "" |
:CH3:LABEL "" |
:CH4:LABEL "" |
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:TRIGGER:A:UPPERTHRESHOLD:CH1 240.0000E-3 |
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:TRIGGER:A:UPPERTHRESHOLD:CH3 1.4000 |
:TRIGGER:A:UPPERTHRESHOLD:CH4 1.4000 |
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:TRIGGER:A:LOWERTHRESHOLD:EXT 0.0E+0 |
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:TRIGGER:A:LOGIC:PATTERN:WHEN:MORELIMIT 8.0000E-9 |
:TRIGGER:A:LOGIC:PATTERN:DELTATIME 8.0000E-9 |
:TRIGGER:A:SETHOLD:CLOCK:SOURCE CH1 |
:TRIGGER:A:SETHOLD:CLOCK:EDGE RISE |
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:TRIGGER:A:SETHOLD:DATA:SOURCE NONE |
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:TRIGGER:A:SETHOLD:HOLDTIME 2.0000E-9 |
:TRIGGER:A:SETHOLD:SETTIME 2.0000E-9 |
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:TRIGGER:A:PULSEWIDTH:POLARITY POSITIVE |
:TRIGGER:A:PULSEWIDTH:WHEN MORETHAN |
:TRIGGER:A:PULSEWIDTH:WIDTH 95.0340E-6 |
:TRIGGER:A:RUNT:POLARITY POSITIVE |
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:TRIGGER:A:RUNT:WIDTH 95.0340E-6 |
:TRIGGER:A:TRANSITION:POLARITY POSITIVE |
:TRIGGER:A:TRANSITION:WHEN SLOWER |
:TRIGGER:A:TRANSITION:DELTATIME 95.0340E-6 |
:TRIGGER:A:VIDEO:STANDARD NTSC |
:TRIGGER:A:VIDEO:SYNC ALLLINES |
:TRIGGER:A:VIDEO:LINE 1 |
:TRIGGER:A:VIDEO:HOLDOFF:FIELD 0.0E+0 |
:TRIGGER:A:VIDEO:POLARITY POSITIVE |
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:TRIGGER:A:BUS:B1:PARALLEL:VALUE "X" |
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:TRIGGER:EXTERNAL:PROBE 10.0000 |
:BUS:B1:RS232C:PARITY NONE |
:BUS:B2:RS232C:PARITY NONE |
:BUS:B1:RS232C:BITRATE 9600 |
:BUS:B2:RS232C:BITRATE 9600 |
:BUS:B1:RS232C:POLARITY NORMAL |
:BUS:B2:RS232C:POLARITY NORMAL |
:BUS:B1:RS232C:DATABITS 8 |
:BUS:B2:RS232C:DATABITS 8 |
:BUS:B1:RS232C:TX:SOURCE CH1 |
:BUS:B2:RS232C:TX:SOURCE CH1 |
:BUS:B1:RS232C:RX:SOURCE D12 |
:BUS:B2:RS232C:RX:SOURCE OFF |
:BUS:B1:RS232C:DISPLAYMODE FRAME |
:BUS:B2:RS232C:DISPLAYMODE FRAME |
:BUS:B1:RS232C:DELIMITER LF |
:BUS:B2:RS232C:DELIMITER LF |
:BUS:B1:STATE 0 |
:BUS:B2:STATE 1 |
:BUS:B1:TYPE PARALLEL |
:BUS:B2:TYPE PARALLEL |
:BUS:B1:POSITION -2.5600 |
:BUS:B2:POSITION 600.0000E-3 |
:BUS:B1:DISPLAY:TYPE BUS |
:BUS:B2:DISPLAY:TYPE BUS |
:BUS:B1:DISPLAY:FORMAT HEXADECIMAL |
:BUS:B2:DISPLAY:FORMAT HEXADECIMAL |
:BUS:B1:LABEL "Parallel" |
:BUS:B2:LABEL "ST_S" |
:BUS:B1:PARALLEL:WIDTH 1 |
:BUS:B2:PARALLEL:WIDTH 4 |
:BUS:B1:PARALLEL:CLOCK:ISCLOCKED YES |
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:BUS:B1:PARALLEL:CLOCK:SOURCE D15 |
:BUS:B2:PARALLEL:CLOCK:SOURCE D15 |
:BUS:B1:PARALLEL:CLOCK:EDGE RISING |
:BUS:B2:PARALLEL:CLOCK:EDGE RISING |
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D0 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D1 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D2 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D3 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D4 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D5 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D6 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D7 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D8 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D9 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D10 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D11 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D12 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D13 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D14 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:D15 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:CH1 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:CH2 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:CH3 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:CH4 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:MATH X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:REF1 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:REF2 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:REF3 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:REF4 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D0 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D1 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D2 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D3 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D4 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D5 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D6 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D7 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D8 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D9 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D10 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D11 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D12 X |
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D14 X |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D15 X |
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:WHEN:LESSLIMIT 8.0000E-9 |
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:WHEN:MORELIMIT 8.0000E-9 |
:SEARCH:SEARCH1:TRIGGER:A:PULSEWIDTH:POLARITY POSITIVE |
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:SEARCH:SEARCH1:TRIGGER:A:PULSEWIDTH:WIDTH 8.0000E-9 |
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:SEARCH:SEARCH1:TRIGGER:A:RUNT:WHEN OCCURS |
:SEARCH:SEARCH1:TRIGGER:A:RUNT:WIDTH 8.0000E-9 |
:SEARCH:SEARCH1:TRIGGER:A:TRANSITION:POLARITY POSITIVE |
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:SEARCH:SEARCH1:TRIGGER:A:TRANSITION:DELTATIME 8.0000E-9 |
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:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:HOLDTIME 2.0000E-9 |
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:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:CH2 0.0E+0 |
:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:CH3 0.0E+0 |
:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:CH4 0.0E+0 |
:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:MATH 0.0E+0 |
:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:REF1 0.0E+0 |
:SEARCH:SEARCH1:TRIGGER:A:SETHOLD:THRESHOLD:REF2 0.0E+0 |
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:ZOOM:MODE 0 |
:ZOOM:ZOOM1:STATE 1 |
:ZOOM:ZOOM1:SCALE 40.0000E-9 |
:ZOOM:ZOOM1:POSITION 50.1181 |
:ZOOM:ZOOM1:HORIZONTAL:POSITION 50.1181 |
:ZOOM:ZOOM1:HORIZONTAL:SCALE 40.0000E-9 |
:CURSOR:FUNCTION OFF |
:CURSOR:MODE INDEPENDENT |
:CURSOR:VBARS:POSITION1 172.4000E-9 |
:CURSOR:VBARS:POSITION2 198.4000E-9 |
:CURSOR:VBARS:UNITS SECONDS |
:CURSOR:HBARS:POSITION1 0.0E+0 |
:CURSOR:HBARS:POSITION2 0.0E+0 |
:CURSOR:HBARS:UNITS BASE |
:CURSOR:XY:READOUT RECTANGULAR |
:CURSOR:XY:RECTANGULAR:X:POSITION1 0.0E+0 |
:CURSOR:XY:RECTANGULAR:X:POSITION2 0.0E+0 |
:CURSOR:XY:RECTANGULAR:Y:POSITION1 0.0E+0 |
:CURSOR:XY:RECTANGULAR:Y:POSITION2 0.0E+0 |
:MEASUREMENT:IMMED:DELAY:DIRECTION FORWARDS |
:MEASUREMENT:IMMED:DELAY:EDGE1 RISE |
:MEASUREMENT:IMMED:DELAY:EDGE2 RISE |
:MEASUREMENT:IMMED:TYPE PERIOD |
:MEASUREMENT:IMMED:SOURCE1 CH1 |
:MEASUREMENT:IMMED:SOURCE2 CH2 |
:MEASUREMENT:MEAS1:DELAY:DIRECTION FORWARDS |
:MEASUREMENT:MEAS2:DELAY:DIRECTION FORWARDS |
:MEASUREMENT:MEAS3:DELAY:DIRECTION FORWARDS |
:MEASUREMENT:MEAS4:DELAY:DIRECTION FORWARDS |
:MEASUREMENT:MEAS1:DELAY:EDGE1 RISE |
:MEASUREMENT:MEAS1:DELAY:EDGE2 RISE |
:MEASUREMENT:MEAS2:DELAY:EDGE1 RISE |
:MEASUREMENT:MEAS2:DELAY:EDGE2 RISE |
:MEASUREMENT:MEAS3:DELAY:EDGE1 RISE |
:MEASUREMENT:MEAS3:DELAY:EDGE2 RISE |
:MEASUREMENT:MEAS4:DELAY:EDGE1 RISE |
:MEASUREMENT:MEAS4:DELAY:EDGE2 RISE |
:MEASUREMENT:MEAS1:TYPE FREQUENCY |
:MEASUREMENT:MEAS2:TYPE PERIOD |
:MEASUREMENT:MEAS3:TYPE PERIOD |
:MEASUREMENT:MEAS4:TYPE PERIOD |
:MEASUREMENT:MEAS1:SOURCE1 D14 |
:MEASUREMENT:MEAS1:SOURCE2 CH2 |
:MEASUREMENT:MEAS2:SOURCE1 CH1 |
:MEASUREMENT:MEAS2:SOURCE2 CH2 |
:MEASUREMENT:MEAS3:SOURCE1 CH1 |
:MEASUREMENT:MEAS3:SOURCE2 CH2 |
|