URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/spi_master_slave/trunk/syn
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/spi_master.vhd
68,7 → 68,7
-- PARALLEL READ SEQUENCE |
-- ====================== |
-- ______ ______ ______ ______ |
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi 2x base clock |
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock |
-- _ __ __ __ __ __ __ __ __ |
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i) |
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg' |
164,16 → 164,18
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock |
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock |
rst_i : in std_logic := 'X'; -- reset core |
---- serial interface ---- |
spi_ssel_o : out std_logic; -- spi bus slave select line |
spi_sck_o : out std_logic; -- spi bus sck |
spi_mosi_o : out std_logic; -- spi bus mosi output |
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input |
---- parallel interface ---- |
di_req_o : out std_logic; -- preload lookahead data request line |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit) |
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle |
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge. |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit) |
--- debug ports: can be removed for the application circuit --- |
--- debug ports: can be removed or left unconnected for the application circuit --- |
do_transfer_o : out std_logic; -- debug: internal transfer driver |
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher |
wren_ack_o : out std_logic; -- debug: wren ack from state machine |
208,10 → 210,10
-- GLOBAL RESET: |
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit |
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and |
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can |
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can |
-- reduce the usability of the slice registers, due to the need to share the control |
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- By using GSR for the initialization, and reducing async RESET local init to the bare |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
-- |
-- internal state signals for register and combinatorial stages |
287,7 → 289,7
-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock |
-- for the core clocking. |
-- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only |
-- interconnect delays. |
-- differential interconnect delay skew. |
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock |
-- enables are used to control clocking of all internal synchronous circuitry. |
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, |
383,34 → 385,6
end process rx_bit_proc; |
|
--============================================================================================= |
-- RTL REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers: synchronous to the spi base reference clock |
core_reg_proc : process (sclk_i) is |
begin |
-- FF registers clocked on rising edge and cleared on sync rst_i |
if sclk_i'event and sclk_i = '1' then |
if rst_i = '1' then -- sync reset |
state_reg <= 0; -- only provide local reset for the state machine |
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm |
state_reg <= state_next; -- state register |
end if; |
end if; |
-- FF registers clocked on rising edge |
if sclk_i'event and sclk_i = '1' then |
if fsm_ce = '1' then |
sh_reg <= sh_next; -- shift register |
ena_ssel_reg <= ena_ssel_next; -- spi select enable |
ena_sck_reg <= ena_sck_next; -- spi clock enable |
do_buffer_reg <= do_buffer_next; -- registered output data buffer |
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer |
di_req_reg <= di_req_next; -- input data request |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC |
--============================================================================================= |
-- do_valid_o and di_req_o strobe output logic |
459,6 → 433,34
end process in_transfer_proc; |
|
--============================================================================================= |
-- RTL REGISTER PROCESSES |
--============================================================================================= |
-- fsm state and data registers: synchronous to the spi base reference clock |
core_reg_proc : process (sclk_i) is |
begin |
-- FF registers clocked on rising edge and cleared on sync rst_i |
if sclk_i'event and sclk_i = '1' then |
if rst_i = '1' then -- sync reset |
state_reg <= 0; -- only provide local reset for the state machine |
elsif fsm_ce = '1' then -- fsm_ce is clock enable for the fsm |
state_reg <= state_next; -- state register |
end if; |
end if; |
-- FF registers clocked on rising edge |
if sclk_i'event and sclk_i = '1' then |
if fsm_ce = '1' then |
sh_reg <= sh_next; -- shift register |
ena_ssel_reg <= ena_ssel_next; -- spi select enable |
ena_sck_reg <= ena_sck_next; -- spi clock enable |
do_buffer_reg <= do_buffer_next; -- registered output data buffer |
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer |
di_req_reg <= di_req_next; -- input data request |
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization |
end if; |
end if; |
end process core_reg_proc; |
|
--============================================================================================= |
-- RTL combinatorial LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinatorial logic |
/readme.txt
25,8 → 25,9
|
|
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer. |
If you find a bug or a model design fault, please open a bug in the bugtracker in this project page at OpenCores. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker. |
|
In any case, thank you very much for testing this core. |
|
|
/grp_debouncer.vhd
14,49 → 14,49
-- |
-- CONCEPTUAL CIRCUIT |
-- ================== |
-- |
-- W |
-- /----------------/----------------\ |
-- | | |
-- | | |
-- | ______ ______ | _____ |
-- | W | | W |fdr | W | W |cmp \ |
-- \----/---| +1 |---/----| |--/--+----/----| \ |
-- | | | | | \ |
-- ------ | | \ | |
-- | | | = |-----\ |
-- |> R | / | | |
-- ---+-- | / | |
-- | CNT_VAL---| / | |
-- | |____/ | |
-- | | |
-- \------------\ | |
-- | | |
-- N ____ | | |
-- /-------/---)) \ ____ | | |
-- | ))XOR |-----) \ | | |
-- | /------))___/ )OR |-----/ | |
-- | | /---)___/ | |
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- |
-- |
-- |
-- W |
-- /----------------/----------------\ |
-- | | |
-- | | |
-- | ______ ______ | _____ |
-- | W | | W |fdr | W | W |cmp \ |
-- \----/---| +1 |---/----| |--/--+----/----| \ |
-- | | | | | \ |
-- ------ | | \ | |
-- | | | = |-----\ |
-- |> R | / | | |
-- ---+-- | / | |
-- | CNT_VAL---| / | |
-- | |____/ | |
-- | | |
-- \------------\ | |
-- | | |
-- N ____ | | |
-- /-------/---)) \ ____ | | |
-- | ))XOR |-----) \ | | |
-- | /------))___/ )OR |-----/ | |
-- | | /---)___/ | |
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- |
-- |
-- PIPELINE LOGIC |
-- ============== |
-- |