OpenCores
URL https://opencores.org/ocsvn/spi_verilog_master_slave/spi_verilog_master_slave/trunk

Subversion Repositories spi_verilog_master_slave

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/spi_verilog_master_slave/branches/verilog/tb_slave.v
0,0 → 1,164
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Design Name: SPI SLAVE TESTBENCH
* Module Name: tbslave
* Project Name: SPI
* Target Devices: Spartan 3E
* Designed by: Santhosh G
*
*
* Author: Santhosh
* santhoshg90@gmail.com
*
* Copyright - 2014 - Santhosh G
* - OpenCores.org
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* THIS IS PROVIDED WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESSFOR A PARTICULAR PURPOSE. IN CASE THE AUTHOR IS RESPONSIBEL FOR
* THE DAMAGES CAUSED BY USE OF THIS. FOR EDUCATIONAL PURPOSE ONLY.
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* This source file is free software; you can redistribute it
* * and/or modify it under the terms of the GNU Lesser General
* Public License as published by the Free Software Foundation;
* either version 2.1 of the License, or (at your option) any
* later version.
*
* You should have received a copy of the GNU Lesser General
* Public License along with this source; if not, download it
* from http://www.opencores.org/lgpl.shtml
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
`timescale 1ns/10ps
module tbslave;
reg rstb = 1'b0;
reg ten = 1'b0;
reg [7:0] tdata = 8'b00000000;
reg mlb = 1'b0;
reg ss = 1'b0;
reg sck = 1'b0;
reg sdin = 1'b0;
wire sdout;
wire done;
wire [7:0] rdata;
 
initial #1200 $stop;
 
SPI_slave UUT (
.rstb(rstb),
.ten(ten),
.tdata(tdata),
.mlb(mlb),
.ss(ss),
.sck(sck),
.sdin(sdin),
.sdout(sdout),
.done(done),
.rdata(rdata));
 
wire [3:0] nbit;
assign nbit=UUT.nb;
 
initial begin
#100;
ss = 1'b1;
sck = 1'b1;
sdin = 1'b1;
#20;
rstb = 1'b1;
#20;
ten = 1'b1;
mlb = 1'b1;
tdata = 8'b01111100;
#20;
ss = 1'b0;
#20;
sck = 1'b0;
sdin = 1'b0;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b1;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b0;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b1;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b0;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b1;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b0;
#20;
sck = 1'b1;
#20;
sck = 1'b0;
sdin = 1'b1;
#20;
sck = 1'b1;
#20;
ss = 1'b1;
#20;
ten = 1'b0;
#100 ten = 1'b0; mlb = 1'b0; tdata = 8'b01110000;
#20 ss = 1'b0;
#20 sck = 1'b0;
sdin = 1'b0;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b1;
#20 sck = 1'b1;
 
#20 sck = 1'b0;
sdin = 1'b0;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b1;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b0;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b1;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b0;
#20 sck = 1'b1;
#20 sck = 1'b0;
sdin = 1'b1;
#20 sck = 1'b1;
#20 ss = 1'b1;
#20 ten = 1'b0;
#100;
 
end
 
endmodule
 
/spi_verilog_master_slave/branches/verilog/spi_slave.v
0,0 → 1,100
//////////////////////////////////////////////////////////////////////////////////
// Design Name: SPI SLAVE MODULE
// Module Name: SPI_slave
// Project Name: SPI
// Target Devices: Spartan 3E
// Designed by: Santhosh G
// Version: 1.1
// Description: for www.elecdude.com
// SPI MODE-3
// CHANGE DATA (sdout) @ NEGEDGE SCK
// read data (sdin) @posedge SCK
//
// DISCLAIMER:
// ```````````
// Author: Santhosh G
// santhoshg90@gmail.com
//
// Copyright - 2014 - Santhosh G
// - OpenCores.org
//
// THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
// RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
// REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
// THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
//
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_slave (rstb,ten,tdata,mlb,ss,sck,sdin, sdout,done,rdata);
input rstb,mlb; //control signals rstb-> active low, mlb=0-> lsb 1st, =1-> MSB 1st
input ten; //slave data out enable if 1, else tri-state
input ss,sck; //SPI interface signals (SS,SCK)
input sdin; //slave in-master out (MOSI)
input [7:0] tdata;//data to be transmitted
output sdout; //slave out-master in (MISO)
output done; //signals transmission completed
output reg [7:0] rdata; //received data
 
reg [7:0] treg,rreg;
reg [3:0] nb; //bit count
wire sout,clr;
reg dw;
assign done= dw & ss;
assign sout= mlb?treg[7]:treg[0]; //select MSB or LSB
 
 
//read from sdin (MOSI)
always @(posedge sck or negedge rstb)
begin
if (rstb==0)
begin rreg = 8'hFF; rdata = 8'h00; dw = 0; nb = 0; end
else if (!ss) begin
if(mlb==0) //LSB first, in@msb -> right shift
begin rreg ={sdin,rreg[7:1]}; end
else //MSB first, in@lsb -> left shift
begin rreg ={rreg[6:0],sdin}; end
//increment bit count
nb=nb+1;
if(nb!=8) dw=0;
else begin rdata=rreg; dw=1; nb=0; end
end
end
 
//send to sdout (MISO)
always @(negedge sck or negedge rstb or negedge ss) begin
if (rstb==0)
begin treg = 8'hFF; end
else begin
if(!ss) begin
if(nb==0)
begin treg=tdata; end
else begin
if(mlb==0) //LSB first, out=lsb -> right shift
begin treg = {1'b1,treg[7:1]}; end
else //MSB first, out=msb -> left shift
begin treg = {treg[6:0],1'b1}; end
end
end //!ss
end //rstb
end //always
 
 
endmodule
 
/spi_verilog_master_slave/branches/verilog/tb_MAS.v
0,0 → 1,119
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Design Name: SPI MASTER TESTBENCH
* Module Name: tb_MASTER
* Project Name: SPI
* Target Devices: Spartan 3E
* Designed by: Santhosh G
*
*
* Author: Santhosh
* santhoshg90@gmail.com
*
* Copyright - 2014 - Santhosh G
* - OpenCores.org
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* THIS IS PROVIDED WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESSFOR A PARTICULAR PURPOSE. IN CASE THE AUTHOR IS RESPONSIBEL FOR
* THE DAMAGES CAUSED BY USE OF THIS. FOR EDUCATIONAL PURPOSE ONLY.
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* This source file is free software; you can redistribute it
* * and/or modify it under the terms of the GNU Lesser General
* Public License as published by the Free Software Foundation;
* either version 2.1 of the License, or (at your option) any
* later version.
*
* You should have received a copy of the GNU Lesser General
* Public License along with this source; if not, download it
* from http://www.opencores.org/lgpl.shtml
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
`timescale 1ns/10ps
module tb_MASTER;
reg rstb;
reg clk = 1'b0;
reg mlb = 1'b0;
reg start = 1'b0;
reg [7:0] tdat = 8'b00000000;
reg [1:0] cdiv = 0;
reg din=1'b0;
wire ss;
wire sck;
wire dout;
wire done;
wire [7:0] rdata;
 
 
initial #7000 $stop;
 
parameter PERIOD = 50;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 100;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
 
spi_master UUT (
.rstb(rstb),
.clk(clk),
.mlb(mlb),
.start(start),
.tdat(tdat),
.cdiv(cdiv),
.din(din),
.ss(ss),
.sck(sck),
.dout(dout),
.done(done),
.rdata(rdata));
 
// $dumpfile("vcd_spi_master.vcd"); $dumpvars;
 
 
initial begin
 
#10 rstb = 1'b0;
#100;
rstb = 1'b1;start = 1'b0;
tdat = 8'b01111100;
cdiv = 2'b00;
#100 start = 1'b1;
#100 start = 1'b0;
#100
#1800 mlb = 1'b1; cdiv=2'b00; tdat=8'b01111100; din=1'b1;
#100 start = 1'b1;
#100 start = 1'b0;
#100
#1200 mlb = 1'b1; cdiv=2'b01; tdat=8'b00011100; din=1'b1;
#100 start = 1'b1;
#100 start = 1'b0;
#2000;
 
end
 
endmodule
 
 
/spi_verilog_master_slave/branches/verilog/SPI_master.v
0,0 → 1,179
////////////////////////////////////////////////////////////////////////////////////
// Design Name: SPI MASTER MODULE
// Module Name: spi_master
// Project Name: SPI
// Target Devices: Spartan 3E
//
// Designed by: Santhosh G
// Version: 1.2
// Description: for www.elecdude.com
// SPI MODE-3
// CHANGE DATA (sdout) @ NEGEDGE SCK
// read data (sdin) @posedge SCK
//
// DISCLAIMER:
// ```````````
// Author: Santhosh G
// santhoshg90@gmail.com
//
// Copyright - 2014 - Santhosh G
// - OpenCores.org
//
// THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
// RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
// REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
// THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
//
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
////////////////////////////////////////////////////////////////////////////////////
 
module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata);
input rstb,clk,mlb,start;
//RSTB-active low asyn reset & CLK-clock & mlb=0->LSB 1st, 1->msb 1st
//START=1- starts data transmission
input [7:0] tdat; //transmit data
input [1:0] cdiv; //clock divider 0=clk/2, 1=clk/4, 2=clk/8, 3=clk/16
input din; //Master in-slave out (MISO)
output reg ss; //slave select
output reg sck; //clock
output reg dout; //Master out-slave in (MOSI)
output done; //ass_werted 1 when transmiss_wion complete
output reg [7:0] rdata; //received data
 
parameter idle=2'b00;
parameter send=2'b10;
parameter finish=2'b11;
reg [1:0] cur,nxt; //state registers
reg [7:0] treg,rreg; //Transmit & receive registers
reg [3:0] nbit; //bit count
reg [4:0] mid,cnt; //for SPI clock generation
reg shift,clr;
 
assign done = ss & (~shift);
//state transistion
always@(negedge clk or negedge rstb) begin
if(rstb==0)
cur<=finish;
else
cur<=nxt;
end
always@(rstb or cur) begin
if(rstb==0)
rdata<=8'hFF;
else if(cur==finish)
rdata<=rreg;
end
 
//FSM input & outputs
always @(start or cur or nbit) begin
nxt=cur;
clr=0;
shift=0;
case(cur)
idle:begin
clr=1;
if(start==1)
begin
case (cdiv)
2'b00: mid=2;
2'b01: mid=4;
2'b10: mid=8;
2'b11: mid=16;
endcase
shift=1; //done=1'b0;
nxt=send;
end
end //idle_ends
send:begin
ss=0;
if(nbit!=8)
begin shift=1; end
else begin
nxt=finish; //rdata=rreg;
end
end//send_ends
finish:begin
shift=0; clr=1;
ss=1; //done=1'b1;
nxt=idle;
end//finish_ends
default: nxt=finish;
endcase
end//always ends here
 
//clock generation
always@(negedge clk or posedge clr) begin
if(clr==1)
begin cnt<=0; //sck=1;
sck<=1;
end
else begin
if(shift==1) begin
//cnt=cnt+1;
// if(cnt==mid) begin
// sck=~sck; //sck=~sck;
// cnt=0;
// end //mid
if(cnt<mid-1)
cnt<=cnt+1;
else
cnt<=0;
if(cnt<mid/2)
sck<=1;
else
sck<=0;
end //shift
end //rst ends here
end //always ends here
 
//sample @ rising edge (read din)
always@(posedge sck or posedge clr ) begin
if(clr==1) begin
nbit<=0; rreg<=8'hFF; end
else begin
if(mlb==0) //LSB first, din@msb -> right shift
begin rreg<={din,rreg[7:1]}; end
else //MSB first, din@lsb -> left shift
begin rreg<={rreg[6:0],din}; end
nbit<=nbit+1;
end //rst ends here
end //always ends here
 
 
//setup @ falling edge (send dout)
always@(negedge sck or posedge clr) begin
if(clr==1) begin
treg=8'hFF; dout=1;
end
else begin
if(nbit==0) begin //load data into TREG
treg=tdat; dout=mlb?treg[7]:treg[0];
end //nbit_if
else begin
if(mlb==0) //LSB first, shift right
begin treg={1'b1,treg[7:1]}; dout=treg[0]; end
else//MSB first shift LEFT
begin treg={treg[6:0],1'b1}; dout=treg[7]; end
end //nbit_else ends here
end //rst ends here
end //always ends here
 
endmodule
 
/spi_verilog_master_slave/branches/verilog/TB_MAS-SLV.v
0,0 → 1,124
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Design Name: SPI MASTER-SLAVE TESTBENCH
* Module Name: TB_SPI_MasSlv
* Project Name: SPI
* Target Devices: Spartan 3E
* Designed by: Santhosh G
*
*
* Author: Santhosh
* santhoshg90@gmail.com
*
* Copyright - 2014 - Santhosh G
* - OpenCores.org
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* THIS IS PROVIDED WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESSFOR A PARTICULAR PURPOSE. IN CASE THE AUTHOR IS RESPONSIBEL FOR
* THE DAMAGES CAUSED BY USE OF THIS. FOR EDUCATIONAL PURPOSE ONLY.
*
* THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT
* RESTRICTION PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT
* REMOVED FROM THE FILE AND THAT ANY DERIVATIVE WORK CONTAINS
* THE ORIGINAL COPYRIGHT NOTICE AND THE ASSOCIATED DISCLAIMER.
*
* This source file is free software; you can redistribute it
* * and/or modify it under the terms of the GNU Lesser General
* Public License as published by the Free Software Foundation;
* either version 2.1 of the License, or (at your option) any
* later version.
*
* You should have received a copy of the GNU Lesser General
* Public License along with this source; if not, download it
* from http://www.opencores.org/lgpl.shtml
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
`timescale 1ns/10ps
module TB_SPI_MasSlv;
//mas
reg rstb;
reg clk;
reg mlb;
reg start;
reg [7:0] M_trans;
reg [1:0] cdiv;
wire miso;
wire ss;
wire sck;
wire mosi;
wire M_done;
wire [7:0] M_rec;
 
reg ten;
reg [7:0] s_tdata;
wire s_done;
wire [7:0] s_receive;
 
parameter PERIOD = 50;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 100;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
 
initial #5100 $stop;
 
spi_master MAS (
.rstb(rstb),
.clk(clk),
.mlb(mlb),
.start(start),
.tdat(M_trans),
.cdiv(cdiv),
.din(miso),
.ss(ss),
.sck(sck),
.dout(mosi),
.done(M_done),
.rdata(M_rec));
 
SPI_slave SLV (
.rstb(rstb),
.ten(ten),
.tdata(s_tdata),
.mlb(mlb),
.ss(ss),
.sck(sck),
.sdin(mosi),
.sdout(miso),
.done(s_done),
.rdata(s_receive));
 
initial begin
#15 rstb = 1'b0;
#50 rstb = 1'b1;start = 1'b0;
cdiv = 2'b00; ten=1; mlb = 1'b0;
M_trans = 8'hFE; // M_trans = 8'h7C;
s_tdata=8'h01; //s_tdata=8'hAC; 8'b11110000
#125 start = 1'b1;
#100 start = 1'b0;
#1200 mlb = 1'b1; cdiv=2'b01; M_trans=8'h1C;s_tdata=8'h64;
#100 start = 1'b1;
#100 start = 1'b0;
#1500;
#1500;
#1000;
end
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.