OpenCores
URL https://opencores.org/ocsvn/spiadc/spiadc/trunk

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/TestBench/RecvMasterTb.vhd
0,0 → 1,92
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
 
-- PROGRAM "Quartus II"
-- VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
-- CREATED ON "Sun Jun 14 20:47:40 2009"
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY work;
 
ENTITY RecvMasterTb IS
PORT
(
CLC : IN STD_LOGIC;
Start : IN STD_LOGIC;
CotinueStart : IN STD_LOGIC;
ShutDown : IN STD_LOGIC;
Res : IN STD_LOGIC;
SDI : IN STD_LOGIC;
SCK : OUT STD_LOGIC;
nSS : OUT STD_LOGIC;
ready : OUT STD_LOGIC;
SDO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END RecvMasterTb;
 
LIBRARY lib;
USE lib.all;
ARCHITECTURE bdf_type OF RecvMasterTb IS
 
COMPONENT adcrecv
GENERIC (DataLen : INTEGER;
DataOffset : INTEGER;
QuietLen : INTEGER;
SDLen : INTEGER;
SDMax : INTEGER;
SPILen : INTEGER
);
PORT(CLK : IN STD_LOGIC;
Start : IN STD_LOGIC;
ContinueStart : IN STD_LOGIC;
ShutDown : IN STD_LOGIC;
reset : IN STD_LOGIC;
SDI : IN STD_LOGIC;
SCK : OUT STD_LOGIC;
nSS : OUT STD_LOGIC;
Ready : OUT STD_LOGIC;
Shift : OUT STD_LOGIC;
DQ : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
 
 
 
BEGIN
 
 
 
b2v_inst : adcrecv
GENERIC MAP(DataLen => 10,
DataOffset => 6,
QuietLen => 1,
SDLen => 1,
SDMax => 10,
SPILen => 16
)
PORT MAP(CLK => CLC,
Start => Start,
ContinueStart => CotinueStart,
ShutDown => ShutDown,
reset => Res,
SDI => SDI,
SCK => SCK,
nSS => nSS,
Ready => ready,
DQ => SDO);
 
 
END bdf_type;
/TestBench/recv-master-tb.vht
0,0 → 1,318
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
 
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "06/12/2009 19:55:56"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : RecvMasterTb
--
-- Simulation tool : 3rd Party
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY RecvMasterTb_vhd_vec_tst IS
END RecvMasterTb_vhd_vec_tst;
ARCHITECTURE RecvMasterTb_arch OF RecvMasterTb_vhd_vec_tst IS
-- constants
-- signals
SIGNAL CLC : STD_LOGIC;
SIGNAL CotinueStart : STD_LOGIC;
SIGNAL nSS : STD_LOGIC;
SIGNAL ready : STD_LOGIC;
SIGNAL Res : STD_LOGIC;
SIGNAL SCK : STD_LOGIC;
SIGNAL SDI : STD_LOGIC;
SIGNAL SDO : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL ShutDown : STD_LOGIC;
SIGNAL Start : STD_LOGIC;
COMPONENT RecvMasterTb
PORT (
CLC : IN STD_LOGIC;
CotinueStart : IN STD_LOGIC;
nSS : OUT STD_LOGIC;
ready : OUT STD_LOGIC;
Res : IN STD_LOGIC;
SCK : OUT STD_LOGIC;
SDI : IN STD_LOGIC;
SDO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
ShutDown : IN STD_LOGIC;
Start : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : RecvMasterTb
PORT MAP (
-- list connections between master ports and signals
CLC => CLC,
CotinueStart => CotinueStart,
nSS => nSS,
ready => ready,
Res => Res,
SCK => SCK,
SDI => SDI,
SDO => SDO,
ShutDown => ShutDown,
Start => Start
);
 
-- CLC
t_prcs_CLC: PROCESS
BEGIN
LOOP
CLC <= '0';
WAIT FOR 25000 ps;
CLC <= '1';
WAIT FOR 25000 ps;
IF (NOW >= 100000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_CLC;
 
-- CotinueStart
t_prcs_CotinueStart: PROCESS
BEGIN
CotinueStart <= '0';
WAIT FOR 25600000 ps;
CotinueStart <= '1';
WAIT FOR 3200000 ps;
CotinueStart <= '0';
WAIT FOR 3200000 ps;
CotinueStart <= '1';
WAIT FOR 3840000 ps;
CotinueStart <= '0';
WAIT;
END PROCESS t_prcs_CotinueStart;
 
-- Res
t_prcs_Res: PROCESS
BEGIN
Res <= '0';
WAIT FOR 20000 ps;
Res <= '1';
WAIT FOR 40000 ps;
Res <= '0';
WAIT;
END PROCESS t_prcs_Res;
 
-- ShutDown
t_prcs_ShutDown: PROCESS
BEGIN
ShutDown <= '0';
WAIT FOR 8800000 ps;
ShutDown <= '1';
WAIT FOR 3200000 ps;
ShutDown <= '0';
WAIT FOR 3040000 ps;
ShutDown <= '1';
WAIT FOR 4160000 ps;
ShutDown <= '0';
WAIT FOR 1600000 ps;
ShutDown <= '1';
WAIT FOR 960000 ps;
ShutDown <= '0';
WAIT;
END PROCESS t_prcs_ShutDown;
 
-- Start
t_prcs_Start: PROCESS
BEGIN
Start <= '0';
WAIT FOR 420000 ps;
Start <= '1';
WAIT FOR 20000 ps;
Start <= '0';
WAIT FOR 2440000 ps;
Start <= '1';
WAIT FOR 5040000 ps;
Start <= '0';
WAIT FOR 1120000 ps;
Start <= '1';
WAIT FOR 4640000 ps;
Start <= '0';
WAIT FOR 3440000 ps;
Start <= '1';
WAIT FOR 160000 ps;
Start <= '0';
WAIT FOR 8000000 ps;
Start <= '1';
WAIT FOR 160000 ps;
Start <= '0';
WAIT FOR 4800000 ps;
Start <= '1';
WAIT FOR 160000 ps;
Start <= '0';
WAIT FOR 1600000 ps;
Start <= '1';
WAIT FOR 160000 ps;
Start <= '0';
WAIT;
END PROCESS t_prcs_Start;
 
-- SDI
t_prcs_SDI: PROCESS
BEGIN
SDI <= '0';
WAIT FOR 3120000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 480000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 160000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 320000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 960000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 160000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 480000 ps;
SDI <= '0';
WAIT FOR 800000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 560000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 320000 ps;
SDI <= '1';
WAIT FOR 320000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 400000 ps;
SDI <= '0';
WAIT FOR 11760000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 480000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 160000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 320000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 960000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 160000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 480000 ps;
SDI <= '0';
WAIT FOR 800000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 560000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 320000 ps;
SDI <= '1';
WAIT FOR 320000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 240000 ps;
SDI <= '1';
WAIT FOR 240000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 160000 ps;
SDI <= '1';
WAIT FOR 80000 ps;
SDI <= '0';
WAIT FOR 400000 ps;
SDI <= '1';
WAIT FOR 400000 ps;
SDI <= '0';
WAIT;
END PROCESS t_prcs_SDI;
END RecvMasterTb_arch;
/TestBench/recv-master-tb.vwf
0,0 → 1,311
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 100000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("CLC")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("CotinueStart")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("Res")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("ShutDown")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("Start")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("SDI")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
TRANSITION_LIST("CLC")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2000;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
 
TRANSITION_LIST("CotinueStart")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 25600.0;
LEVEL 1 FOR 3200.0;
LEVEL 0 FOR 3200.0;
LEVEL 1 FOR 3840.0;
LEVEL 0 FOR 64160.0;
}
}
 
TRANSITION_LIST("Res")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 99940.0;
}
}
 
TRANSITION_LIST("ShutDown")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 8800.0;
LEVEL 1 FOR 3200.0;
LEVEL 0 FOR 3040.0;
LEVEL 1 FOR 4160.0;
LEVEL 0 FOR 1600.0;
LEVEL 1 FOR 960.0;
LEVEL 0 FOR 78240.0;
}
}
 
TRANSITION_LIST("Start")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 420.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 2440.0;
LEVEL 1 FOR 5040.0;
LEVEL 0 FOR 1120.0;
LEVEL 1 FOR 4640.0;
LEVEL 0 FOR 3440.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 8000.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 4800.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 1600.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 67840.0;
}
}
 
TRANSITION_LIST("SDI")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 3120.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 480.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 960.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 480.0;
LEVEL 0 FOR 800.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
LEVEL 0 FOR 11760.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 480.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 960.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 480.0;
LEVEL 0 FOR 800.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 560.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 320.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
LEVEL 0 FOR 63840.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "CLC";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "CotinueStart";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "Res";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "ShutDown";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "Start";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "SDI";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
 
TIME_BAR
{
TIME = 13125;
MASTER = TRUE;
}
;
/AdcRecv.bsf
0,0 → 1,137
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 216 176)
(text "AdcRecv" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 144 25 156)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "CLK" (rect 0 0 21 12)(font "Arial" ))
(text "CLK" (rect 21 27 42 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "Start" (rect 0 0 23 12)(font "Arial" ))
(text "Start" (rect 21 43 44 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "ContinueStart" (rect 0 0 67 12)(font "Arial" ))
(text "ContinueStart" (rect 21 59 88 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "ShutDown" (rect 0 0 49 12)(font "Arial" ))
(text "ShutDown" (rect 21 75 70 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "reset" (rect 0 0 24 12)(font "Arial" ))
(text "reset" (rect 21 91 45 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "SDI" (rect 0 0 18 12)(font "Arial" ))
(text "SDI" (rect 21 107 39 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 200 32)
(output)
(text "SCK" (rect 0 0 22 12)(font "Arial" ))
(text "SCK" (rect 157 27 179 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 1))
)
(port
(pt 200 48)
(output)
(text "nSS" (rect 0 0 20 12)(font "Arial" ))
(text "nSS" (rect 159 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 1))
)
(port
(pt 200 64)
(output)
(text "DQ[datalen-1..0]" (rect 0 0 81 12)(font "Arial" ))
(text "DQ[datalen-1..0]" (rect 98 59 179 71)(font "Arial" ))
(line (pt 200 64)(pt 184 64)(line_width 3))
)
(port
(pt 200 80)
(output)
(text "Ready" (rect 0 0 33 12)(font "Arial" ))
(text "Ready" (rect 146 75 179 87)(font "Arial" ))
(line (pt 200 80)(pt 184 80)(line_width 1))
)
(port
(pt 200 96)
(output)
(text "Shift" (rect 0 0 23 12)(font "Arial" ))
(text "Shift" (rect 156 91 179 103)(font "Arial" ))
(line (pt 200 96)(pt 184 96)(line_width 1))
)
(parameter
"SPILen"
"16"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DataLen"
"16"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"DataOffset"
"0"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SDLen"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"SDMax"
"10"
""
(type "PARAMETER_SIGNED_DEC") )
(parameter
"QuietLen"
"1"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 184 144)(line_width 1))
)
(annotation_block (parameter)(rect 216 -64 316 16))
)
/adcrecv.vhd
0,0 → 1,258
-- synthesis library lib
 
--------------------------------------------------------------------
-- Project : SPI receivers master
-- Author : AlexRayne
-- Date : 2009.03.16.03
-- File :
-- Design :
--------------------------------------------------------------------
 
 
 
 
 
 
 
 
-- Description : SPI master-receiver minimalistic costs
-- intended for loading ADC AD747x, capable produce shut-down frames.
-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
-- data loads on rising front SCK, last frame bit have no falling edge SCK,
-- SCK='1' durung inactive period.
--------------------------------------------------------------------
-- $Log$
--------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
-- Entity Declaration
ENTITY AdcRecv IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
GENERIC(
SPILen : positive := 16;
DataLen : positive := 16;
DataOffset : natural := 0;
-- ShutDownLen sets len of short spi sequence for poweroff purposes
SDLen : natural := 1;
SDMax : natural := 10;
-- requred TimeOut before start
QuietLen : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
Start : IN STD_LOGIC;
 
-- if false then spi produce controling sequense of xfer entry and inter-frame pause
-- else spi start new frame xfer immeidate after completing current frame
ContinueStart : in STD_LOGIC := '0';
ShutDown: IN STD_LOGIC;
reset : IN STD_LOGIC;
 
SDI : IN STD_LOGIC;
SCK : OUT STD_LOGIC;
nSS : OUT STD_LOGIC;
 
DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
-- rising edge of ready can be used for loading DQ data to dest.
Ready : OUT STD_LOGIC;
-- used to expand load logic to parallel loading registers, to make a multi chanel reciever
Shift : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END AdcRecv;
 
 
-- Architecture Body
 
ARCHITECTURE BEH OF AdcRecv IS
signal SS : std_logic;
signal Data : std_logic_vector(DataLen-1 downto 0);
signal iSCK : std_logic;
signal iReady : std_logic;
 
subtype BitIndex is natural range 0 to SPILen-1;
signal BitNo : BitIndex;
 
subtype QuietIndex is natural range 0 to QuietLen;
signal QuietCnt : QuietIndex;
signal QuietOk : std_logic;
 
signal isLastBit : std_logic;
signal isLastDataBit: std_logic;
signal isFirstBit : std_logic;
signal Transfer : std_logic := '0';
signal PrepTransfer : std_logic := '0';
signal ReceiveWindow : std_logic := '0';
 
type States is ( stSerLoading, stQuietCheck); --stReady,
signal FSMState : States;
signal NextState : States;
 
signal SDEnough : std_logic;
signal SDDone : std_logic;
signal NeedSD : std_logic;
signal Enable : std_logic;
begin
BitCounter : process(CLK, reset, Enable, Transfer, isLastBit, FSMState) is begin
if (reset = '1') or (FSMState = stQuietCheck) then -- (Enable = '0') then
BitNo <= 0;
else
if falling_edge(CLK) then
if isLastBit = '1' then
BitNo <= 0;
else
if Transfer = '1' then
BitNo <= BitNo+1;
end if;
end if;
end if;
end if;
end process;
 
isFirstBit <= '1' when (BitNo = 0) else '0';
isLastBit <= '1' when (BitNo = SPILen-1) else '0';
isLastDataBit <= '1'when (BitNo = DataOffset + DataLen-1) else '0';
 
ReceiveWindow <= '1' when (BitNo >= DataOffset) and (BitNo <= DataOffset + DataLen-1)
else '0';
 
SDEnough <= '1' when (BitNo >= SDLen) and (BitNo < SDMax) else '0';
 
SDmonitor : process(SS, enable, iSCK, NeedSD, SDEnough, Reset) is begin
if (reset = '1') or (iSCK = '0') then
SDDone <= '0';
elsif falling_edge(enable) then
SDDone <= SDEnough;
end if;
end process;
 
Qsafer: if QuietLen > 1 generate
QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
 
QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
if (reset = '1')
or (FSMState = stSerLoading)
then
QuietCnt <= 0;
else
if rising_edge(CLK) then
if QuietOk = '0' then
QuietCnt <= QuietCnt+1;
end if;
end if;
end if;
end process;
end generate;
 
EmptyQsafer: if QuietLen <= 1 generate
QuietOk <= '1';
end generate;
 
EnableReg: process(Start, NeedSD, iReady, NextState, FSMState, CLK, Reset) is begin
if (reset = '1') then
Enable <= '0';
elsif rising_edge(CLK) then
if (iReady and (Start or NeedSD)) = '1' then
Enable <= '1';
else
if (FSMState = stSerLoading) and (NextState /= stSerLoading) then
Enable <= '0';
end if;
end if;
end if;
end process;
 
SDRequest: process(ShutDown, SDDone, Reset) is begin
if (Reset = '1') or (SDDone = '1') then
NeedSD <= '0';
elsif (ShutDown = '1') and (SDDone = '0') then
NeedSD <= '1';
end if;
end process;
-- NeedSD <= ShutDown and not SDDone;
-- NeedSD <= '1' when ShutDown and not SDDone else
-- '0' when ;
 
FSMStepper : process(NextState, CLK, Reset) is begin
if reset = '1' then
FSMState <= stQuietCheck;
elsif falling_edge(CLK) then
FSMState <= NextState;
end if;
end process;
 
FSM : process(FSMState, CLK, QuietOk, isLastBit, ContinueStart
, ShutDown, SDEnough, Start, NeedSD, Reset, Enable)
is begin
case FSMState is
when stSerLoading =>
if (ShutDown = '1') and (SDEnough = '1') then
NextState <= stQuietCheck;
elsif (isLastBit = '1') then
if ContinueStart = '0' then
NextState <= stQuietCheck;
else
NextState <= stSerLoading;--stReady;
end if;
else
NextState <= stSerLoading;
end if;
when stQuietCheck =>
if (QuietOk = '1') then
if ((Enable = '1') or (NeedSD = '1')) then
NextState <= stSerLoading;
else
NextState <= stQuietCheck;--stReady;
end if;
else
NextState <= stQuietCheck;
end if;
when others =>
NextState <= stQuietCheck;
end case;
end process;
 
Transfer <= '1' when (FSMState = stSerLoading) else '0';
-- SS must contain gap with '1' about 1/2cycle on SCK at start and end of frames
SS <= Transfer or Enable;
iSCK <= CLK or not Enable; --when (FSMState = stSerLoading) else '1';
 
nSS <= not SS;
SCK <= iSCK;
 
DataCell : process (Data, CLK, reset, ReceiveWindow, SS) is begin
if reset = '1' then
Data <= (others => '0');
elsif rising_edge(CLK) then
if (ReceiveWindow = '1') and (SS = '1') then
Data(Data'high downto 1) <= Data(Data'high-1 downto 0);
Data(0) <= SDI;
end if;
end if;
end process;
DQ <= Data;
Shift <= CLK and ReceiveWindow;
 
readyMoitor: process(CLK, FSMState, isFirstbit, isLastDataBit, Reset) is begin
if (reset = '1') or (FSMState = stQuietCheck) then
iready <= '1';
elsif (FSMState = stSerLoading) and (isFirstbit = '1') and (CLK = '1') then
iready <= '0';
elsif falling_edge(CLK) then
if isLastDataBit = '1' then
iready <= '1';
end if;
end if;
end process;
 
Ready <= iReady;
end architecture BEH;

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