URL
https://opencores.org/ocsvn/spiadc/spiadc/trunk
Subversion Repositories spiadc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spiadc/trunk
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/AdcRecv.bsf
100,6 → 100,13
(text "Shift" (rect 156 91 179 103)(font "Arial" )) |
(line (pt 200 96)(pt 184 96)(line_width 1)) |
) |
(port |
(pt 200 112) |
(output) |
(text "Sleeping" (rect 0 0 41 12)(font "Arial" )) |
(text "Sleeping" (rect 138 107 179 119)(font "Arial" )) |
(line (pt 200 112)(pt 184 112)(line_width 1)) |
) |
(parameter |
"SPILen" |
"16" |
/adcrecv.vhd
10,8 → 10,8
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21,6 → 21,28
-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start, |
-- data loads on rising front SCK, last frame bit have no falling edge SCK, |
-- SCK='1' durung inactive period. |
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-- SDLen, SDMax: |
-- sets len of short spi sequence for poweroff purposes short (SDLen) and maximum (SDMax) length |
-- QuietLen: |
-- requred TimeOut before start |
-- Start: |
--Start lock on rising CLK, and changes ignores during transmition. if one still high after transmition |
-- ends, then new frame starts after QuietLen timeout if ContinueStart not active |
-- ContinueStart: |
-- if false then spi produce controling sequense of xfer entry and inter-frame pause |
-- else spi start new frame xfer immeidate after completing current frame |
-- ShutDown |
-- locks by high level, after Shuting down complete new SutDown sequence can be forced by Start |
-- if one activate during transmition, then it forces current frame to close if it can (beetween SDLen..SDMax bits) |
-- or generate short shutdown frame after completing current frae else |
-- Ready: |
-- rising edge of ready can be used for loading DQ data to dest. |
-- Shift: |
-- shift clock for internal data register intended to expand load logic to parallel loading registers, |
-- to make a multi chanel reciever |
-- Sleeping |
-- State of ADC power mode - is it shutdowned. |
-------------------------------------------------------------------- |
-- $Log$ |
-------------------------------------------------------------------- |
35,10 → 57,8
SPILen : positive := 16; |
DataLen : positive := 16; |
DataOffset : natural := 0; |
-- ShutDownLen sets len of short spi sequence for poweroff purposes |
SDLen : natural := 1; |
SDMax : natural := 10; |
-- requred TimeOut before start |
QuietLen : natural := 1 |
); |
PORT |
45,9 → 65,6
( |
CLK : IN STD_LOGIC; |
Start : IN STD_LOGIC; |
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-- if false then spi produce controling sequense of xfer entry and inter-frame pause |
-- else spi start new frame xfer immeidate after completing current frame |
ContinueStart : in STD_LOGIC := '0'; |
ShutDown: IN STD_LOGIC; |
reset : IN STD_LOGIC; |
57,10 → 74,9
nSS : OUT STD_LOGIC; |
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DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0); |
-- rising edge of ready can be used for loading DQ data to dest. |
Ready : OUT STD_LOGIC; |
-- used to expand load logic to parallel loading registers, to make a multi chanel reciever |
Shift : OUT STD_LOGIC |
Shift : OUT STD_LOGIC; |
Sleeping : OUT STD_LOGIC |
); |
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! |
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131,6 → 147,8
SDDone <= SDEnough; |
end if; |
end process; |
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Sleeping <= SDDone; |
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Qsafer: if QuietLen > 1 generate |
QuietOk <= '1' when (QuietCnt >= QuietLen) else '0'; |