Subversion Repositories spimaster

/trunk/syn/spiMaster.qpf File deleted

/trunk/syn/spiMaster.qsf File deleted \ No newline at end of file

/trunk/bench/testHarness.v File deleted

/trunk/bench/testCase0.v File deleted

/trunk/model/wb_master_model.v File deleted

/trunk/model/sdModel.v File deleted

/trunk/RTL/readWriteSPIWireData.v File deleted \ No newline at end of file

/trunk/RTL/readWriteSDBlock.v File deleted \ No newline at end of file

/trunk/RTL/initSD.v File deleted \ No newline at end of file

/trunk/RTL/sm_RxFifo.v File deleted

/trunk/RTL/sm_TxFifo.v File deleted

/trunk/RTL/sm_fifoRTL.v File deleted

/trunk/RTL/spiMaster_defines.v File deleted

/trunk/RTL/timescale.v File deleted

/trunk/RTL/spiMaster.v File deleted

/trunk/RTL/sm_RxFifoBI.v File deleted

/trunk/RTL/ctrlStsRegBI.v File deleted

/trunk/RTL/sm_dpMem_dc.v File deleted

/trunk/RTL/sm_TxFifoBI.v File deleted

/trunk/RTL/spiTxRxData.v File deleted

/trunk/RTL/sendCmd.v File deleted \ No newline at end of file

/trunk/RTL/spiCtrl.v File deleted \ No newline at end of file

/trunk/RTL/spiMasterWishBoneBI.v File deleted

/trunk/doc/spiMaster_Specification.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/doc/spiMaster_Specification.pdf

trunk/doc/spiMaster_Specification.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/spiMaster_FSM.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/spiMaster_FSM.pdf =================================================================== --- trunk/doc/spiMaster_FSM.pdf (revision 3) +++ trunk/doc/spiMaster_FSM.pdf (nonexistent)

trunk/doc/spiMaster_FSM.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/src/spiMaster_Specification.sxw =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/spiMaster_Specification.sxw =================================================================== --- trunk/doc/src/spiMaster_Specification.sxw (revision 3) +++ trunk/doc/src/spiMaster_Specification.sxw (nonexistent)

trunk/doc/src/spiMaster_Specification.sxw Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/Aldec/design0/fsm.set =================================================================== --- trunk/Aldec/design0/fsm.set (revision 3) +++ trunk/Aldec/design0/fsm.set (nonexistent) @@ -1,5 +0,0 @@ -FSMSET_CUTHEADER=1 -FSMSET_GENCOMMENTS=1 -FSMSET_USEDEFINE=1 -FSMSET_OMITGENNULL=0 -FSMSET_ENABLEPARSING=1 Index: trunk/Aldec/design0/design0.adf =================================================================== --- trunk/Aldec/design0/design0.adf (revision 3) +++ trunk/Aldec/design0/design0.adf (nonexistent) @@ -1,48 +0,0 @@ -[Project] -Current Flow=Generic -VCS=0 -version=1 -Current Config=compile - -[Configurations] -compile=design0 - -[Library] -design0=.\design0.LIB - -[$LibMap$] -design0=. - -[Settings] -FLOW_TYPE=HDL -LANGUAGE=VHDL - -[Files] -/readWriteSPIWireData.asf=-1 -/initSD.asf=-1 -/sendCmd.asf=-1 -/readWriteSDBlock.asf=-1 -/spiCtrl.asf=-1 - -[Files.Data] -.\src\readWriteSPIWireData.asf=State Diagram -.\src\initSD.asf=State Diagram -.\src\sendCmd.asf=State Diagram -.\src\readWriteSDBlock.asf=State Diagram -.\src\spiCtrl.asf=State Diagram - -[file_out:/initSD.asf] -/\compile\initSD.v=-1 - -[file_out:/sendCmd.asf] -/\compile\sendCmd.v=-1 - -[file_out:/readWriteSDBlock.asf] -/\compile\readWriteSDBlock.v=-1 - -[file_out:/spiCtrl.asf] -/\compile\spiCtrl.v=-1 - -[file_out:/readWriteSPIWireData.asf] -/\compile\readWriteSPIWireData.v=-1 - Index: trunk/Aldec/design0/src/readWriteSPIWireData.asf =================================================================== --- trunk/Aldec/design0/src/readWriteSPIWireData.asf (revision 3) +++ trunk/Aldec/design0/src/readWriteSPIWireData.asf (nonexistent) @@ -1,121 +0,0 @@ -VERSION=1.15 -HEADER -FILE="readWriteSPIWireData.asf" -FID=4788d213 -LANGUAGE=VERILOG -ENTITY="readWriteSPIWireData" -FRAMES=ON -FREEOID=95 -"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSPIWireData.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// Wait for TX data bytes. When data is ready generate\n//// SPI TX data, SPI CLK, and read SPI RX data\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" -END -BUNDLES -B T "Declarations" 0,0,255 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0 -B T "Conditions" 0,0,0 0 0 0 255,255,255 0 2844 0 0110 1 "Arial" 0 -B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Actions" 0,0,0 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0 -B T "Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 0 -B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 -B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 -B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -B T "State Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 4 -B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 -B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -END -INSTHEADER 1 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 5000,5000 10000,10000 -END -INSTHEADER 57 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -OBJECTS -G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: readWriteSPIWireData" -A 5 0 1 TEXT "Actions" | 30673,274317 1 0 0 "-- diagram ACTION" -F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,246400 -L 7 6 0 TEXT "Labels" | 31400,243400 1 0 0 "rwSPISt" -L 8 9 0 TEXT "Labels" | 167524,266756 1 0 0 "txDataFull" -I 9 0 2 Builtin InPort | 161524,266756 "" "" -L 10 11 0 TEXT "Labels" | 165076,262648 1 0 0 "txDataFullClr" -I 11 0 2 Builtin OutPort | 159076,262648 "" "" -L 12 13 0 TEXT "Labels" | 122918,264250 1 0 0 "rxDataRdySet" -I 13 0 2 Builtin OutPort | 116918,264250 "" "" -L 14 15 0 TEXT "Labels" | 167406,271658 1 0 0 "txDataIn[7:0]" -I 15 0 130 Builtin InPort | 161406,271658 "" "" -L 16 17 0 TEXT "Labels" | 123072,269174 1 0 0 "rxDataOut[7:0]" -I 17 0 130 Builtin OutPort | 117072,269174 "" "" -L 18 19 0 TEXT "State Labels" | 110704,231360 1 0 0 "WT_TX_DATA\n/0/" -S 19 6 0 ELLIPSE "States" | 110704,231360 6500 6500 -L 20 21 0 TEXT "State Labels" | 112226,189022 1 0 0 "CLK_HI\n/1/" -S 21 6 4096 ELLIPSE "States" | 112226,189022 6500 6500 -W 22 6 0 19 21 BEZIER "Transitions" | 110470,224884 110707,219468 110980,207626 111395,195467 -C 23 22 0 TEXT "Conditions" | 116947,226592 1 0 0 "txDataFull == 1'b1" -A 24 22 16 TEXT "Actions" | 104644,222649 1 0 0 "txDataShiftReg <= txDataIn;\nrxDataShiftReg <= 8'h00;\nbitCnt <= 4'h0;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b1;\ntxDataEmpty <= 1'b0;" -L 25 26 0 TEXT "Labels" | 85178,260017 1 0 0 "txDataShiftReg[7:0]" -I 26 0 130 Builtin Signal | 82178,260017 "" "" -L 27 28 0 TEXT "Labels" | 85450,264368 1 0 0 "bitCnt[3:0]" -I 28 0 130 Builtin Signal | 82450,264368 "" "" -L 29 30 0 TEXT "Labels" | 45301,255946 1 0 0 "clkDelay[7:0]" -I 30 0 130 Builtin InPort | 39301,255946 "" "" -L 31 32 0 TEXT "Labels" | 85178,269538 1 0 0 "clkDelayCnt[7:0]" -I 32 0 130 Builtin Signal | 82178,269538 "" "" -L 33 34 0 TEXT "State Labels" | 112064,143714 1 0 0 "CLK_LO\n/2/" -S 34 6 8192 ELLIPSE "States" | 112064,143714 6500 6500 -W 35 6 0 21 34 BEZIER "Transitions" | 111477,182571 110721,178461 111926,154930 111406,150180 -A 36 35 16 TEXT "Actions" | 117201,173770 1 0 0 "spiClkOut <= 1'b0;\nspiDataOut <= txDataShiftReg[7];\ntxDataShiftReg <= {txDataShiftReg[6:0], 1'b0};\nrxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn};\nclkDelayCnt <= 8'h00;" -A 40 34 4 TEXT "Actions" | 129744,145618 1 0 0 "clkDelayCnt <= clkDelayCnt + 1'b1;" -C 41 39 0 TEXT "Conditions" | 113864,136917 1 0 0 "bitCnt == 4'h8" -W 39 6 1 34 57 BEZIER "Transitions" | 112175,137251 112384,130999 112714,101841 111797,94879 -W 50 6 2 34 21 BEZIER "Transitions" | 108826,149348 101042,157950 83708,154801 80796,161835\ - 77884,168870 77971,186684 79172,191015 80374,195346\ - 85000,196884 88570,197360 92140,197836 101831,194594\ - 106220,191507 -A 51 50 16 TEXT "Actions" | 64275,179271 1 0 0 "spiClkOut <= 1'b1;\nbitCnt <= bitCnt + 1'b1;\nclkDelayCnt <= 8'h00;" -C 52 50 0 TEXT "Conditions" | 69697,159224 1 0 0 "clkDelayCnt == clkDelay" -A 53 21 4 TEXT "Actions" | 129906,194545 1 0 0 "clkDelayCnt <= clkDelayCnt + 1'b1;\ntxDataFullClr <= 1'b0;\nrxDataRdySet <= 1'b0;" -C 54 35 0 TEXT "Conditions" | 112616,182259 1 0 0 "clkDelayCnt == clkDelay" -L 56 57 0 TEXT "State Labels" | 112441,91219 1 0 0 "J1" -S 57 6 12292 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 111975,91295 3595 3595 -H 58 57 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -I 61 58 0 Builtin Entry | 96520,182880 -I 62 58 0 Builtin Exit | 123838,149654 -W 63 58 0 61 62 BEZIER "Transitions" | 100327,182880 105881,175159 115604,157376 121159,149654 -A 55 39 16 TEXT "Actions" | 101170,118509 1 0 0 "rxDataRdySet <= 1'b1;\nrxDataOut <= rxDataShiftReg;" -A 79 78 4 TEXT "Actions" | 172448,235984 1 0 0 "bitCnt <= 4'h0;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b0;\nrxDataRdySet <= 1'b0;\ntxDataShiftReg <= 8'h00;\nrxDataShiftReg <= 8'h00;\nrxDataOut <= 8'h00;\nspiDataOut <= 1'b0;\nspiClkOut <= 1'b0;\ntxDataEmpty <= 1'b0;" -S 78 6 16384 ELLIPSE "States" | 163200,234352 6500 6500 -L 77 78 0 TEXT "State Labels" | 163200,234352 1 0 0 "ST_RW_WIRE\n/3/" -C 75 70 0 TEXT "Conditions" | 67748,241498 1 0 0 "rst == 1'b1" -I 74 0 2 Builtin InPort | 195700,267632 "" "" -L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" -I 72 0 3 Builtin InPort | 195700,272800 "" "" -L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" -W 70 6 0 69 78 BEZIER "Transitions" | 53584,240424 67019,243331 142652,244275 157000,236303 -I 69 6 0 Builtin Reset | 53584,240424 -W 65 6 1 57 21 BEZIER "Transitions" | 108870,93105 102326,112538 73109,121258 64708,125153\ - 56308,129049 47906,146800 45670,157910 43435,169021\ - 42893,195716 46449,203811 50006,211907 64777,217599\ - 73008,216616 81239,215634 100244,201596 107791,193773 -C 66 65 0 TEXT "Conditions" | 72805,108285 1 0 0 "txDataFull == 1'b1" -W 67 6 2 57 19 BEZIER "Transitions" | 108779,92940 102622,102639 71923,91036 67388,98354\ - 62853,105673 50345,122275 43604,135689 36864,149103\ - 35643,196122 41029,209502 46416,222883 69180,229387\ - 78123,230877 87066,232368 97753,231428 104224,231859 -A 68 65 16 TEXT "Actions" | 47229,151610 1 0 0 "txDataShiftReg <= txDataIn;\nbitCnt <= 3'b000;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b1;" -L 88 87 0 TEXT "Labels" | 85310,255376 1 0 0 "rxDataShiftReg[7:0]" -I 87 0 130 Builtin Signal | 82310,255376 "" "" -I 86 0 2 Builtin OutPort | 37191,270020 "" "" -L 85 86 0 TEXT "Labels" | 43191,270020 1 0 0 "spiClkOut" -I 84 0 2 Builtin InPort | 39102,260465 "" "" -L 83 84 0 TEXT "Labels" | 45102,260465 1 0 0 "spiDataIn" -I 82 0 2 Builtin OutPort | 37191,265379 "" "" -L 81 82 0 TEXT "Labels" | 43191,265379 1 0 0 "spiDataOut" -W 80 6 0 78 19 BEZIER "Transitions" | 156735,233684 145855,233140 128082,232022 117202,231478 -A 92 19 4 TEXT "Actions" | 71554,227603 1 0 0 "rxDataRdySet <= 1'b0;\ntxDataEmpty <= 1'b1;" -L 93 94 0 TEXT "Labels" | 165150,258150 1 0 0 "txDataEmpty" -I 94 0 2 Builtin OutPort | 159150,258150 "" "" -END Index: trunk/Aldec/design0/src/readWriteSDBlock.asf =================================================================== --- trunk/Aldec/design0/src/readWriteSDBlock.asf (revision 3) +++ trunk/Aldec/design0/src/readWriteSDBlock.asf (nonexistent) @@ -1,528 +0,0 @@ -VERSION=1.15 -HEADER -FILE="readWriteSDBlock.asf" -FID=4788d213 -LANGUAGE=VERILOG -ENTITY="readWriteSDBlock" -FRAMES=ON -FREEOID=575 -"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSDBlock.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or\n//// READ_SD_BLOCK, then write or read a 512 byte block\n//// of SD memory\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" -END -BUNDLES -B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 -B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 -B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 -B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 -B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 -B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 -B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -END -INSTHEADER 1 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 5000,5000 10000,10000 -END -INSTHEADER 84 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 118 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 130 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 169 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 224 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 302 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 327 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 337 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 389 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 415 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -OBJECTS -W 559 170 0 278 558 BEZIER "Transitions" | 159514,250710 169909,244734 184439,233702 194834,227726 -S 558 170 229376 ELLIPSE "States" | 199680,223395 6500 6500 -L 557 558 0 TEXT "State Labels" | 199680,223395 1 0 0 "DEL\n/47/" -A 556 315 4 TEXT "Actions" | 131150,199900 1 0 0 "sendCmdReq <= 1'b0;" -A 555 105 4 TEXT "Actions" | 131275,200525 1 0 0 "sendCmdReq <= 1'b0;" -I 554 0 130 Builtin Signal | 33764,246565 "" "" -L 553 554 0 TEXT "Labels" | 36764,246565 1 0 0 "locRespByte[7:0]" -I 552 0 130 Builtin Signal | 160575,273050 "" "" -L 551 552 0 TEXT "Labels" | 163575,273050 1 0 0 "timeOutCnt[11:0]" -I 548 0 130 Builtin InPort | 32700,254660 "" "" -L 547 548 0 TEXT "Labels" | 38700,254660 1 0 0 "blockAddr[31:0]" -I 546 0 130 Builtin Signal | 161380,256608 "" "" -L 545 546 0 TEXT "Labels" | 164380,256608 1 0 0 "delCnt2[7:0]" -I 544 0 130 Builtin Signal | 161114,261928 "" "" -W 287 170 3 273 278 BEZIER "Transitions" | 153140,203509 147585,209132 136504,218759 133963,224585\ - 131423,230411 132372,242472 134709,246197 137046,249923\ - 143477,251737 147677,253159 -C 283 275 0 TEXT "Conditions" | 163404,220919 1 0 0 "rxDataRdy == 1'b1" -L 282 273 0 TEXT "State Labels" | 158403,199697 1 0 0 "CHK_RESP\n/20/" -L 281 280 0 TEXT "State Labels" | 155702,223714 1 0 0 "REQ_RESP_FIN\n/22/" -S 280 170 106496 ELLIPSE "States" | 155702,223714 6500 6500 -L 279 278 0 TEXT "State Labels" | 154080,254276 1 0 0 "REQ_RESP_ST\n/21/" -S 278 170 102400 ELLIPSE "States" | 154080,254276 6500 6500 -I 277 170 0 Builtin Exit | 145690,169066 -A 276 275 16 TEXT "Actions" | 150887,216503 1 0 0 "locRespByte <= rxDataIn;" -W 275 170 0 280 273 BEZIER "Transitions" | 156440,217258 156900,213346 157290,210028 157662,206152 -S 273 170 98304 ELLIPSE "States" | 158403,199697 6500 6500 -G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: readWriteSDBlock" -A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION" -F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,27210 212900,223210 -L 7 6 0 TEXT "Labels" | 32996,218270 1 0 0 "rwBlkSt" -A 574 348 16 TEXT "Actions" | 112284,154324 1 0 0 "locRespByte <= rxDataIn;" -A 573 374 16 TEXT "Actions" | 60519,153465 1 0 0 "timeOutCnt <= timeOutCnt + 1'b1;\ndelCnt1 <= 8'h00;" -A 572 239 16 TEXT "Actions" | 42138,190870 1 0 0 "timeOutCnt <= timeOutCnt + 1'b1;" -A 571 235 16 TEXT "Actions" | 97926,168996 1 0 0 "locRespByte <= rxDataIn;" -A 570 380 4 TEXT "Actions" | 118523,190933 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" -C 569 459 0 TEXT "Conditions" | 151001,57686 1 0 0 "txDataEmpty == 1'b1" -C 568 456 0 TEXT "Conditions" | 82775,122525 1 0 0 "loopCnt == 9'b000000000" -C 566 296 0 TEXT "Conditions" | 164031,44934 1 0 0 "txDataEmpty == 1'b1" -I 565 0 2 Builtin InPort | 116956,228328 "" "" -L 564 565 0 TEXT "Labels" | 122956,228328 1 0 0 "txDataEmpty" -A 563 562 16 TEXT "Actions" | 167684,228749 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" -W 562 170 0 558 280 BEZIER "Transitions" | 193184,223621 184656,223621 170729,223805 162201,223805 -A 560 559 16 TEXT "Actions" | 163700,256139 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\ntimeOutCnt <= timeOutCnt + 1'b1;\nrxDataRdyClr <= 1'b1;" -L 303 302 0 TEXT "State Labels" | 155866,114847 1 0 0 "RD_CMD" -S 302 6 110596 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155866,114847 6500 6500 -W 301 6 0 169 224 BEZIER "Transitions" | 116491,60040 116453,54383 116661,57097 116661,51812 -W 300 6 0 130 169 BEZIER "Transitions" | 116096,82088 116419,75091 116419,77840 116311,72556 -W 299 6 0 84 130 BEZIER "Transitions" | 115210,103426 115637,98573 116012,99639 116012,95047 -W 298 6 0 128 84 BEZIER "Transitions" | 114213,168601 114343,164295 115365,122584 115190,116371 -W 297 6 0 82 128 BEZIER "Transitions" | 112965,189035 113095,186752 113278,183816 113408,181533 -W 296 170 0 204 278 BEZIER "Transitions" | 153459,62290 160628,57734 172959,48292 179659,46684\ - 186359,45076 198821,47756 201970,53652 205119,59548\ - 205253,80452 198486,92679 191719,104907 164517,132913\ - 153797,143566 143077,154219 127399,168825 124585,181588\ - 121771,194352 126193,230800 129007,242190 131821,253580\ - 138655,262692 141703,264836 144752,266980 150112,266444\ - 151686,265539 153261,264635 153717,262299 154186,260758 -A 295 291 16 TEXT "Actions" | 160354,178019 1 0 0 "writeError <= `WRITE_DATA_ERROR;" -C 294 291 0 TEXT "Conditions" | 162436,185390 1 0 0 "timeOutCnt == `WR_RESP_TOUT" -I 293 170 0 Builtin Link | 189438,166068 -L 292 293 0 TEXT "Labels" | 195438,166068 1 0 0 "WT_REQ" -W 291 170 1 273 293 BEZIER "Transitions" | 162433,194598 169133,187027 182738,171639 189438,164068 -C 290 288 0 TEXT "Conditions" | 126676,185877 1 0 0 "locRespByte[4:0] == 5'h5" -W 288 170 2 273 277 BEZIER "Transitions" | 156465,193495 155043,188346 148800,175094 145760,171065 -I 319 304 0 Builtin Link | 156420,111673 -I 318 304 0 Builtin Exit | 144032,98711 -A 317 305 4 TEXT "Actions" | 129068,241820 1 0 0 "cmdByte <= 8'h51; //CMD17 Block Read\ndataByte1 <= blockAddr[31:24];\ndataByte2 <= blockAddr[23:16];\ndataByte3 <= blockAddr[15:8];\ndataByte4 <= blockAddr[7:0];\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;" -L 316 315 0 TEXT "State Labels" | 113784,198353 1 0 0 "DEL\n/25/" -S 315 304 122880 ELLIPSE "States" | 113784,198353 6500 6500 -L 314 313 0 TEXT "State Labels" | 113242,173421 1 0 0 "WT_FIN\n/24/" -S 313 304 118784 ELLIPSE "States" | 113242,173421 6500 6500 -W 312 304 0 305 315 BEZIER "Transitions" | 113342,219069 113342,214801 113400,209100 113400,204832 -W 311 304 0 315 313 BEZIER "Transitions" | 113290,191878 113155,188152 113070,183636 112935,179910 -W 310 304 0 307 305 BEZIER "Transitions" | 74238,246230 83316,241623 99061,233757 108139,229150 -C 309 308 0 TEXT "Conditions" | 118993,167630 1 0 0 "sendCmdRdy == 1'b1" -W 308 304 0 313 327 BEZIER "Transitions" | 116637,167879 123539,156637 117794,149336 126648,141321 -I 307 304 0 Builtin Entry | 70580,246230 -L 306 305 0 TEXT "State Labels" | 113556,225558 1 0 0 "SEND_CMD\n/23/" -S 305 304 114688 ELLIPSE "States" | 113556,225558 6500 6500 -H 304 302 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -A 335 334 16 TEXT "Actions" | 134500,139322 1 0 0 "spiCS_n <= 1'b0;\nreadWriteSDBlockRdy <= 1'b0;\nreadError <= `READ_NO_ERROR;" -W 334 6 0 128 302 BEZIER "Transitions" | 119969,172153 128545,167673 154370,136857 153592,120935 -A 333 298 16 TEXT "Actions" | 76094,136596 1 0 0 "spiCS_n <= 1'b0;\nreadWriteSDBlockRdy <= 1'b0;\nwriteError <= `WRITE_NO_ERROR;" -A 332 128 4 TEXT "Actions" | 66248,183412 1 0 0 "spiCS_n <= 1'b1;\nreadWriteSDBlockRdy <= 1'b1;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;" -W 331 328 0 329 330 BEZIER "Transitions" | 100205,182880 103344,179877 105196,169695 108335,166692 -I 330 328 0 Builtin Exit | 110928,166692 -I 329 328 0 Builtin Entry | 96520,182880 -S 327 304 126980 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 128874,139185 3156 3017 -L 326 327 0 TEXT "State Labels" | 128942,138847 1 0 0 "J2" -W 325 304 3 327 318 BEZIER "Transitions" | 129847,136319 133174,127641 137870,107389 141197,98711 -A 323 321 16 TEXT "Actions" | 139238,127895 1 0 0 "readError <= `READ_CMD_ERROR;" -C 322 321 0 TEXT "Conditions" | 137153,138885 1 0 0 "respTout == 1'b1 || respByte != 8'h00" -W 321 304 2 327 319 BEZIER "Transitions" | 131177,137123 136826,130398 150771,116398 156420,109673 -L 320 319 0 TEXT "Labels" | 162420,111673 1 0 0 "WT_REQ" -H 328 327 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -S 351 338 139264 ELLIPSE "States" | 106026,166550 6500 6500 -W 350 338 0 368 369 BEZIER "Transitions" | 67549,239359 76627,234752 86180,250238 95258,245631 -C 349 348 0 TEXT "Conditions" | 111780,160832 1 0 0 "rxDataRdy == 1'b1" -W 348 338 0 351 346 BEZIER "Transitions" | 109408,161002 116386,149688 110826,148678 118545,137753 -L 347 346 0 TEXT "State Labels" | 122076,132298 1 0 0 "CHK_LOOP\n/26/" -S 346 338 135168 ELLIPSE "States" | 122076,132298 6500 6500 -H 338 337 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -S 337 6 131076 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155556,94377 6500 6500 -L 336 337 0 TEXT "State Labels" | 155556,94377 1 0 0 "RD_TOKEN" -I 74 0 2 Builtin InPort | 195700,267632 "" "" -L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" -I 72 0 3 Builtin InPort | 195700,272800 "" "" -L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" -L 367 359 0 TEXT "State Labels" | 106340,218687 1 0 0 "SEND_CMD\n/28/" -L 366 365 0 TEXT "State Labels" | 53406,179998 1 0 0 "DEL2\n/29/" -S 365 338 147456 ELLIPSE "States" | 53406,179998 6500 6500 -W 364 338 3 346 361 BEZIER "Transitions" | 123583,125978 114391,113159 121643,95942 132878,90341 -I 361 338 0 Builtin Exit | 135456,90208 -A 360 359 4 TEXT "Actions" | 121852,234949 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;" -S 359 338 143360 ELLIPSE "States" | 106340,218687 6500 6500 -L 352 351 0 TEXT "State Labels" | 106026,166550 1 0 0 "WT_FIN\n/27/" -L 81 82 0 TEXT "State Labels" | 113220,195514 1 0 0 "ST_RW_SD\n/0/" -S 82 6 0 ELLIPSE "States" | 113220,195514 6500 6500 -L 83 84 0 TEXT "State Labels" | 115395,109896 1 0 0 "WR_CMD" -S 84 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115395,109896 6500 6500 -H 85 84 0 RECT 0,0,0 0 0 1 255,255,255 0 | 27860,28670 212360,276670 -S 92 85 8192 ELLIPSE "States" | 113016,225828 6500 6500 -L 93 92 0 TEXT "State Labels" | 113016,225828 1 0 0 "SEND_CMD\n/1/" -I 94 85 0 Builtin Entry | 70040,246500 -W 383 338 2 346 385 BEZIER "Transitions" | 128455,133541 138850,135296 180442,141646 191036,142273 -W 382 338 0 380 351 BEZIER "Transitions" | 105524,186872 105457,182130 105515,177755 105448,173013 -W 381 338 0 359 380 BEZIER "Transitions" | 105523,212247 105320,208453 105367,203608 105164,199814 -S 380 338 155648 ELLIPSE "States" | 105765,193344 6500 6500 -L 379 380 0 TEXT "State Labels" | 105765,193344 1 0 0 "DEL1\n/31/" -C 377 374 0 TEXT "Conditions" | 32353,125947 1 0 0 "locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS" -C 376 375 0 TEXT "Conditions" | 37395,199964 1 0 0 "delCnt1 == `MAX_8_BIT" -W 375 338 1 365 359 BEZIER "Transitions" | 55933,185983 60073,191941 68179,216209 76636,218125\ - 85094,220041 90522,226339 93570,226372 96618,226406\ - 99403,224529 101638,223174 -W 374 338 1 346 365 BEZIER "Transitions" | 116959,136304 87922,130964 55868,158884 57051,176025 -A 373 365 4 TEXT "Actions" | 64312,187877 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" -L 372 369 0 TEXT "State Labels" | 101285,243200 1 0 0 "INIT_LOOP\n/30/" -W 371 338 0 369 359 BEZIER "Transitions" | 101997,236742 102942,232760 103652,228930 104597,224948 -A 370 369 4 TEXT "Actions" | 114245,248870 1 0 0 "timeOutCnt <= 12'h000;" -S 369 338 151552 ELLIPSE "States" | 101285,243200 6500 6500 -I 368 338 0 Builtin Entry | 63364,239359 -W 98 85 0 103 118 BEZIER "Transitions" | 116097,168149 122999,156907 117254,149606 126108,141591 -C 99 98 0 TEXT "Conditions" | 118453,167900 1 0 0 "sendCmdRdy == 1'b1" -W 100 85 0 94 92 BEZIER "Transitions" | 73698,246500 82776,241893 98521,234027 107599,229420 -W 101 85 0 105 103 BEZIER "Transitions" | 112750,192148 112615,188422 112530,183906 112395,180180 -W 102 85 0 92 105 BEZIER "Transitions" | 112802,219339 112802,215071 112860,209370 112860,205102 -S 103 85 12288 ELLIPSE "States" | 112702,173691 6500 6500 -L 104 103 0 TEXT "State Labels" | 112702,173691 1 0 0 "WT_FIN\n/2/" -S 105 85 16384 ELLIPSE "States" | 113244,198623 6500 6500 -L 106 105 0 TEXT "State Labels" | 113244,198623 1 0 0 "DEL\n/3/" -A 107 92 4 TEXT "Actions" | 128528,242090 1 0 0 "cmdByte <= 8'h58; //CMD24 Block Write\ndataByte1 <= blockAddr[31:24];\ndataByte2 <= blockAddr[23:16];\ndataByte3 <= blockAddr[15:8];\ndataByte4 <= blockAddr[7:0];\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;" -I 108 85 0 Builtin Exit | 143492,98981 -I 109 85 0 Builtin Link | 155880,111943 -L 110 109 0 TEXT "Labels" | 161880,111943 1 0 0 "WT_REQ" -W 111 85 2 118 109 BEZIER "Transitions" | 130637,137393 136286,130668 150231,116668 155880,109943 -A 387 383 16 TEXT "Actions" | 144060,138060 1 0 0 "readError <= `READ_TOKEN_ERROR;" -C 386 383 0 TEXT "Conditions" | 128229,146101 1 0 0 "timeOutCnt == `ONE_HUNDRED_MS" -I 385 338 0 Builtin Link | 190990,144650 -L 384 385 0 TEXT "Labels" | 196990,144650 1 0 0 "WT_REQ" -C 112 111 0 TEXT "Conditions" | 136613,139155 1 0 0 "respTout == 1'b1 || respByte != 8'h00" -A 113 111 16 TEXT "Actions" | 138698,128165 1 0 0 "writeError <= `WRITE_CMD_ERROR;" -W 116 85 3 118 108 BEZIER "Transitions" | 129307,136589 132634,127911 137330,107659 140657,98981 -L 117 118 0 TEXT "State Labels" | 128402,139117 1 0 0 "J1" -S 118 85 20484 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 128334,139455 3156 3017 -H 119 118 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -I 122 119 0 Builtin Entry | 96520,182880 -I 123 119 0 Builtin Exit | 110928,166692 -W 126 119 0 122 123 BEZIER "Transitions" | 100205,182880 103344,179877 105196,169695 108335,166692 -L 127 128 0 TEXT "State Labels" | 114166,175079 1 0 0 "WT_REQ\n/4/" -L 388 389 0 TEXT "State Labels" | 155343,73929 1 0 0 "RD_DATA" -S 389 6 159748 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155343,73929 6500 6500 -H 390 389 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -S 128 6 24576 ELLIPSE "States" | 114166,175079 6500 6500 -L 129 130 0 TEXT "State Labels" | 116508,88574 1 0 0 "WR_TOKEN" -S 130 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116508,88574 6500 6500 -H 131 130 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -W 138 131 0 144 141 BEZIER "Transitions" | 93143,232118 93346,228934 95399,216673 95425,213277 -A 139 138 16 TEXT "Actions" | 83596,226272 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -C 140 138 0 TEXT "Conditions" | 95421,232225 1 0 0 "txDataFull == 1'b0" -S 141 131 32768 ELLIPSE "States" | 95726,206806 6500 6500 -L 142 141 0 TEXT "State Labels" | 95726,206806 1 0 0 "FF1_FIN\n/5/" -A 143 141 4 TEXT "Actions" | 105171,209122 1 0 0 "txDataWen <= 1'b0;" -L 400 401 0 TEXT "State Labels" | 77852,226948 1 0 0 "ST_LOOP\n/32/" -S 401 390 163840 ELLIPSE "States" | 77852,226948 6500 6500 -A 402 401 4 TEXT "Actions" | 95196,229658 1 0 0 "txDataWen <= 1'b1;\ntxDataOut <= 8'hff;\nloopCnt <= loopCnt + 1'b1;" -L 403 404 0 TEXT "State Labels" | 78936,199306 1 0 0 "WT_DATA\n/33/" -S 404 390 167936 ELLIPSE "States" | 78936,199306 6500 6500 -W 406 390 0 401 404 BEZIER "Transitions" | 77695,220483 77762,216960 78169,209653 78270,205764 -A 408 404 4 TEXT "Actions" | 97364,200119 1 0 0 "txDataWen <= 1'b0;" -L 409 410 0 TEXT "State Labels" | 81375,162450 1 0 0 "CHK_LOOP\n/34/" -S 410 390 172032 ELLIPSE "States" | 81375,162450 6500 6500 -W 411 390 0 404 410 BEZIER "Transitions" | 79226,192822 79632,188351 80587,173613 80938,168928 -C 412 411 0 TEXT "Conditions" | 81955,194246 1 0 0 "rxDataRdy == 1'b1" -A 413 411 16 TEXT "Actions" | 74786,189659 1 0 0 "rxFifoWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\nrxFifoData <= rxDataIn;" -L 414 415 0 TEXT "State Labels" | 83004,136975 1 0 0 "J1" -S 415 390 176132 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 83043,136396 3569 3569 -S 144 131 36864 ELLIPSE "States" | 92762,238598 6500 6500 -L 145 144 0 TEXT "State Labels" | 92762,238598 1 0 0 "FF1_ST\n/6/" -I 146 131 0 Builtin Entry | 51952,266176 -S 147 131 40960 ELLIPSE "States" | 101439,148824 6500 6500 -A 148 147 4 TEXT "Actions" | 110884,151140 1 0 0 "txDataWen <= 1'b0;" -L 149 147 0 TEXT "State Labels" | 101439,148824 1 0 0 "FF2_FIN\n/7/" -W 150 131 0 153 147 BEZIER "Transitions" | 98856,174136 99059,170952 101112,158691 101138,155295 -C 151 150 0 TEXT "Conditions" | 101134,174243 1 0 0 "txDataFull == 1'b0" -A 152 150 16 TEXT "Actions" | 89309,168290 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -S 153 131 45056 ELLIPSE "States" | 98475,180616 6500 6500 -L 154 153 0 TEXT "State Labels" | 98475,180616 1 0 0 "FF2_ST\n/8/" -S 155 131 49152 ELLIPSE "States" | 107423,92248 6500 6500 -A 156 155 4 TEXT "Actions" | 116868,94564 1 0 0 "txDataWen <= 1'b0;" -L 157 155 0 TEXT "State Labels" | 107423,92248 1 0 0 "FE_FIN\n/9/" -W 158 131 0 161 155 BEZIER "Transitions" | 104840,117560 105043,114376 107096,102115 107122,98719 -C 159 158 0 TEXT "Conditions" | 107118,117667 1 0 0 "txDataFull == 1'b0" -H 416 415 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -I 419 416 0 Builtin Entry | 126004,141930 -I 420 416 0 Builtin Exit | 144780,121920 -W 423 416 0 419 420 BEZIER "Transitions" | 129826,141930 134057,136743 137819,127107 142050,121920 -W 424 390 0 410 415 BEZIER "Transitions" | 81407,156099 81677,152387 82370,143719 82390,139900 -A 425 424 16 TEXT "Actions" | 80070,154260 1 0 0 "rxDataRdyClr <= 1'b0;\nrxFifoWen <= 1'b0;" -I 426 390 0 Builtin Entry | 42810,270090 -L 427 428 0 TEXT "State Labels" | 97350,266040 1 0 0 "CLR_RX\n/35/" -S 428 390 180224 ELLIPSE "States" | 97350,266040 6500 6500 -W 429 390 0 426 428 BEZIER "Transitions" | 46995,270090 55230,269685 82688,267193 90992,267387 -A 430 429 16 TEXT "Actions" | 55533,269709 1 0 0 "rxDataRdyClr <= 1'b1;" -W 431 390 0 428 401 BEZIER "Transitions" | 94484,260209 90569,252717 84564,240304 80649,232812 -A 160 158 16 TEXT "Actions" | 95293,111714 1 0 0 "txDataOut <= 8'hfe;\ntxDataWen <= 1'b1;" -S 161 131 53248 ELLIPSE "States" | 104459,124040 6500 6500 -L 162 161 0 TEXT "State Labels" | 104459,124040 1 0 0 "FE_ST\n/10/" -W 163 131 0 146 144 BEZIER "Transitions" | 55624,266176 64736,260940 79060,248435 88172,243199 -W 164 131 0 141 153 BEZIER "Transitions" | 95785,200373 96397,196089 96746,191299 97358,187015 -I 165 131 0 Builtin Exit | 140624,67616 -W 166 131 0 147 161 BEZIER "Transitions" | 101803,142336 102279,138596 102801,134171 103277,130431 -W 167 131 0 155 165 BEZIER "Transitions" | 112534,88234 120218,83134 130356,72716 138040,67616 -L 168 169 0 TEXT "State Labels" | 116501,66078 1 0 0 "WR_DATA" -S 169 6 229380 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116501,66078 6500 6500 -H 170 169 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -A 432 431 16 TEXT "Actions" | 85200,253080 1 0 0 "rxDataRdyClr <= 1'b0;\nloopCnt <= 9'b000000000;" -W 433 390 2 415 401 BEZIER "Transitions" | 79771,137821 72144,141736 57457,148725 53070,158681\ - 48683,168637 46387,200633 47433,211027 48480,221422\ - 54960,231008 58470,232695 61980,234383 68385,231511\ - 72165,230094 -W 440 390 0 451 441 BEZIER "Transitions" | 138130,91528 138333,88344 140386,76083 140412,72687 -S 441 390 184320 ELLIPSE "States" | 140713,66216 6500 6500 -L 442 441 0 TEXT "State Labels" | 140713,66216 1 0 0 "CS_FIN2\n/36/" -S 443 390 188416 ELLIPSE "States" | 75739,66216 6500 6500 -A 444 443 4 TEXT "Actions" | 85184,68532 1 0 0 "txDataWen <= 1'b0;" -L 445 443 0 TEXT "State Labels" | 75739,66216 1 0 0 "CS_FIN1\n/37/" -W 446 390 0 449 443 BEZIER "Transitions" | 73156,91528 73359,88344 75412,76083 75438,72687 -C 447 446 0 TEXT "Conditions" | 75434,91635 1 0 0 "txDataFull == 1'b0" -S 177 170 61440 ELLIPSE "States" | 78305,137464 6500 6500 -A 178 177 4 TEXT "Actions" | 87750,139780 1 0 0 "txDataWen <= 1'b0;" -L 179 177 0 TEXT "State Labels" | 78305,137464 1 0 0 "D_FIN\n/11/" -W 180 170 0 183 177 BEZIER "Transitions" | 75722,162776 75925,159592 77978,147331 78004,143935 -C 181 180 0 TEXT "Conditions" | 78000,162883 1 0 0 "txDataFull == 1'b0" -A 182 180 16 TEXT "Actions" | 66175,156930 1 0 0 "txDataOut <= txFifoData;\ntxDataWen <= 1'b1;" -S 183 170 65536 ELLIPSE "States" | 75341,169256 6500 6500 -L 184 183 0 TEXT "State Labels" | 75341,169256 1 0 0 "D_ST\n/12/" -L 187 188 0 TEXT "State Labels" | 72867,227889 1 0 0 "RD_FIFO1\n/13/" -S 188 170 69632 ELLIPSE "States" | 72867,227889 6500 6500 -L 189 190 0 TEXT "State Labels" | 73959,201135 1 0 0 "RD_FIFO2\n/14/" -S 190 170 73728 ELLIPSE "States" | 73959,201135 6500 6500 -A 191 188 4 TEXT "Actions" | 80895,230061 1 0 0 "txFifoRen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" -A 448 446 16 TEXT "Actions" | 63609,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -S 449 390 192512 ELLIPSE "States" | 72775,98008 6500 6500 -L 450 449 0 TEXT "State Labels" | 72775,98008 1 0 0 "CS_ST1\n/38/" -S 451 390 196608 ELLIPSE "States" | 137749,98008 6500 6500 -L 452 451 0 TEXT "State Labels" | 137749,98008 1 0 0 "CS_ST2\n/39/" -A 453 440 16 TEXT "Actions" | 128583,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -C 454 440 0 TEXT "Conditions" | 140408,91635 1 0 0 "txDataFull == 1'b0" -A 455 441 4 TEXT "Actions" | 150158,68532 1 0 0 "txDataWen <= 1'b0;" -W 456 390 1 415 449 BEZIER "Transitions" | 82185,132936 79630,124866 76715,112427 74160,104357 -W 457 390 0 443 451 BEZIER "Transitions" | 78514,60339 82952,55834 89399,47074 95182,45998\ - 100965,44922 115223,49631 117845,56120 120468,62609\ - 116702,83861 117071,91594 117441,99328 122688,109012\ - 125276,109920 127865,110828 131449,106344 134004,103318 -I 458 390 0 Builtin Exit | 161625,43107 -W 459 390 0 441 458 BEZIER "Transitions" | 144285,60786 148925,56213 153892,47680 158532,43107 -W 460 6 0 302 337 BEZIER "Transitions" | 155788,108419 155653,104081 155771,105011 155438,100848 -W 461 6 0 337 389 BEZIER "Transitions" | 155952,87899 155619,83040 155938,84926 155805,80404 -W 462 6 0 389 128 BEZIER "Transitions" | 160766,72622 181673,64668 193592,81881 194705,86831\ - 195819,91782 193010,106602 196539,114884 200068,123167\ - 183067,150177 177992,160070 172917,169964 164106,188182\ - 156924,189345 149743,190509 134447,187583 129526,185887\ - 124606,184192 121267,181269 119073,179341 -W 463 6 0 224 128 BEZIER "Transitions" | 112148,42964 96171,38095 88076,46646 81324,48345\ - 74572,50044 62626,66620 61422,77634 60219,88648\ - 53118,140235 53550,154499 53982,168763 75928,188049\ - 79879,189622 83830,191195 94548,186386 97872,185422\ - 101197,184458 106213,181091 109338,179429 -A 192 190 4 TEXT "Actions" | 82521,204408 1 0 0 "txFifoRen <= 1'b0;" -L 193 194 0 TEXT "State Labels" | 72048,257646 1 0 0 "LOOP_INIT\n/15/" -S 194 170 77824 ELLIPSE "States" | 72048,257646 6500 6500 -A 195 194 4 TEXT "Actions" | 89247,259284 1 0 0 "loopCnt <= 9'b000000000;" -S 196 170 81920 ELLIPSE "States" | 80801,98549 6500 6500 -L 197 196 0 TEXT "State Labels" | 80801,98549 1 0 0 "CS_ST1\n/16/" -W 198 170 0 196 201 BEZIER "Transitions" | 81182,92069 81385,88885 83438,76624 83464,73228 -A 199 198 16 TEXT "Actions" | 71635,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -C 200 198 0 TEXT "Conditions" | 83460,92176 1 0 0 "txDataFull == 1'b0" -S 201 170 86016 ELLIPSE "States" | 83765,66757 6500 6500 -L 202 201 0 TEXT "State Labels" | 83765,66757 1 0 0 "CS_FIN1\n/17/" -A 203 201 4 TEXT "Actions" | 93210,69073 1 0 0 "txDataWen <= 1'b0;" -S 204 170 90112 ELLIPSE "States" | 148739,66757 6500 6500 -A 205 204 4 TEXT "Actions" | 158184,69073 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 12'h000;" -L 206 204 0 TEXT "State Labels" | 148739,66757 1 0 0 "CS_FIN2\n/18/" -W 207 170 0 210 204 BEZIER "Transitions" | 146156,92069 146359,88885 148412,76624 148438,73228 -C 464 334 0 TEXT "Conditions" | 94994,146397 1 0 0 "readWriteSDBlockReq == `READ_SD_BLOCK" -C 465 298 0 TEXT "Conditions" | 55739,152492 1 0 0 "readWriteSDBlockReq == `WRITE_SD_BLOCK" -I 475 6 0 Builtin Reset | 49660,206134 -W 476 6 0 475 82 BEZIER "Transitions" | 49660,206134 64556,204256 92040,199052 106936,197174 -C 477 476 0 TEXT "Conditions" | 62428,209528 1 0 0 "rst == 1'b1" -L 478 479 0 TEXT "Labels" | 122230,269291 1 0 0 "readWriteSDBlockReq[1:0]" -I 479 0 130 Builtin InPort | 116230,269291 "" "" -L 223 224 0 TEXT "State Labels" | 116398,45340 1 0 0 "WR_BUSY" -C 208 207 0 TEXT "Conditions" | 148434,92176 1 0 0 "txDataFull == 1'b0" -A 209 207 16 TEXT "Actions" | 136609,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" -S 210 170 94208 ELLIPSE "States" | 145775,98549 6500 6500 -L 211 210 0 TEXT "State Labels" | 145775,98549 1 0 0 "CS_ST2\n/19/" -W 212 170 1 177 196 BEZIER "Transitions" | 78835,130988 79312,123617 80043,112406 80520,105035 -C 213 212 0 TEXT "Conditions" | 81603,129336 1 0 0 "loopCnt == 9'b000000000" -W 214 170 0 194 188 BEZIER "Transitions" | 72189,251169 72121,246119 72460,239413 72392,234363 -W 215 170 0 188 190 BEZIER "Transitions" | 72773,221428 73182,217197 73251,211851 73660,207620 -W 216 170 0 190 183 BEZIER "Transitions" | 74343,194648 74411,189188 74887,181191 74955,175731 -W 217 170 2 177 188 BEZIER "Transitions" | 71806,137461 65254,138211 53484,138960 49969,147866\ - 46455,156772 45498,190898 45396,201715 45294,212532\ - 45840,221679 48843,224169 51846,226660 60640,227203\ - 66373,227612 -W 218 170 0 201 210 BEZIER "Transitions" | 87098,61178 91397,57971 97506,51735 102658,50541\ - 107811,49347 119823,50985 122894,57434 125965,63884\ - 126239,88045 127637,96576 129036,105107 134361,115072\ - 136749,115515 139137,115959 142020,108931 144135,104836 -I 221 170 0 Builtin Entry | 39834,267201 -W 222 170 0 221 194 BEZIER "Transitions" | 43519,267201 49798,265427 59580,261403 65859,259629 -L 480 481 0 TEXT "Labels" | 120083,264098 1 0 0 "readWriteSDBlockRdy" -I 481 0 2 Builtin OutPort | 114083,264098 "" "" -L 482 483 0 TEXT "Labels" | 120083,259063 1 0 0 "spiCS_n" -I 483 0 2 Builtin OutPort | 114083,259063 "" "" -I 484 0 130 Builtin OutPort | 69013,272215 "" "" -L 485 484 0 TEXT "Labels" | 75013,272215 1 0 0 "cmdByte[7:0]" -I 486 0 130 Builtin OutPort | 68768,267735 "" "" -L 487 486 0 TEXT "Labels" | 74768,267735 1 0 0 "dataByte1[7:0]" -I 488 0 130 Builtin OutPort | 68965,262525 "" "" -L 489 488 0 TEXT "Labels" | 74965,262525 1 0 0 "dataByte2[7:0]" -I 490 0 130 Builtin OutPort | 69212,257832 "" "" -L 491 490 0 TEXT "Labels" | 75212,257832 1 0 0 "dataByte3[7:0]" -I 492 0 130 Builtin OutPort | 69212,253139 "" "" -L 493 492 0 TEXT "Labels" | 75212,253139 1 0 0 "dataByte4[7:0]" -I 494 0 130 Builtin OutPort | 69088,248199 "" "" -L 495 494 0 TEXT "Labels" | 75088,248199 1 0 0 "checkSumByte[7:0]" -W 239 225 1 237 241 BEZIER "Transitions" | 110570,148995 94430,151147 64068,154038 55628,162847\ - 47189,171657 45708,202593 49575,212814 53442,223036\ - 70390,232990 77013,235243 83637,237496 90160,236699\ - 94934,236229 -L 238 237 0 TEXT "State Labels" | 117061,148658 1 0 0 "CHK_FIN\n/40/" -S 237 225 200704 ELLIPSE "States" | 117061,148658 6500 6500 -C 236 235 0 TEXT "Conditions" | 106765,177192 1 0 0 "rxDataRdy == 1'b1" -W 235 225 0 232 237 BEZIER "Transitions" | 104393,177362 111371,166048 105811,165038 113530,154113 -W 234 225 0 240 268 BEZIER "Transitions" | 62534,255719 71612,251112 81165,266598 90243,261991 -L 233 232 0 TEXT "State Labels" | 101011,182910 1 0 0 "WT_FIN1\n/41/" -S 232 225 204800 ELLIPSE "States" | 101011,182910 6500 6500 -H 225 224 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -S 224 6 57348 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116398,45340 6500 6500 -I 496 0 2 Builtin OutPort | 69306,243719 "" "" -L 497 496 0 TEXT "Labels" | 75306,243719 1 0 0 "sendCmdReq" -I 498 0 2 Builtin InPort | 71520,238553 "" "" -L 499 498 0 TEXT "Labels" | 77520,238553 1 0 0 "sendCmdRdy" -I 500 0 130 Builtin InPort | 71328,234058 "" "" -L 501 500 0 TEXT "Labels" | 77328,234058 1 0 0 "respByte[7:0]" -I 502 0 2 Builtin InPort | 150168,237862 "" "" -L 503 502 0 TEXT "Labels" | 156168,237862 1 0 0 "rxDataRdy" -I 504 0 2 Builtin InPort | 117135,232948 "" "" -L 505 504 0 TEXT "Labels" | 123135,232948 1 0 0 "txDataFull" -I 506 0 2 Builtin OutPort | 114678,237589 "" "" -L 507 506 0 TEXT "Labels" | 120678,237589 1 0 0 "txDataWen" -I 508 0 130 Builtin InPort | 149895,241957 "" "" -L 509 508 0 TEXT "Labels" | 155895,241957 1 0 0 "rxDataIn[7:0]" -I 510 0 130 Builtin OutPort | 114678,242230 "" "" -L 511 510 0 TEXT "Labels" | 120678,242230 1 0 0 "txDataOut[7:0]" -L 527 528 0 TEXT "Labels" | 190950,242120 1 0 0 "rxFifoData[7:0]" -I 526 0 2 Builtin OutPort | 185220,246980 "" "" -L 525 526 0 TEXT "Labels" | 191220,246980 1 0 0 "rxFifoWen" -I 524 0 130 Builtin InPort | 187380,252110 "" "" -L 523 524 0 TEXT "Labels" | 193380,252110 1 0 0 "txFifoData[7:0]" -I 522 0 2 Builtin OutPort | 184950,256970 "" "" -L 521 522 0 TEXT "Labels" | 190950,256970 1 0 0 "txFifoRen" -W 248 225 2 237 251 BEZIER "Transitions" | 121126,143587 165099,138575 140782,115097 127863,106694 -A 249 248 16 TEXT "Actions" | 144590,131826 1 0 0 "writeError <= `WRITE_BUSY_ERROR;" -C 250 248 0 TEXT "Conditions" | 128858,147492 1 0 0 "timeOutCnt == `TWO_FIFTY_MS" -C 255 254 0 TEXT "Conditions" | 114470,200483 1 0 0 "delCnt1 == `MAX_8_BIT" -W 254 225 1 243 232 BEZIER "Transitions" | 151179,193271 142375,193953 126550,195706 120373,194853\ - 114197,194000 109072,189975 105523,187587 -W 253 225 0 241 243 BEZIER "Transitions" | 101358,228597 101904,225390 102458,220616 103686,217545\ - 104915,214475 108737,208604 114128,207171 119520,205738\ - 137266,205875 142862,205499 148458,205124 153100,203486\ - 154430,202496 155761,201507 156185,199858 156526,198698 -A 252 241 4 TEXT "Actions" | 116837,251309 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\ndelCnt1 <= 8'h00;" -I 251 225 0 Builtin Exit | 130441,106568 -C 247 239 0 TEXT "Conditions" | 32326,147044 1 0 0 "locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS" -W 245 225 3 237 251 BEZIER "Transitions" | 118568,142338 109376,129519 116628,112302 127863,106701 -L 244 243 0 TEXT "State Labels" | 157604,192293 1 0 0 "DEL1\n/42/" -S 243 225 208896 ELLIPSE "States" | 157604,192293 6500 6500 -L 242 241 0 TEXT "State Labels" | 101325,235047 1 0 0 "SEND_CMD1\n/43/" -S 241 225 212992 ELLIPSE "States" | 101325,235047 6500 6500 -I 240 225 0 Builtin Entry | 58349,255719 -I 512 0 2 Builtin OutPort | 147984,233494 "" "" -L 513 512 0 TEXT "Labels" | 153984,233494 1 0 0 "rxDataRdyClr" -L 514 515 0 TEXT "Labels" | 77500,229855 1 0 0 "respTout" -I 515 0 2 Builtin InPort | 71500,229855 "" "" -A 516 82 4 TEXT "Actions" | 160072,222273 1 0 0 "readWriteSDBlockRdy <= 1'b0;\nspiCS_n <= 1'b1;\nreadError <= 1'b0;\nwriteError <= 1'b0;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 8'h00;\ndelCnt2 <= 8'h00;\nreadError <= `READ_NO_ERROR;\nwriteError <= `WRITE_NO_ERROR;\ntxFifoRen <= 1'b0;\nrxFifoWen <= 1'b0;\nrxFifoData <= 8'h00;\ntimeOutCnt <= 12'h000;\nlocRespByte <= 8'h00;" -L 517 518 0 TEXT "Labels" | 120142,254523 1 0 0 "readError[1:0]" -I 518 0 130 Builtin OutPort | 114142,254523 "" "" -L 519 520 0 TEXT "Labels" | 119971,249897 1 0 0 "writeError[1:0]" -I 520 0 130 Builtin OutPort | 113971,249897 "" "" -L 543 544 0 TEXT "Labels" | 164114,261928 1 0 0 "delCnt1[7:0]" -C 542 541 0 TEXT "Conditions" | 31702,154694 1 0 0 "delCnt2 == 8'hff" -W 541 338 0 537 365 BEZIER "Transitions" | 45749,147689 44744,152468 35773,163628 34769,167402\ - 33765,171176 35012,179071 36950,181044 38889,183018\ - 44071,182291 47325,182291 -W 539 338 2 365 537 BEZIER "Transitions" | 51640,173745 51294,168275 56598,148666 56246,142125 -A 538 537 4 TEXT "Actions" | 36466,135651 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" -S 537 338 225280 ELLIPSE "States" | 49762,142576 6500 6500 -L 536 537 0 TEXT "State Labels" | 49762,142576 1 0 0 "DEL3\n/46/" -C 535 534 0 TEXT "Conditions" | 154260,170964 1 0 0 "delCnt2 == 8'hff" -W 534 225 0 530 243 BEZIER "Transitions" | 179888,172413 174851,172206 165921,171447 162609,173482\ - 159297,175518 158039,181622 156452,185900 -A 533 530 4 TEXT "Actions" | 166680,162960 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" -W 531 225 2 243 530 BEZIER "Transitions" | 163308,189179 168294,185855 176215,180648 181201,177324 -S 530 225 217088 ELLIPSE "States" | 186323,173323 6500 6500 -L 529 530 0 TEXT "State Labels" | 186323,173323 1 0 0 "DEL2\n/44/" -I 528 0 130 Builtin OutPort | 184950,242120 "" "" -A 270 268 4 TEXT "Actions" | 109230,265230 1 0 0 "timeOutCnt <= 12'h000;" -W 269 225 0 268 241 BEZIER "Transitions" | 96982,253102 97927,249120 98637,245290 99582,241308 -S 268 225 221184 ELLIPSE "States" | 96270,259560 6500 6500 -L 267 268 0 TEXT "State Labels" | 96270,259560 1 0 0 "INIT_LOOP\n/45/" -I 264 0 130 Builtin Signal | 161063,266638 "" "" -L 263 264 0 TEXT "Labels" | 164063,266638 1 0 0 "loopCnt[8:0]" -A 259 243 4 TEXT "Actions" | 166374,212237 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ndelCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" -END Index: trunk/Aldec/design0/src/initSD.asf =================================================================== --- trunk/Aldec/design0/src/initSD.asf (revision 3) +++ trunk/Aldec/design0/src/initSD.asf (nonexistent) @@ -1,226 +0,0 @@ -VERSION=1.15 -HEADER -FILE="initSD.asf" -FID=4788d213 -LANGUAGE=VERILOG -ENTITY="initSD" -FRAMES=ON -FREEOID=430 -"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// initSD.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// When SDInitReq asserted, initialise SD card\n//// \n//// \n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" -END -BUNDLES -B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 -B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 -B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 -B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 -B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 -B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 -B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -END -INSTHEADER 1 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 5000,5000 10000,10000 -END -INSTHEADER 141 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 168 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -INSTHEADER 322 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -OBJECTS -S 286 169 24576 ELLIPSE "States" | 105808,239248 6500 6500 -L 285 286 0 TEXT "State Labels" | 105808,239248 1 0 0 "SEND_CMD\n/4/" -I 284 169 0 Builtin Entry | 62832,259920 -G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: initSD" -A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION" -F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603 -L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "initSDSt" -W 303 169 1 300 286 BEZIER "Transitions" | 115053,153196 98913,155348 68551,158239 60111,167048\ - 51672,175858 50191,206794 54058,217015 57925,227237\ - 74873,237191 81496,239444 88120,241697 94643,240900\ - 99417,240430 -S 300 169 36864 ELLIPSE "States" | 121544,152859 6500 6500 -L 299 300 0 TEXT "State Labels" | 121544,152859 1 0 0 "CHK_FIN\n/7/" -C 298 297 0 TEXT "Conditions" | 111248,181393 1 0 0 "sendCmdRdy == 1'b1" -W 297 169 0 292 300 BEZIER "Transitions" | 108876,181563 115854,170249 110294,169239 118013,158314 -W 295 169 0 284 286 BEZIER "Transitions" | 66490,259920 75568,255313 91313,247447 100391,242840 -W 294 169 0 290 292 BEZIER "Transitions" | 105542,205568 105407,201842 105322,197326 105187,193600 -W 293 169 0 286 290 BEZIER "Transitions" | 105594,232759 105594,228491 105652,222790 105652,218522 -S 292 169 32768 ELLIPSE "States" | 105494,187111 6500 6500 -L 291 292 0 TEXT "State Labels" | 105494,187111 1 0 0 "WT_FIN\n/6/" -S 290 169 28672 ELLIPSE "States" | 106036,212043 6500 6500 -L 289 290 0 TEXT "State Labels" | 106036,212043 1 0 0 "DEL\n/5/" -A 288 286 4 TEXT "Actions" | 121320,255510 1 0 0 "cmdByte <= 8'h40; //CMD0\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h95;\nsendCmdReq <= 1'b1;\nloopCnt <= loopCnt + 1'b1;\nspiCS_n <= 1'b0;" -I 319 169 0 Builtin Exit | 136284,112401 -I 318 169 0 Builtin Link | 148672,125363 -L 317 318 0 TEXT "Labels" | 154672,125363 1 0 0 "WT_INIT_REQ" -C 316 310 0 TEXT "Conditions" | 131001,148174 1 0 0 "respTout == 1'b1 || respByte != 8'h01" -A 313 312 16 TEXT "Actions" | 106611,116426 1 0 0 "loopCnt <= 8'h00;" -W 312 6 0 141 168 BEZIER "Transitions" | 111141,120168 111512,114462 111940,106474 111681,102457 -A 311 310 16 TEXT "Actions" | 132446,138965 1 0 0 "initError <= `INIT_CMD0_ERROR;" -W 310 169 2 300 318 BEZIER "Transitions" | 125449,147664 131098,140939 143023,130088 148672,123363 -C 304 303 0 TEXT "Conditions" | 36809,151245 1 0 0 "(respTout == 1'b1 || respByte != 8'h01) && loopCnt != 8'hff" -L 335 334 0 TEXT "State Labels" | 100580,187111 1 0 0 "WT_FIN\n/8/" -S 334 349 45056 ELLIPSE "States" | 100580,187111 6500 6500 -W 331 349 0 325 323 BEZIER "Transitions" | 61576,259920 70654,255313 86399,247447 95477,242840 -W 330 349 0 334 327 BEZIER "Transitions" | 103962,181563 110940,170249 105380,169239 113099,158314 -C 329 330 0 TEXT "Conditions" | 106334,181393 1 0 0 "sendCmdRdy == 1'b1" -L 328 327 0 TEXT "State Labels" | 116630,152859 1 0 0 "CHK_FIN\n/9/" -S 327 349 49152 ELLIPSE "States" | 116630,152859 6500 6500 -W 326 349 1 327 323 BEZIER "Transitions" | 110139,153196 93999,155348 63637,158239 55197,167048\ - 46758,175858 45277,206794 49144,217015 53011,227237\ - 69959,237191 76582,239444 83206,241697 89729,240900\ - 94503,240430 -I 325 349 0 Builtin Entry | 57918,259920 -L 324 323 0 TEXT "State Labels" | 100894,239248 1 0 0 "SEND_CMD\n/10/" -S 323 349 53248 ELLIPSE "States" | 100894,239248 6500 6500 -S 322 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112467,68151 6500 6500 -A 321 297 16 TEXT "Actions" | 108930,174030 1 0 0 "spiCS_n <= 1'b1;" -W 320 169 3 300 319 BEZIER "Transitions" | 123051,146539 126378,137861 129956,121079 133283,112401 -S 351 349 57344 ELLIPSE "States" | 157173,196494 6500 6500 -L 350 351 0 TEXT "State Labels" | 157173,196494 1 0 0 "DEL1\n/11/" -L 348 322 0 TEXT "State Labels" | 112467,68151 1 0 0 "INIT" -W 347 349 3 327 339 BEZIER "Transitions" | 118137,146539 108945,133720 116197,116503 127432,110902 -A 346 330 16 TEXT "Actions" | 104016,174030 1 0 0 "spiCS_n <= 1'b1;" -C 345 326 0 TEXT "Conditions" | 31895,151245 1 0 0 "(respTout == 1'b1 || respByte != 8'h00) && loopCnt != 8'hff" -W 344 349 2 327 339 BEZIER "Transitions" | 120695,147788 164668,142776 140351,119298 127432,110895 -A 343 344 16 TEXT "Actions" | 144159,136027 1 0 0 "initError <= `INIT_CMD1_ERROR;" -C 342 344 0 TEXT "Conditions" | 128427,151693 1 0 0 "respTout == 1'b1 || respByte != 8'h00" -I 339 349 0 Builtin Exit | 130010,110769 -A 338 323 4 TEXT "Actions" | 116406,255510 1 0 0 "cmdByte <= 8'h41; //CMD1\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;\nloopCnt <= loopCnt + 1'b1;\nspiCS_n <= 1'b0;\ndelCnt1 <= 10'h000;" -H 349 322 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -I 74 0 2 Builtin InPort | 195700,267632 "" "" -L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" -I 72 0 3 Builtin InPort | 195700,272800 "" "" -L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" -I 366 0 130 Builtin OutPort | 86503,262498 "" "" -L 365 366 0 TEXT "Labels" | 92503,262498 1 0 0 "cmdByte[7:0]" -L 367 368 0 TEXT "Labels" | 92258,258018 1 0 0 "dataByte1[7:0]" -W 363 6 0 322 102 BEZIER "Transitions" | 107085,71794 94246,83115 68667,103061 63765,115078\ - 58864,127095 64936,152522 71324,159511 77712,166500\ - 95428,168622 105168,169887 -W 362 6 0 168 322 BEZIER "Transitions" | 111422,89512 111675,84705 111722,79427 111975,74620 -W 361 349 0 323 351 BEZIER "Transitions" | 100927,232798 101473,229591 102027,224817 103255,221746\ - 104484,218676 108306,212805 113697,211372 119089,209939\ - 136835,210076 142431,209700 148027,209325 152669,207687\ - 153999,206697 155330,205708 155754,204059 156095,202899 -C 360 359 0 TEXT "Conditions" | 114039,204684 1 0 0 "delCnt1 == `TWO_MS" -W 359 349 1 351 334 BEZIER "Transitions" | 150748,197472 141944,198154 126119,199907 119942,199054\ - 113766,198201 108641,194176 105092,191788 -C 358 357 0 TEXT "Conditions" | 157694,164664 1 0 0 "delCnt2 == 8'hff" -W 357 349 0 353 351 BEZIER "Transitions" | 163535,169133 171628,167736 181061,162846 187169,163119\ - 193277,163392 202696,170901 204880,177350 207064,183799\ - 206381,202091 201331,206561 196281,211032 176760,210621\ - 171096,209359 165432,208097 162592,204050 161023,201730 -W 356 349 2 351 353 BEZIER "Transitions" | 158302,190095 158438,187775 158562,182275 158679,179771 -A 355 351 4 TEXT "Actions" | 166182,199224 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;\nsendCmdReq <= 1'b0;" -A 354 353 4 TEXT "Actions" | 166728,176565 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" -S 353 349 61440 ELLIPSE "States" | 158538,173289 6500 6500 -L 352 353 0 TEXT "State Labels" | 158538,173289 1 0 0 "DEL2\n/12/" -L 95 96 0 TEXT "Labels" | 155940,273023 1 0 0 "SDInitRdy" -I 368 0 130 Builtin OutPort | 86258,258018 "" "" -I 371 0 130 Builtin OutPort | 86455,252808 "" "" -L 372 371 0 TEXT "Labels" | 92455,252808 1 0 0 "dataByte2[7:0]" -I 373 0 130 Builtin OutPort | 86702,248115 "" "" -L 374 373 0 TEXT "Labels" | 92702,248115 1 0 0 "dataByte3[7:0]" -I 375 0 130 Builtin OutPort | 86702,243422 "" "" -L 376 375 0 TEXT "Labels" | 92702,243422 1 0 0 "dataByte4[7:0]" -L 383 384 0 TEXT "Labels" | 43326,249254 1 0 0 "delCnt1[9:0]" -I 382 0 2 Builtin InPort | 89010,228836 "" "" -L 381 382 0 TEXT "Labels" | 95010,228836 1 0 0 "sendCmdRdy" -I 380 0 2 Builtin OutPort | 86796,234002 "" "" -L 379 380 0 TEXT "Labels" | 92796,234002 1 0 0 "sendCmdReq" -I 378 0 130 Builtin OutPort | 86578,238482 "" "" -L 377 378 0 TEXT "Labels" | 92578,238482 1 0 0 "checkSumByte[7:0]" -I 111 0 2 Builtin OutPort | 142296,249682 "" "" -L 110 109 0 TEXT "Labels" | 150753,245041 1 0 0 "txDataFull" -I 109 0 2 Builtin InPort | 144753,245041 "" "" -W 106 6 0 102 141 BEZIER "Transitions" | 111478,164116 111546,159885 111249,139164 110939,132984 -W 105 6 0 100 102 BEZIER "Transitions" | 111805,187037 111601,183898 111568,180194 111364,177055 -S 102 6 4096 ELLIPSE "States" | 111630,170580 6500 6500 -L 101 102 0 TEXT "State Labels" | 111630,170580 1 0 0 "WT_INIT_REQ\n/1/" -S 100 6 0 ELLIPSE "States" | 112176,193512 6500 6500 -L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/0/" -I 96 0 2 Builtin OutPort | 149940,273023 "" "" -L 97 98 0 TEXT "Labels" | 158664,268382 1 0 0 "SDInitReq" -I 98 0 2 Builtin InPort | 152664,268382 "" "" -I 399 0 130 Builtin InPort | 179837,253714 "" "" -L 398 399 0 TEXT "Labels" | 185837,253714 1 0 0 "spiClkDelayIn[7:0]" -I 397 0 130 Builtin OutPort | 150335,263636 "" "" -L 396 397 0 TEXT "Labels" | 156335,263636 1 0 0 "initError[1:0]" -I 395 0 2 Builtin OutPort | 142620,234260 "" "" -L 394 395 0 TEXT "Labels" | 148620,234260 1 0 0 "spiCS_n" -I 391 0 130 Builtin InPort | 88818,224341 "" "" -L 390 391 0 TEXT "Labels" | 94818,224341 1 0 0 "respByte[7:0]" -C 389 388 0 TEXT "Conditions" | 64133,197548 1 0 0 "rst == 1'b1" -W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019 -I 387 6 0 Builtin Reset | 49555,202550 -I 386 0 130 Builtin Signal | 40326,244334 "" "" -L 385 386 0 TEXT "Labels" | 43326,244334 1 0 0 "delCnt2[7:0]" -I 384 0 130 Builtin Signal | 40326,249254 "" "" -C 123 106 0 TEXT "Conditions" | 112795,161807 1 0 0 "SDInitReq == 1'b1" -L 118 117 0 TEXT "Labels" | 148296,254323 1 0 0 "txDataOut[7:0]" -I 117 0 130 Builtin OutPort | 142296,254323 "" "" -L 112 111 0 TEXT "Labels" | 148296,249682 1 0 0 "txDataWen" -L 392 393 0 TEXT "Labels" | 94804,219488 1 0 0 "respTout" -I 393 0 2 Builtin InPort | 88804,219488 "" "" -I 405 0 2 Builtin InPort | 123780,223280 "" "" -L 404 405 0 TEXT "Labels" | 129780,223280 1 0 0 "rxDataRdy" -I 403 0 2 Builtin OutPort | 121620,218480 "" "" -L 402 403 0 TEXT "Labels" | 127620,218480 1 0 0 "rxDataRdyClr" -S 401 142 65536 ELLIPSE "States" | 119702,164354 6500 6500 -L 400 401 0 TEXT "State Labels" | 119702,164354 1 0 0 "WT_DATA_EMPTY\n/13/" -L 135 136 0 TEXT "Labels" | 92903,270215 1 0 0 "spiClkDelayOut[7:0]" -I 136 0 130 Builtin OutPort | 86903,270215 "" "" -A 137 100 4 TEXT "Actions" | 166381,206571 1 0 0 "spiClkDelayOut <= spiClkDelayIn;\nSDInitRdy <= 1'b0;\nspiCS_n <= 1'b1;\ninitError <= `INIT_NO_ERROR;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 10'h000;\ndelCnt2 <= 8'h00;\nrxDataRdyClr <= 1'b0;" -A 138 102 4 TEXT "Actions" | 122260,190788 1 0 0 "SDInitRdy <= 1'b1;\nspiClkDelayOut <= spiClkDelayIn;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;" -A 139 106 16 TEXT "Actions" | 102988,155532 1 0 0 "SDInitRdy <= 1'b0;\nloopCnt <= 8'h00;\nspiClkDelayOut <= `SLOW_SPI_CLK;\ninitError <= `INIT_NO_ERROR;" -L 140 141 0 TEXT "State Labels" | 111114,126510 1 0 0 "CLK_SEQ" -S 141 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111114,126510 6500 6500 -H 142 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -A 425 290 4 TEXT "Actions" | 124357,213854 1 0 0 "sendCmdReq <= 1'b0;" -I 421 142 0 Builtin Exit | 134364,140858 -I 145 142 0 Builtin Entry | 63487,251949 -S 149 142 12288 ELLIPSE "States" | 82209,235260 6500 6500 -L 150 149 0 TEXT "State Labels" | 82209,235260 1 0 0 "SEND_FF\n/2/" -S 151 142 16384 ELLIPSE "States" | 83028,207141 6500 6500 -L 152 151 0 TEXT "State Labels" | 83028,207141 1 0 0 "CHK_FIN\n/3/" -W 153 142 0 149 151 BEZIER "Transitions" | 82316,228817 82452,225541 82726,217079 82876,213607 -C 154 153 0 TEXT "Conditions" | 86589,230362 1 0 0 "txDataFull == 1'b0" -A 155 153 16 TEXT "Actions" | 85757,225151 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" -A 156 151 4 TEXT "Actions" | 101046,207687 1 0 0 "txDataWen <= 1'b0;" -L 426 427 0 TEXT "Labels" | 150400,240650 1 0 0 "txDataEmpty" -I 427 0 2 Builtin InPort | 144400,240650 "" "" -W 428 142 0 401 421 BEZIER "Transitions" | 123115,158823 126115,154198 128614,145483 131614,140858 -C 429 428 0 TEXT "Conditions" | 127025,156275 1 0 0 "txDataEmpty == 1'b1" -W 162 142 0 145 149 BEZIER "Transitions" | 67172,251949 70925,248810 74553,243594 78306,240455 -W 164 142 1 151 401 BEZIER "Transitions" | 85234,201030 86934,197154 103559,165433 113217,164792 -C 165 164 0 TEXT "Conditions" | 91028,195541 1 0 0 "loopCnt == `SD_INIT_START_SEQ_LEN" -W 166 142 2 151 149 BEZIER "Transitions" | 76635,205968 69903,206580 58140,206268 54570,210178\ - 51000,214088 50184,228504 53380,232380 56576,236256\ - 69005,235825 75805,236369 -L 167 168 0 TEXT "State Labels" | 111972,95982 1 0 0 "RESET" -S 168 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111972,95982 6500 6500 -H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -L 191 192 0 TEXT "Labels" | 43350,253948 1 0 0 "loopCnt[7:0]" -I 192 0 130 Builtin Signal | 40350,253948 "" "" -END Index: trunk/Aldec/design0/src/sendCmd.asf =================================================================== --- trunk/Aldec/design0/src/sendCmd.asf (revision 3) +++ trunk/Aldec/design0/src/sendCmd.asf (nonexistent) @@ -1,231 +0,0 @@ -VERSION=1.15 -HEADER -FILE="sendCmd.asf" -FID=4788d213 -LANGUAGE=VERILOG -ENTITY="sendCmd" -FRAMES=ON -FREEOID=426 -"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendCmd.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// If sendCmdReq asserted, then send command to \n//// SD card. Command consists of command byte,\n//// 4 data bytes, and a checksum byte. \n//// Waits for response byte from SD card\n//// or times out if no response\n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n\n" -END -BUNDLES -B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 -B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 -B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 -B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 -B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 -B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 -B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -END -INSTHEADER 1 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 5000,5000 10000,10000 -END -INSTHEADER 168 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -OBJECTS -S 287 169 36864 ELLIPSE "States" | 58145,42664 6500 6500 -C 286 284 0 TEXT "Conditions" | 58455,63310 1 0 0 "txDataFull == 1'b0" -A 285 284 16 TEXT "Actions" | 58389,58640 1 0 0 "txDataOut <= dataByte3;\ntxDataWen <= 1'b1;" -W 284 169 0 289 287 BEZIER "Transitions" | 55994,62919 56515,59615 56972,52449 57396,49118 -G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: sendCmd" -A 5 0 1 TEXT "Actions" | 30400,270465 1 0 0 "-- diagram ACTION\nalways @(sendCmdReq1 or sendCmdReq2 ) begin\n sendCmdReq <= sendCmdReq1 | sendCmdReq2;\nend\n\nalways @(posedge clk) begin\n cmdByte <= cmdByte_1 | cmdByte_2;\n dataByte1 <= dataByte1_1 | dataByte1_2;\n dataByte2 <= dataByte2_1 | dataByte2_2;\n dataByte3 <= dataByte3_1 | dataByte3_2;\n dataByte4 <= dataByte4_1 | dataByte4_2;\n checkSumByte <= checkSumByte_1 | checkSumByte_2;\nend" -F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,208764 -L 7 6 0 TEXT "Labels" | 33841,199139 1 0 0 "sndCmdSt" -L 298 297 0 TEXT "State Labels" | 119183,117704 1 0 0 "D_BYTE4_ST\n/12/" -S 297 169 49152 ELLIPSE "States" | 119183,117704 6500 6500 -L 296 295 0 TEXT "State Labels" | 121962,90985 1 0 0 "D_BYTE4_FIN\n/11/" -S 295 169 45056 ELLIPSE "States" | 121962,90985 6500 6500 -C 294 292 0 TEXT "Conditions" | 122272,111631 1 0 0 "txDataFull == 1'b0" -A 293 292 16 TEXT "Actions" | 122206,106961 1 0 0 "txDataOut <= dataByte4;\ntxDataWen <= 1'b1;" -W 292 169 0 297 295 BEZIER "Transitions" | 119811,111240 120332,107936 120789,100770 121213,97439 -L 290 289 0 TEXT "State Labels" | 55366,69383 1 0 0 "D_BYTE3_ST\n/10/" -S 289 169 40960 ELLIPSE "States" | 55366,69383 6500 6500 -L 288 287 0 TEXT "State Labels" | 58145,42664 1 0 0 "D_BYTE3_FIN\n/9/" -W 319 169 0 205 247 BEZIER "Transitions" | 63983,140499 60844,135517 56583,126997 53444,122015 -A 318 295 4 TEXT "Actions" | 139150,86599 1 0 0 "txDataWen <= 1'b0;" -A 317 287 4 TEXT "Actions" | 76633,44284 1 0 0 "txDataWen <= 1'b0;" -A 316 225 4 TEXT "Actions" | 71992,91513 1 0 0 "txDataWen <= 1'b0;" -A 315 311 4 TEXT "Actions" | 134912,45978 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 10'h000;" -L 314 313 0 TEXT "State Labels" | 122732,70475 1 0 0 "CS_ST\n/14/" -S 313 169 57344 ELLIPSE "States" | 122732,70475 6500 6500 -L 312 311 0 TEXT "State Labels" | 125511,43756 1 0 0 "CS_FIN\n/13/" -S 311 169 53248 ELLIPSE "States" | 125511,43756 6500 6500 -C 310 308 0 TEXT "Conditions" | 125821,64402 1 0 0 "txDataFull == 1'b0" -A 309 308 16 TEXT "Actions" | 125755,59732 1 0 0 "txDataOut <= checkSumByte;\ntxDataWen <= 1'b1;" -W 308 169 0 313 311 BEZIER "Transitions" | 123360,64011 123881,60707 124338,53541 124762,50210 -W 335 169 0 332 182 BEZIER "Transitions" | 45364,251903 47642,252271 81651,254936 85013,246121 -W 334 169 0 185 332 BEZIER "Transitions" | 41073,269282 40336,265731 39290,259500 38553,255949 -S 332 169 61440 ELLIPSE "States" | 39325,249500 6500 6500 -L 331 332 0 TEXT "State Labels" | 39325,251108 1 0 0 "SEND_FF_ST\n/15/" -I 329 0 2 Builtin Signal | 178213,215725 "" "" -L 328 329 0 TEXT "Labels" | 181213,215725 1 0 0 "sendCmdReq" -L 327 326 0 TEXT "Labels" | 157273,263636 1 0 0 "sendCmdReq2" -I 326 0 2 Builtin InPort | 151273,263636 "" "" -I 325 0 2 Builtin InPort | 151961,268514 "" "" -L 324 325 0 TEXT "Labels" | 157961,268514 1 0 0 "sendCmdReq1" -W 322 169 0 295 313 BEZIER "Transitions" | 122244,84497 122585,81836 122598,79603 122939,76942 -W 321 169 0 287 297 BEZIER "Transitions" | 63804,39468 72608,38035 85574,34251 91921,34114\ - 98268,33978 106049,36299 107653,41212 109257,46126\ - 107891,63463 106287,73597 104684,83732 99633,106938\ - 99837,114069 100042,121201 105913,126526 108335,126867\ - 110758,127208 113121,124683 115032,122704 -W 320 169 0 225 289 BEZIER "Transitions" | 54252,82625 54525,80100 54595,78388 54868,75863 -A 351 260 16 TEXT "Actions" | 146029,190376 1 0 0 "respTout <= 1'b1;" -A 338 335 16 TEXT "Actions" | 57237,258852 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1" -C 337 335 0 TEXT "Conditions" | 46128,249292 1 0 0 "txDataFull == 1'b0" -I 74 0 2 Builtin InPort | 195700,267632 "" "" -L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" -I 72 0 3 Builtin InPort | 195700,272800 "" "" -L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" -L 367 366 0 TEXT "Labels" | 118445,251448 1 0 0 "dataByte2_2[7:0]" -I 366 0 130 Builtin InPort | 112445,251448 "" "" -L 365 364 0 TEXT "Labels" | 118188,256588 1 0 0 "dataByte2_1[7:0]" -I 364 0 130 Builtin InPort | 112188,256588 "" "" -L 363 362 0 TEXT "Labels" | 118445,261214 1 0 0 "dataByte1_2[7:0]" -I 362 0 130 Builtin InPort | 112445,261214 "" "" -I 361 0 130 Builtin InPort | 112448,265583 "" "" -L 360 361 0 TEXT "Labels" | 118448,265583 1 0 0 "dataByte1_1[7:0]" -A 358 253 16 TEXT "Actions" | 138128,223118 1 0 0 "respByte <= rxDataIn;" -C 357 356 0 TEXT "Conditions" | 73122,198009 1 0 0 "rst == 1'b1" -W 356 6 0 355 100 BEZIER "Transitions" | 60594,200141 72339,199739 94500,197787 106245,197385 -I 355 6 0 Builtin Reset | 60594,200141 -W 354 6 0 168 102 BEZIER "Transitions" | 105630,145031 98556,147323 85638,151108 82264,155037\ - 78891,158967 79547,170103 83247,173083 86948,176063\ - 98835,174994 105909,175387 -L 95 96 0 TEXT "Labels" | 155940,273023 1 0 0 "sendCmdRdy" -I 383 0 130 Builtin Signal | 177941,226776 "" "" -L 382 383 0 TEXT "Labels" | 180941,226776 1 0 0 "dataByte4[7:0]" -I 381 0 130 Builtin Signal | 178198,220865 "" "" -L 380 381 0 TEXT "Labels" | 181198,220865 1 0 0 "checkSumByte[7:0]" -L 379 378 0 TEXT "Labels" | 117931,223949 1 0 0 "checkSumByte_2[7:0]" -I 378 0 130 Builtin InPort | 111931,223949 "" "" -L 377 376 0 TEXT "Labels" | 117931,228318 1 0 0 "checkSumByte_1[7:0]" -I 376 0 130 Builtin InPort | 111931,228318 "" "" -L 375 374 0 TEXT "Labels" | 118188,232687 1 0 0 "dataByte4_2[7:0]" -I 374 0 130 Builtin InPort | 112188,232687 "" "" -L 373 372 0 TEXT "Labels" | 118188,237313 1 0 0 "dataByte4_1[7:0]" -I 372 0 130 Builtin InPort | 112188,237313 "" "" -L 371 370 0 TEXT "Labels" | 118188,241939 1 0 0 "dataByte3_2[7:0]" -I 370 0 130 Builtin InPort | 112188,241939 "" "" -L 369 368 0 TEXT "Labels" | 118188,246822 1 0 0 "dataByte3_1[7:0]" -I 368 0 130 Builtin InPort | 112188,246822 "" "" -I 111 0 2 Builtin OutPort | 150520,249425 "" "" -L 110 109 0 TEXT "Labels" | 158977,244784 1 0 0 "txDataFull" -I 109 0 2 Builtin InPort | 152977,244784 "" "" -L 108 107 0 TEXT "Labels" | 192010,249698 1 0 0 "rxDataRdy" -I 107 0 2 Builtin InPort | 186010,249698 "" "" -W 106 6 0 102 168 BEZIER "Transitions" | 112025,167024 112028,164120 111877,156052 111880,149910 -W 105 6 0 100 102 BEZIER "Transitions" | 112303,189956 112099,186817 112066,183113 111862,179974 -S 102 6 65536 ELLIPSE "States" | 112128,173499 6500 6500 -L 101 102 0 TEXT "State Labels" | 112128,173499 1 0 0 "WT_CMD\n/17/" -S 100 6 69632 ELLIPSE "States" | 112674,196431 6500 6500 -L 99 100 0 TEXT "State Labels" | 112674,196431 1 0 0 "ST_S_CMD\n/18/" -I 96 0 2 Builtin OutPort | 149940,273023 "" "" -I 391 0 130 Builtin OutPort | 109748,219216 "" "" -L 390 391 0 TEXT "Labels" | 115748,219216 1 0 0 "respByte[7:0]" -L 389 388 0 TEXT "Labels" | 181327,240140 1 0 0 "dataByte1[7:0]" -I 388 0 130 Builtin Signal | 178327,240140 "" "" -L 387 386 0 TEXT "Labels" | 181327,235771 1 0 0 "dataByte2[7:0]" -I 386 0 130 Builtin Signal | 178327,235771 "" "" -L 385 384 0 TEXT "Labels" | 181070,231402 1 0 0 "dataByte3[7:0]" -I 384 0 130 Builtin Signal | 178070,231402 "" "" -C 123 106 0 TEXT "Conditions" | 113758,166364 1 0 0 "sendCmdReq == 1'b1" -L 122 121 0 TEXT "Labels" | 189826,245330 1 0 0 "rxDataRdyClr" -I 121 0 2 Builtin OutPort | 183826,245330 "" "" -L 118 117 0 TEXT "Labels" | 156520,254066 1 0 0 "txDataOut[7:0]" -I 117 0 130 Builtin OutPort | 150520,254066 "" "" -L 116 115 0 TEXT "Labels" | 191737,253793 1 0 0 "rxDataIn[7:0]" -I 115 0 130 Builtin InPort | 185737,253793 "" "" -L 112 111 0 TEXT "Labels" | 156520,249425 1 0 0 "txDataWen" -L 392 393 0 TEXT "Labels" | 155040,236450 1 0 0 "cmdByte_1[7:0]" -I 393 0 130 Builtin InPort | 149040,236450 "" "" -L 394 395 0 TEXT "Labels" | 155040,232130 1 0 0 "cmdByte_2[7:0]" -I 395 0 130 Builtin InPort | 149040,232130 "" "" -L 396 397 0 TEXT "Labels" | 115350,214850 1 0 0 "respTout" -I 397 0 2 Builtin OutPort | 109350,214850 "" "" -L 398 399 0 TEXT "Labels" | 156083,221028 1 0 0 "cmdByte[7:0]" -I 399 0 130 Builtin Signal | 153083,221028 "" "" -A 137 100 4 TEXT "Actions" | 132312,205914 1 0 0 "sendCmdRdy <= 1'b0;\ntxDataWen <= 1'b0;\ntxDataOut <= 8'h00;\nrxDataRdyClr <= 1'b0;\nrespByte <= 8'h00;\nrespTout <= 1'b0;\ntimeOutCnt <= 10'h000;" -A 138 102 4 TEXT "Actions" | 124218,176348 1 0 0 "sendCmdRdy <= 1'b1;" -A 139 106 16 TEXT "Actions" | 108893,161005 1 0 0 "sendCmdRdy <= 1'b0;\nrespTout <= 1'b0;" -L 400 401 0 TEXT "Labels" | 156156,216020 1 0 0 "timeOutCnt[9:0]" -I 401 0 130 Builtin Signal | 153156,216020 "" "" -L 407 408 0 TEXT "Labels" | 158650,240900 1 0 0 "txDataEmpty" -I 408 0 2 Builtin InPort | 152650,240900 "" "" -A 412 410 16 TEXT "Actions" | 187604,127904 1 0 0 "" -C 411 410 0 TEXT "Conditions" | 176525,34775 1 0 0 "txDataEmpty == 1'b1" -W 410 169 0 311 234 BEZIER "Transitions" | 129680,38771 133617,37459 138963,34462 145962,34024\ - 152962,33587 173088,34463 180556,35962 188025,37462\ - 197775,42588 199431,55306 201088,68025 197962,113775\ - 186681,128962 175400,144150 133400,159150 122119,165962\ - 110838,172775 107712,185025 107774,191306 107837,197587\ - 111213,210463 112150,219431 113087,228400 113463,251400\ - 114962,258243 116462,265087 122088,269463 125056,270025\ - 128025,270588 133111,267776 136236,266714 -L 420 421 0 TEXT "State Labels" | 197224,232320 1 0 0 "DEL\n/19/" -S 421 169 77824 ELLIPSE "States" | 197224,232320 6500 6500 -W 422 169 0 234 421 BEZIER "Transitions" | 147223,260243 159499,254229 180037,242591 192313,236577 -A 423 422 16 TEXT "Actions" | 153948,265428 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\ntimeOutCnt <= timeOutCnt + 1'b1;\nrxDataRdyClr <= 1'b1;" -W 424 169 0 421 237 BEZIER "Transitions" | 190754,232933 178974,233801 160757,232683 148977,233551 -A 425 424 16 TEXT "Actions" | 157420,238644 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" -L 167 168 0 TEXT "State Labels" | 111928,143426 1 0 0 "CMD" -S 168 6 73732 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111928,143426 6500 6500 -H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28668,29070 213168,277070 -S 176 169 65536 ELLIPSE "States" | 60614,226551 6500 6500 -A 177 176 4 TEXT "Actions" | 78632,227097 1 0 0 "txDataWen <= 1'b0;" -W 178 169 0 182 176 BEZIER "Transitions" | 85317,242783 68957,244509 60312,236489 60462,233017 -L 181 176 0 TEXT "State Labels" | 60614,226551 1 0 0 "CMD_BYTE_ST\n/16/" -S 182 169 8192 ELLIPSE "States" | 91419,245022 6500 6500 -L 183 182 0 TEXT "State Labels" | 91419,245558 1 0 0 "SEND_FF_FIN\n/2/" -I 184 169 0 Builtin Exit | 133914,177514 -I 185 169 0 Builtin Entry | 41073,271359 -L 193 194 0 TEXT "State Labels" | 61318,198350 1 0 0 "CMD_BYTE_FIN\n/3/" -S 194 169 12288 ELLIPSE "States" | 61318,198350 6500 6500 -W 197 169 0 176 194 BEZIER "Transitions" | 60038,220079 60241,216895 60646,208095 60689,204810 -C 200 197 0 TEXT "Conditions" | 62427,219576 1 0 0 "txDataFull == 1'b0" -A 201 197 16 TEXT "Actions" | 62131,214610 1 0 0 "txDataOut <= cmdByte;\ntxDataWen <= 1'b1;" -W 202 169 0 242 205 BEZIER "Transitions" | 65275,171028 65478,167844 67531,155583 67557,152187 -A 203 202 16 TEXT "Actions" | 55728,165182 1 0 0 "txDataOut <= dataByte1;\ntxDataWen <= 1'b1;" -C 204 202 0 TEXT "Conditions" | 67553,171135 1 0 0 "txDataFull == 1'b0" -S 205 169 16384 ELLIPSE "States" | 67858,145716 6500 6500 -L 206 205 0 TEXT "State Labels" | 67858,145716 1 0 0 "D_BYTE1_FIN\n/4/" -W 222 169 0 247 225 BEZIER "Transitions" | 52145,109346 52666,106042 53123,98876 53547,95545 -A 223 222 16 TEXT "Actions" | 54540,105067 1 0 0 "txDataOut <= dataByte2;\ntxDataWen <= 1'b1;" -C 224 222 0 TEXT "Conditions" | 54606,109737 1 0 0 "txDataFull == 1'b0" -S 225 169 0 ELLIPSE "States" | 54296,89091 6500 6500 -L 226 225 0 TEXT "State Labels" | 54296,89091 1 0 0 "D_BYTE2_FIN\n/0/" -L 233 234 0 TEXT "State Labels" | 141088,262390 1 0 0 "REQ_RESP_ST\n/5/" -S 234 169 20480 ELLIPSE "States" | 141088,262390 6500 6500 -L 236 237 0 TEXT "State Labels" | 142710,231828 1 0 0 "REQ_RESP_FIN\n/6/" -S 237 169 24576 ELLIPSE "States" | 142710,231828 6500 6500 -L 238 239 0 TEXT "State Labels" | 145411,207811 1 0 0 "CHK_RESP\n/7/" -S 239 169 28672 ELLIPSE "States" | 145411,207811 6500 6500 -C 255 253 0 TEXT "Conditions" | 150412,229033 1 0 0 "rxDataRdy == 1'b1" -W 253 169 0 237 239 BEZIER "Transitions" | 143448,225372 143908,221460 144298,218142 144670,214266 -S 247 169 4096 ELLIPSE "States" | 51517,115810 6500 6500 -L 246 247 0 TEXT "State Labels" | 51517,115810 1 0 0 "D_BYTE2_ST\n/1/" -W 245 169 0 194 242 BEZIER "Transitions" | 62217,191914 62763,188911 63074,186881 63620,183878 -A 243 205 4 TEXT "Actions" | 77303,148032 1 0 0 "txDataWen <= 1'b0;" -S 242 169 32768 ELLIPSE "States" | 64894,177508 6500 6500 -L 241 242 0 TEXT "State Labels" | 64894,177508 1 0 0 "D_BYTE1_ST\n/8/" -A 240 194 4 TEXT "Actions" | 71835,200982 1 0 0 "txDataWen <= 1'b0;" -W 264 169 3 239 234 BEZIER "Transitions" | 140148,211623 134593,217246 123512,226873 120971,232699\ - 118431,238525 119380,250586 121717,254311 124054,258037\ - 130485,259851 134685,261273 -C 263 262 0 TEXT "Conditions" | 112592,197061 1 0 0 "respByte[7] == 1'b0" -W 262 169 2 239 184 BEZIER "Transitions" | 143473,201609 142051,196460 135404,184680 133914,179562 -C 261 260 0 TEXT "Conditions" | 158534,204974 1 0 0 "timeOutCnt == 10'h200" -W 260 169 1 239 184 BEZIER "Transitions" | 151546,205667 157905,203655 172683,180675 136858,177514 -END Index: trunk/Aldec/design0/src/spiCtrl.asf =================================================================== --- trunk/Aldec/design0/src/spiCtrl.asf (revision 3) +++ trunk/Aldec/design0/src/spiCtrl.asf (nonexistent) @@ -1,141 +0,0 @@ -VERSION=1.15 -HEADER -FILE="spiCtrl.asf" -FID=4788d213 -LANGUAGE=VERILOG -ENTITY="spiCtrl" -FRAMES=ON -FREEOID=187 -"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// spiCtrl.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// Controls access to the 3 types of SPI access\n//// Direct SPI access, SD initialisation, and SD block read/write\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" -END -BUNDLES -B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 -B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 -B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 -B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 -B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 -B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 -B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 -B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 -B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 -END -INSTHEADER 1 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 5000,5000 10000,10000 -END -INSTHEADER 99 -PAGE 25400,25400 215900,279400 -UPPERLEFT 0,0 -GRID=OFF -GRIDSIZE 0,0 10000,10000 -END -OBJECTS -G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: spiCtrl" -A 5 0 1 TEXT "Actions" | 30673,274317 1 0 0 "-- diagram ACTION" -F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,232796 -L 7 6 0 TEXT "Labels" | 32486,211363 1 0 0 "spiCtrlSt" -L 8 9 0 TEXT "Labels" | 166432,268121 1 0 0 "spiTransCtrl" -I 9 0 2 Builtin InPort | 160432,268121 "" "" -L 10 11 0 TEXT "Labels" | 164257,264286 1 0 0 "spiTransSts" -I 11 0 2 Builtin OutPort | 158257,264286 "" "" -L 14 15 0 TEXT "Labels" | 166314,272204 1 0 0 "spiTransType[1:0]" -I 15 0 130 Builtin InPort | 160314,272204 "" "" -S 78 6 0 ELLIPSE "States" | 117132,210174 6500 6500 -L 77 78 0 TEXT "State Labels" | 117132,210174 1 0 0 "ST_S_CTRL\n/0/" -C 75 70 0 TEXT "Conditions" | 64251,212776 1 0 0 "rst == 1'b1" -I 74 0 2 Builtin InPort | 195973,268451 "" "" -L 73 74 0 TEXT "Labels" | 201973,268451 1 0 0 "rst" -I 72 0 3 Builtin InPort | 195700,272800 "" "" -L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" -W 70 6 0 69 78 BEZIER "Transitions" | 55625,209356 74109,218718 92075,219949 111473,213370 -I 69 6 0 Builtin Reset | 54670,208387 -I 92 0 2 Builtin InPort | 99404,245269 "" "" -L 91 92 0 TEXT "Labels" | 105404,245269 1 0 0 "SDInitRdy" -I 90 0 2 Builtin OutPort | 97222,240694 "" "" -L 89 90 0 TEXT "Labels" | 103222,240694 1 0 0 "SDInitReq" -L 95 96 0 TEXT "State Labels" | 61517,181659 1 0 0 "WT_S_CTRL_REQ\n/1/" -S 96 6 4096 ELLIPSE "States" | 61517,181659 6500 6500 -W 97 6 0 78 96 BEZIER "Transitions" | 111858,206376 102862,186278 81827,184985 67818,183250 -L 98 99 0 TEXT "State Labels" | 61244,155715 1 0 0 "J1" -S 99 6 8196 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 61335,155624 3871 3871 -W 100 6 0 96 99 BEZIER "Transitions" | 61562,175246 61630,170469 58461,163807 60148,158618 -C 101 100 0 TEXT "Conditions" | 62422,174791 1 0 0 "spiTransCtrl == `TRANS_START" -A 102 100 16 TEXT "Actions" | 58411,169566 1 0 0 "spiTransSts <= `TRANS_BUSY;" -H 103 99 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 -I 106 103 0 Builtin Entry | 96520,182880 -I 107 103 0 Builtin Exit | 144780,121920 -W 108 103 0 106 107 BEZIER "Transitions" | 100342,182880 105892,175161 136499,129639 142050,121920 -L 110 111 0 TEXT "State Labels" | 138174,125339 1 0 0 "DIR_ACC\n/3/" -S 111 6 16384 ELLIPSE "States" | 138174,125339 6500 6500 -W 113 6 0 99 111 BEZIER "Transitions" | 61166,151770 61234,146806 61130,137919 61640,134485\ - 62150,131051 64054,127243 73166,126223 82278,125203\ - 114404,125351 131676,125215 -C 115 113 0 TEXT "Conditions" | 67726,131051 1 0 0 "spiTransType == `DIRECT_ACCESS" -L 120 121 0 TEXT "Labels" | 46442,250017 1 0 0 "txDataWen" -I 121 0 2 Builtin OutPort | 40442,250017 "" "" -A 123 113 16 TEXT "Actions" | 94110,126699 1 0 0 "txDataWen <= 1'b1;\nspiCS_n <= 1'b0;" -A 125 111 4 TEXT "Actions" | 125118,137851 1 0 0 "txDataWen <= 1'b0;" -L 126 127 0 TEXT "State Labels" | 164014,125067 1 0 0 "WT_FIN1\n/2/" -S 127 6 12288 ELLIPSE "States" | 164014,125067 6500 6500 -W 128 6 0 111 127 BEZIER "Transitions" | 144619,124502 150739,124502 151363,124352 157533,124582 -W 136 6 0 127 96 BEZIER "Transitions" | 162717,131431 160337,140339 156330,157231 149122,163725\ - 141914,170219 117842,178379 106656,180181 95470,181983\ - 78345,181829 68009,181353 -C 137 136 0 TEXT "Conditions" | 156126,140571 1 0 0 "rxDataRdy == 1'b1" -A 138 136 16 TEXT "Actions" | 144158,151179 1 0 0 "rxDataRdyClr <= 1'b1;\nspiCS_n <= 1'b1;" -A 139 96 4 TEXT "Actions" | 42430,197963 1 0 0 "rxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;" -L 140 141 0 TEXT "State Labels" | 138990,98683 1 0 0 "INIT\n/4/" -S 141 6 20480 ELLIPSE "States" | 138990,98683 6500 6500 -W 142 6 0 99 141 BEZIER "Transitions" | 60786,151798 60378,142958 58886,126563 58818,120307\ - 58750,114051 59294,106707 60280,104225 61266,101743\ - 64666,99159 74118,98581 83570,98003 115288,98421\ - 132492,98557 -C 144 142 0 TEXT "Conditions" | 66910,103851 1 0 0 "spiTransType == `INIT_SD" -A 146 142 16 TEXT "Actions" | 93022,99499 1 0 0 "SDInitReq <= 1'b1;" -L 147 148 0 TEXT "State Labels" | 163742,99499 1 0 0 "WT_FIN2\n/5/" -S 148 6 24576 ELLIPSE "States" | 163742,99499 6500 6500 -W 149 6 0 141 148 BEZIER "Transitions" | 145474,99128 150302,99196 152415,99360 157243,99428 -A 150 141 4 TEXT "Actions" | 122126,110651 1 0 0 "SDInitReq <= 1'b0;" -W 151 6 0 148 96 BEZIER "Transitions" | 168589,103829 172805,107705 180470,114663 182272,121531\ - 184074,128399 182850,148119 177444,156007 172038,163895\ - 151638,175727 141812,179059 131986,182391 113082,183887\ - 103562,183887 94042,183887 77595,182762 68007,182014 -C 152 151 0 TEXT "Conditions" | 162382,115003 1 0 0 "SDInitRdy == 1'b1" -L 153 154 0 TEXT "State Labels" | 139806,74203 1 0 0 "RW\n/6/" -S 154 6 28672 ELLIPSE "States" | 139806,74203 6500 6500 -L 155 156 0 TEXT "State Labels" | 165374,73931 1 0 0 "WT_FIN3\n/7/" -S 156 6 32768 ELLIPSE "States" | 165374,73931 6500 6500 -W 161 6 0 99 154 BEZIER "Transitions" | 60982,151777 60302,133009 58070,97323 58546,87327\ - 59022,77331 62286,74883 71942,74271 81598,73659\ - 115628,74049 133308,74049 -W 162 6 0 99 154 BEZIER "Transitions" | 61169,151767 60217,127151 57526,79507 57832,66587\ - 58138,53667 62998,56357 73205,49463 83413,42570\ - 122689,61354 133487,72683 -W 163 6 0 154 156 BEZIER "Transitions" | 146246,75076 150598,74736 154569,75047 158921,74707 -C 165 161 0 TEXT "Conditions" | 65006,80459 1 0 0 "spiTransType == `RW_WRITE_SD_BLOCK" -C 166 162 0 TEXT "Conditions" | 61742,61486 1 0 0 "spiTransType == `RW_READ_SD_BLOCK" -A 167 161 16 TEXT "Actions" | 64462,75019 1 0 0 "readWriteSDBlockReq <= `WRITE_SD_BLOCK;" -A 168 162 16 TEXT "Actions" | 60862,54842 1 0 0 "readWriteSDBlockReq <= `READ_SD_BLOCK;" -A 169 154 4 TEXT "Actions" | 103358,87803 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;" -W 170 6 0 156 96 BEZIER "Transitions" | 171013,77161 178425,82737 192778,92291 196144,105313\ - 199510,118335 198150,159271 192336,170967 186522,182663\ - 164626,188511 153678,189531 142730,190551 120834,188783\ - 109886,187661 98938,186539 78902,183914 67954,182554 -C 171 170 0 TEXT "Conditions" | 168638,86715 1 0 0 "readWriteSDBlockRdy == 1'b1" -L 172 173 0 TEXT "Labels" | 46441,240515 1 0 0 "rxDataRdyClr" -I 173 0 2 Builtin OutPort | 40441,240515 "" "" -L 176 177 0 TEXT "Labels" | 133432,244833 1 0 0 "readWriteSDBlockReq[1:0]" -I 177 0 130 Builtin OutPort | 127432,244833 "" "" -L 178 179 0 TEXT "Labels" | 48477,245479 1 0 0 "rxDataRdy" -I 179 0 2 Builtin InPort | 42477,245479 "" "" -L 182 183 0 TEXT "Labels" | 135468,240330 1 0 0 "readWriteSDBlockRdy" -I 183 0 2 Builtin InPort | 129468,240330 "" "" -A 184 78 4 TEXT "Actions" | 131510,229116 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;\ntxDataWen <= 1'b0;\nSDInitReq <= 1'b0;\nrxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;\nspiCS_n <= 1'b1;" -L 185 186 0 TEXT "Labels" | 165711,256531 1 0 0 "spiCS_n" -I 186 0 2 Builtin OutPort | 159711,256531 "" "" -END Index: trunk/sim/run_icarus.bat =================================================================== --- trunk/sim/run_icarus.bat (revision 3) +++ trunk/sim/run_icarus.bat (nonexistent) @@ -1,2 +0,0 @@ -vvp testHarness - Index: trunk/sim/filelist.icarus =================================================================== --- trunk/sim/filelist.icarus (revision 3) +++ trunk/sim/filelist.icarus (nonexistent) @@ -1,22 +0,0 @@ -../rtl/spiMaster.v -../rtl/sm_dpMem_dc.v -../rtl/sm_fifoRTL.v -../rtl/sm_RxFifoBI.v -../rtl/sm_TxFifoBI.v -../rtl/sm_RxFifo.v -../rtl/sm_TxFifo.v -../rtl/initSD.v -../rtl/readWriteSPIWireData.v -../rtl/readWriteSDBlock.v -../rtl/sendCmd.v -../rtl/spiCtrl.v -../rtl/spiTxRxData.v -../rtl/spiMasterWishBoneBI.v -../rtl/ctrlStsRegBI.v -../model/wb_master_model.v -../model/sdModel.v -../bench/testHarness.v -../bench/testCase0.v -+incdir+../rtl -+define+SIM_COMPILE - Index: trunk/sim/wave.do =================================================================== --- trunk/sim/wave.do (revision 3) +++ trunk/sim/wave.do (nonexistent) @@ -1,177 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider ctrlStsRegBI -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataIn -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/address -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/writeEn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/strobe_i -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/busClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiSysClk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/ctrlStsRegSel -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransType -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatus -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxData -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxData -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromWire -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToBusClkOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkOut -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteError -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadError -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitError -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDAddr -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiClkDelay -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/clk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstShift -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromBus -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxDataSTB -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxDataSTB -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransTypeSTB -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlSTB -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusSTB -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkFirst -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlShift -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg1 -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg2 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteErrorSTB -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadErrorSTB -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitErrorSTB -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg1 -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg2 -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg3 -add wave -noupdate -divider spiTxRxData -add wave -noupdate -divider readWriteSPIWireData -add wave -noupdate -divider spiCtrl -add wave -noupdate -divider initSD -add wave -noupdate -divider sendCmd -add wave -noupdate -divider sdModel -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataIn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiCS_n -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/rxByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/respByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/smSt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/cnt -add wave -noupdate -divider txFifo -add wave -noupdate -divider txFifoBI -add wave -noupdate -divider readWriteSDBlock -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/blockAddr -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/clk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockReq -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respByte -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respTout -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rst -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataIn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdy -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdRdy -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataEmpty -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataFull -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoData -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/checkSumByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/cmdByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte1 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte2 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte3 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte4 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readError -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockRdy -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdyClr -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoData -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoWen -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdReq -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/spiCS_n -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataWen -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoRen -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/writeError -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_checkSumByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_cmdByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte1 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte2 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte3 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte4 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readError -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readWriteSDBlockRdy -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxDataRdyClr -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoData -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoWen -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_sendCmdReq -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_spiCS_n -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataWen -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txFifoRen -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_writeError -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt1 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt1 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt2 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt2 -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/locRespByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_locRespByte -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/loopCnt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_loopCnt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/timeOutCnt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_timeOutCnt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/CurrState_rwBlkSt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/NextState_rwBlkSt -add wave -noupdate -divider sm_fifo -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataOut -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataIn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rdClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/wrClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoREn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoWEn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmptySyncToWrClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rstSyncToRdClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmptySyncToRdClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rstSyncToWrClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmpty -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferCnt -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/numElementsInFifo -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndex -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/FIFO_DEPTH -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndexSyncToWrClk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndex -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndexSyncToRdClk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndexToMem -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/ADDR_WIDTH -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/FIFO_WIDTH -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataFromMem -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoFull -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoREnDelayed -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndexToMem -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoEmpty -add wave -noupdate -divider TxFifoBI -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busDataIn -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/address -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/writeEn -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/strobe_i -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/spiSysClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/rstSyncToBusClk -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/fifoSelect -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToBusClk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/numElementsInFifo -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/fifoWEn -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busDataOut -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToSpiClk -add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptyShift -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmpty -add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToSpiClkFirst -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {717201000 ps} 0} {{Cursor 2} {102093853 ps} 0} -configure wave -namecolwidth 456 -configure wave -valuecolwidth 73 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {7327222362 ps} {7443209350 ps} Index: trunk/sim/run.do =================================================================== --- trunk/sim/run.do (revision 3) +++ trunk/sim/run.do (nonexistent) @@ -1,5 +0,0 @@ -vsim testCase0 testHarness -do wave.do -run -all - - Index: trunk/sim/modelsim.ini =================================================================== --- trunk/sim/modelsim.ini (revision 3) +++ trunk/sim/modelsim.ini (nonexistent) @@ -1,332 +0,0 @@ -; Copyright 1991-2007 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -others = $MODEL_TECH/../modelsim.ini - -; Actel Primitive Libraries -; -; VHDL Section -; -;aact1 = $MODEL_TECH/../actel/vhdl/aact1 -;aact2 = $MODEL_TECH/../actel/vhdl/aact2 -;aact3 = $MODEL_TECH/../actel/vhdl/aact3 -;a3200dx = $MODEL_TECH/../actel/vhdl/a3200dx -;a40mx = $MODEL_TECH/../actel/vhdl/a40mx -;a42mx = $MODEL_TECH/../actel/vhdl/a42mx -;a54sxa = $MODEL_TECH/../actel/vhdl/a54sxa -; -; Verilog Section -; -;act1 = $MODEL_TECH/../actel/verilog/act1 -;act2 = $MODEL_TECH/../actel/verilog/act2 -;act3 = $MODEL_TECH/../actel/verilog/act3 -;3200dx = $MODEL_TECH/../actel/verilog/3200dx -;40mx = $MODEL_TECH/../actel/verilog/40mx -;42mx = $MODEL_TECH/../actel/verilog/42mx -;54sxa = $MODEL_TECH/../actel/verilog/54sxa - -work = work -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -VHDL93 = 2002 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -[vlog] - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Turn on incremental compilation of modules. Default is off. -; Incremental = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -[vsim] -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = ps - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 5000 - -; Directive to license manager: -; vhdl Immediately reserve a VHDL license -; vlog Immediately reserve a Verilog license -; plus Immediately reserve a VHDL and Verilog license -; nomgc Do not look for Mentor Graphics Licenses -; nomti Do not look for Model Technology Licenses -; noqueue Do not wait in the license queue when a license isn't available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license -; License = plus - -; Stop the simulator after a VHDL/Verilog assertion message -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Assertion Message Format -; %S - Severity Level -; %R - Report Message -; %T - Time of assertion -; %D - Delta -; %I - Instance or Region pathname (if available) -; %% - print '%' character -; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Assertion File - alternate file for storing VHDL/Verilog assertion messages -; AssertFile = assert.log - -; Default radix for all windows and commands... -; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned -DefaultRadix = symbolic - -; VSIM Startup command -; Startup = do startup.do - -; File for saving command transcript -TranscriptFile = transcript - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example, sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings from the std_logic_arith, std_logic_unsigned -; and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from the IEEE numeric_std and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Control the format of the (VHDL) FOR generate statement label -; for each iteration. Do not quote it. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate_label; the %d represents the generate parameter value -; at a particular generate iteration (this is the position number if -; the generate parameter is of an enumeration type). Embedded whitespace -; is allowed (but discouraged); leading and trailing whitespace is ignored. -; Application of the format must result in a unique scope name over all -; such names in the design so that name lookup can function properly. -; GenerateFormat = %s__%d - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -; DefaultRestartOptions = -force - -; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs -; (> 500 megabyte memory footprint). Default is disabled. -; Specify number of megabytes to lock. -; LockedMemory = 1000 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -[lmc] - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; Examples: -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3043 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of elaboration/runtime messages. -; The default is to have messages appear in the transcript and -; recorded in the wlf file (messages that are recorded in the -; wlf file can be viewed in the MsgViewer). The other settings -; are to send messages only to the transcript or only to the -; wlf file. The valid values are -; both {default} -; tran {transcript only} -; wlf {wlf file only} -; msgmode = both Index: trunk/sim/compile.do =================================================================== --- trunk/sim/compile.do (revision 3) +++ trunk/sim/compile.do (nonexistent) @@ -1,22 +0,0 @@ - -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_dpMem_dc.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_fifoRTL.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_RxFifoBI.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_TxFifoBI.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_RxFifo.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_TxFifo.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/initSD.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSPIWireData.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSDBlock.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sendCmd.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiCtrl.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiTxRxData.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMaster.v -vlog +define+SIM_COMPILE +incdir+../rtl ../model/wb_master_model.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMasterWishBoneBI.v -vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/ctrlStsRegBI.v -vlog +define+SIM_COMPILE +incdir+../rtl ../model/sdModel.v -vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testHarness.v -vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testCase0.v - - Index: trunk/sim/build_icarus.bat =================================================================== --- trunk/sim/build_icarus.bat (revision 3) +++ trunk/sim/build_icarus.bat (nonexistent) @@ -1,4 +0,0 @@ -iverilog -o testHarness -cfilelist.icarus - -pause - Index: spimaster/trunk/bench/testCase0.v =================================================================== --- spimaster/trunk/bench/testCase0.v (nonexistent) +++ spimaster/trunk/bench/testCase0.v (revision 4) @@ -0,0 +1,144 @@ +// ---------------------------------- testcase0.v ---------------------------- +`include "timescale.v" +`include "spiMaster_defines.v" + +module testCase0(); + +reg ack; +reg [7:0] data; +reg [15:0] dataWord; +reg [7:0] dataRead; +reg [7:0] dataWrite; +integer i; +integer j; + +initial +begin + $write("\n\n"); + //testHarness.reset; + #1000; + + //write to block addr reg, and read back + //testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , 8'h5a); + $write("Testing register read/write\n"); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12); + + //write one byte to spi bus, and wait for complete + $write("Testing SPI bus direct access\n"); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `DIRECT_ACCESS}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'h5f); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + + //write one byte to spi bus, and wait for complete + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'haa); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + + //init test + $write("Testing SD init\n"); + testHarness.u_sdModel.setRespByte(8'h01); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `INIT_SD}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #60000; + testHarness.u_sdModel.setRespByte(8'h00); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[1:0] == `INIT_NO_ERROR) + $write("SD init test passed\n"); + else + $write("---- ERROR: SD init test failed. Error code = 0x%01x\n", dataRead[1:0] ); + + //block write + $write("Testing block write\n"); + dataWrite = 8'h00; + for (i=0; i<=2; i=i+1) begin + testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_DATA_REG , dataWrite); + dataWrite = dataWrite + 1'b1; + end + testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_CONTROL_REG , 8'h01); //empty the fifo + dataWrite = 8'h00; + for (i=0; i<=511; i=i+1) begin + testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_DATA_REG , dataWrite); + dataWrite = dataWrite + 1'b1; + end + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_WRITE_SD_BLOCK}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #100000; + testHarness.u_sdModel.setRespByte(8'h05); //write response + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + if (dataRead[0] == `TRANS_BUSY) begin + $write("---- ERROR: SD block write failed to complete\n"); + end + else begin + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[5:4] == `WRITE_NO_ERROR) + $write("SD block write passed\n"); + else + $write("---- ERROR: SD block write failed. Error code = 0x%01x\n", dataRead[5:4] ); + end + + //block read + $write("Testing block read\n"); + testHarness.u_sdModel.setRespByte(8'h00); //cmd response + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_READ_SD_BLOCK}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #100000; + testHarness.u_sdModel.setRespByte(8'hfe); //read response + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + #8000000; + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + if (dataRead[0] == `TRANS_BUSY) begin + $write("---- ERROR: SD block read failed to complete\n"); + end + else begin + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[3:2] == `READ_NO_ERROR) begin + $write("SD block read passed\n"); + for (j=0; j<=15; j=j+1) begin + $write("Data 0x%0x = ",j*32); + for (i=0; i<=31; i=i+1) begin + testHarness.u_wb_master_model.wb_read(1, `RX_FIFO_BASE+`FIFO_DATA_REG , dataRead); + $write("0x%0x ",dataRead); + end + $write("\n"); + end + end + else + $write("---- ERROR: SD block read failed. Error code = 0x%01x\n", dataRead[3:2] ); + end + + $write("Finished all tests\n"); + $stop; + +end + +endmodule + Index: spimaster/trunk/bench/testHarness.v =================================================================== --- spimaster/trunk/bench/testHarness.v (nonexistent) +++ spimaster/trunk/bench/testHarness.v (revision 4) @@ -0,0 +1,105 @@ +`include "timescale.v" + +module testHarness( ); + + +// ----------------------------------- +// Local Wires +// ----------------------------------- +reg clk; +reg rst; +reg spiSysClk; +wire [7:0] adr; +wire [7:0] masterDout; +wire [7:0] masterDin; +wire stb; +wire we; +wire ack; +wire spiClk; +wire spiMasterDataIn; +wire spiMasterDataOut; +wire spiCS_n; + + +initial begin +$dumpfile("wave.vcd"); +$dumpvars(0, u_spiMaster); +end + +spiMaster u_spiMaster ( + //Wishbone bus + .clk_i(clk), + .rst_i(rst), + .address_i(adr), + .data_i(masterDout), + .data_o(masterDin), + .strobe_i(stb), + .we_i(we), + .ack_o(ack), + + // SPI logic clock + .spiSysClk(spiSysClk), + + //SPI bus + .spiClkOut(spiClk), + .spiDataIn(spiMasterDataIn), + .spiDataOut(spiMasterDataOut), + .spiCS_n(spiCS_n) +); + +wb_master_model #(.dwidth(8), .awidth(8)) u_wb_master_model ( + .clk(clk), + .rst(rst), + .adr(adr), + .din(masterDin), + .dout(masterDout), + .cyc(), + .stb(stb), + .we(we), + .sel(), + .ack(ack), + .err(1'b0), + .rty(1'b0) +); + +sdModel u_sdModel ( + .spiClk(spiClk), + .spiDataIn(spiMasterDataOut), + .spiDataOut(spiMasterDataIn), + .spiCS_n(spiCS_n) +); +//--------------- reset --------------- +initial begin + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + rst <= 1'b1; + @(posedge clk); + rst <= 1'b0; + @(posedge clk); +end + +// ****************************** Clock section ****************************** +`define CLK_50MHZ_HALF_PERIOD 10 +`define CLK_25MHZ_HALF_PERIOD 20 + +always begin + #`CLK_25MHZ_HALF_PERIOD clk <= 1'b0; + #`CLK_25MHZ_HALF_PERIOD clk <= 1'b1; +end + +always begin + #`CLK_50MHZ_HALF_PERIOD spiSysClk <= 1'b0; + #`CLK_50MHZ_HALF_PERIOD spiSysClk <= 1'b1; +end + + + + +endmodule + Index: spimaster/trunk/RTL/readWriteSPIWireData.v =================================================================== --- spimaster/trunk/RTL/readWriteSPIWireData.v (nonexistent) +++ spimaster/trunk/RTL/readWriteSPIWireData.v (revision 4) @@ -0,0 +1,228 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// readWriteSPIWireData.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Wait for TX data bytes. When data is ready generate +//// SPI TX data, SPI CLK, and read SPI RX data +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module readWriteSPIWireData (clk, clkDelay, rst, rxDataOut, rxDataRdySet, spiClkOut, spiDataIn, spiDataOut, txDataEmpty, txDataFull, txDataFullClr, txDataIn); +input clk; +input [7:0]clkDelay; +input rst; +input spiDataIn; +input txDataFull; +input [7:0]txDataIn; +output [7:0]rxDataOut; +output rxDataRdySet; +output spiClkOut; +output spiDataOut; +output txDataEmpty; +output txDataFullClr; + +wire clk; +wire [7:0]clkDelay; +wire rst; +reg [7:0]rxDataOut, next_rxDataOut; +reg rxDataRdySet, next_rxDataRdySet; +reg spiClkOut, next_spiClkOut; +wire spiDataIn; +reg spiDataOut, next_spiDataOut; +reg txDataEmpty, next_txDataEmpty; +wire txDataFull; +reg txDataFullClr, next_txDataFullClr; +wire [7:0]txDataIn; + +// diagram signals declarations +reg [3:0]bitCnt, next_bitCnt; +reg [7:0]clkDelayCnt, next_clkDelayCnt; +reg [7:0]rxDataShiftReg, next_rxDataShiftReg; +reg [7:0]txDataShiftReg, next_txDataShiftReg; + +// BINARY ENCODED state machine: rwSPISt +// State codes definitions: +`define WT_TX_DATA 2'b00 +`define CLK_HI 2'b01 +`define CLK_LO 2'b10 +`define ST_RW_WIRE 2'b11 + +reg [1:0]CurrState_rwSPISt, NextState_rwSPISt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: rwSPISt + +// NextState logic (combinatorial) +always @ (txDataFull or txDataIn or clkDelayCnt or clkDelay or txDataShiftReg or rxDataShiftReg or spiDataIn or bitCnt or rxDataRdySet or txDataEmpty or txDataFullClr or spiClkOut or spiDataOut or rxDataOut or CurrState_rwSPISt) +begin + NextState_rwSPISt <= CurrState_rwSPISt; + // Set default values for outputs and signals + next_rxDataRdySet <= rxDataRdySet; + next_txDataEmpty <= txDataEmpty; + next_txDataShiftReg <= txDataShiftReg; + next_rxDataShiftReg <= rxDataShiftReg; + next_bitCnt <= bitCnt; + next_clkDelayCnt <= clkDelayCnt; + next_txDataFullClr <= txDataFullClr; + next_spiClkOut <= spiClkOut; + next_spiDataOut <= spiDataOut; + next_rxDataOut <= rxDataOut; + case (CurrState_rwSPISt) // synopsys parallel_case full_case + `WT_TX_DATA: + begin + next_rxDataRdySet <= 1'b0; + next_txDataEmpty <= 1'b1; + if (txDataFull == 1'b1) + begin + NextState_rwSPISt <= `CLK_HI; + next_txDataShiftReg <= txDataIn; + next_rxDataShiftReg <= 8'h00; + next_bitCnt <= 4'h0; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b1; + next_txDataEmpty <= 1'b0; + end + end + `CLK_HI: + begin + next_clkDelayCnt <= clkDelayCnt + 1'b1; + next_txDataFullClr <= 1'b0; + next_rxDataRdySet <= 1'b0; + if (clkDelayCnt == clkDelay) + begin + NextState_rwSPISt <= `CLK_LO; + next_spiClkOut <= 1'b0; + next_spiDataOut <= txDataShiftReg[7]; + next_txDataShiftReg <= {txDataShiftReg[6:0], 1'b0}; + next_rxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn}; + next_clkDelayCnt <= 8'h00; + end + end + `CLK_LO: + begin + next_clkDelayCnt <= clkDelayCnt + 1'b1; + if ((bitCnt == 4'h8) && (txDataFull == 1'b1)) + begin + NextState_rwSPISt <= `CLK_HI; + next_rxDataRdySet <= 1'b1; + next_rxDataOut <= rxDataShiftReg; + next_txDataShiftReg <= txDataIn; + next_bitCnt <= 3'b000; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b1; + end + else if (bitCnt == 4'h8) + begin + NextState_rwSPISt <= `WT_TX_DATA; + next_rxDataRdySet <= 1'b1; + next_rxDataOut <= rxDataShiftReg; + end + else if (clkDelayCnt == clkDelay) + begin + NextState_rwSPISt <= `CLK_HI; + next_spiClkOut <= 1'b1; + next_bitCnt <= bitCnt + 1'b1; + next_clkDelayCnt <= 8'h00; + end + end + `ST_RW_WIRE: + begin + next_bitCnt <= 4'h0; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b0; + next_rxDataRdySet <= 1'b0; + next_txDataShiftReg <= 8'h00; + next_rxDataShiftReg <= 8'h00; + next_rxDataOut <= 8'h00; + next_spiDataOut <= 1'b0; + next_spiClkOut <= 1'b0; + next_txDataEmpty <= 1'b0; + NextState_rwSPISt <= `WT_TX_DATA; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_rwSPISt <= `ST_RW_WIRE; + else + CurrState_rwSPISt <= NextState_rwSPISt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + rxDataRdySet <= 1'b0; + txDataEmpty <= 1'b0; + txDataFullClr <= 1'b0; + spiClkOut <= 1'b0; + spiDataOut <= 1'b0; + rxDataOut <= 8'h00; + txDataShiftReg <= 8'h00; + rxDataShiftReg <= 8'h00; + bitCnt <= 4'h0; + clkDelayCnt <= 8'h00; + end + else + begin + rxDataRdySet <= next_rxDataRdySet; + txDataEmpty <= next_txDataEmpty; + txDataFullClr <= next_txDataFullClr; + spiClkOut <= next_spiClkOut; + spiDataOut <= next_spiDataOut; + rxDataOut <= next_rxDataOut; + txDataShiftReg <= next_txDataShiftReg; + rxDataShiftReg <= next_rxDataShiftReg; + bitCnt <= next_bitCnt; + clkDelayCnt <= next_clkDelayCnt; + end +end + +endmodule \ No newline at end of file Index: spimaster/trunk/RTL/spiMaster_defines.v =================================================================== --- spimaster/trunk/RTL/spiMaster_defines.v (nonexistent) +++ spimaster/trunk/RTL/spiMaster_defines.v (revision 4) @@ -0,0 +1,138 @@ +// ------------------------ spiMaster_defines.v ---------------------- +// Version 0.0 - April 2008. Created +// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and +// spiSysClk. Fixed bug in bus accessible reset. Changed names of +// fifo related modules to avoid conflict with other IP cores. +// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug +// in wb_ack. Fixed file headers, and added description +// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data +// from the SPI bus on the rising edge of SCLK. This increases the +// tsetup timing margin when reading SPI data. It turns out that the timing +// was marginal for some SD cards when using a 24Mhz SPI clock. +// Problem was exacerbated by the fact that the design prevents the +// final SPI interface Flipflops being pushed into the IO blocks. + +`define SPI_MASTER_VERSION_NUM 8'h12 +`define SPI_SYS_CLK_48MHZ +//`define SPI_SYS_CLK_30MHZ + +//memoryMap +`define CTRL_STS_REG_BASE 8'h00 +`define RX_FIFO_BASE 8'h10 +`define TX_FIFO_BASE 8'h20 +`define ADDRESS_DECODE_MASK 8'hf0 +`define SPI_MASTER_VERSION_REG 8'h00 +`define SPI_MASTER_CONTROL_REG 8'h01 +`define TRANS_TYPE_REG 8'h02 +`define TRANS_CTRL_REG 8'h03 +`define TRANS_STS_REG 8'h04 +`define TRANS_ERROR_REG 8'h05 +`define DIRECT_ACCESS_DATA_REG 8'h06 +`define SD_ADDR_7_0_REG 8'h07 +`define SD_ADDR_15_8_REG 8'h08 +`define SD_ADDR_23_16_REG 8'h09 +`define SD_ADDR_31_24_REG 8'h0a +`define SPI_CLK_DEL_REG 8'h0b + + +//FifoAddresses +`define FIFO_DATA_REG 3'b000 +`define FIFO_STATUS_REG 3'b001 +`define FIFO_DATA_COUNT_MSB 3'b010 +`define FIFO_DATA_COUNT_LSB 3'b011 +`define FIFO_CONTROL_REG 3'b100 + + +`ifdef SIM_COMPILE +`define SLOW_SPI_CLK 8'h2 +`define FAST_SPI_CLK 8'h00 +`define TWO_MS 10'h001 +`define TWO_FIFTY_MS 12'h001 +`define ONE_HUNDRED_MS 12'h00c +`else //not SIM_COMPILE + +`ifdef SPI_SYS_CLK_48MHZ + +// --------------- spiSysClk = 48MHz +// if you change the clock frequency you will need to change these constants + +// SLOW_SPI_CLK controls the SPI clock at start up. +// should be aiming for 400KHz +// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1 +`define SLOW_SPI_CLK 8'h3b +// controls the SPI clock after init is complete. +// should be aiming for 24MHz ? +// controls the SPI clock after init is complete. +// should be aiming for 24MHz ? +// if spiSysClk >= 48MHz +// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1 +// else FAST_SPI_CLK = 0 +`define FAST_SPI_CLK 8'h00 +// TWO_MS = ((2mS * spiSysClk) / 256) - 1 +`define TWO_MS 10'h177 +// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1 +`define TWO_FIFTY_MS 12'h0b6 +// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1 +`define ONE_HUNDRED_MS 12'h048 + +`else //not SPI_SYS_CLK_48MHZ + +`ifdef SPI_SYS_CLK_30MHZ +// --------------- spiSysClk = 30MHz +`define SLOW_SPI_CLK 8'h24 +`define FAST_SPI_CLK 8'h00 +`define TWO_MS 10'h0e9 +`define TWO_FIFTY_MS 12'h071 +`define ONE_HUNDRED_MS 12'h02c + +`endif //SPI_SYS_CLK_30MHZ +`endif //SPI_SYS_CLK_48MHZ +`endif //SIM_COMPILE + + + +`ifdef SIM_COMPILE +`define SD_INIT_START_SEQ_LEN 8'h03 +`define MAX_8_BIT 8'h08 +`else +`define SD_INIT_START_SEQ_LEN 8'ha0 +`define MAX_8_BIT 8'hff +`endif + + +`define WR_RESP_TOUT 12'hf00 + +`define NO_BLOCK_REQ 2'b00 +`define WRITE_SD_BLOCK 2'b01 +`define READ_SD_BLOCK 2'b10 + +`define READ_NO_ERROR 2'b00 +`define READ_CMD_ERROR 2'b01 +`define READ_TOKEN_ERROR 2'b10 + +`define WRITE_NO_ERROR 2'b00 +`define WRITE_CMD_ERROR 2'b01 +`define WRITE_DATA_ERROR 2'b10 +`define WRITE_BUSY_ERROR 2'b11 + + +`define TRANS_NOT_BUSY 1'b0 +`define TRANS_BUSY 1'b1 + +`define TRANS_START 1'b1 +`define TRANS_STOP 1'b0 + +`define DIRECT_ACCESS 2'b00 +`define INIT_SD 2'b01 +`define RW_READ_SD_BLOCK 2'b10 +`define RW_WRITE_SD_BLOCK 2'b11 + +`define INIT_NO_ERROR 2'b00 +`define INIT_CMD0_ERROR 2'b01 +`define INIT_CMD1_ERROR 2'b10 + +`define TX_FIFO_DEPTH 512 +`define TX_FIFO_ADDR_WIDTH 9 +`define RX_FIFO_DEPTH 512 +`define RX_FIFO_ADDR_WIDTH 9 + Index: spimaster/trunk/RTL/spiTxRxData.v =================================================================== --- spimaster/trunk/RTL/spiTxRxData.v (nonexistent) +++ spimaster/trunk/RTL/spiTxRxData.v (revision 4) @@ -0,0 +1,153 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spiTxRxData.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Mux access to SPI RX and TX data +//// +//// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +//`include "timescale.v" + +module spiTxRxData ( + clk, + rst, + + tx1DataIn, + tx2DataIn, + tx3DataIn, + tx4DataIn, + tx1DataWEn, + tx2DataWEn, + tx3DataWEn, + tx4DataWEn, + + txDataOut, + txDataFull, + txDataFullClr, + + rx1DataRdyClr, + rx2DataRdyClr, + rx3DataRdyClr, + rx4DataRdyClr, + + rxDataIn, + rxDataOut, + rxDataRdy, + rxDataRdySet +); + +input clk; +input rst; + +input [7:0] tx1DataIn; +input [7:0] tx2DataIn; +input [7:0] tx3DataIn; +input [7:0] tx4DataIn; +input tx1DataWEn; +input tx2DataWEn; +input tx3DataWEn; +input tx4DataWEn; + +output [7:0] txDataOut; +reg [7:0] txDataOut; +output txDataFull; +reg txDataFull; +input txDataFullClr; + +input rx1DataRdyClr; +input rx2DataRdyClr; +input rx3DataRdyClr; +input rx4DataRdyClr; + +input [7:0] rxDataIn; +output [7:0] rxDataOut; +reg [7:0] rxDataOut; +output rxDataRdy; +reg rxDataRdy; +input rxDataRdySet; + + +// --- Transmit control +always @(posedge clk) begin + if (rst == 1'b1) begin + txDataOut <= 8'h00; + txDataFull <= 1'b0; + end + else begin + if (tx1DataWEn == 1'b1) begin + txDataOut <= tx1DataIn; + txDataFull <= 1'b1; + end + else if (tx2DataWEn == 1'b1) begin + txDataOut <= tx2DataIn; + txDataFull <= 1'b1; + end + else if (tx3DataWEn == 1'b1) begin + txDataOut <= tx3DataIn; + txDataFull <= 1'b1; + end + else if (tx4DataWEn == 1'b1) begin + txDataOut <= tx4DataIn; + txDataFull <= 1'b1; + end + if (txDataFullClr == 1'b1) + txDataFull <= 1'b0; + end +end + +// --- Receive control +always @(posedge clk) begin + if (rst == 1'b1) begin + rxDataOut <= 8'h00; + rxDataRdy <= 1'b0; + end + else begin + if (rx1DataRdyClr == 1'b1 || rx2DataRdyClr == 1'b1 || rx3DataRdyClr == 1'b1 || rx4DataRdyClr == 1'b1) begin + rxDataRdy <= 1'b0; + end + if (rxDataRdySet == 1'b1) begin + rxDataRdy <= 1'b1; + rxDataOut <= rxDataIn; + end + end +end + +endmodule + Index: spimaster/trunk/RTL/sendCmd.v =================================================================== --- spimaster/trunk/RTL/sendCmd.v (nonexistent) +++ spimaster/trunk/RTL/sendCmd.v (revision 4) @@ -0,0 +1,370 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// sendCmd.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// If sendCmdReq asserted, then send command to +//// SD card. Command consists of command byte, +//// 4 data bytes, and a checksum byte. +//// Waits for response byte from SD card +//// or times out if no response +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + + +module sendCmd (checkSumByte_1, checkSumByte_2, clk, cmdByte_1, cmdByte_2, dataByte1_1, dataByte1_2, dataByte2_1, dataByte2_2, dataByte3_1, dataByte3_2, dataByte4_1, dataByte4_2, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, sendCmdRdy, sendCmdReq1, sendCmdReq2, txDataEmpty, txDataFull, txDataOut, txDataWen); +input [7:0]checkSumByte_1; +input [7:0]checkSumByte_2; +input clk; +input [7:0]cmdByte_1; +input [7:0]cmdByte_2; +input [7:0]dataByte1_1; +input [7:0]dataByte1_2; +input [7:0]dataByte2_1; +input [7:0]dataByte2_2; +input [7:0]dataByte3_1; +input [7:0]dataByte3_2; +input [7:0]dataByte4_1; +input [7:0]dataByte4_2; +input rst; +input [7:0]rxDataIn; +input rxDataRdy; +input sendCmdReq1; +input sendCmdReq2; +input txDataEmpty; +input txDataFull; +output [7:0]respByte; +output respTout; +output rxDataRdyClr; +output sendCmdRdy; +output [7:0]txDataOut; +output txDataWen; + +wire [7:0]checkSumByte_1; +wire [7:0]checkSumByte_2; +wire clk; +wire [7:0]cmdByte_1; +wire [7:0]cmdByte_2; +wire [7:0]dataByte1_1; +wire [7:0]dataByte1_2; +wire [7:0]dataByte2_1; +wire [7:0]dataByte2_2; +wire [7:0]dataByte3_1; +wire [7:0]dataByte3_2; +wire [7:0]dataByte4_1; +wire [7:0]dataByte4_2; +reg [7:0]respByte, next_respByte; +reg respTout, next_respTout; +wire rst; +wire [7:0]rxDataIn; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg sendCmdRdy, next_sendCmdRdy; +wire sendCmdReq1; +wire sendCmdReq2; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; + +// diagram signals declarations +reg [7:0]checkSumByte, next_checkSumByte; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg sendCmdReq, next_sendCmdReq; +reg [9:0]timeOutCnt, next_timeOutCnt; + +// BINARY ENCODED state machine: sndCmdSt +// State codes definitions: +`define CMD_D_BYTE2_FIN 5'b00000 +`define CMD_D_BYTE2_ST 5'b00001 +`define CMD_SEND_FF_FIN 5'b00010 +`define CMD_CMD_BYTE_FIN 5'b00011 +`define CMD_D_BYTE1_FIN 5'b00100 +`define CMD_REQ_RESP_ST 5'b00101 +`define CMD_REQ_RESP_FIN 5'b00110 +`define CMD_CHK_RESP 5'b00111 +`define CMD_D_BYTE1_ST 5'b01000 +`define CMD_D_BYTE3_FIN 5'b01001 +`define CMD_D_BYTE3_ST 5'b01010 +`define CMD_D_BYTE4_FIN 5'b01011 +`define CMD_D_BYTE4_ST 5'b01100 +`define CMD_CS_FIN 5'b01101 +`define CMD_CS_ST 5'b01110 +`define CMD_SEND_FF_ST 5'b01111 +`define CMD_CMD_BYTE_ST 5'b10000 +`define WT_CMD 5'b10001 +`define ST_S_CMD 5'b10010 +`define CMD_DEL 5'b10011 + +reg [4:0]CurrState_sndCmdSt, NextState_sndCmdSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION +always @(sendCmdReq1 or sendCmdReq2 ) begin +sendCmdReq <= sendCmdReq1 | sendCmdReq2; +end +always @(posedge clk) begin +cmdByte <= cmdByte_1 | cmdByte_2; +dataByte1 <= dataByte1_1 | dataByte1_2; +dataByte2 <= dataByte2_1 | dataByte2_2; +dataByte3 <= dataByte3_1 | dataByte3_2; +dataByte4 <= dataByte4_1 | dataByte4_2; +checkSumByte <= checkSumByte_1 | checkSumByte_2; +end + + +// Machine: sndCmdSt + +// NextState logic (combinatorial) +always @ (txDataFull or dataByte2 or timeOutCnt or rxDataRdy or rxDataIn or respByte or dataByte1 or dataByte3 or dataByte4 or txDataEmpty or checkSumByte or cmdByte or sendCmdReq or txDataWen or txDataOut or rxDataRdyClr or respTout or sendCmdRdy or CurrState_sndCmdSt) +begin + NextState_sndCmdSt <= CurrState_sndCmdSt; + // Set default values for outputs and signals + next_txDataWen <= txDataWen; + next_txDataOut <= txDataOut; + next_timeOutCnt <= timeOutCnt; + next_rxDataRdyClr <= rxDataRdyClr; + next_respByte <= respByte; + next_respTout <= respTout; + next_sendCmdRdy <= sendCmdRdy; + case (CurrState_sndCmdSt) // synopsys parallel_case full_case + `WT_CMD: + begin + next_sendCmdRdy <= 1'b1; + if (sendCmdReq == 1'b1) + begin + NextState_sndCmdSt <= `CMD_SEND_FF_ST; + next_sendCmdRdy <= 1'b0; + next_respTout <= 1'b0; + end + end + `ST_S_CMD: + begin + next_sendCmdRdy <= 1'b0; + next_txDataWen <= 1'b0; + next_txDataOut <= 8'h00; + next_rxDataRdyClr <= 1'b0; + next_respByte <= 8'h00; + next_respTout <= 1'b0; + next_timeOutCnt <= 10'h000; + NextState_sndCmdSt <= `WT_CMD; + end + `CMD_D_BYTE2_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE3_ST; + end + `CMD_D_BYTE2_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE2_FIN; + next_txDataOut <= dataByte2; + next_txDataWen <= 1'b1; + end + end + `CMD_SEND_FF_FIN: + begin + NextState_sndCmdSt <= `CMD_CMD_BYTE_ST; + end + `CMD_CMD_BYTE_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE1_ST; + end + `CMD_D_BYTE1_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE2_ST; + end + `CMD_REQ_RESP_ST: + begin + NextState_sndCmdSt <= `CMD_DEL; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_rxDataRdyClr <= 1'b1; + end + `CMD_REQ_RESP_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_sndCmdSt <= `CMD_CHK_RESP; + next_respByte <= rxDataIn; + end + end + `CMD_CHK_RESP: + begin + if (timeOutCnt == 10'h200) + begin + NextState_sndCmdSt <= `WT_CMD; + next_respTout <= 1'b1; + end + else if (respByte[7] == 1'b0) + begin + NextState_sndCmdSt <= `WT_CMD; + end + else + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_ST; + end + end + `CMD_D_BYTE1_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE1_FIN; + next_txDataOut <= dataByte1; + next_txDataWen <= 1'b1; + end + end + `CMD_D_BYTE3_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE4_ST; + end + `CMD_D_BYTE3_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE3_FIN; + next_txDataOut <= dataByte3; + next_txDataWen <= 1'b1; + end + end + `CMD_D_BYTE4_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_CS_ST; + end + `CMD_D_BYTE4_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE4_FIN; + next_txDataOut <= dataByte4; + next_txDataWen <= 1'b1; + end + end + `CMD_CS_FIN: + begin + next_txDataWen <= 1'b0; + next_timeOutCnt <= 10'h000; + if (txDataEmpty == 1'b1) + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_ST; + end + end + `CMD_CS_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_CS_FIN; + next_txDataOut <= checkSumByte; + next_txDataWen <= 1'b1; + end + end + `CMD_SEND_FF_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_SEND_FF_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `CMD_CMD_BYTE_ST: + begin + next_txDataWen <= 1'b0; + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_CMD_BYTE_FIN; + next_txDataOut <= cmdByte; + next_txDataWen <= 1'b1; + end + end + `CMD_DEL: + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_FIN; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_sndCmdSt <= `ST_S_CMD; + else + CurrState_sndCmdSt <= NextState_sndCmdSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + txDataWen <= 1'b0; + txDataOut <= 8'h00; + rxDataRdyClr <= 1'b0; + respByte <= 8'h00; + respTout <= 1'b0; + sendCmdRdy <= 1'b0; + timeOutCnt <= 10'h000; + end + else + begin + txDataWen <= next_txDataWen; + txDataOut <= next_txDataOut; + rxDataRdyClr <= next_rxDataRdyClr; + respByte <= next_respByte; + respTout <= next_respTout; + sendCmdRdy <= next_sendCmdRdy; + timeOutCnt <= next_timeOutCnt; + end +end + +endmodule \ No newline at end of file Index: spimaster/trunk/RTL/spiCtrl.v =================================================================== --- spimaster/trunk/RTL/spiCtrl.v (nonexistent) +++ spimaster/trunk/RTL/spiCtrl.v (revision 4) @@ -0,0 +1,223 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// spiCtrl.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Controls access to the 3 types of SPI access +//// Direct SPI access, SD initialisation, and SD block read/write +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module spiCtrl (clk, readWriteSDBlockRdy, readWriteSDBlockReq, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, spiCS_n, spiTransCtrl, spiTransSts, spiTransType, txDataWen); +input clk; +input readWriteSDBlockRdy; +input rst; +input rxDataRdy; +input SDInitRdy; +input spiTransCtrl; +input [1:0]spiTransType; +output [1:0]readWriteSDBlockReq; +output rxDataRdyClr; +output SDInitReq; +output spiCS_n; +output spiTransSts; +output txDataWen; + +wire clk; +wire readWriteSDBlockRdy; +reg [1:0]readWriteSDBlockReq, next_readWriteSDBlockReq; +wire rst; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +wire SDInitRdy; +reg SDInitReq, next_SDInitReq; +reg spiCS_n, next_spiCS_n; +wire spiTransCtrl; +reg spiTransSts, next_spiTransSts; +wire [1:0]spiTransType; +reg txDataWen, next_txDataWen; + +// BINARY ENCODED state machine: spiCtrlSt +// State codes definitions: +`define ST_S_CTRL 3'b000 +`define WT_S_CTRL_REQ 3'b001 +`define WT_FIN1 3'b010 +`define DIR_ACC 3'b011 +`define INIT 3'b100 +`define WT_FIN2 3'b101 +`define RW 3'b110 +`define WT_FIN3 3'b111 + +reg [2:0]CurrState_spiCtrlSt, NextState_spiCtrlSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: spiCtrlSt + +// NextState logic (combinatorial) +always @ (spiTransCtrl or rxDataRdy or spiTransType or SDInitRdy or readWriteSDBlockRdy or readWriteSDBlockReq or txDataWen or SDInitReq or rxDataRdyClr or spiTransSts or spiCS_n or CurrState_spiCtrlSt) +begin + NextState_spiCtrlSt <= CurrState_spiCtrlSt; + // Set default values for outputs and signals + next_readWriteSDBlockReq <= readWriteSDBlockReq; + next_txDataWen <= txDataWen; + next_SDInitReq <= SDInitReq; + next_rxDataRdyClr <= rxDataRdyClr; + next_spiTransSts <= spiTransSts; + next_spiCS_n <= spiCS_n; + case (CurrState_spiCtrlSt) // synopsys parallel_case full_case + `ST_S_CTRL: + begin + next_readWriteSDBlockReq <= `NO_BLOCK_REQ; + next_txDataWen <= 1'b0; + next_SDInitReq <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_spiTransSts <= `TRANS_NOT_BUSY; + next_spiCS_n <= 1'b1; + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + `WT_S_CTRL_REQ: + begin + next_rxDataRdyClr <= 1'b0; + next_spiTransSts <= `TRANS_NOT_BUSY; + if ((spiTransCtrl == `TRANS_START) && (spiTransType == `INIT_SD)) + begin + NextState_spiCtrlSt <= `INIT; + next_spiTransSts <= `TRANS_BUSY; + next_SDInitReq <= 1'b1; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_WRITE_SD_BLOCK)) + begin + NextState_spiCtrlSt <= `RW; + next_spiTransSts <= `TRANS_BUSY; + next_readWriteSDBlockReq <= `WRITE_SD_BLOCK; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_READ_SD_BLOCK)) + begin + NextState_spiCtrlSt <= `RW; + next_spiTransSts <= `TRANS_BUSY; + next_readWriteSDBlockReq <= `READ_SD_BLOCK; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `DIRECT_ACCESS)) + begin + NextState_spiCtrlSt <= `DIR_ACC; + next_spiTransSts <= `TRANS_BUSY; + next_txDataWen <= 1'b1; + next_spiCS_n <= 1'b0; + end + end + `WT_FIN1: + begin + if (rxDataRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + next_rxDataRdyClr <= 1'b1; + next_spiCS_n <= 1'b1; + end + end + `DIR_ACC: + begin + next_txDataWen <= 1'b0; + NextState_spiCtrlSt <= `WT_FIN1; + end + `INIT: + begin + next_SDInitReq <= 1'b0; + NextState_spiCtrlSt <= `WT_FIN2; + end + `WT_FIN2: + begin + if (SDInitRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + end + `RW: + begin + next_readWriteSDBlockReq <= `NO_BLOCK_REQ; + NextState_spiCtrlSt <= `WT_FIN3; + end + `WT_FIN3: + begin + if (readWriteSDBlockRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_spiCtrlSt <= `ST_S_CTRL; + else + CurrState_spiCtrlSt <= NextState_spiCtrlSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + readWriteSDBlockReq <= `NO_BLOCK_REQ; + txDataWen <= 1'b0; + SDInitReq <= 1'b0; + rxDataRdyClr <= 1'b0; + spiTransSts <= `TRANS_NOT_BUSY; + spiCS_n <= 1'b1; + end + else + begin + readWriteSDBlockReq <= next_readWriteSDBlockReq; + txDataWen <= next_txDataWen; + SDInitReq <= next_SDInitReq; + rxDataRdyClr <= next_rxDataRdyClr; + spiTransSts <= next_spiTransSts; + spiCS_n <= next_spiCS_n; + end +end + +endmodule \ No newline at end of file Index: spimaster/trunk/RTL/spiMasterWishBoneBI.v =================================================================== --- spimaster/trunk/RTL/spiMasterWishBoneBI.v (nonexistent) +++ spimaster/trunk/RTL/spiMasterWishBoneBI.v (revision 4) @@ -0,0 +1,145 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spiMasterWishBoneBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Control WB access to fifos and control and status registers +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + + +module spiMasterWishBoneBI ( + clk, rst, + address, dataIn, dataOut, writeEn, + strobe_i, + ack_o, + ctrlStsRegSel, + rxFifoSel, txFifoSel, + dataFromCtrlStsReg, + dataFromRxFifo, + dataFromTxFifo + ); +input clk; +input rst; +input [7:0] address; +input [7:0] dataIn; +output [7:0] dataOut; +input strobe_i; +output ack_o; +input writeEn; +output ctrlStsRegSel; +output rxFifoSel; +output txFifoSel; +input [7:0] dataFromCtrlStsReg; +input [7:0] dataFromRxFifo; +input [7:0] dataFromTxFifo; + + +wire clk; +wire rst; +wire [7:0] address; +wire [7:0] dataIn; +reg [7:0] dataOut; +wire writeEn; +wire strobe_i; +reg ack_o; +reg ctrlStsRegSel; +reg rxFifoSel; +reg txFifoSel; +wire [7:0] dataFromCtrlStsReg; +wire [7:0] dataFromRxFifo; +wire [7:0] dataFromTxFifo; + +//internal wires and regs +reg ack_delayed; +reg ack_immediate; + +//address decode and data mux +always @(address or + dataFromCtrlStsReg or + dataFromRxFifo or + dataFromTxFifo) +begin + ctrlStsRegSel <= 1'b0; + rxFifoSel <= 1'b0; + txFifoSel <= 1'b0; + case (address & `ADDRESS_DECODE_MASK) + `CTRL_STS_REG_BASE : begin + ctrlStsRegSel <= 1'b1; + dataOut <= dataFromCtrlStsReg; + end + `RX_FIFO_BASE : begin + rxFifoSel <= 1'b1; + dataOut <= dataFromRxFifo; + end + `TX_FIFO_BASE : begin + txFifoSel <= 1'b1; + dataOut <= dataFromTxFifo; + end + default: + dataOut <= 8'h00; + endcase +end + +//delayed ack +always @(posedge clk) begin + ack_delayed <= strobe_i; +end + +//immediate ack +always @(strobe_i) begin + ack_immediate <= strobe_i; +end + +//select between immediate and delayed ack +always @(writeEn or address or ack_delayed or ack_immediate) begin + if (writeEn == 1'b0 && + (address == `RX_FIFO_BASE + `FIFO_DATA_REG || + address == `TX_FIFO_BASE + `FIFO_DATA_REG) ) + begin + ack_o <= ack_delayed & ack_immediate; + end + else + begin + ack_o <= ack_immediate; + end +end + +endmodule Index: spimaster/trunk/RTL/readWriteSDBlock.v =================================================================== --- spimaster/trunk/RTL/readWriteSDBlock.v (nonexistent) +++ spimaster/trunk/RTL/readWriteSDBlock.v (revision 4) @@ -0,0 +1,730 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// readWriteSDBlock.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or +//// READ_SD_BLOCK, then write or read a 512 byte block +//// of SD memory +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module readWriteSDBlock (blockAddr, checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, readError, readWriteSDBlockRdy, readWriteSDBlockReq, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, rxFifoData, rxFifoWen, sendCmdRdy, sendCmdReq, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen, txFifoData, txFifoRen, writeError); +input [31:0]blockAddr; +input clk; +input [1:0]readWriteSDBlockReq; +input [7:0]respByte; +input respTout; +input rst; +input [7:0]rxDataIn; +input rxDataRdy; +input sendCmdRdy; +input txDataEmpty; +input txDataFull; +input [7:0]txFifoData; +output [7:0]checkSumByte; +output [7:0]cmdByte; +output [7:0]dataByte1; +output [7:0]dataByte2; +output [7:0]dataByte3; +output [7:0]dataByte4; +output [1:0]readError; +output readWriteSDBlockRdy; +output rxDataRdyClr; +output [7:0]rxFifoData; +output rxFifoWen; +output sendCmdReq; +output spiCS_n; +output [7:0]txDataOut; +output txDataWen; +output txFifoRen; +output [1:0]writeError; + +wire [31:0]blockAddr; +reg [7:0]checkSumByte, next_checkSumByte; +wire clk; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg [1:0]readError, next_readError; +reg readWriteSDBlockRdy, next_readWriteSDBlockRdy; +wire [1:0]readWriteSDBlockReq; +wire [7:0]respByte; +wire respTout; +wire rst; +wire [7:0]rxDataIn; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg [7:0]rxFifoData, next_rxFifoData; +reg rxFifoWen, next_rxFifoWen; +wire sendCmdRdy; +reg sendCmdReq, next_sendCmdReq; +reg spiCS_n, next_spiCS_n; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; +wire [7:0]txFifoData; +reg txFifoRen, next_txFifoRen; +reg [1:0]writeError, next_writeError; + +// diagram signals declarations +reg [7:0]delCnt1, next_delCnt1; +reg [7:0]delCnt2, next_delCnt2; +reg [7:0]locRespByte, next_locRespByte; +reg [8:0]loopCnt, next_loopCnt; +reg [11:0]timeOutCnt, next_timeOutCnt; + +// BINARY ENCODED state machine: rwBlkSt +// State codes definitions: +`define ST_RW_SD 6'b000000 +`define WR_CMD_SEND_CMD 6'b000001 +`define WR_CMD_WT_FIN 6'b000010 +`define WR_CMD_DEL 6'b000011 +`define WT_REQ 6'b000100 +`define WR_TOKEN_FF1_FIN 6'b000101 +`define WR_TOKEN_FF1_ST 6'b000110 +`define WR_TOKEN_FF2_FIN 6'b000111 +`define WR_TOKEN_FF2_ST 6'b001000 +`define WR_TOKEN_FE_FIN 6'b001001 +`define WR_TOKEN_FE_ST 6'b001010 +`define WR_DATA_D_FIN 6'b001011 +`define WR_DATA_D_ST 6'b001100 +`define WR_DATA_RD_FIFO1 6'b001101 +`define WR_DATA_RD_FIFO2 6'b001110 +`define WR_DATA_LOOP_INIT 6'b001111 +`define WR_DATA_CS_ST1 6'b010000 +`define WR_DATA_CS_FIN1 6'b010001 +`define WR_DATA_CS_FIN2 6'b010010 +`define WR_DATA_CS_ST2 6'b010011 +`define WR_DATA_CHK_RESP 6'b010100 +`define WR_DATA_REQ_RESP_ST 6'b010101 +`define WR_DATA_REQ_RESP_FIN 6'b010110 +`define RD_CMD_SEND_CMD 6'b010111 +`define RD_CMD_WT_FIN 6'b011000 +`define RD_CMD_DEL 6'b011001 +`define RD_TOKEN_CHK_LOOP 6'b011010 +`define RD_TOKEN_WT_FIN 6'b011011 +`define RD_TOKEN_SEND_CMD 6'b011100 +`define RD_TOKEN_DEL2 6'b011101 +`define RD_TOKEN_INIT_LOOP 6'b011110 +`define RD_TOKEN_DEL1 6'b011111 +`define RD_DATA_ST_LOOP 6'b100000 +`define RD_DATA_WT_DATA 6'b100001 +`define RD_DATA_CHK_LOOP 6'b100010 +`define RD_DATA_CLR_RX 6'b100011 +`define RD_DATA_CS_FIN2 6'b100100 +`define RD_DATA_CS_FIN1 6'b100101 +`define RD_DATA_CS_ST1 6'b100110 +`define RD_DATA_CS_ST2 6'b100111 +`define WR_BUSY_CHK_FIN 6'b101000 +`define WR_BUSY_WT_FIN1 6'b101001 +`define WR_BUSY_DEL1 6'b101010 +`define WR_BUSY_SEND_CMD1 6'b101011 +`define WR_BUSY_DEL2 6'b101100 +`define WR_BUSY_INIT_LOOP 6'b101101 +`define RD_TOKEN_DEL3 6'b101110 +`define WR_DATA_DEL 6'b101111 + +reg [5:0]CurrState_rwBlkSt, NextState_rwBlkSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: rwBlkSt + +// NextState logic (combinatorial) +always @ (blockAddr or sendCmdRdy or respTout or respByte or readWriteSDBlockReq or txDataFull or loopCnt or txFifoData or txDataEmpty or timeOutCnt or locRespByte or rxDataRdy or rxDataIn or delCnt1 or delCnt2 or readWriteSDBlockRdy or spiCS_n or readError or writeError or txDataOut or txDataWen or rxDataRdyClr or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or txFifoRen or rxFifoWen or rxFifoData or CurrState_rwBlkSt) +begin + NextState_rwBlkSt <= CurrState_rwBlkSt; + // Set default values for outputs and signals + next_readWriteSDBlockRdy <= readWriteSDBlockRdy; + next_spiCS_n <= spiCS_n; + next_readError <= readError; + next_writeError <= writeError; + next_txDataOut <= txDataOut; + next_txDataWen <= txDataWen; + next_rxDataRdyClr <= rxDataRdyClr; + next_cmdByte <= cmdByte; + next_dataByte1 <= dataByte1; + next_dataByte2 <= dataByte2; + next_dataByte3 <= dataByte3; + next_dataByte4 <= dataByte4; + next_checkSumByte <= checkSumByte; + next_sendCmdReq <= sendCmdReq; + next_loopCnt <= loopCnt; + next_delCnt1 <= delCnt1; + next_delCnt2 <= delCnt2; + next_txFifoRen <= txFifoRen; + next_rxFifoWen <= rxFifoWen; + next_rxFifoData <= rxFifoData; + next_timeOutCnt <= timeOutCnt; + next_locRespByte <= locRespByte; + case (CurrState_rwBlkSt) // synopsys parallel_case full_case + `ST_RW_SD: + begin + next_readWriteSDBlockRdy <= 1'b0; + next_spiCS_n <= 1'b1; + next_readError <= 1'b0; + next_writeError <= 1'b0; + next_txDataOut <= 8'h00; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + next_sendCmdReq <= 1'b0; + next_loopCnt <= 8'h00; + next_delCnt1 <= 8'h00; + next_delCnt2 <= 8'h00; + next_readError <= `READ_NO_ERROR; + next_writeError <= `WRITE_NO_ERROR; + next_txFifoRen <= 1'b0; + next_rxFifoWen <= 1'b0; + next_rxFifoData <= 8'h00; + next_timeOutCnt <= 12'h000; + next_locRespByte <= 8'h00; + NextState_rwBlkSt <= `WT_REQ; + end + `WT_REQ: + begin + next_spiCS_n <= 1'b1; + next_readWriteSDBlockRdy <= 1'b1; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + if (readWriteSDBlockReq == `READ_SD_BLOCK) + begin + NextState_rwBlkSt <= `RD_CMD_SEND_CMD; + next_spiCS_n <= 1'b0; + next_readWriteSDBlockRdy <= 1'b0; + next_readError <= `READ_NO_ERROR; + end + else if (readWriteSDBlockReq == `WRITE_SD_BLOCK) + begin + NextState_rwBlkSt <= `WR_CMD_SEND_CMD; + next_spiCS_n <= 1'b0; + next_readWriteSDBlockRdy <= 1'b0; + next_writeError <= `WRITE_NO_ERROR; + end + end + `WR_CMD_SEND_CMD: + begin + next_cmdByte <= 8'h58; + //CMD24 Block Write + next_dataByte1 <= blockAddr[31:24]; + next_dataByte2 <= blockAddr[23:16]; + next_dataByte3 <= blockAddr[15:8]; + next_dataByte4 <= blockAddr[7:0]; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + NextState_rwBlkSt <= `WR_CMD_DEL; + end + `WR_CMD_WT_FIN: + begin + if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00)) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_CMD_ERROR; + end + else if (sendCmdRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF1_ST; + end + end + `WR_CMD_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_rwBlkSt <= `WR_CMD_WT_FIN; + end + `WR_TOKEN_FF1_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_TOKEN_FF2_ST; + end + `WR_TOKEN_FF1_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF1_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_TOKEN_FF2_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_TOKEN_FE_ST; + end + `WR_TOKEN_FF2_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF2_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_TOKEN_FE_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_LOOP_INIT; + end + `WR_TOKEN_FE_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FE_FIN; + next_txDataOut <= 8'hfe; + next_txDataWen <= 1'b1; + end + end + `WR_BUSY_CHK_FIN: + begin + if (locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS) + begin + NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1; + next_timeOutCnt <= timeOutCnt + 1'b1; + end + else if (timeOutCnt == `TWO_FIFTY_MS) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_BUSY_ERROR; + end + else + begin + NextState_rwBlkSt <= `WT_REQ; + end + end + `WR_BUSY_WT_FIN1: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_BUSY_CHK_FIN; + next_locRespByte <= rxDataIn; + end + end + `WR_BUSY_DEL1: + begin + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + if (delCnt1 == `MAX_8_BIT) + begin + NextState_rwBlkSt <= `WR_BUSY_WT_FIN1; + end + else + begin + NextState_rwBlkSt <= `WR_BUSY_DEL2; + end + end + `WR_BUSY_SEND_CMD1: + begin + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + next_delCnt1 <= 8'h00; + NextState_rwBlkSt <= `WR_BUSY_DEL1; + end + `WR_BUSY_DEL2: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_rwBlkSt <= `WR_BUSY_DEL1; + end + end + `WR_BUSY_INIT_LOOP: + begin + next_timeOutCnt <= 12'h000; + NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1; + end + `RD_CMD_SEND_CMD: + begin + next_cmdByte <= 8'h51; + //CMD17 Block Read + next_dataByte1 <= blockAddr[31:24]; + next_dataByte2 <= blockAddr[23:16]; + next_dataByte3 <= blockAddr[15:8]; + next_dataByte4 <= blockAddr[7:0]; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + NextState_rwBlkSt <= `RD_CMD_DEL; + end + `RD_CMD_WT_FIN: + begin + if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00)) + begin + NextState_rwBlkSt <= `WT_REQ; + next_readError <= `READ_CMD_ERROR; + end + else if (sendCmdRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP; + end + end + `RD_CMD_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_rwBlkSt <= `RD_CMD_WT_FIN; + end + `RD_TOKEN_CHK_LOOP: + begin + if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS) + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL2; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_delCnt1 <= 8'h00; + end + else if (timeOutCnt == `ONE_HUNDRED_MS) + begin + NextState_rwBlkSt <= `WT_REQ; + next_readError <= `READ_TOKEN_ERROR; + end + else + begin + NextState_rwBlkSt <= `RD_DATA_CLR_RX; + next_rxDataRdyClr <= 1'b1; + end + end + `RD_TOKEN_WT_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP; + next_locRespByte <= rxDataIn; + end + end + `RD_TOKEN_SEND_CMD: + begin + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + NextState_rwBlkSt <= `RD_TOKEN_DEL1; + end + `RD_TOKEN_DEL2: + begin + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + if (delCnt1 == `MAX_8_BIT) + begin + NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD; + end + else + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL3; + end + end + `RD_TOKEN_INIT_LOOP: + begin + next_timeOutCnt <= 12'h000; + NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD; + end + `RD_TOKEN_DEL1: + begin + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + NextState_rwBlkSt <= `RD_TOKEN_WT_FIN; + end + `RD_TOKEN_DEL3: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL2; + end + end + `RD_DATA_ST_LOOP: + begin + next_txDataWen <= 1'b1; + next_txDataOut <= 8'hff; + next_loopCnt <= loopCnt + 1'b1; + NextState_rwBlkSt <= `RD_DATA_WT_DATA; + end + `RD_DATA_WT_DATA: + begin + next_txDataWen <= 1'b0; + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_DATA_CHK_LOOP; + next_rxFifoWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + next_rxFifoData <= rxDataIn; + end + end + `RD_DATA_CHK_LOOP: + begin + if (loopCnt == 9'b000000000) + begin + NextState_rwBlkSt <= `RD_DATA_CS_ST1; + next_rxDataRdyClr <= 1'b0; + next_rxFifoWen <= 1'b0; + end + else + begin + NextState_rwBlkSt <= `RD_DATA_ST_LOOP; + next_rxDataRdyClr <= 1'b0; + next_rxFifoWen <= 1'b0; + end + end + `RD_DATA_CLR_RX: + begin + NextState_rwBlkSt <= `RD_DATA_ST_LOOP; + next_rxDataRdyClr <= 1'b0; + next_loopCnt <= 9'b000000000; + end + `RD_DATA_CS_FIN2: + begin + next_txDataWen <= 1'b0; + if (txDataEmpty == 1'b1) + begin + NextState_rwBlkSt <= `WT_REQ; + end + end + `RD_DATA_CS_FIN1: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `RD_DATA_CS_ST2; + end + `RD_DATA_CS_ST1: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `RD_DATA_CS_FIN1; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `RD_DATA_CS_ST2: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `RD_DATA_CS_FIN2; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_D_FIN: + begin + next_txDataWen <= 1'b0; + if (loopCnt == 9'b000000000) + begin + NextState_rwBlkSt <= `WR_DATA_CS_ST1; + end + else + begin + NextState_rwBlkSt <= `WR_DATA_RD_FIFO1; + end + end + `WR_DATA_D_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_D_FIN; + next_txDataOut <= txFifoData; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_RD_FIFO1: + begin + next_txFifoRen <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + NextState_rwBlkSt <= `WR_DATA_RD_FIFO2; + end + `WR_DATA_RD_FIFO2: + begin + next_txFifoRen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_D_ST; + end + `WR_DATA_LOOP_INIT: + begin + next_loopCnt <= 9'b000000000; + NextState_rwBlkSt <= `WR_DATA_RD_FIFO1; + end + `WR_DATA_CS_ST1: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_CS_FIN1; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_CS_FIN1: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_CS_ST2; + end + `WR_DATA_CS_FIN2: + begin + next_txDataWen <= 1'b0; + next_timeOutCnt <= 12'h000; + if (txDataEmpty == 1'b1) + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST; + end + end + `WR_DATA_CS_ST2: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_CS_FIN2; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_CHK_RESP: + begin + if (timeOutCnt == `WR_RESP_TOUT) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_DATA_ERROR; + end + else if (locRespByte[4:0] == 5'h5) + begin + NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP; + end + else + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST; + end + end + `WR_DATA_REQ_RESP_ST: + begin + NextState_rwBlkSt <= `WR_DATA_DEL; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_rxDataRdyClr <= 1'b1; + end + `WR_DATA_REQ_RESP_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_DATA_CHK_RESP; + next_locRespByte <= rxDataIn; + end + end + `WR_DATA_DEL: + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_rwBlkSt <= `ST_RW_SD; + else + CurrState_rwBlkSt <= NextState_rwBlkSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + readWriteSDBlockRdy <= 1'b0; + spiCS_n <= 1'b1; + readError <= 1'b0; + writeError <= 1'b0; + txDataOut <= 8'h00; + txDataWen <= 1'b0; + rxDataRdyClr <= 1'b0; + cmdByte <= 8'h00; + dataByte1 <= 8'h00; + dataByte2 <= 8'h00; + dataByte3 <= 8'h00; + dataByte4 <= 8'h00; + checkSumByte <= 8'h00; + sendCmdReq <= 1'b0; + txFifoRen <= 1'b0; + rxFifoWen <= 1'b0; + rxFifoData <= 8'h00; + loopCnt <= 8'h00; + delCnt1 <= 8'h00; + delCnt2 <= 8'h00; + timeOutCnt <= 12'h000; + locRespByte <= 8'h00; + end + else + begin + readWriteSDBlockRdy <= next_readWriteSDBlockRdy; + spiCS_n <= next_spiCS_n; + readError <= next_readError; + writeError <= next_writeError; + txDataOut <= next_txDataOut; + txDataWen <= next_txDataWen; + rxDataRdyClr <= next_rxDataRdyClr; + cmdByte <= next_cmdByte; + dataByte1 <= next_dataByte1; + dataByte2 <= next_dataByte2; + dataByte3 <= next_dataByte3; + dataByte4 <= next_dataByte4; + checkSumByte <= next_checkSumByte; + sendCmdReq <= next_sendCmdReq; + txFifoRen <= next_txFifoRen; + rxFifoWen <= next_rxFifoWen; + rxFifoData <= next_rxFifoData; + loopCnt <= next_loopCnt; + delCnt1 <= next_delCnt1; + delCnt2 <= next_delCnt2; + timeOutCnt <= next_timeOutCnt; + locRespByte <= next_locRespByte; + end +end + +endmodule \ No newline at end of file Index: spimaster/trunk/RTL/initSD.v =================================================================== --- spimaster/trunk/RTL/initSD.v (nonexistent) +++ spimaster/trunk/RTL/initSD.v (revision 4) @@ -0,0 +1,386 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// initSD.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// When SDInitReq asserted, initialise SD card +//// +//// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module initSD (checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, initError, respByte, respTout, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, sendCmdRdy, sendCmdReq, spiClkDelayIn, spiClkDelayOut, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen); +input clk; +input [7:0]respByte; +input respTout; +input rst; +input rxDataRdy; +input SDInitReq; +input sendCmdRdy; +input [7:0]spiClkDelayIn; +input txDataEmpty; +input txDataFull; +output [7:0]checkSumByte; +output [7:0]cmdByte; +output [7:0]dataByte1; +output [7:0]dataByte2; +output [7:0]dataByte3; +output [7:0]dataByte4; +output [1:0]initError; +output rxDataRdyClr; +output SDInitRdy; +output sendCmdReq; +output [7:0]spiClkDelayOut; +output spiCS_n; +output [7:0]txDataOut; +output txDataWen; + +reg [7:0]checkSumByte, next_checkSumByte; +wire clk; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg [1:0]initError, next_initError; +wire [7:0]respByte; +wire respTout; +wire rst; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg SDInitRdy, next_SDInitRdy; +wire SDInitReq; +wire sendCmdRdy; +reg sendCmdReq, next_sendCmdReq; +wire [7:0]spiClkDelayIn; +reg [7:0]spiClkDelayOut, next_spiClkDelayOut; +reg spiCS_n, next_spiCS_n; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; + +// diagram signals declarations +reg [9:0]delCnt1, next_delCnt1; +reg [7:0]delCnt2, next_delCnt2; +reg [7:0]loopCnt, next_loopCnt; + +// BINARY ENCODED state machine: initSDSt +// State codes definitions: +`define START 4'b0000 +`define WT_INIT_REQ 4'b0001 +`define CLK_SEQ_SEND_FF 4'b0010 +`define CLK_SEQ_CHK_FIN 4'b0011 +`define RESET_SEND_CMD 4'b0100 +`define RESET_DEL 4'b0101 +`define RESET_WT_FIN 4'b0110 +`define RESET_CHK_FIN 4'b0111 +`define INIT_WT_FIN 4'b1000 +`define INIT_CHK_FIN 4'b1001 +`define INIT_SEND_CMD 4'b1010 +`define INIT_DEL1 4'b1011 +`define INIT_DEL2 4'b1100 +`define CLK_SEQ_WT_DATA_EMPTY 4'b1101 + +reg [3:0]CurrState_initSDSt, NextState_initSDSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: initSDSt + +// NextState logic (combinatorial) +always @ (spiClkDelayIn or SDInitReq or txDataFull or loopCnt or sendCmdRdy or respTout or respByte or delCnt1 or delCnt2 or txDataEmpty or spiClkDelayOut or SDInitRdy or spiCS_n or initError or txDataOut or txDataWen or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or rxDataRdyClr or CurrState_initSDSt) +begin + NextState_initSDSt <= CurrState_initSDSt; + // Set default values for outputs and signals + next_spiClkDelayOut <= spiClkDelayOut; + next_SDInitRdy <= SDInitRdy; + next_spiCS_n <= spiCS_n; + next_initError <= initError; + next_txDataOut <= txDataOut; + next_txDataWen <= txDataWen; + next_cmdByte <= cmdByte; + next_dataByte1 <= dataByte1; + next_dataByte2 <= dataByte2; + next_dataByte3 <= dataByte3; + next_dataByte4 <= dataByte4; + next_checkSumByte <= checkSumByte; + next_sendCmdReq <= sendCmdReq; + next_loopCnt <= loopCnt; + next_delCnt1 <= delCnt1; + next_delCnt2 <= delCnt2; + next_rxDataRdyClr <= rxDataRdyClr; + case (CurrState_initSDSt) // synopsys parallel_case full_case + `START: + begin + next_spiClkDelayOut <= spiClkDelayIn; + next_SDInitRdy <= 1'b0; + next_spiCS_n <= 1'b1; + next_initError <= `INIT_NO_ERROR; + next_txDataOut <= 8'h00; + next_txDataWen <= 1'b0; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + next_sendCmdReq <= 1'b0; + next_loopCnt <= 8'h00; + next_delCnt1 <= 10'h000; + next_delCnt2 <= 8'h00; + next_rxDataRdyClr <= 1'b0; + NextState_initSDSt <= `WT_INIT_REQ; + end + `WT_INIT_REQ: + begin + next_SDInitRdy <= 1'b1; + next_spiClkDelayOut <= spiClkDelayIn; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + if (SDInitReq == 1'b1) + begin + NextState_initSDSt <= `CLK_SEQ_SEND_FF; + next_SDInitRdy <= 1'b0; + next_loopCnt <= 8'h00; + next_spiClkDelayOut <= `SLOW_SPI_CLK; + next_initError <= `INIT_NO_ERROR; + end + end + `CLK_SEQ_SEND_FF: + begin + if (txDataFull == 1'b0) + begin + NextState_initSDSt <= `CLK_SEQ_CHK_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + end + end + `CLK_SEQ_CHK_FIN: + begin + next_txDataWen <= 1'b0; + if (loopCnt == `SD_INIT_START_SEQ_LEN) + begin + NextState_initSDSt <= `CLK_SEQ_WT_DATA_EMPTY; + end + else + begin + NextState_initSDSt <= `CLK_SEQ_SEND_FF; + end + end + `CLK_SEQ_WT_DATA_EMPTY: + begin + if (txDataEmpty == 1'b1) + begin + NextState_initSDSt <= `RESET_SEND_CMD; + next_loopCnt <= 8'h00; + end + end + `RESET_SEND_CMD: + begin + next_cmdByte <= 8'h40; + //CMD0 + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h95; + next_sendCmdReq <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + next_spiCS_n <= 1'b0; + NextState_initSDSt <= `RESET_DEL; + end + `RESET_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_initSDSt <= `RESET_WT_FIN; + end + `RESET_WT_FIN: + begin + if (sendCmdRdy == 1'b1) + begin + NextState_initSDSt <= `RESET_CHK_FIN; + next_spiCS_n <= 1'b1; + end + end + `RESET_CHK_FIN: + begin + if ((respTout == 1'b1 || respByte != 8'h01) && loopCnt != 8'hff) + begin + NextState_initSDSt <= `RESET_SEND_CMD; + end + else if (respTout == 1'b1 || respByte != 8'h01) + begin + NextState_initSDSt <= `WT_INIT_REQ; + next_initError <= `INIT_CMD0_ERROR; + end + else + begin + NextState_initSDSt <= `INIT_SEND_CMD; + end + end + `INIT_WT_FIN: + begin + if (sendCmdRdy == 1'b1) + begin + NextState_initSDSt <= `INIT_CHK_FIN; + next_spiCS_n <= 1'b1; + end + end + `INIT_CHK_FIN: + begin + if ((respTout == 1'b1 || respByte != 8'h00) && loopCnt != 8'hff) + begin + NextState_initSDSt <= `INIT_SEND_CMD; + end + else if (respTout == 1'b1 || respByte != 8'h00) + begin + NextState_initSDSt <= `WT_INIT_REQ; + next_initError <= `INIT_CMD1_ERROR; + end + else + begin + NextState_initSDSt <= `WT_INIT_REQ; + end + end + `INIT_SEND_CMD: + begin + next_cmdByte <= 8'h41; + //CMD1 + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + next_spiCS_n <= 1'b0; + next_delCnt1 <= 10'h000; + NextState_initSDSt <= `INIT_DEL1; + end + `INIT_DEL1: + begin + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + next_sendCmdReq <= 1'b0; + if (delCnt1 == `TWO_MS) + begin + NextState_initSDSt <= `INIT_WT_FIN; + end + else + begin + NextState_initSDSt <= `INIT_DEL2; + end + end + `INIT_DEL2: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_initSDSt <= `INIT_DEL1; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_initSDSt <= `START; + else + CurrState_initSDSt <= NextState_initSDSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + spiClkDelayOut <= spiClkDelayIn; + SDInitRdy <= 1'b0; + spiCS_n <= 1'b1; + initError <= `INIT_NO_ERROR; + txDataOut <= 8'h00; + txDataWen <= 1'b0; + cmdByte <= 8'h00; + dataByte1 <= 8'h00; + dataByte2 <= 8'h00; + dataByte3 <= 8'h00; + dataByte4 <= 8'h00; + checkSumByte <= 8'h00; + sendCmdReq <= 1'b0; + rxDataRdyClr <= 1'b0; + loopCnt <= 8'h00; + delCnt1 <= 10'h000; + delCnt2 <= 8'h00; + end + else + begin + spiClkDelayOut <= next_spiClkDelayOut; + SDInitRdy <= next_SDInitRdy; + spiCS_n <= next_spiCS_n; + initError <= next_initError; + txDataOut <= next_txDataOut; + txDataWen <= next_txDataWen; + cmdByte <= next_cmdByte; + dataByte1 <= next_dataByte1; + dataByte2 <= next_dataByte2; + dataByte3 <= next_dataByte3; + dataByte4 <= next_dataByte4; + checkSumByte <= next_checkSumByte; + sendCmdReq <= next_sendCmdReq; + rxDataRdyClr <= next_rxDataRdyClr; + loopCnt <= next_loopCnt; + delCnt1 <= next_delCnt1; + delCnt2 <= next_delCnt2; + end +end + +endmodule \ No newline at end of file Index: spimaster/trunk/RTL/sm_RxFifo.v =================================================================== --- spimaster/trunk/RTL/sm_RxFifo.v (nonexistent) +++ spimaster/trunk/RTL/sm_RxFifo.v (revision 4) @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_RxFifo.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo read access via bus interface, fifo write access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module sm_RxFifo( + busClk, + spiSysClk, + rstSyncToBusClk, + rstSyncToSpiClk, + fifoWEn, + fifoFull, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataIn ); + //FIFO_DEPTH = 2^ADDR_WIDTH + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input rstSyncToSpiClk; +input fifoWEn; +output fifoFull; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +input [7:0] fifoDataIn; + +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire rstSyncToSpiClk; +wire fifoWEn; +wire fifoFull; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataIn; + +//internal wires and regs +wire [7:0] dataFromFifoToBus; +wire fifoREn; +wire forceEmptySyncToBusClk; +wire forceEmptySyncToSpiClk; +wire [15:0] numElementsInFifo; +wire fifoEmpty; //not used + +sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo( + .wrClk(spiSysClk), + .rdClk(busClk), + .rstSyncToWrClk(rstSyncToSpiClk), + .rstSyncToRdClk(rstSyncToBusClk), + .dataIn(fifoDataIn), + .dataOut(dataFromFifoToBus), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToSpiClk), + .forceEmptySyncToRdClk(forceEmptySyncToBusClk), + .numElementsInFifo(numElementsInFifo) ); + +sm_RxfifoBI u_sm_RxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .spiSysClk(spiSysClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .fifoDataIn(dataFromFifoToBus), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoREn(fifoREn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToSpiClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule Index: spimaster/trunk/RTL/sm_TxFifo.v =================================================================== --- spimaster/trunk/RTL/sm_TxFifo.v (nonexistent) +++ spimaster/trunk/RTL/sm_TxFifo.v (revision 4) @@ -0,0 +1,132 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_TxFifo.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo write access via bus interface, fifo read access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module sm_TxFifo( + busClk, + spiSysClk, + rstSyncToBusClk, + rstSyncToSpiClk, + fifoREn, + fifoEmpty, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataOut ); + //FIFO_DEPTH = 2^ADDR_WIDTH + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input rstSyncToSpiClk; +input fifoREn; +output fifoEmpty; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +output [7:0] fifoDataOut; + +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire rstSyncToSpiClk; +wire fifoREn; +wire fifoEmpty; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataOut; + +//internal wires and regs +wire fifoWEn; +wire forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoFull; + +sm_fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_sm_fifo( + .wrClk(busClk), + .rdClk(spiSysClk), + .rstSyncToWrClk(rstSyncToBusClk), + .rstSyncToRdClk(rstSyncToSpiClk), + .dataIn(busDataIn), + .dataOut(fifoDataOut), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToBusClk), + .forceEmptySyncToRdClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) ); + +sm_TxfifoBI u_sm_TxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .spiSysClk(spiSysClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoWEn(fifoWEn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToSpiClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule Index: spimaster/trunk/RTL/sm_fifoRTL.v =================================================================== --- spimaster/trunk/RTL/sm_fifoRTL.v (nonexistent) +++ spimaster/trunk/RTL/sm_fifoRTL.v (revision 4) @@ -0,0 +1,164 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_fifoRTL.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module sm_fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, + dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, + forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo); +//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +// Two clock domains within this module +// These ports are within 'wrClk' domain +input wrClk; +input rstSyncToWrClk; +input [FIFO_WIDTH-1:0] dataIn; +input fifoWEn; +input forceEmptySyncToWrClk; +output fifoFull; + +// These ports are within 'rdClk' domain +input rdClk; +input rstSyncToRdClk; +output [FIFO_WIDTH-1:0] dataOut; +input fifoREn; +input forceEmptySyncToRdClk; +output fifoEmpty; +output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536 + +wire wrClk; +wire rdClk; +wire rstSyncToWrClk; +wire rstSyncToRdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire fifoWEn; +wire fifoREn; +reg fifoFull; +reg fifoEmpty; +wire forceEmpty; +reg [15:0]numElementsInFifo; + + +// local registers +reg [ADDR_WIDTH:0]bufferInIndex; +reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk; +reg [ADDR_WIDTH:0]bufferOutIndex; +reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk; +reg [ADDR_WIDTH-1:0]bufferInIndexToMem; +reg [ADDR_WIDTH-1:0]bufferOutIndexToMem; +reg [ADDR_WIDTH:0]bufferCnt; +reg fifoREnDelayed; +wire [FIFO_WIDTH-1:0] dataFromMem; + +always @(posedge wrClk) +begin + bufferOutIndexSyncToWrClk <= bufferOutIndex; + if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) + begin + fifoFull <= 1'b0; + bufferInIndex <= 0; + end + else + begin + if (fifoWEn == 1'b1) begin + bufferInIndex <= bufferInIndex + 1'b1; + end + if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) && + (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) ) + fifoFull <= 1'b1; + else + fifoFull <= 1'b0; + end +end + +always @(bufferInIndexSyncToRdClk or bufferOutIndex) + bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex; + +always @(posedge rdClk) +begin + numElementsInFifo <= { {16-ADDR_WIDTH-1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes + bufferInIndexSyncToRdClk <= bufferInIndex; + if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) + begin + fifoEmpty <= 1'b1; + bufferOutIndex <= 0; + fifoREnDelayed <= 1'b0; + end + else + begin + fifoREnDelayed <= fifoREn; + if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin + dataOut <= dataFromMem; + bufferOutIndex <= bufferOutIndex + 1'b1; + end + if (bufferInIndexSyncToRdClk == bufferOutIndex) + fifoEmpty <= 1'b1; + else + fifoEmpty <= 1'b0; + end +end + + +always @(bufferInIndex or bufferOutIndex) begin + bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0]; + bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0]; +end + +sm_dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_sm_dpMem_dc ( + .addrIn(bufferInIndexToMem), + .addrOut(bufferOutIndexToMem), + .wrClk(wrClk), + .rdClk(rdClk), + .dataIn(dataIn), + .writeEn(fifoWEn), + .readEn(fifoREn), + .dataOut(dataFromMem)); + +endmodule Index: spimaster/trunk/RTL/timescale.v =================================================================== --- spimaster/trunk/RTL/timescale.v (nonexistent) +++ spimaster/trunk/RTL/timescale.v (revision 4) @@ -0,0 +1,5 @@ +////////////////////////////////////////////////////////////////////// +// timescale.v +////////////////////////////////////////////////////////////////////// +`timescale 1ns / 1ps + Index: spimaster/trunk/RTL/ctrlStsRegBI.v =================================================================== --- spimaster/trunk/RTL/ctrlStsRegBI.v (nonexistent) +++ spimaster/trunk/RTL/ctrlStsRegBI.v (revision 4) @@ -0,0 +1,270 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// ctrlStsRegBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Wishbone bus interface to spiMaster control and status regs +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module ctrlStsRegBI ( + busClk, + rstFromWire, + dataIn, + dataOut, + address, + writeEn, + strobe_i, + spiSysClk, + spiTransType, + spiTransCtrl, + spiTransStatus, + spiDirectAccessTxData, + spiDirectAccessRxData, + ctrlStsRegSel, + rstSyncToBusClkOut, + rstSyncToSpiClkOut, + SDWriteError, + SDReadError, + SDInitError, + SDAddr, + spiClkDelay +); + +input [7:0] dataIn; +input [7:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +output [7:0] dataOut; +input ctrlStsRegSel; +output [1:0] spiTransType; +output spiTransCtrl; +input spiTransStatus; +output [7:0] spiDirectAccessTxData; +reg [7:0] spiDirectAccessTxData; +input [7:0] spiDirectAccessRxData; +input rstFromWire; +output rstSyncToBusClkOut; +output rstSyncToSpiClkOut; +input [1:0] SDWriteError; +input [1:0] SDReadError; +input [1:0] SDInitError; +output [31:0] SDAddr; +reg [31:0] SDAddr; +output [7:0] spiClkDelay; +reg [7:0] spiClkDelay; + +wire [7:0] dataIn; +wire [7:0] address; +wire writeEn; +wire strobe_i; +wire clk; +reg [7:0] dataOut; +reg [1:0] spiTransType; +reg spiTransCtrl; +wire ctrlStsRegSel; +wire rstFromWire; +reg rstSyncToBusClkOut; +reg rstSyncToSpiClkOut; + +//internal wire and regs +reg [5:0] rstShift; +reg rstFromBus; +reg [7:0] spiDirectAccessTxDataSTB; +reg [7:0] spiDirectAccessRxDataSTB; +reg [1:0] spiTransTypeSTB; +reg spiTransCtrlSTB; +reg spiTransStatusSTB; +reg rstSyncToSpiClkFirst; +reg [5:0] spiTransCtrlShift; +reg spiTransStatusReg1; +reg spiTransStatusReg2; +reg spiTransStatusReg3; +reg [1:0] SDWriteErrorSTB; +reg [1:0] SDReadErrorSTB; +reg [1:0] SDInitErrorSTB; +reg spiTransCtrl_reg1; +reg spiTransCtrl_reg2; +reg spiTransCtrl_reg3; + +//sync write demux +always @(posedge busClk) +begin + if (rstSyncToBusClkOut == 1'b1) begin + spiTransTypeSTB <= `DIRECT_ACCESS; + spiTransCtrlSTB <= `TRANS_STOP; + spiDirectAccessTxDataSTB <= 8'h00; + spiClkDelay <= `FAST_SPI_CLK; + end + else begin + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `SPI_MASTER_CONTROL_REG && dataIn[0] == 1'b1 ) + rstFromBus <= 1'b1; + else + rstFromBus <= 1'b0; + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `TRANS_CTRL_REG && dataIn[0] == 1'b1 ) + spiTransCtrlSTB <= 1'b1; + else + spiTransCtrlSTB <= 1'b0; + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1) begin + case (address) + `TRANS_TYPE_REG: spiTransTypeSTB <= dataIn[1:0]; + `SD_ADDR_7_0_REG: SDAddr[7:0] <= dataIn; + `SD_ADDR_15_8_REG: SDAddr[15:8] <= dataIn; + `SD_ADDR_23_16_REG: SDAddr[23:16] <= dataIn; + `SD_ADDR_31_24_REG: SDAddr[31:24] <= dataIn; + `SPI_CLK_DEL_REG: spiClkDelay <= dataIn; + `DIRECT_ACCESS_DATA_REG: spiDirectAccessTxDataSTB <= dataIn; + endcase + end + end +end + +// async read mux +always @(address or spiTransTypeSTB or spiTransCtrlSTB or + spiTransStatusSTB or spiDirectAccessRxDataSTB or + SDAddr or SDInitErrorSTB or SDReadErrorSTB or SDWriteErrorSTB or + spiClkDelay) +begin + case (address) + `SPI_MASTER_VERSION_REG: dataOut <= `SPI_MASTER_VERSION_NUM; + `TRANS_TYPE_REG: dataOut <= { 6'b000000, spiTransTypeSTB}; + `TRANS_CTRL_REG: dataOut <= { 7'b0000000, spiTransCtrlSTB}; + `TRANS_STS_REG: dataOut <= { 7'b0000000, spiTransStatusSTB}; + `TRANS_ERROR_REG: dataOut <= {2'b00, SDWriteErrorSTB, SDReadErrorSTB, SDInitErrorSTB}; + `SD_ADDR_7_0_REG: dataOut <= SDAddr[7:0]; + `SD_ADDR_15_8_REG: dataOut <= SDAddr[15:8]; + `SD_ADDR_23_16_REG: dataOut <= SDAddr[23:16]; + `SD_ADDR_31_24_REG: dataOut <= SDAddr[31:24]; + `SPI_CLK_DEL_REG: dataOut <= spiClkDelay; + `DIRECT_ACCESS_DATA_REG: dataOut <= spiDirectAccessRxDataSTB; + default: dataOut <= 8'h00; + endcase +end + +// reset control +//generate 'rstSyncToBusClk' +//assuming that 'busClk' < 5 * 'spiSysClk'. +always @(posedge busClk) begin + if (rstFromWire == 1'b1 || rstFromBus == 1'b1) + rstShift <= 6'b111111; + else + rstShift <= {1'b0, rstShift[5:1]}; +end + +always @(rstShift) + rstSyncToBusClkOut <= rstShift[0]; + +// double sync across clock domains to generate 'rstSyncToSpiClkOut' +always @(posedge spiSysClk) begin + rstSyncToSpiClkFirst <= rstSyncToBusClkOut; + rstSyncToSpiClkOut <= rstSyncToSpiClkFirst; +end + + +// spi transaction control +//assuming that 'busClk' < 5 * 'spiSysClk'. +always @(posedge busClk) begin + if (rstSyncToBusClkOut == 1'b1) + spiTransCtrlShift <= 6'b000000; + else if (spiTransCtrlSTB == 1'b1) + spiTransCtrlShift <= 6'b111111; + else + spiTransCtrlShift <= {1'b0, spiTransCtrlShift[5:1]}; +end + +//re-sync to spiSysClk +always @(posedge spiSysClk) begin + if (rstSyncToSpiClkOut == 1'b1) begin + spiTransCtrl_reg1 <= 1'b0; + spiTransCtrl_reg2 <= 1'b0; + spiTransCtrl_reg3 <= 1'b0; + end + else begin + spiTransCtrl_reg1 <= spiTransCtrlShift[0]; + spiTransCtrl_reg2 <= spiTransCtrl_reg1; + spiTransCtrl_reg3 <= spiTransCtrl_reg2; + if (spiTransCtrl_reg3 == 1'b0 && spiTransCtrl_reg2 == 1'b1) + spiTransCtrl <= `TRANS_START; + else + spiTransCtrl <= `TRANS_STOP; + end +end + + + +//re-sync from busClk to spiSysClk. +always @(posedge spiSysClk) begin + if (rstSyncToSpiClkOut == 1'b1) begin + spiTransType <= `DIRECT_ACCESS; + spiDirectAccessTxData <= 8'h00; + end + else begin + spiDirectAccessTxData <= spiDirectAccessTxDataSTB; + spiTransType <= spiTransTypeSTB; + end +end + +//re-sync from spiSysClk to busClk +always @(posedge busClk) begin + if (rstSyncToBusClkOut == 1'b1) begin + spiTransStatusSTB <= `TRANS_NOT_BUSY; + spiTransStatusReg1 <= `TRANS_NOT_BUSY; + spiTransStatusReg2 <= `TRANS_NOT_BUSY; + spiTransStatusReg3 <= `TRANS_NOT_BUSY; + end + else begin + spiTransStatusReg1 <= spiTransStatus; + spiTransStatusReg2 <= spiTransStatusReg1; + spiTransStatusReg3 <= spiTransStatusReg2; + if (spiTransCtrlSTB == `TRANS_START) + spiTransStatusSTB <= `TRANS_BUSY; + else if (spiTransStatusReg3 == `TRANS_BUSY && spiTransStatusReg2 == `TRANS_NOT_BUSY) + spiTransStatusSTB <= `TRANS_NOT_BUSY; + end + spiDirectAccessRxDataSTB <= spiDirectAccessRxData; + SDWriteErrorSTB <= SDWriteError; + SDReadErrorSTB <= SDReadError; + SDInitErrorSTB <= SDInitError; +end + +endmodule + Index: spimaster/trunk/RTL/sm_RxFifoBI.v =================================================================== --- spimaster/trunk/RTL/sm_RxFifoBI.v (nonexistent) +++ spimaster/trunk/RTL/sm_RxFifoBI.v (revision 4) @@ -0,0 +1,154 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_RxfifoBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module sm_RxfifoBI ( + address, + writeEn, + strobe_i, + busClk, + spiSysClk, + rstSyncToBusClk, + fifoSelect, + fifoDataIn, + busDataIn, + busDataOut, + fifoREn, + forceEmptySyncToSpiClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input [7:0] fifoDataIn; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoREn; +output forceEmptySyncToSpiClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire [7:0] fifoDataIn; +wire [7:0] busDataIn; +reg [7:0] busDataOut; +reg fifoREn; +wire forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg forceEmptyReg; +reg forceEmpty; +reg forceEmptyToggle; +reg [2:0] forceEmptyToggleSyncToSpiClk; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//detect rising edge of 'forceEmpty', and generate toggle signal +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + forceEmptyReg <= 1'b0; + forceEmptyToggle <= 1'b0; + end + else begin + if (forceEmpty == 1'b1) + forceEmptyReg <= 1'b1; + else + forceEmptyReg <= 1'b0; + if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) + forceEmptyToggle <= ~forceEmptyToggle; + end +end +assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0; + + +// double sync across clock domains to generate 'forceEmptySyncToSpiClk' +always @(posedge spiSysClk) begin + forceEmptyToggleSyncToSpiClk <= {forceEmptyToggleSyncToSpiClk[1:0], forceEmptyToggle}; +end +assign forceEmptySyncToSpiClk = forceEmptyToggleSyncToSpiClk[2] ^ forceEmptyToggleSyncToSpiClk[1]; + +// async read mux +always @(address or fifoDataIn or numElementsInFifo) +begin + case (address) + `FIFO_DATA_REG : busDataOut <= fifoDataIn; + `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8]; + `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0]; + default: busDataOut <= 8'h00; + endcase +end + +//generate fifo read strobe +always @(address or writeEn or strobe_i or fifoSelect) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b0 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoREn <= 1'b1; + else + fifoREn <= 1'b0; +end + + +endmodule Index: spimaster/trunk/RTL/sm_dpMem_dc.v =================================================================== --- spimaster/trunk/RTL/sm_dpMem_dc.v (nonexistent) +++ spimaster/trunk/RTL/sm_dpMem_dc.v (revision 4) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_dpMem_dc.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Synchronous dual port memory with dual clocks +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module sm_dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input wrClk; +input rdClk; +input [FIFO_WIDTH-1:0] dataIn; +output [FIFO_WIDTH-1:0] dataOut; +input writeEn; +input readEn; +input [ADDR_WIDTH-1:0] addrIn; +input [ADDR_WIDTH-1:0] addrOut; + +wire wrClk; +wire rdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire writeEn; +wire readEn; +wire [ADDR_WIDTH-1:0] addrIn; +wire [ADDR_WIDTH-1:0] addrOut; + +reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1]; + +// synchronous read. Introduces one clock cycle delay +always @(posedge rdClk) begin + dataOut <= buffer[addrOut]; +end + +// synchronous write +always @(posedge wrClk) begin + if (writeEn == 1'b1) + buffer[addrIn] <= dataIn; +end + + +endmodule Index: spimaster/trunk/RTL/spiMaster.v =================================================================== --- spimaster/trunk/RTL/spiMaster.v (nonexistent) +++ spimaster/trunk/RTL/spiMaster.v (revision 4) @@ -0,0 +1,383 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spiMaster.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Top level module +//// +//// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module spiMaster( + clk_i, + rst_i, + address_i, + data_i, + data_o, + strobe_i, + we_i, + ack_o, + + // SPI logic clock + spiSysClk, + + //SPI bus + spiClkOut, + spiDataIn, + spiDataOut, + spiCS_n +); + +//Wishbone bus +input clk_i; +input rst_i; +input [7:0] address_i; +input [7:0] data_i; +output [7:0] data_o; +input strobe_i; +input we_i; +output ack_o; + +// SPI logic clock +input spiSysClk; + +//SPI bus +output spiClkOut; +input spiDataIn; +output spiDataOut; +output spiCS_n; + +// local wires and regs +wire spiSysClk; +wire [7:0] spiClkDelayFromInitSD; +wire rstSyncToSpiClk; +wire [7:0] rxDataFromRWSPIWireData; +wire rxDataRdySetFromRWSPIWireData; +wire txDataFullFromSpiTxRxData; +wire txDataFullClrFromRWSPIWireData; +wire [7:0] txDataToRWSPIWireData; +wire rxDataRdyClrFromRWSDBlock; +wire rxDataRdyClrFromSendCmd; +wire [7:0] rxDataFromSpiTxRxData; +wire rxDataRdy; +wire [7:0] txDataFromRWSDBlock; +wire txDataWenFromRWSDBlock; +wire [7:0] txDataFromSendCmd; +wire txDataWenFromSendCmd; +wire [7:0] txDataFromInitSD; +wire txDataWenFromInitSD; +wire [7:0] dataFromCtrlStsReg; +wire [7:0] dataFromTxFifo; +wire [7:0] dataFromRxFifo; +wire [1:0] spiTransType; +wire [7:0] spiDirectAccessTxData; +wire [1:0] readWriteSDBlockReq; +wire [1:0] SDWriteError; +wire [1:0] SDReadError; +wire [1:0] SDInitError; +wire [7:0] cmdByteFromInitSD; +wire [7:0] dataByte1FromInitSD; +wire [7:0] dataByte2FromInitSD; +wire [7:0] dataByte3FromInitSD; +wire [7:0] dataByte4FromInitSD; +wire [7:0] checkSumByteFromInitSD; +wire [7:0] sendCmdRespByte; +wire [7:0] cmdByteFromRWSDBlock; +wire [7:0] dataByte1FromRWSDBlock; +wire [7:0] dataByte2FromRWSDBlock; +wire [7:0] dataByte3FromRWSDBlock; +wire [7:0] dataByte4FromRWSDBlock; +wire [7:0] checkSumByteFromRWSDBlock; +wire [7:0] txFifoDataOut; +wire [7:0] rxFifoDataIn; +wire [31:0] SDAddr; +wire [7:0] spiClkDelayFromCtrlStsReg; +wire spiCS_nFromInitSD; +wire spiCS_nFromRWSDBlock; +wire spiCS_nFromSpiCtrl; + + +assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl; + +// ----------------------------------- +// Instance of Module: wishBoneBI +// ----------------------------------- +spiMasterWishBoneBI u_spiMasterWishBoneBI( + .ack_o( ack_o ), + .address( address_i ), + .clk( clk_i ), + .ctrlStsRegSel( ctrlStsRegSel ), + .dataFromCtrlStsReg( dataFromCtrlStsReg ), + .dataFromRxFifo( dataFromRxFifo ), + .dataFromTxFifo( dataFromTxFifo ), + .dataIn( data_i ), + .dataOut( data_o ), + .rst( rst_i ), + .rxFifoSel( rxFifoSel ), + .strobe_i( strobe_i ), + .txFifoSel( txFifoSel ), + .writeEn( we_i ) + ); + +// ----------------------------------- +// Instance of Module: ctrlStsRegBI +// ----------------------------------- +ctrlStsRegBI u_ctrlStsRegBI( + .busClk( clk_i ), + .spiSysClk( spiSysClk ), + .rstSyncToBusClkOut( rstSyncToBusClk ), + .rstSyncToSpiClkOut( rstSyncToSpiClk ), + .rstFromWire( rst_i ), + .address( address_i ), + .strobe_i( strobe_i ), + .dataIn( data_i ), + .dataOut( dataFromCtrlStsReg ), + .ctrlStsRegSel( ctrlStsRegSel ), + .spiTransType( spiTransType ), + .spiTransCtrl( spiTransCtrl ), + .spiTransStatus( spiTransSts ), + .spiDirectAccessTxData(spiDirectAccessTxData), + .spiDirectAccessRxData(rxDataFromSpiTxRxData), + .writeEn( we_i ), + .SDWriteError( SDWriteError ), + .SDReadError( SDReadError ), + .SDInitError( SDInitError ), + .SDAddr( SDAddr ), + .spiClkDelay( spiClkDelayFromCtrlStsReg) + ); + +// ----------------------------------- +// Instance of Module: spiCtrl +// ----------------------------------- +spiCtrl u_spiCtrl( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .SDInitReq( SDInitReq ), + .SDInitRdy( SDInitRdy ), + .readWriteSDBlockReq( readWriteSDBlockReq ), + .readWriteSDBlockRdy( readWriteSDBlockRdy ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromSpiCtrl), + .spiTransType( spiTransType ), + .spiTransCtrl( spiTransCtrl ), + .spiTransSts( spiTransSts ), + .txDataWen( txDataWenFromSpiCtrl ), + .spiCS_n( spiCS_nFromSpiCtrl ) + ); + + +// ----------------------------------- +// Instance of Module: initSD +// ----------------------------------- +initSD u_initSD( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .SDInitReq( SDInitReq ), + .SDInitRdy( SDInitRdy ), + .initError( SDInitError ), + .sendCmdReq( sendCmdReqFromInitSD ), + .sendCmdRdy( sendCmdRdy ), + .cmdByte( cmdByteFromInitSD ), + .dataByte1( dataByte1FromInitSD ), + .dataByte2( dataByte2FromInitSD ), + .dataByte3( dataByte3FromInitSD ), + .dataByte4( dataByte4FromInitSD ), + .checkSumByte( checkSumByteFromInitSD), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .spiCS_n( spiCS_nFromInitSD ), + .spiClkDelayOut( spiClkDelayFromInitSD ), + .spiClkDelayIn( spiClkDelayFromCtrlStsReg), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromInitSD ), + .txDataWen( txDataWenFromInitSD ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromInitSD) + ); + +// ----------------------------------- +// Instance of Module: readWriteSDBlock +// ----------------------------------- +readWriteSDBlock u_readWriteSDBlock( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .readWriteSDBlockReq( readWriteSDBlockReq ), + .readWriteSDBlockRdy( readWriteSDBlockRdy ), + .cmdByte( cmdByteFromRWSDBlock ), + .dataByte1( dataByte1FromRWSDBlock), + .dataByte2( dataByte2FromRWSDBlock), + .dataByte3( dataByte3FromRWSDBlock), + .dataByte4( dataByte4FromRWSDBlock), + .checkSumByte( checkSumByteFromRWSDBlock), + .readError( SDReadError ), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .rxDataIn( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromRWSDBlock), + .sendCmdRdy( sendCmdRdy ), + .sendCmdReq( sendCmdReqFromRWSDBlock), + .spiCS_n( spiCS_nFromRWSDBlock ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromRWSDBlock ), + .txDataWen( txDataWenFromRWSDBlock), + .txFifoData( txFifoDataOut ), + .txFifoRen( txFifoRE ), + .rxFifoData( rxFifoDataIn ), + .rxFifoWen( rRxFifoWE ), + .writeError( SDWriteError ), + .blockAddr( SDAddr ) + + ); + +// ----------------------------------- +// Instance of Module: sendCmd +// ----------------------------------- +sendCmd u_sendCmd( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .sendCmdReq1( sendCmdReqFromInitSD ), + .sendCmdReq2( sendCmdReqFromRWSDBlock), + .sendCmdRdy( sendCmdRdy ), + .cmdByte_1( cmdByteFromInitSD ), + .cmdByte_2( cmdByteFromRWSDBlock ), + .dataByte1_1( dataByte1FromInitSD ), + .dataByte1_2( dataByte1FromRWSDBlock), + .dataByte2_1( dataByte2FromInitSD ), + .dataByte2_2( dataByte2FromRWSDBlock), + .dataByte3_1( dataByte3FromInitSD ), + .dataByte3_2( dataByte3FromRWSDBlock), + .dataByte4_1( dataByte4FromInitSD ), + .dataByte4_2( dataByte4FromRWSDBlock), + .checkSumByte_1( checkSumByteFromInitSD), + .checkSumByte_2( checkSumByteFromRWSDBlock), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .rxDataIn( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromSendCmd), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromSendCmd ), + .txDataWen( txDataWenFromSendCmd ) + ); + +// ----------------------------------- +// Instance of Module: spiTxRxData +// ----------------------------------- +spiTxRxData u_spiTxRxData( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .rx1DataRdyClr( rxDataRdyClrFromRWSDBlock), + .rx2DataRdyClr( rxDataRdyClrFromSendCmd), + .rx3DataRdyClr( rxDataRdyClrFromInitSD), + .rx4DataRdyClr( rxDataRdyClrFromSpiCtrl), + .rxDataIn( rxDataFromRWSPIWireData), + .rxDataOut( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdySet( rxDataRdySetFromRWSPIWireData), + .tx1DataIn( txDataFromRWSDBlock ), + .tx1DataWEn( txDataWenFromRWSDBlock), + .tx2DataIn( txDataFromSendCmd ), + .tx2DataWEn( txDataWenFromSendCmd ), + .tx3DataIn( txDataFromInitSD ), + .tx3DataWEn( txDataWenFromInitSD ), + .tx4DataIn( spiDirectAccessTxData ), + .tx4DataWEn( txDataWenFromSpiCtrl ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataFullClr( txDataFullClrFromRWSPIWireData), + .txDataOut( txDataToRWSPIWireData ) + ); + +// ----------------------------------- +// Instance of Module: readWriteSPIWireData +// ----------------------------------- +readWriteSPIWireData u_readWriteSPIWireData( + .clk( spiSysClk ), + .clkDelay( spiClkDelayFromInitSD ), + .rst( rstSyncToSpiClk ), + .rxDataOut( rxDataFromRWSPIWireData), + .rxDataRdySet( rxDataRdySetFromRWSPIWireData), + .spiClkOut( spiClkOut ), + .spiDataIn( spiDataIn ), + .spiDataOut( spiDataOut ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataFullClr( txDataFullClrFromRWSPIWireData), + .txDataIn( txDataToRWSPIWireData ), + .txDataEmpty( txDataEmptyFromRWSPIWireData) + ); + +sm_TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_sm_txFifo ( + .spiSysClk(spiSysClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToSpiClk(rstSyncToSpiClk), + .fifoREn(txFifoRE), + .fifoEmpty(hostTxFifoEmpty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(txFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromTxFifo), + .fifoDataOut(txFifoDataOut) ); + + +sm_RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_sm_rxFifo( + .spiSysClk(spiSysClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToSpiClk(rstSyncToSpiClk), + .fifoWEn(rRxFifoWE), + .fifoFull(hostRxFifoFull), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(rxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromRxFifo), + .fifoDataIn(rxFifoDataIn) ); + +endmodule + Index: spimaster/trunk/RTL/sm_TxFifoBI.v =================================================================== --- spimaster/trunk/RTL/sm_TxFifoBI.v (nonexistent) +++ spimaster/trunk/RTL/sm_TxFifoBI.v (revision 4) @@ -0,0 +1,141 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// sm_TxfifoBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module sm_TxfifoBI ( + address, writeEn, strobe_i, + busClk, + spiSysClk, + rstSyncToBusClk, + fifoSelect, + busDataIn, + busDataOut, + fifoWEn, + forceEmptySyncToSpiClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoWEn; +output forceEmptySyncToSpiClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +reg fifoWEn; +wire forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg forceEmptyReg; +reg forceEmpty; +reg forceEmptyToggle; +reg [2:0] forceEmptyToggleSyncToSpiClk; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//detect rising edge of 'forceEmpty', and generate toggle signal +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) begin + forceEmptyReg <= 1'b0; + forceEmptyToggle <= 1'b0; + end + else begin + if (forceEmpty == 1'b1) + forceEmptyReg <= 1'b1; + else + forceEmptyReg <= 1'b0; + if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) + forceEmptyToggle <= ~forceEmptyToggle; + end +end +assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0; + +// double sync across clock domains to generate 'forceEmptySyncToSpiClk' +always @(posedge spiSysClk) begin + forceEmptyToggleSyncToSpiClk <= {forceEmptyToggleSyncToSpiClk[1:0], forceEmptyToggle}; +end +assign forceEmptySyncToSpiClk = forceEmptyToggleSyncToSpiClk[2] ^ forceEmptyToggleSyncToSpiClk[1]; + +// async read mux +assign busDataOut = 8'h00; + + +//generate fifo write strobe +always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b1 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoWEn <= 1'b1; + else + fifoWEn <= 1'b0; +end + + +endmodule Index: spimaster/trunk/doc/spiMaster_Specification.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spimaster/trunk/doc/spiMaster_Specification.pdf =================================================================== --- spimaster/trunk/doc/spiMaster_Specification.pdf (nonexistent) +++ spimaster/trunk/doc/spiMaster_Specification.pdf (revision 4)

spimaster/trunk/doc/spiMaster_Specification.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spimaster/trunk/doc/src/spiMaster_Specification.sxw =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spimaster/trunk/doc/src/spiMaster_Specification.sxw =================================================================== --- spimaster/trunk/doc/src/spiMaster_Specification.sxw (nonexistent) +++ spimaster/trunk/doc/src/spiMaster_Specification.sxw (revision 4)

spimaster/trunk/doc/src/spiMaster_Specification.sxw Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spimaster/trunk/doc/spiMaster_FSM.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: spimaster/trunk/doc/spiMaster_FSM.pdf =================================================================== --- spimaster/trunk/doc/spiMaster_FSM.pdf (nonexistent) +++ spimaster/trunk/doc/spiMaster_FSM.pdf (revision 4)

spimaster/trunk/doc/spiMaster_FSM.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: spimaster/trunk/Aldec/design0/design0.adf =================================================================== --- spimaster/trunk/Aldec/design0/design0.adf (nonexistent) +++ spimaster/trunk/Aldec/design0/design0.adf (revision 4) @@ -0,0 +1,48 @@ +[Project] +Current Flow=Generic +VCS=0 +version=1 +Current Config=compile + +[Configurations] +compile=design0 + +[Library] +design0=.\design0.LIB + +[$LibMap$] +design0=. + +[Settings] +FLOW_TYPE=HDL +LANGUAGE=VHDL + +[Files] +/readWriteSPIWireData.asf=-1 +/initSD.asf=-1 +/sendCmd.asf=-1 +/readWriteSDBlock.asf=-1 +/spiCtrl.asf=-1 + +[Files.Data] +.\src\readWriteSPIWireData.asf=State Diagram +.\src\initSD.asf=State Diagram +.\src\sendCmd.asf=State Diagram +.\src\readWriteSDBlock.asf=State Diagram +.\src\spiCtrl.asf=State Diagram + +[file_out:/initSD.asf] +/\compile\initSD.v=-1 + +[file_out:/sendCmd.asf] +/\compile\sendCmd.v=-1 + +[file_out:/readWriteSDBlock.asf] +/\compile\readWriteSDBlock.v=-1 + +[file_out:/spiCtrl.asf] +/\compile\spiCtrl.v=-1 + +[file_out:/readWriteSPIWireData.asf] +/\compile\readWriteSPIWireData.v=-1 + Index: spimaster/trunk/Aldec/design0/src/readWriteSPIWireData.asf =================================================================== --- spimaster/trunk/Aldec/design0/src/readWriteSPIWireData.asf (nonexistent) +++ spimaster/trunk/Aldec/design0/src/readWriteSPIWireData.asf (revision 4) @@ -0,0 +1,121 @@ +VERSION=1.15 +HEADER +FILE="readWriteSPIWireData.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="readWriteSPIWireData" +FRAMES=ON +FREEOID=95 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSPIWireData.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// Wait for TX data bytes. When data is ready generate\n//// SPI TX data, SPI CLK, and read SPI RX data\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 2844 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 2844 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 2844 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 57 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: readWriteSPIWireData" +A 5 0 1 TEXT "Actions" | 30673,274317 1 0 0 "-- diagram ACTION" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,246400 +L 7 6 0 TEXT "Labels" | 31400,243400 1 0 0 "rwSPISt" +L 8 9 0 TEXT "Labels" | 167524,266756 1 0 0 "txDataFull" +I 9 0 2 Builtin InPort | 161524,266756 "" "" +L 10 11 0 TEXT "Labels" | 165076,262648 1 0 0 "txDataFullClr" +I 11 0 2 Builtin OutPort | 159076,262648 "" "" +L 12 13 0 TEXT "Labels" | 122918,264250 1 0 0 "rxDataRdySet" +I 13 0 2 Builtin OutPort | 116918,264250 "" "" +L 14 15 0 TEXT "Labels" | 167406,271658 1 0 0 "txDataIn[7:0]" +I 15 0 130 Builtin InPort | 161406,271658 "" "" +L 16 17 0 TEXT "Labels" | 123072,269174 1 0 0 "rxDataOut[7:0]" +I 17 0 130 Builtin OutPort | 117072,269174 "" "" +L 18 19 0 TEXT "State Labels" | 110704,231360 1 0 0 "WT_TX_DATA\n/0/" +S 19 6 0 ELLIPSE "States" | 110704,231360 6500 6500 +L 20 21 0 TEXT "State Labels" | 112226,189022 1 0 0 "CLK_HI\n/1/" +S 21 6 4096 ELLIPSE "States" | 112226,189022 6500 6500 +W 22 6 0 19 21 BEZIER "Transitions" | 110470,224884 110707,219468 110980,207626 111395,195467 +C 23 22 0 TEXT "Conditions" | 116947,226592 1 0 0 "txDataFull == 1'b1" +A 24 22 16 TEXT "Actions" | 104644,222649 1 0 0 "txDataShiftReg <= txDataIn;\nrxDataShiftReg <= 8'h00;\nbitCnt <= 4'h0;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b1;\ntxDataEmpty <= 1'b0;" +L 25 26 0 TEXT "Labels" | 85178,260017 1 0 0 "txDataShiftReg[7:0]" +I 26 0 130 Builtin Signal | 82178,260017 "" "" +L 27 28 0 TEXT "Labels" | 85450,264368 1 0 0 "bitCnt[3:0]" +I 28 0 130 Builtin Signal | 82450,264368 "" "" +L 29 30 0 TEXT "Labels" | 45301,255946 1 0 0 "clkDelay[7:0]" +I 30 0 130 Builtin InPort | 39301,255946 "" "" +L 31 32 0 TEXT "Labels" | 85178,269538 1 0 0 "clkDelayCnt[7:0]" +I 32 0 130 Builtin Signal | 82178,269538 "" "" +L 33 34 0 TEXT "State Labels" | 112064,143714 1 0 0 "CLK_LO\n/2/" +S 34 6 8192 ELLIPSE "States" | 112064,143714 6500 6500 +W 35 6 0 21 34 BEZIER "Transitions" | 111477,182571 110721,178461 111926,154930 111406,150180 +A 36 35 16 TEXT "Actions" | 117201,173770 1 0 0 "spiClkOut <= 1'b0;\nspiDataOut <= txDataShiftReg[7];\ntxDataShiftReg <= {txDataShiftReg[6:0], 1'b0};\nrxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn};\nclkDelayCnt <= 8'h00;" +A 40 34 4 TEXT "Actions" | 129744,145618 1 0 0 "clkDelayCnt <= clkDelayCnt + 1'b1;" +C 41 39 0 TEXT "Conditions" | 113864,136917 1 0 0 "bitCnt == 4'h8" +W 39 6 1 34 57 BEZIER "Transitions" | 112175,137251 112384,130999 112714,101841 111797,94879 +W 50 6 2 34 21 BEZIER "Transitions" | 108826,149348 101042,157950 83708,154801 80796,161835\ + 77884,168870 77971,186684 79172,191015 80374,195346\ + 85000,196884 88570,197360 92140,197836 101831,194594\ + 106220,191507 +A 51 50 16 TEXT "Actions" | 64275,179271 1 0 0 "spiClkOut <= 1'b1;\nbitCnt <= bitCnt + 1'b1;\nclkDelayCnt <= 8'h00;" +C 52 50 0 TEXT "Conditions" | 69697,159224 1 0 0 "clkDelayCnt == clkDelay" +A 53 21 4 TEXT "Actions" | 129906,194545 1 0 0 "clkDelayCnt <= clkDelayCnt + 1'b1;\ntxDataFullClr <= 1'b0;\nrxDataRdySet <= 1'b0;" +C 54 35 0 TEXT "Conditions" | 112616,182259 1 0 0 "clkDelayCnt == clkDelay" +L 56 57 0 TEXT "State Labels" | 112441,91219 1 0 0 "J1" +S 57 6 12292 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 111975,91295 3595 3595 +H 58 57 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 61 58 0 Builtin Entry | 96520,182880 +I 62 58 0 Builtin Exit | 123838,149654 +W 63 58 0 61 62 BEZIER "Transitions" | 100327,182880 105881,175159 115604,157376 121159,149654 +A 55 39 16 TEXT "Actions" | 101170,118509 1 0 0 "rxDataRdySet <= 1'b1;\nrxDataOut <= rxDataShiftReg;" +A 79 78 4 TEXT "Actions" | 172448,235984 1 0 0 "bitCnt <= 4'h0;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b0;\nrxDataRdySet <= 1'b0;\ntxDataShiftReg <= 8'h00;\nrxDataShiftReg <= 8'h00;\nrxDataOut <= 8'h00;\nspiDataOut <= 1'b0;\nspiClkOut <= 1'b0;\ntxDataEmpty <= 1'b0;" +S 78 6 16384 ELLIPSE "States" | 163200,234352 6500 6500 +L 77 78 0 TEXT "State Labels" | 163200,234352 1 0 0 "ST_RW_WIRE\n/3/" +C 75 70 0 TEXT "Conditions" | 67748,241498 1 0 0 "rst == 1'b1" +I 74 0 2 Builtin InPort | 195700,267632 "" "" +L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +W 70 6 0 69 78 BEZIER "Transitions" | 53584,240424 67019,243331 142652,244275 157000,236303 +I 69 6 0 Builtin Reset | 53584,240424 +W 65 6 1 57 21 BEZIER "Transitions" | 108870,93105 102326,112538 73109,121258 64708,125153\ + 56308,129049 47906,146800 45670,157910 43435,169021\ + 42893,195716 46449,203811 50006,211907 64777,217599\ + 73008,216616 81239,215634 100244,201596 107791,193773 +C 66 65 0 TEXT "Conditions" | 72805,108285 1 0 0 "txDataFull == 1'b1" +W 67 6 2 57 19 BEZIER "Transitions" | 108779,92940 102622,102639 71923,91036 67388,98354\ + 62853,105673 50345,122275 43604,135689 36864,149103\ + 35643,196122 41029,209502 46416,222883 69180,229387\ + 78123,230877 87066,232368 97753,231428 104224,231859 +A 68 65 16 TEXT "Actions" | 47229,151610 1 0 0 "txDataShiftReg <= txDataIn;\nbitCnt <= 3'b000;\nclkDelayCnt <= 8'h00;\ntxDataFullClr <= 1'b1;" +L 88 87 0 TEXT "Labels" | 85310,255376 1 0 0 "rxDataShiftReg[7:0]" +I 87 0 130 Builtin Signal | 82310,255376 "" "" +I 86 0 2 Builtin OutPort | 37191,270020 "" "" +L 85 86 0 TEXT "Labels" | 43191,270020 1 0 0 "spiClkOut" +I 84 0 2 Builtin InPort | 39102,260465 "" "" +L 83 84 0 TEXT "Labels" | 45102,260465 1 0 0 "spiDataIn" +I 82 0 2 Builtin OutPort | 37191,265379 "" "" +L 81 82 0 TEXT "Labels" | 43191,265379 1 0 0 "spiDataOut" +W 80 6 0 78 19 BEZIER "Transitions" | 156735,233684 145855,233140 128082,232022 117202,231478 +A 92 19 4 TEXT "Actions" | 71554,227603 1 0 0 "rxDataRdySet <= 1'b0;\ntxDataEmpty <= 1'b1;" +L 93 94 0 TEXT "Labels" | 165150,258150 1 0 0 "txDataEmpty" +I 94 0 2 Builtin OutPort | 159150,258150 "" "" +END Index: spimaster/trunk/Aldec/design0/src/readWriteSDBlock.asf =================================================================== --- spimaster/trunk/Aldec/design0/src/readWriteSDBlock.asf (nonexistent) +++ spimaster/trunk/Aldec/design0/src/readWriteSDBlock.asf (revision 4) @@ -0,0 +1,528 @@ +VERSION=1.15 +HEADER +FILE="readWriteSDBlock.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="readWriteSDBlock" +FRAMES=ON +FREEOID=575 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSDBlock.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or\n//// READ_SD_BLOCK, then write or read a 512 byte block\n//// of SD memory\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 84 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 118 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 130 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 169 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 224 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 302 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 327 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 337 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 389 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 415 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +W 559 170 0 278 558 BEZIER "Transitions" | 159514,250710 169909,244734 184439,233702 194834,227726 +S 558 170 229376 ELLIPSE "States" | 199680,223395 6500 6500 +L 557 558 0 TEXT "State Labels" | 199680,223395 1 0 0 "DEL\n/47/" +A 556 315 4 TEXT "Actions" | 131150,199900 1 0 0 "sendCmdReq <= 1'b0;" +A 555 105 4 TEXT "Actions" | 131275,200525 1 0 0 "sendCmdReq <= 1'b0;" +I 554 0 130 Builtin Signal | 33764,246565 "" "" +L 553 554 0 TEXT "Labels" | 36764,246565 1 0 0 "locRespByte[7:0]" +I 552 0 130 Builtin Signal | 160575,273050 "" "" +L 551 552 0 TEXT "Labels" | 163575,273050 1 0 0 "timeOutCnt[11:0]" +I 548 0 130 Builtin InPort | 32700,254660 "" "" +L 547 548 0 TEXT "Labels" | 38700,254660 1 0 0 "blockAddr[31:0]" +I 546 0 130 Builtin Signal | 161380,256608 "" "" +L 545 546 0 TEXT "Labels" | 164380,256608 1 0 0 "delCnt2[7:0]" +I 544 0 130 Builtin Signal | 161114,261928 "" "" +W 287 170 3 273 278 BEZIER "Transitions" | 153140,203509 147585,209132 136504,218759 133963,224585\ + 131423,230411 132372,242472 134709,246197 137046,249923\ + 143477,251737 147677,253159 +C 283 275 0 TEXT "Conditions" | 163404,220919 1 0 0 "rxDataRdy == 1'b1" +L 282 273 0 TEXT "State Labels" | 158403,199697 1 0 0 "CHK_RESP\n/20/" +L 281 280 0 TEXT "State Labels" | 155702,223714 1 0 0 "REQ_RESP_FIN\n/22/" +S 280 170 106496 ELLIPSE "States" | 155702,223714 6500 6500 +L 279 278 0 TEXT "State Labels" | 154080,254276 1 0 0 "REQ_RESP_ST\n/21/" +S 278 170 102400 ELLIPSE "States" | 154080,254276 6500 6500 +I 277 170 0 Builtin Exit | 145690,169066 +A 276 275 16 TEXT "Actions" | 150887,216503 1 0 0 "locRespByte <= rxDataIn;" +W 275 170 0 280 273 BEZIER "Transitions" | 156440,217258 156900,213346 157290,210028 157662,206152 +S 273 170 98304 ELLIPSE "States" | 158403,199697 6500 6500 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: readWriteSDBlock" +A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,27210 212900,223210 +L 7 6 0 TEXT "Labels" | 32996,218270 1 0 0 "rwBlkSt" +A 574 348 16 TEXT "Actions" | 112284,154324 1 0 0 "locRespByte <= rxDataIn;" +A 573 374 16 TEXT "Actions" | 60519,153465 1 0 0 "timeOutCnt <= timeOutCnt + 1'b1;\ndelCnt1 <= 8'h00;" +A 572 239 16 TEXT "Actions" | 42138,190870 1 0 0 "timeOutCnt <= timeOutCnt + 1'b1;" +A 571 235 16 TEXT "Actions" | 97926,168996 1 0 0 "locRespByte <= rxDataIn;" +A 570 380 4 TEXT "Actions" | 118523,190933 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" +C 569 459 0 TEXT "Conditions" | 151001,57686 1 0 0 "txDataEmpty == 1'b1" +C 568 456 0 TEXT "Conditions" | 82775,122525 1 0 0 "loopCnt == 9'b000000000" +C 566 296 0 TEXT "Conditions" | 164031,44934 1 0 0 "txDataEmpty == 1'b1" +I 565 0 2 Builtin InPort | 116956,228328 "" "" +L 564 565 0 TEXT "Labels" | 122956,228328 1 0 0 "txDataEmpty" +A 563 562 16 TEXT "Actions" | 167684,228749 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" +W 562 170 0 558 280 BEZIER "Transitions" | 193184,223621 184656,223621 170729,223805 162201,223805 +A 560 559 16 TEXT "Actions" | 163700,256139 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\ntimeOutCnt <= timeOutCnt + 1'b1;\nrxDataRdyClr <= 1'b1;" +L 303 302 0 TEXT "State Labels" | 155866,114847 1 0 0 "RD_CMD" +S 302 6 110596 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155866,114847 6500 6500 +W 301 6 0 169 224 BEZIER "Transitions" | 116491,60040 116453,54383 116661,57097 116661,51812 +W 300 6 0 130 169 BEZIER "Transitions" | 116096,82088 116419,75091 116419,77840 116311,72556 +W 299 6 0 84 130 BEZIER "Transitions" | 115210,103426 115637,98573 116012,99639 116012,95047 +W 298 6 0 128 84 BEZIER "Transitions" | 114213,168601 114343,164295 115365,122584 115190,116371 +W 297 6 0 82 128 BEZIER "Transitions" | 112965,189035 113095,186752 113278,183816 113408,181533 +W 296 170 0 204 278 BEZIER "Transitions" | 153459,62290 160628,57734 172959,48292 179659,46684\ + 186359,45076 198821,47756 201970,53652 205119,59548\ + 205253,80452 198486,92679 191719,104907 164517,132913\ + 153797,143566 143077,154219 127399,168825 124585,181588\ + 121771,194352 126193,230800 129007,242190 131821,253580\ + 138655,262692 141703,264836 144752,266980 150112,266444\ + 151686,265539 153261,264635 153717,262299 154186,260758 +A 295 291 16 TEXT "Actions" | 160354,178019 1 0 0 "writeError <= `WRITE_DATA_ERROR;" +C 294 291 0 TEXT "Conditions" | 162436,185390 1 0 0 "timeOutCnt == `WR_RESP_TOUT" +I 293 170 0 Builtin Link | 189438,166068 +L 292 293 0 TEXT "Labels" | 195438,166068 1 0 0 "WT_REQ" +W 291 170 1 273 293 BEZIER "Transitions" | 162433,194598 169133,187027 182738,171639 189438,164068 +C 290 288 0 TEXT "Conditions" | 126676,185877 1 0 0 "locRespByte[4:0] == 5'h5" +W 288 170 2 273 277 BEZIER "Transitions" | 156465,193495 155043,188346 148800,175094 145760,171065 +I 319 304 0 Builtin Link | 156420,111673 +I 318 304 0 Builtin Exit | 144032,98711 +A 317 305 4 TEXT "Actions" | 129068,241820 1 0 0 "cmdByte <= 8'h51; //CMD17 Block Read\ndataByte1 <= blockAddr[31:24];\ndataByte2 <= blockAddr[23:16];\ndataByte3 <= blockAddr[15:8];\ndataByte4 <= blockAddr[7:0];\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;" +L 316 315 0 TEXT "State Labels" | 113784,198353 1 0 0 "DEL\n/25/" +S 315 304 122880 ELLIPSE "States" | 113784,198353 6500 6500 +L 314 313 0 TEXT "State Labels" | 113242,173421 1 0 0 "WT_FIN\n/24/" +S 313 304 118784 ELLIPSE "States" | 113242,173421 6500 6500 +W 312 304 0 305 315 BEZIER "Transitions" | 113342,219069 113342,214801 113400,209100 113400,204832 +W 311 304 0 315 313 BEZIER "Transitions" | 113290,191878 113155,188152 113070,183636 112935,179910 +W 310 304 0 307 305 BEZIER "Transitions" | 74238,246230 83316,241623 99061,233757 108139,229150 +C 309 308 0 TEXT "Conditions" | 118993,167630 1 0 0 "sendCmdRdy == 1'b1" +W 308 304 0 313 327 BEZIER "Transitions" | 116637,167879 123539,156637 117794,149336 126648,141321 +I 307 304 0 Builtin Entry | 70580,246230 +L 306 305 0 TEXT "State Labels" | 113556,225558 1 0 0 "SEND_CMD\n/23/" +S 305 304 114688 ELLIPSE "States" | 113556,225558 6500 6500 +H 304 302 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +A 335 334 16 TEXT "Actions" | 134500,139322 1 0 0 "spiCS_n <= 1'b0;\nreadWriteSDBlockRdy <= 1'b0;\nreadError <= `READ_NO_ERROR;" +W 334 6 0 128 302 BEZIER "Transitions" | 119969,172153 128545,167673 154370,136857 153592,120935 +A 333 298 16 TEXT "Actions" | 76094,136596 1 0 0 "spiCS_n <= 1'b0;\nreadWriteSDBlockRdy <= 1'b0;\nwriteError <= `WRITE_NO_ERROR;" +A 332 128 4 TEXT "Actions" | 66248,183412 1 0 0 "spiCS_n <= 1'b1;\nreadWriteSDBlockRdy <= 1'b1;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;" +W 331 328 0 329 330 BEZIER "Transitions" | 100205,182880 103344,179877 105196,169695 108335,166692 +I 330 328 0 Builtin Exit | 110928,166692 +I 329 328 0 Builtin Entry | 96520,182880 +S 327 304 126980 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 128874,139185 3156 3017 +L 326 327 0 TEXT "State Labels" | 128942,138847 1 0 0 "J2" +W 325 304 3 327 318 BEZIER "Transitions" | 129847,136319 133174,127641 137870,107389 141197,98711 +A 323 321 16 TEXT "Actions" | 139238,127895 1 0 0 "readError <= `READ_CMD_ERROR;" +C 322 321 0 TEXT "Conditions" | 137153,138885 1 0 0 "respTout == 1'b1 || respByte != 8'h00" +W 321 304 2 327 319 BEZIER "Transitions" | 131177,137123 136826,130398 150771,116398 156420,109673 +L 320 319 0 TEXT "Labels" | 162420,111673 1 0 0 "WT_REQ" +H 328 327 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 351 338 139264 ELLIPSE "States" | 106026,166550 6500 6500 +W 350 338 0 368 369 BEZIER "Transitions" | 67549,239359 76627,234752 86180,250238 95258,245631 +C 349 348 0 TEXT "Conditions" | 111780,160832 1 0 0 "rxDataRdy == 1'b1" +W 348 338 0 351 346 BEZIER "Transitions" | 109408,161002 116386,149688 110826,148678 118545,137753 +L 347 346 0 TEXT "State Labels" | 122076,132298 1 0 0 "CHK_LOOP\n/26/" +S 346 338 135168 ELLIPSE "States" | 122076,132298 6500 6500 +H 338 337 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 337 6 131076 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155556,94377 6500 6500 +L 336 337 0 TEXT "State Labels" | 155556,94377 1 0 0 "RD_TOKEN" +I 74 0 2 Builtin InPort | 195700,267632 "" "" +L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +L 367 359 0 TEXT "State Labels" | 106340,218687 1 0 0 "SEND_CMD\n/28/" +L 366 365 0 TEXT "State Labels" | 53406,179998 1 0 0 "DEL2\n/29/" +S 365 338 147456 ELLIPSE "States" | 53406,179998 6500 6500 +W 364 338 3 346 361 BEZIER "Transitions" | 123583,125978 114391,113159 121643,95942 132878,90341 +I 361 338 0 Builtin Exit | 135456,90208 +A 360 359 4 TEXT "Actions" | 121852,234949 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;" +S 359 338 143360 ELLIPSE "States" | 106340,218687 6500 6500 +L 352 351 0 TEXT "State Labels" | 106026,166550 1 0 0 "WT_FIN\n/27/" +L 81 82 0 TEXT "State Labels" | 113220,195514 1 0 0 "ST_RW_SD\n/0/" +S 82 6 0 ELLIPSE "States" | 113220,195514 6500 6500 +L 83 84 0 TEXT "State Labels" | 115395,109896 1 0 0 "WR_CMD" +S 84 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115395,109896 6500 6500 +H 85 84 0 RECT 0,0,0 0 0 1 255,255,255 0 | 27860,28670 212360,276670 +S 92 85 8192 ELLIPSE "States" | 113016,225828 6500 6500 +L 93 92 0 TEXT "State Labels" | 113016,225828 1 0 0 "SEND_CMD\n/1/" +I 94 85 0 Builtin Entry | 70040,246500 +W 383 338 2 346 385 BEZIER "Transitions" | 128455,133541 138850,135296 180442,141646 191036,142273 +W 382 338 0 380 351 BEZIER "Transitions" | 105524,186872 105457,182130 105515,177755 105448,173013 +W 381 338 0 359 380 BEZIER "Transitions" | 105523,212247 105320,208453 105367,203608 105164,199814 +S 380 338 155648 ELLIPSE "States" | 105765,193344 6500 6500 +L 379 380 0 TEXT "State Labels" | 105765,193344 1 0 0 "DEL1\n/31/" +C 377 374 0 TEXT "Conditions" | 32353,125947 1 0 0 "locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS" +C 376 375 0 TEXT "Conditions" | 37395,199964 1 0 0 "delCnt1 == `MAX_8_BIT" +W 375 338 1 365 359 BEZIER "Transitions" | 55933,185983 60073,191941 68179,216209 76636,218125\ + 85094,220041 90522,226339 93570,226372 96618,226406\ + 99403,224529 101638,223174 +W 374 338 1 346 365 BEZIER "Transitions" | 116959,136304 87922,130964 55868,158884 57051,176025 +A 373 365 4 TEXT "Actions" | 64312,187877 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" +L 372 369 0 TEXT "State Labels" | 101285,243200 1 0 0 "INIT_LOOP\n/30/" +W 371 338 0 369 359 BEZIER "Transitions" | 101997,236742 102942,232760 103652,228930 104597,224948 +A 370 369 4 TEXT "Actions" | 114245,248870 1 0 0 "timeOutCnt <= 12'h000;" +S 369 338 151552 ELLIPSE "States" | 101285,243200 6500 6500 +I 368 338 0 Builtin Entry | 63364,239359 +W 98 85 0 103 118 BEZIER "Transitions" | 116097,168149 122999,156907 117254,149606 126108,141591 +C 99 98 0 TEXT "Conditions" | 118453,167900 1 0 0 "sendCmdRdy == 1'b1" +W 100 85 0 94 92 BEZIER "Transitions" | 73698,246500 82776,241893 98521,234027 107599,229420 +W 101 85 0 105 103 BEZIER "Transitions" | 112750,192148 112615,188422 112530,183906 112395,180180 +W 102 85 0 92 105 BEZIER "Transitions" | 112802,219339 112802,215071 112860,209370 112860,205102 +S 103 85 12288 ELLIPSE "States" | 112702,173691 6500 6500 +L 104 103 0 TEXT "State Labels" | 112702,173691 1 0 0 "WT_FIN\n/2/" +S 105 85 16384 ELLIPSE "States" | 113244,198623 6500 6500 +L 106 105 0 TEXT "State Labels" | 113244,198623 1 0 0 "DEL\n/3/" +A 107 92 4 TEXT "Actions" | 128528,242090 1 0 0 "cmdByte <= 8'h58; //CMD24 Block Write\ndataByte1 <= blockAddr[31:24];\ndataByte2 <= blockAddr[23:16];\ndataByte3 <= blockAddr[15:8];\ndataByte4 <= blockAddr[7:0];\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;" +I 108 85 0 Builtin Exit | 143492,98981 +I 109 85 0 Builtin Link | 155880,111943 +L 110 109 0 TEXT "Labels" | 161880,111943 1 0 0 "WT_REQ" +W 111 85 2 118 109 BEZIER "Transitions" | 130637,137393 136286,130668 150231,116668 155880,109943 +A 387 383 16 TEXT "Actions" | 144060,138060 1 0 0 "readError <= `READ_TOKEN_ERROR;" +C 386 383 0 TEXT "Conditions" | 128229,146101 1 0 0 "timeOutCnt == `ONE_HUNDRED_MS" +I 385 338 0 Builtin Link | 190990,144650 +L 384 385 0 TEXT "Labels" | 196990,144650 1 0 0 "WT_REQ" +C 112 111 0 TEXT "Conditions" | 136613,139155 1 0 0 "respTout == 1'b1 || respByte != 8'h00" +A 113 111 16 TEXT "Actions" | 138698,128165 1 0 0 "writeError <= `WRITE_CMD_ERROR;" +W 116 85 3 118 108 BEZIER "Transitions" | 129307,136589 132634,127911 137330,107659 140657,98981 +L 117 118 0 TEXT "State Labels" | 128402,139117 1 0 0 "J1" +S 118 85 20484 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 128334,139455 3156 3017 +H 119 118 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 122 119 0 Builtin Entry | 96520,182880 +I 123 119 0 Builtin Exit | 110928,166692 +W 126 119 0 122 123 BEZIER "Transitions" | 100205,182880 103344,179877 105196,169695 108335,166692 +L 127 128 0 TEXT "State Labels" | 114166,175079 1 0 0 "WT_REQ\n/4/" +L 388 389 0 TEXT "State Labels" | 155343,73929 1 0 0 "RD_DATA" +S 389 6 159748 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155343,73929 6500 6500 +H 390 389 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 128 6 24576 ELLIPSE "States" | 114166,175079 6500 6500 +L 129 130 0 TEXT "State Labels" | 116508,88574 1 0 0 "WR_TOKEN" +S 130 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116508,88574 6500 6500 +H 131 130 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +W 138 131 0 144 141 BEZIER "Transitions" | 93143,232118 93346,228934 95399,216673 95425,213277 +A 139 138 16 TEXT "Actions" | 83596,226272 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 140 138 0 TEXT "Conditions" | 95421,232225 1 0 0 "txDataFull == 1'b0" +S 141 131 32768 ELLIPSE "States" | 95726,206806 6500 6500 +L 142 141 0 TEXT "State Labels" | 95726,206806 1 0 0 "FF1_FIN\n/5/" +A 143 141 4 TEXT "Actions" | 105171,209122 1 0 0 "txDataWen <= 1'b0;" +L 400 401 0 TEXT "State Labels" | 77852,226948 1 0 0 "ST_LOOP\n/32/" +S 401 390 163840 ELLIPSE "States" | 77852,226948 6500 6500 +A 402 401 4 TEXT "Actions" | 95196,229658 1 0 0 "txDataWen <= 1'b1;\ntxDataOut <= 8'hff;\nloopCnt <= loopCnt + 1'b1;" +L 403 404 0 TEXT "State Labels" | 78936,199306 1 0 0 "WT_DATA\n/33/" +S 404 390 167936 ELLIPSE "States" | 78936,199306 6500 6500 +W 406 390 0 401 404 BEZIER "Transitions" | 77695,220483 77762,216960 78169,209653 78270,205764 +A 408 404 4 TEXT "Actions" | 97364,200119 1 0 0 "txDataWen <= 1'b0;" +L 409 410 0 TEXT "State Labels" | 81375,162450 1 0 0 "CHK_LOOP\n/34/" +S 410 390 172032 ELLIPSE "States" | 81375,162450 6500 6500 +W 411 390 0 404 410 BEZIER "Transitions" | 79226,192822 79632,188351 80587,173613 80938,168928 +C 412 411 0 TEXT "Conditions" | 81955,194246 1 0 0 "rxDataRdy == 1'b1" +A 413 411 16 TEXT "Actions" | 74786,189659 1 0 0 "rxFifoWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\nrxFifoData <= rxDataIn;" +L 414 415 0 TEXT "State Labels" | 83004,136975 1 0 0 "J1" +S 415 390 176132 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 83043,136396 3569 3569 +S 144 131 36864 ELLIPSE "States" | 92762,238598 6500 6500 +L 145 144 0 TEXT "State Labels" | 92762,238598 1 0 0 "FF1_ST\n/6/" +I 146 131 0 Builtin Entry | 51952,266176 +S 147 131 40960 ELLIPSE "States" | 101439,148824 6500 6500 +A 148 147 4 TEXT "Actions" | 110884,151140 1 0 0 "txDataWen <= 1'b0;" +L 149 147 0 TEXT "State Labels" | 101439,148824 1 0 0 "FF2_FIN\n/7/" +W 150 131 0 153 147 BEZIER "Transitions" | 98856,174136 99059,170952 101112,158691 101138,155295 +C 151 150 0 TEXT "Conditions" | 101134,174243 1 0 0 "txDataFull == 1'b0" +A 152 150 16 TEXT "Actions" | 89309,168290 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 153 131 45056 ELLIPSE "States" | 98475,180616 6500 6500 +L 154 153 0 TEXT "State Labels" | 98475,180616 1 0 0 "FF2_ST\n/8/" +S 155 131 49152 ELLIPSE "States" | 107423,92248 6500 6500 +A 156 155 4 TEXT "Actions" | 116868,94564 1 0 0 "txDataWen <= 1'b0;" +L 157 155 0 TEXT "State Labels" | 107423,92248 1 0 0 "FE_FIN\n/9/" +W 158 131 0 161 155 BEZIER "Transitions" | 104840,117560 105043,114376 107096,102115 107122,98719 +C 159 158 0 TEXT "Conditions" | 107118,117667 1 0 0 "txDataFull == 1'b0" +H 416 415 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 419 416 0 Builtin Entry | 126004,141930 +I 420 416 0 Builtin Exit | 144780,121920 +W 423 416 0 419 420 BEZIER "Transitions" | 129826,141930 134057,136743 137819,127107 142050,121920 +W 424 390 0 410 415 BEZIER "Transitions" | 81407,156099 81677,152387 82370,143719 82390,139900 +A 425 424 16 TEXT "Actions" | 80070,154260 1 0 0 "rxDataRdyClr <= 1'b0;\nrxFifoWen <= 1'b0;" +I 426 390 0 Builtin Entry | 42810,270090 +L 427 428 0 TEXT "State Labels" | 97350,266040 1 0 0 "CLR_RX\n/35/" +S 428 390 180224 ELLIPSE "States" | 97350,266040 6500 6500 +W 429 390 0 426 428 BEZIER "Transitions" | 46995,270090 55230,269685 82688,267193 90992,267387 +A 430 429 16 TEXT "Actions" | 55533,269709 1 0 0 "rxDataRdyClr <= 1'b1;" +W 431 390 0 428 401 BEZIER "Transitions" | 94484,260209 90569,252717 84564,240304 80649,232812 +A 160 158 16 TEXT "Actions" | 95293,111714 1 0 0 "txDataOut <= 8'hfe;\ntxDataWen <= 1'b1;" +S 161 131 53248 ELLIPSE "States" | 104459,124040 6500 6500 +L 162 161 0 TEXT "State Labels" | 104459,124040 1 0 0 "FE_ST\n/10/" +W 163 131 0 146 144 BEZIER "Transitions" | 55624,266176 64736,260940 79060,248435 88172,243199 +W 164 131 0 141 153 BEZIER "Transitions" | 95785,200373 96397,196089 96746,191299 97358,187015 +I 165 131 0 Builtin Exit | 140624,67616 +W 166 131 0 147 161 BEZIER "Transitions" | 101803,142336 102279,138596 102801,134171 103277,130431 +W 167 131 0 155 165 BEZIER "Transitions" | 112534,88234 120218,83134 130356,72716 138040,67616 +L 168 169 0 TEXT "State Labels" | 116501,66078 1 0 0 "WR_DATA" +S 169 6 229380 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116501,66078 6500 6500 +H 170 169 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +A 432 431 16 TEXT "Actions" | 85200,253080 1 0 0 "rxDataRdyClr <= 1'b0;\nloopCnt <= 9'b000000000;" +W 433 390 2 415 401 BEZIER "Transitions" | 79771,137821 72144,141736 57457,148725 53070,158681\ + 48683,168637 46387,200633 47433,211027 48480,221422\ + 54960,231008 58470,232695 61980,234383 68385,231511\ + 72165,230094 +W 440 390 0 451 441 BEZIER "Transitions" | 138130,91528 138333,88344 140386,76083 140412,72687 +S 441 390 184320 ELLIPSE "States" | 140713,66216 6500 6500 +L 442 441 0 TEXT "State Labels" | 140713,66216 1 0 0 "CS_FIN2\n/36/" +S 443 390 188416 ELLIPSE "States" | 75739,66216 6500 6500 +A 444 443 4 TEXT "Actions" | 85184,68532 1 0 0 "txDataWen <= 1'b0;" +L 445 443 0 TEXT "State Labels" | 75739,66216 1 0 0 "CS_FIN1\n/37/" +W 446 390 0 449 443 BEZIER "Transitions" | 73156,91528 73359,88344 75412,76083 75438,72687 +C 447 446 0 TEXT "Conditions" | 75434,91635 1 0 0 "txDataFull == 1'b0" +S 177 170 61440 ELLIPSE "States" | 78305,137464 6500 6500 +A 178 177 4 TEXT "Actions" | 87750,139780 1 0 0 "txDataWen <= 1'b0;" +L 179 177 0 TEXT "State Labels" | 78305,137464 1 0 0 "D_FIN\n/11/" +W 180 170 0 183 177 BEZIER "Transitions" | 75722,162776 75925,159592 77978,147331 78004,143935 +C 181 180 0 TEXT "Conditions" | 78000,162883 1 0 0 "txDataFull == 1'b0" +A 182 180 16 TEXT "Actions" | 66175,156930 1 0 0 "txDataOut <= txFifoData;\ntxDataWen <= 1'b1;" +S 183 170 65536 ELLIPSE "States" | 75341,169256 6500 6500 +L 184 183 0 TEXT "State Labels" | 75341,169256 1 0 0 "D_ST\n/12/" +L 187 188 0 TEXT "State Labels" | 72867,227889 1 0 0 "RD_FIFO1\n/13/" +S 188 170 69632 ELLIPSE "States" | 72867,227889 6500 6500 +L 189 190 0 TEXT "State Labels" | 73959,201135 1 0 0 "RD_FIFO2\n/14/" +S 190 170 73728 ELLIPSE "States" | 73959,201135 6500 6500 +A 191 188 4 TEXT "Actions" | 80895,230061 1 0 0 "txFifoRen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" +A 448 446 16 TEXT "Actions" | 63609,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 449 390 192512 ELLIPSE "States" | 72775,98008 6500 6500 +L 450 449 0 TEXT "State Labels" | 72775,98008 1 0 0 "CS_ST1\n/38/" +S 451 390 196608 ELLIPSE "States" | 137749,98008 6500 6500 +L 452 451 0 TEXT "State Labels" | 137749,98008 1 0 0 "CS_ST2\n/39/" +A 453 440 16 TEXT "Actions" | 128583,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 454 440 0 TEXT "Conditions" | 140408,91635 1 0 0 "txDataFull == 1'b0" +A 455 441 4 TEXT "Actions" | 150158,68532 1 0 0 "txDataWen <= 1'b0;" +W 456 390 1 415 449 BEZIER "Transitions" | 82185,132936 79630,124866 76715,112427 74160,104357 +W 457 390 0 443 451 BEZIER "Transitions" | 78514,60339 82952,55834 89399,47074 95182,45998\ + 100965,44922 115223,49631 117845,56120 120468,62609\ + 116702,83861 117071,91594 117441,99328 122688,109012\ + 125276,109920 127865,110828 131449,106344 134004,103318 +I 458 390 0 Builtin Exit | 161625,43107 +W 459 390 0 441 458 BEZIER "Transitions" | 144285,60786 148925,56213 153892,47680 158532,43107 +W 460 6 0 302 337 BEZIER "Transitions" | 155788,108419 155653,104081 155771,105011 155438,100848 +W 461 6 0 337 389 BEZIER "Transitions" | 155952,87899 155619,83040 155938,84926 155805,80404 +W 462 6 0 389 128 BEZIER "Transitions" | 160766,72622 181673,64668 193592,81881 194705,86831\ + 195819,91782 193010,106602 196539,114884 200068,123167\ + 183067,150177 177992,160070 172917,169964 164106,188182\ + 156924,189345 149743,190509 134447,187583 129526,185887\ + 124606,184192 121267,181269 119073,179341 +W 463 6 0 224 128 BEZIER "Transitions" | 112148,42964 96171,38095 88076,46646 81324,48345\ + 74572,50044 62626,66620 61422,77634 60219,88648\ + 53118,140235 53550,154499 53982,168763 75928,188049\ + 79879,189622 83830,191195 94548,186386 97872,185422\ + 101197,184458 106213,181091 109338,179429 +A 192 190 4 TEXT "Actions" | 82521,204408 1 0 0 "txFifoRen <= 1'b0;" +L 193 194 0 TEXT "State Labels" | 72048,257646 1 0 0 "LOOP_INIT\n/15/" +S 194 170 77824 ELLIPSE "States" | 72048,257646 6500 6500 +A 195 194 4 TEXT "Actions" | 89247,259284 1 0 0 "loopCnt <= 9'b000000000;" +S 196 170 81920 ELLIPSE "States" | 80801,98549 6500 6500 +L 197 196 0 TEXT "State Labels" | 80801,98549 1 0 0 "CS_ST1\n/16/" +W 198 170 0 196 201 BEZIER "Transitions" | 81182,92069 81385,88885 83438,76624 83464,73228 +A 199 198 16 TEXT "Actions" | 71635,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 200 198 0 TEXT "Conditions" | 83460,92176 1 0 0 "txDataFull == 1'b0" +S 201 170 86016 ELLIPSE "States" | 83765,66757 6500 6500 +L 202 201 0 TEXT "State Labels" | 83765,66757 1 0 0 "CS_FIN1\n/17/" +A 203 201 4 TEXT "Actions" | 93210,69073 1 0 0 "txDataWen <= 1'b0;" +S 204 170 90112 ELLIPSE "States" | 148739,66757 6500 6500 +A 205 204 4 TEXT "Actions" | 158184,69073 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 12'h000;" +L 206 204 0 TEXT "State Labels" | 148739,66757 1 0 0 "CS_FIN2\n/18/" +W 207 170 0 210 204 BEZIER "Transitions" | 146156,92069 146359,88885 148412,76624 148438,73228 +C 464 334 0 TEXT "Conditions" | 94994,146397 1 0 0 "readWriteSDBlockReq == `READ_SD_BLOCK" +C 465 298 0 TEXT "Conditions" | 55739,152492 1 0 0 "readWriteSDBlockReq == `WRITE_SD_BLOCK" +I 475 6 0 Builtin Reset | 49660,206134 +W 476 6 0 475 82 BEZIER "Transitions" | 49660,206134 64556,204256 92040,199052 106936,197174 +C 477 476 0 TEXT "Conditions" | 62428,209528 1 0 0 "rst == 1'b1" +L 478 479 0 TEXT "Labels" | 122230,269291 1 0 0 "readWriteSDBlockReq[1:0]" +I 479 0 130 Builtin InPort | 116230,269291 "" "" +L 223 224 0 TEXT "State Labels" | 116398,45340 1 0 0 "WR_BUSY" +C 208 207 0 TEXT "Conditions" | 148434,92176 1 0 0 "txDataFull == 1'b0" +A 209 207 16 TEXT "Actions" | 136609,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 210 170 94208 ELLIPSE "States" | 145775,98549 6500 6500 +L 211 210 0 TEXT "State Labels" | 145775,98549 1 0 0 "CS_ST2\n/19/" +W 212 170 1 177 196 BEZIER "Transitions" | 78835,130988 79312,123617 80043,112406 80520,105035 +C 213 212 0 TEXT "Conditions" | 81603,129336 1 0 0 "loopCnt == 9'b000000000" +W 214 170 0 194 188 BEZIER "Transitions" | 72189,251169 72121,246119 72460,239413 72392,234363 +W 215 170 0 188 190 BEZIER "Transitions" | 72773,221428 73182,217197 73251,211851 73660,207620 +W 216 170 0 190 183 BEZIER "Transitions" | 74343,194648 74411,189188 74887,181191 74955,175731 +W 217 170 2 177 188 BEZIER "Transitions" | 71806,137461 65254,138211 53484,138960 49969,147866\ + 46455,156772 45498,190898 45396,201715 45294,212532\ + 45840,221679 48843,224169 51846,226660 60640,227203\ + 66373,227612 +W 218 170 0 201 210 BEZIER "Transitions" | 87098,61178 91397,57971 97506,51735 102658,50541\ + 107811,49347 119823,50985 122894,57434 125965,63884\ + 126239,88045 127637,96576 129036,105107 134361,115072\ + 136749,115515 139137,115959 142020,108931 144135,104836 +I 221 170 0 Builtin Entry | 39834,267201 +W 222 170 0 221 194 BEZIER "Transitions" | 43519,267201 49798,265427 59580,261403 65859,259629 +L 480 481 0 TEXT "Labels" | 120083,264098 1 0 0 "readWriteSDBlockRdy" +I 481 0 2 Builtin OutPort | 114083,264098 "" "" +L 482 483 0 TEXT "Labels" | 120083,259063 1 0 0 "spiCS_n" +I 483 0 2 Builtin OutPort | 114083,259063 "" "" +I 484 0 130 Builtin OutPort | 69013,272215 "" "" +L 485 484 0 TEXT "Labels" | 75013,272215 1 0 0 "cmdByte[7:0]" +I 486 0 130 Builtin OutPort | 68768,267735 "" "" +L 487 486 0 TEXT "Labels" | 74768,267735 1 0 0 "dataByte1[7:0]" +I 488 0 130 Builtin OutPort | 68965,262525 "" "" +L 489 488 0 TEXT "Labels" | 74965,262525 1 0 0 "dataByte2[7:0]" +I 490 0 130 Builtin OutPort | 69212,257832 "" "" +L 491 490 0 TEXT "Labels" | 75212,257832 1 0 0 "dataByte3[7:0]" +I 492 0 130 Builtin OutPort | 69212,253139 "" "" +L 493 492 0 TEXT "Labels" | 75212,253139 1 0 0 "dataByte4[7:0]" +I 494 0 130 Builtin OutPort | 69088,248199 "" "" +L 495 494 0 TEXT "Labels" | 75088,248199 1 0 0 "checkSumByte[7:0]" +W 239 225 1 237 241 BEZIER "Transitions" | 110570,148995 94430,151147 64068,154038 55628,162847\ + 47189,171657 45708,202593 49575,212814 53442,223036\ + 70390,232990 77013,235243 83637,237496 90160,236699\ + 94934,236229 +L 238 237 0 TEXT "State Labels" | 117061,148658 1 0 0 "CHK_FIN\n/40/" +S 237 225 200704 ELLIPSE "States" | 117061,148658 6500 6500 +C 236 235 0 TEXT "Conditions" | 106765,177192 1 0 0 "rxDataRdy == 1'b1" +W 235 225 0 232 237 BEZIER "Transitions" | 104393,177362 111371,166048 105811,165038 113530,154113 +W 234 225 0 240 268 BEZIER "Transitions" | 62534,255719 71612,251112 81165,266598 90243,261991 +L 233 232 0 TEXT "State Labels" | 101011,182910 1 0 0 "WT_FIN1\n/41/" +S 232 225 204800 ELLIPSE "States" | 101011,182910 6500 6500 +H 225 224 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 224 6 57348 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116398,45340 6500 6500 +I 496 0 2 Builtin OutPort | 69306,243719 "" "" +L 497 496 0 TEXT "Labels" | 75306,243719 1 0 0 "sendCmdReq" +I 498 0 2 Builtin InPort | 71520,238553 "" "" +L 499 498 0 TEXT "Labels" | 77520,238553 1 0 0 "sendCmdRdy" +I 500 0 130 Builtin InPort | 71328,234058 "" "" +L 501 500 0 TEXT "Labels" | 77328,234058 1 0 0 "respByte[7:0]" +I 502 0 2 Builtin InPort | 150168,237862 "" "" +L 503 502 0 TEXT "Labels" | 156168,237862 1 0 0 "rxDataRdy" +I 504 0 2 Builtin InPort | 117135,232948 "" "" +L 505 504 0 TEXT "Labels" | 123135,232948 1 0 0 "txDataFull" +I 506 0 2 Builtin OutPort | 114678,237589 "" "" +L 507 506 0 TEXT "Labels" | 120678,237589 1 0 0 "txDataWen" +I 508 0 130 Builtin InPort | 149895,241957 "" "" +L 509 508 0 TEXT "Labels" | 155895,241957 1 0 0 "rxDataIn[7:0]" +I 510 0 130 Builtin OutPort | 114678,242230 "" "" +L 511 510 0 TEXT "Labels" | 120678,242230 1 0 0 "txDataOut[7:0]" +L 527 528 0 TEXT "Labels" | 190950,242120 1 0 0 "rxFifoData[7:0]" +I 526 0 2 Builtin OutPort | 185220,246980 "" "" +L 525 526 0 TEXT "Labels" | 191220,246980 1 0 0 "rxFifoWen" +I 524 0 130 Builtin InPort | 187380,252110 "" "" +L 523 524 0 TEXT "Labels" | 193380,252110 1 0 0 "txFifoData[7:0]" +I 522 0 2 Builtin OutPort | 184950,256970 "" "" +L 521 522 0 TEXT "Labels" | 190950,256970 1 0 0 "txFifoRen" +W 248 225 2 237 251 BEZIER "Transitions" | 121126,143587 165099,138575 140782,115097 127863,106694 +A 249 248 16 TEXT "Actions" | 144590,131826 1 0 0 "writeError <= `WRITE_BUSY_ERROR;" +C 250 248 0 TEXT "Conditions" | 128858,147492 1 0 0 "timeOutCnt == `TWO_FIFTY_MS" +C 255 254 0 TEXT "Conditions" | 114470,200483 1 0 0 "delCnt1 == `MAX_8_BIT" +W 254 225 1 243 232 BEZIER "Transitions" | 151179,193271 142375,193953 126550,195706 120373,194853\ + 114197,194000 109072,189975 105523,187587 +W 253 225 0 241 243 BEZIER "Transitions" | 101358,228597 101904,225390 102458,220616 103686,217545\ + 104915,214475 108737,208604 114128,207171 119520,205738\ + 137266,205875 142862,205499 148458,205124 153100,203486\ + 154430,202496 155761,201507 156185,199858 156526,198698 +A 252 241 4 TEXT "Actions" | 116837,251309 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\ndelCnt1 <= 8'h00;" +I 251 225 0 Builtin Exit | 130441,106568 +C 247 239 0 TEXT "Conditions" | 32326,147044 1 0 0 "locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS" +W 245 225 3 237 251 BEZIER "Transitions" | 118568,142338 109376,129519 116628,112302 127863,106701 +L 244 243 0 TEXT "State Labels" | 157604,192293 1 0 0 "DEL1\n/42/" +S 243 225 208896 ELLIPSE "States" | 157604,192293 6500 6500 +L 242 241 0 TEXT "State Labels" | 101325,235047 1 0 0 "SEND_CMD1\n/43/" +S 241 225 212992 ELLIPSE "States" | 101325,235047 6500 6500 +I 240 225 0 Builtin Entry | 58349,255719 +I 512 0 2 Builtin OutPort | 147984,233494 "" "" +L 513 512 0 TEXT "Labels" | 153984,233494 1 0 0 "rxDataRdyClr" +L 514 515 0 TEXT "Labels" | 77500,229855 1 0 0 "respTout" +I 515 0 2 Builtin InPort | 71500,229855 "" "" +A 516 82 4 TEXT "Actions" | 160072,222273 1 0 0 "readWriteSDBlockRdy <= 1'b0;\nspiCS_n <= 1'b1;\nreadError <= 1'b0;\nwriteError <= 1'b0;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 8'h00;\ndelCnt2 <= 8'h00;\nreadError <= `READ_NO_ERROR;\nwriteError <= `WRITE_NO_ERROR;\ntxFifoRen <= 1'b0;\nrxFifoWen <= 1'b0;\nrxFifoData <= 8'h00;\ntimeOutCnt <= 12'h000;\nlocRespByte <= 8'h00;" +L 517 518 0 TEXT "Labels" | 120142,254523 1 0 0 "readError[1:0]" +I 518 0 130 Builtin OutPort | 114142,254523 "" "" +L 519 520 0 TEXT "Labels" | 119971,249897 1 0 0 "writeError[1:0]" +I 520 0 130 Builtin OutPort | 113971,249897 "" "" +L 543 544 0 TEXT "Labels" | 164114,261928 1 0 0 "delCnt1[7:0]" +C 542 541 0 TEXT "Conditions" | 31702,154694 1 0 0 "delCnt2 == 8'hff" +W 541 338 0 537 365 BEZIER "Transitions" | 45749,147689 44744,152468 35773,163628 34769,167402\ + 33765,171176 35012,179071 36950,181044 38889,183018\ + 44071,182291 47325,182291 +W 539 338 2 365 537 BEZIER "Transitions" | 51640,173745 51294,168275 56598,148666 56246,142125 +A 538 537 4 TEXT "Actions" | 36466,135651 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +S 537 338 225280 ELLIPSE "States" | 49762,142576 6500 6500 +L 536 537 0 TEXT "State Labels" | 49762,142576 1 0 0 "DEL3\n/46/" +C 535 534 0 TEXT "Conditions" | 154260,170964 1 0 0 "delCnt2 == 8'hff" +W 534 225 0 530 243 BEZIER "Transitions" | 179888,172413 174851,172206 165921,171447 162609,173482\ + 159297,175518 158039,181622 156452,185900 +A 533 530 4 TEXT "Actions" | 166680,162960 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +W 531 225 2 243 530 BEZIER "Transitions" | 163308,189179 168294,185855 176215,180648 181201,177324 +S 530 225 217088 ELLIPSE "States" | 186323,173323 6500 6500 +L 529 530 0 TEXT "State Labels" | 186323,173323 1 0 0 "DEL2\n/44/" +I 528 0 130 Builtin OutPort | 184950,242120 "" "" +A 270 268 4 TEXT "Actions" | 109230,265230 1 0 0 "timeOutCnt <= 12'h000;" +W 269 225 0 268 241 BEZIER "Transitions" | 96982,253102 97927,249120 98637,245290 99582,241308 +S 268 225 221184 ELLIPSE "States" | 96270,259560 6500 6500 +L 267 268 0 TEXT "State Labels" | 96270,259560 1 0 0 "INIT_LOOP\n/45/" +I 264 0 130 Builtin Signal | 161063,266638 "" "" +L 263 264 0 TEXT "Labels" | 164063,266638 1 0 0 "loopCnt[8:0]" +A 259 243 4 TEXT "Actions" | 166374,212237 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ndelCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" +END Index: spimaster/trunk/Aldec/design0/src/initSD.asf =================================================================== --- spimaster/trunk/Aldec/design0/src/initSD.asf (nonexistent) +++ spimaster/trunk/Aldec/design0/src/initSD.asf (revision 4) @@ -0,0 +1,226 @@ +VERSION=1.15 +HEADER +FILE="initSD.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="initSD" +FRAMES=ON +FREEOID=430 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// initSD.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// When SDInitReq asserted, initialise SD card\n//// \n//// \n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 141 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 168 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +INSTHEADER 322 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +S 286 169 24576 ELLIPSE "States" | 105808,239248 6500 6500 +L 285 286 0 TEXT "State Labels" | 105808,239248 1 0 0 "SEND_CMD\n/4/" +I 284 169 0 Builtin Entry | 62832,259920 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: initSD" +A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603 +L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "initSDSt" +W 303 169 1 300 286 BEZIER "Transitions" | 115053,153196 98913,155348 68551,158239 60111,167048\ + 51672,175858 50191,206794 54058,217015 57925,227237\ + 74873,237191 81496,239444 88120,241697 94643,240900\ + 99417,240430 +S 300 169 36864 ELLIPSE "States" | 121544,152859 6500 6500 +L 299 300 0 TEXT "State Labels" | 121544,152859 1 0 0 "CHK_FIN\n/7/" +C 298 297 0 TEXT "Conditions" | 111248,181393 1 0 0 "sendCmdRdy == 1'b1" +W 297 169 0 292 300 BEZIER "Transitions" | 108876,181563 115854,170249 110294,169239 118013,158314 +W 295 169 0 284 286 BEZIER "Transitions" | 66490,259920 75568,255313 91313,247447 100391,242840 +W 294 169 0 290 292 BEZIER "Transitions" | 105542,205568 105407,201842 105322,197326 105187,193600 +W 293 169 0 286 290 BEZIER "Transitions" | 105594,232759 105594,228491 105652,222790 105652,218522 +S 292 169 32768 ELLIPSE "States" | 105494,187111 6500 6500 +L 291 292 0 TEXT "State Labels" | 105494,187111 1 0 0 "WT_FIN\n/6/" +S 290 169 28672 ELLIPSE "States" | 106036,212043 6500 6500 +L 289 290 0 TEXT "State Labels" | 106036,212043 1 0 0 "DEL\n/5/" +A 288 286 4 TEXT "Actions" | 121320,255510 1 0 0 "cmdByte <= 8'h40; //CMD0\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h95;\nsendCmdReq <= 1'b1;\nloopCnt <= loopCnt + 1'b1;\nspiCS_n <= 1'b0;" +I 319 169 0 Builtin Exit | 136284,112401 +I 318 169 0 Builtin Link | 148672,125363 +L 317 318 0 TEXT "Labels" | 154672,125363 1 0 0 "WT_INIT_REQ" +C 316 310 0 TEXT "Conditions" | 131001,148174 1 0 0 "respTout == 1'b1 || respByte != 8'h01" +A 313 312 16 TEXT "Actions" | 106611,116426 1 0 0 "loopCnt <= 8'h00;" +W 312 6 0 141 168 BEZIER "Transitions" | 111141,120168 111512,114462 111940,106474 111681,102457 +A 311 310 16 TEXT "Actions" | 132446,138965 1 0 0 "initError <= `INIT_CMD0_ERROR;" +W 310 169 2 300 318 BEZIER "Transitions" | 125449,147664 131098,140939 143023,130088 148672,123363 +C 304 303 0 TEXT "Conditions" | 36809,151245 1 0 0 "(respTout == 1'b1 || respByte != 8'h01) && loopCnt != 8'hff" +L 335 334 0 TEXT "State Labels" | 100580,187111 1 0 0 "WT_FIN\n/8/" +S 334 349 45056 ELLIPSE "States" | 100580,187111 6500 6500 +W 331 349 0 325 323 BEZIER "Transitions" | 61576,259920 70654,255313 86399,247447 95477,242840 +W 330 349 0 334 327 BEZIER "Transitions" | 103962,181563 110940,170249 105380,169239 113099,158314 +C 329 330 0 TEXT "Conditions" | 106334,181393 1 0 0 "sendCmdRdy == 1'b1" +L 328 327 0 TEXT "State Labels" | 116630,152859 1 0 0 "CHK_FIN\n/9/" +S 327 349 49152 ELLIPSE "States" | 116630,152859 6500 6500 +W 326 349 1 327 323 BEZIER "Transitions" | 110139,153196 93999,155348 63637,158239 55197,167048\ + 46758,175858 45277,206794 49144,217015 53011,227237\ + 69959,237191 76582,239444 83206,241697 89729,240900\ + 94503,240430 +I 325 349 0 Builtin Entry | 57918,259920 +L 324 323 0 TEXT "State Labels" | 100894,239248 1 0 0 "SEND_CMD\n/10/" +S 323 349 53248 ELLIPSE "States" | 100894,239248 6500 6500 +S 322 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112467,68151 6500 6500 +A 321 297 16 TEXT "Actions" | 108930,174030 1 0 0 "spiCS_n <= 1'b1;" +W 320 169 3 300 319 BEZIER "Transitions" | 123051,146539 126378,137861 129956,121079 133283,112401 +S 351 349 57344 ELLIPSE "States" | 157173,196494 6500 6500 +L 350 351 0 TEXT "State Labels" | 157173,196494 1 0 0 "DEL1\n/11/" +L 348 322 0 TEXT "State Labels" | 112467,68151 1 0 0 "INIT" +W 347 349 3 327 339 BEZIER "Transitions" | 118137,146539 108945,133720 116197,116503 127432,110902 +A 346 330 16 TEXT "Actions" | 104016,174030 1 0 0 "spiCS_n <= 1'b1;" +C 345 326 0 TEXT "Conditions" | 31895,151245 1 0 0 "(respTout == 1'b1 || respByte != 8'h00) && loopCnt != 8'hff" +W 344 349 2 327 339 BEZIER "Transitions" | 120695,147788 164668,142776 140351,119298 127432,110895 +A 343 344 16 TEXT "Actions" | 144159,136027 1 0 0 "initError <= `INIT_CMD1_ERROR;" +C 342 344 0 TEXT "Conditions" | 128427,151693 1 0 0 "respTout == 1'b1 || respByte != 8'h00" +I 339 349 0 Builtin Exit | 130010,110769 +A 338 323 4 TEXT "Actions" | 116406,255510 1 0 0 "cmdByte <= 8'h41; //CMD1\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;\nloopCnt <= loopCnt + 1'b1;\nspiCS_n <= 1'b0;\ndelCnt1 <= 10'h000;" +H 349 322 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 74 0 2 Builtin InPort | 195700,267632 "" "" +L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +I 366 0 130 Builtin OutPort | 86503,262498 "" "" +L 365 366 0 TEXT "Labels" | 92503,262498 1 0 0 "cmdByte[7:0]" +L 367 368 0 TEXT "Labels" | 92258,258018 1 0 0 "dataByte1[7:0]" +W 363 6 0 322 102 BEZIER "Transitions" | 107085,71794 94246,83115 68667,103061 63765,115078\ + 58864,127095 64936,152522 71324,159511 77712,166500\ + 95428,168622 105168,169887 +W 362 6 0 168 322 BEZIER "Transitions" | 111422,89512 111675,84705 111722,79427 111975,74620 +W 361 349 0 323 351 BEZIER "Transitions" | 100927,232798 101473,229591 102027,224817 103255,221746\ + 104484,218676 108306,212805 113697,211372 119089,209939\ + 136835,210076 142431,209700 148027,209325 152669,207687\ + 153999,206697 155330,205708 155754,204059 156095,202899 +C 360 359 0 TEXT "Conditions" | 114039,204684 1 0 0 "delCnt1 == `TWO_MS" +W 359 349 1 351 334 BEZIER "Transitions" | 150748,197472 141944,198154 126119,199907 119942,199054\ + 113766,198201 108641,194176 105092,191788 +C 358 357 0 TEXT "Conditions" | 157694,164664 1 0 0 "delCnt2 == 8'hff" +W 357 349 0 353 351 BEZIER "Transitions" | 163535,169133 171628,167736 181061,162846 187169,163119\ + 193277,163392 202696,170901 204880,177350 207064,183799\ + 206381,202091 201331,206561 196281,211032 176760,210621\ + 171096,209359 165432,208097 162592,204050 161023,201730 +W 356 349 2 351 353 BEZIER "Transitions" | 158302,190095 158438,187775 158562,182275 158679,179771 +A 355 351 4 TEXT "Actions" | 166182,199224 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;\nsendCmdReq <= 1'b0;" +A 354 353 4 TEXT "Actions" | 166728,176565 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +S 353 349 61440 ELLIPSE "States" | 158538,173289 6500 6500 +L 352 353 0 TEXT "State Labels" | 158538,173289 1 0 0 "DEL2\n/12/" +L 95 96 0 TEXT "Labels" | 155940,273023 1 0 0 "SDInitRdy" +I 368 0 130 Builtin OutPort | 86258,258018 "" "" +I 371 0 130 Builtin OutPort | 86455,252808 "" "" +L 372 371 0 TEXT "Labels" | 92455,252808 1 0 0 "dataByte2[7:0]" +I 373 0 130 Builtin OutPort | 86702,248115 "" "" +L 374 373 0 TEXT "Labels" | 92702,248115 1 0 0 "dataByte3[7:0]" +I 375 0 130 Builtin OutPort | 86702,243422 "" "" +L 376 375 0 TEXT "Labels" | 92702,243422 1 0 0 "dataByte4[7:0]" +L 383 384 0 TEXT "Labels" | 43326,249254 1 0 0 "delCnt1[9:0]" +I 382 0 2 Builtin InPort | 89010,228836 "" "" +L 381 382 0 TEXT "Labels" | 95010,228836 1 0 0 "sendCmdRdy" +I 380 0 2 Builtin OutPort | 86796,234002 "" "" +L 379 380 0 TEXT "Labels" | 92796,234002 1 0 0 "sendCmdReq" +I 378 0 130 Builtin OutPort | 86578,238482 "" "" +L 377 378 0 TEXT "Labels" | 92578,238482 1 0 0 "checkSumByte[7:0]" +I 111 0 2 Builtin OutPort | 142296,249682 "" "" +L 110 109 0 TEXT "Labels" | 150753,245041 1 0 0 "txDataFull" +I 109 0 2 Builtin InPort | 144753,245041 "" "" +W 106 6 0 102 141 BEZIER "Transitions" | 111478,164116 111546,159885 111249,139164 110939,132984 +W 105 6 0 100 102 BEZIER "Transitions" | 111805,187037 111601,183898 111568,180194 111364,177055 +S 102 6 4096 ELLIPSE "States" | 111630,170580 6500 6500 +L 101 102 0 TEXT "State Labels" | 111630,170580 1 0 0 "WT_INIT_REQ\n/1/" +S 100 6 0 ELLIPSE "States" | 112176,193512 6500 6500 +L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/0/" +I 96 0 2 Builtin OutPort | 149940,273023 "" "" +L 97 98 0 TEXT "Labels" | 158664,268382 1 0 0 "SDInitReq" +I 98 0 2 Builtin InPort | 152664,268382 "" "" +I 399 0 130 Builtin InPort | 179837,253714 "" "" +L 398 399 0 TEXT "Labels" | 185837,253714 1 0 0 "spiClkDelayIn[7:0]" +I 397 0 130 Builtin OutPort | 150335,263636 "" "" +L 396 397 0 TEXT "Labels" | 156335,263636 1 0 0 "initError[1:0]" +I 395 0 2 Builtin OutPort | 142620,234260 "" "" +L 394 395 0 TEXT "Labels" | 148620,234260 1 0 0 "spiCS_n" +I 391 0 130 Builtin InPort | 88818,224341 "" "" +L 390 391 0 TEXT "Labels" | 94818,224341 1 0 0 "respByte[7:0]" +C 389 388 0 TEXT "Conditions" | 64133,197548 1 0 0 "rst == 1'b1" +W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019 +I 387 6 0 Builtin Reset | 49555,202550 +I 386 0 130 Builtin Signal | 40326,244334 "" "" +L 385 386 0 TEXT "Labels" | 43326,244334 1 0 0 "delCnt2[7:0]" +I 384 0 130 Builtin Signal | 40326,249254 "" "" +C 123 106 0 TEXT "Conditions" | 112795,161807 1 0 0 "SDInitReq == 1'b1" +L 118 117 0 TEXT "Labels" | 148296,254323 1 0 0 "txDataOut[7:0]" +I 117 0 130 Builtin OutPort | 142296,254323 "" "" +L 112 111 0 TEXT "Labels" | 148296,249682 1 0 0 "txDataWen" +L 392 393 0 TEXT "Labels" | 94804,219488 1 0 0 "respTout" +I 393 0 2 Builtin InPort | 88804,219488 "" "" +I 405 0 2 Builtin InPort | 123780,223280 "" "" +L 404 405 0 TEXT "Labels" | 129780,223280 1 0 0 "rxDataRdy" +I 403 0 2 Builtin OutPort | 121620,218480 "" "" +L 402 403 0 TEXT "Labels" | 127620,218480 1 0 0 "rxDataRdyClr" +S 401 142 65536 ELLIPSE "States" | 119702,164354 6500 6500 +L 400 401 0 TEXT "State Labels" | 119702,164354 1 0 0 "WT_DATA_EMPTY\n/13/" +L 135 136 0 TEXT "Labels" | 92903,270215 1 0 0 "spiClkDelayOut[7:0]" +I 136 0 130 Builtin OutPort | 86903,270215 "" "" +A 137 100 4 TEXT "Actions" | 166381,206571 1 0 0 "spiClkDelayOut <= spiClkDelayIn;\nSDInitRdy <= 1'b0;\nspiCS_n <= 1'b1;\ninitError <= `INIT_NO_ERROR;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 10'h000;\ndelCnt2 <= 8'h00;\nrxDataRdyClr <= 1'b0;" +A 138 102 4 TEXT "Actions" | 122260,190788 1 0 0 "SDInitRdy <= 1'b1;\nspiClkDelayOut <= spiClkDelayIn;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;" +A 139 106 16 TEXT "Actions" | 102988,155532 1 0 0 "SDInitRdy <= 1'b0;\nloopCnt <= 8'h00;\nspiClkDelayOut <= `SLOW_SPI_CLK;\ninitError <= `INIT_NO_ERROR;" +L 140 141 0 TEXT "State Labels" | 111114,126510 1 0 0 "CLK_SEQ" +S 141 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111114,126510 6500 6500 +H 142 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +A 425 290 4 TEXT "Actions" | 124357,213854 1 0 0 "sendCmdReq <= 1'b0;" +I 421 142 0 Builtin Exit | 134364,140858 +I 145 142 0 Builtin Entry | 63487,251949 +S 149 142 12288 ELLIPSE "States" | 82209,235260 6500 6500 +L 150 149 0 TEXT "State Labels" | 82209,235260 1 0 0 "SEND_FF\n/2/" +S 151 142 16384 ELLIPSE "States" | 83028,207141 6500 6500 +L 152 151 0 TEXT "State Labels" | 83028,207141 1 0 0 "CHK_FIN\n/3/" +W 153 142 0 149 151 BEZIER "Transitions" | 82316,228817 82452,225541 82726,217079 82876,213607 +C 154 153 0 TEXT "Conditions" | 86589,230362 1 0 0 "txDataFull == 1'b0" +A 155 153 16 TEXT "Actions" | 85757,225151 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" +A 156 151 4 TEXT "Actions" | 101046,207687 1 0 0 "txDataWen <= 1'b0;" +L 426 427 0 TEXT "Labels" | 150400,240650 1 0 0 "txDataEmpty" +I 427 0 2 Builtin InPort | 144400,240650 "" "" +W 428 142 0 401 421 BEZIER "Transitions" | 123115,158823 126115,154198 128614,145483 131614,140858 +C 429 428 0 TEXT "Conditions" | 127025,156275 1 0 0 "txDataEmpty == 1'b1" +W 162 142 0 145 149 BEZIER "Transitions" | 67172,251949 70925,248810 74553,243594 78306,240455 +W 164 142 1 151 401 BEZIER "Transitions" | 85234,201030 86934,197154 103559,165433 113217,164792 +C 165 164 0 TEXT "Conditions" | 91028,195541 1 0 0 "loopCnt == `SD_INIT_START_SEQ_LEN" +W 166 142 2 151 149 BEZIER "Transitions" | 76635,205968 69903,206580 58140,206268 54570,210178\ + 51000,214088 50184,228504 53380,232380 56576,236256\ + 69005,235825 75805,236369 +L 167 168 0 TEXT "State Labels" | 111972,95982 1 0 0 "RESET" +S 168 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111972,95982 6500 6500 +H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +L 191 192 0 TEXT "Labels" | 43350,253948 1 0 0 "loopCnt[7:0]" +I 192 0 130 Builtin Signal | 40350,253948 "" "" +END Index: spimaster/trunk/Aldec/design0/src/sendCmd.asf =================================================================== --- spimaster/trunk/Aldec/design0/src/sendCmd.asf (nonexistent) +++ spimaster/trunk/Aldec/design0/src/sendCmd.asf (revision 4) @@ -0,0 +1,231 @@ +VERSION=1.15 +HEADER +FILE="sendCmd.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="sendCmd" +FRAMES=ON +FREEOID=426 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendCmd.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// If sendCmdReq asserted, then send command to \n//// SD card. Command consists of command byte,\n//// 4 data bytes, and a checksum byte. \n//// Waits for response byte from SD card\n//// or times out if no response\n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 168 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +S 287 169 36864 ELLIPSE "States" | 58145,42664 6500 6500 +C 286 284 0 TEXT "Conditions" | 58455,63310 1 0 0 "txDataFull == 1'b0" +A 285 284 16 TEXT "Actions" | 58389,58640 1 0 0 "txDataOut <= dataByte3;\ntxDataWen <= 1'b1;" +W 284 169 0 289 287 BEZIER "Transitions" | 55994,62919 56515,59615 56972,52449 57396,49118 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: sendCmd" +A 5 0 1 TEXT "Actions" | 30400,270465 1 0 0 "-- diagram ACTION\nalways @(sendCmdReq1 or sendCmdReq2 ) begin\n sendCmdReq <= sendCmdReq1 | sendCmdReq2;\nend\n\nalways @(posedge clk) begin\n cmdByte <= cmdByte_1 | cmdByte_2;\n dataByte1 <= dataByte1_1 | dataByte1_2;\n dataByte2 <= dataByte2_1 | dataByte2_2;\n dataByte3 <= dataByte3_1 | dataByte3_2;\n dataByte4 <= dataByte4_1 | dataByte4_2;\n checkSumByte <= checkSumByte_1 | checkSumByte_2;\nend" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,208764 +L 7 6 0 TEXT "Labels" | 33841,199139 1 0 0 "sndCmdSt" +L 298 297 0 TEXT "State Labels" | 119183,117704 1 0 0 "D_BYTE4_ST\n/12/" +S 297 169 49152 ELLIPSE "States" | 119183,117704 6500 6500 +L 296 295 0 TEXT "State Labels" | 121962,90985 1 0 0 "D_BYTE4_FIN\n/11/" +S 295 169 45056 ELLIPSE "States" | 121962,90985 6500 6500 +C 294 292 0 TEXT "Conditions" | 122272,111631 1 0 0 "txDataFull == 1'b0" +A 293 292 16 TEXT "Actions" | 122206,106961 1 0 0 "txDataOut <= dataByte4;\ntxDataWen <= 1'b1;" +W 292 169 0 297 295 BEZIER "Transitions" | 119811,111240 120332,107936 120789,100770 121213,97439 +L 290 289 0 TEXT "State Labels" | 55366,69383 1 0 0 "D_BYTE3_ST\n/10/" +S 289 169 40960 ELLIPSE "States" | 55366,69383 6500 6500 +L 288 287 0 TEXT "State Labels" | 58145,42664 1 0 0 "D_BYTE3_FIN\n/9/" +W 319 169 0 205 247 BEZIER "Transitions" | 63983,140499 60844,135517 56583,126997 53444,122015 +A 318 295 4 TEXT "Actions" | 139150,86599 1 0 0 "txDataWen <= 1'b0;" +A 317 287 4 TEXT "Actions" | 76633,44284 1 0 0 "txDataWen <= 1'b0;" +A 316 225 4 TEXT "Actions" | 71992,91513 1 0 0 "txDataWen <= 1'b0;" +A 315 311 4 TEXT "Actions" | 134912,45978 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 10'h000;" +L 314 313 0 TEXT "State Labels" | 122732,70475 1 0 0 "CS_ST\n/14/" +S 313 169 57344 ELLIPSE "States" | 122732,70475 6500 6500 +L 312 311 0 TEXT "State Labels" | 125511,43756 1 0 0 "CS_FIN\n/13/" +S 311 169 53248 ELLIPSE "States" | 125511,43756 6500 6500 +C 310 308 0 TEXT "Conditions" | 125821,64402 1 0 0 "txDataFull == 1'b0" +A 309 308 16 TEXT "Actions" | 125755,59732 1 0 0 "txDataOut <= checkSumByte;\ntxDataWen <= 1'b1;" +W 308 169 0 313 311 BEZIER "Transitions" | 123360,64011 123881,60707 124338,53541 124762,50210 +W 335 169 0 332 182 BEZIER "Transitions" | 45364,251903 47642,252271 81651,254936 85013,246121 +W 334 169 0 185 332 BEZIER "Transitions" | 41073,269282 40336,265731 39290,259500 38553,255949 +S 332 169 61440 ELLIPSE "States" | 39325,249500 6500 6500 +L 331 332 0 TEXT "State Labels" | 39325,251108 1 0 0 "SEND_FF_ST\n/15/" +I 329 0 2 Builtin Signal | 178213,215725 "" "" +L 328 329 0 TEXT "Labels" | 181213,215725 1 0 0 "sendCmdReq" +L 327 326 0 TEXT "Labels" | 157273,263636 1 0 0 "sendCmdReq2" +I 326 0 2 Builtin InPort | 151273,263636 "" "" +I 325 0 2 Builtin InPort | 151961,268514 "" "" +L 324 325 0 TEXT "Labels" | 157961,268514 1 0 0 "sendCmdReq1" +W 322 169 0 295 313 BEZIER "Transitions" | 122244,84497 122585,81836 122598,79603 122939,76942 +W 321 169 0 287 297 BEZIER "Transitions" | 63804,39468 72608,38035 85574,34251 91921,34114\ + 98268,33978 106049,36299 107653,41212 109257,46126\ + 107891,63463 106287,73597 104684,83732 99633,106938\ + 99837,114069 100042,121201 105913,126526 108335,126867\ + 110758,127208 113121,124683 115032,122704 +W 320 169 0 225 289 BEZIER "Transitions" | 54252,82625 54525,80100 54595,78388 54868,75863 +A 351 260 16 TEXT "Actions" | 146029,190376 1 0 0 "respTout <= 1'b1;" +A 338 335 16 TEXT "Actions" | 57237,258852 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1" +C 337 335 0 TEXT "Conditions" | 46128,249292 1 0 0 "txDataFull == 1'b0" +I 74 0 2 Builtin InPort | 195700,267632 "" "" +L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +L 367 366 0 TEXT "Labels" | 118445,251448 1 0 0 "dataByte2_2[7:0]" +I 366 0 130 Builtin InPort | 112445,251448 "" "" +L 365 364 0 TEXT "Labels" | 118188,256588 1 0 0 "dataByte2_1[7:0]" +I 364 0 130 Builtin InPort | 112188,256588 "" "" +L 363 362 0 TEXT "Labels" | 118445,261214 1 0 0 "dataByte1_2[7:0]" +I 362 0 130 Builtin InPort | 112445,261214 "" "" +I 361 0 130 Builtin InPort | 112448,265583 "" "" +L 360 361 0 TEXT "Labels" | 118448,265583 1 0 0 "dataByte1_1[7:0]" +A 358 253 16 TEXT "Actions" | 138128,223118 1 0 0 "respByte <= rxDataIn;" +C 357 356 0 TEXT "Conditions" | 73122,198009 1 0 0 "rst == 1'b1" +W 356 6 0 355 100 BEZIER "Transitions" | 60594,200141 72339,199739 94500,197787 106245,197385 +I 355 6 0 Builtin Reset | 60594,200141 +W 354 6 0 168 102 BEZIER "Transitions" | 105630,145031 98556,147323 85638,151108 82264,155037\ + 78891,158967 79547,170103 83247,173083 86948,176063\ + 98835,174994 105909,175387 +L 95 96 0 TEXT "Labels" | 155940,273023 1 0 0 "sendCmdRdy" +I 383 0 130 Builtin Signal | 177941,226776 "" "" +L 382 383 0 TEXT "Labels" | 180941,226776 1 0 0 "dataByte4[7:0]" +I 381 0 130 Builtin Signal | 178198,220865 "" "" +L 380 381 0 TEXT "Labels" | 181198,220865 1 0 0 "checkSumByte[7:0]" +L 379 378 0 TEXT "Labels" | 117931,223949 1 0 0 "checkSumByte_2[7:0]" +I 378 0 130 Builtin InPort | 111931,223949 "" "" +L 377 376 0 TEXT "Labels" | 117931,228318 1 0 0 "checkSumByte_1[7:0]" +I 376 0 130 Builtin InPort | 111931,228318 "" "" +L 375 374 0 TEXT "Labels" | 118188,232687 1 0 0 "dataByte4_2[7:0]" +I 374 0 130 Builtin InPort | 112188,232687 "" "" +L 373 372 0 TEXT "Labels" | 118188,237313 1 0 0 "dataByte4_1[7:0]" +I 372 0 130 Builtin InPort | 112188,237313 "" "" +L 371 370 0 TEXT "Labels" | 118188,241939 1 0 0 "dataByte3_2[7:0]" +I 370 0 130 Builtin InPort | 112188,241939 "" "" +L 369 368 0 TEXT "Labels" | 118188,246822 1 0 0 "dataByte3_1[7:0]" +I 368 0 130 Builtin InPort | 112188,246822 "" "" +I 111 0 2 Builtin OutPort | 150520,249425 "" "" +L 110 109 0 TEXT "Labels" | 158977,244784 1 0 0 "txDataFull" +I 109 0 2 Builtin InPort | 152977,244784 "" "" +L 108 107 0 TEXT "Labels" | 192010,249698 1 0 0 "rxDataRdy" +I 107 0 2 Builtin InPort | 186010,249698 "" "" +W 106 6 0 102 168 BEZIER "Transitions" | 112025,167024 112028,164120 111877,156052 111880,149910 +W 105 6 0 100 102 BEZIER "Transitions" | 112303,189956 112099,186817 112066,183113 111862,179974 +S 102 6 65536 ELLIPSE "States" | 112128,173499 6500 6500 +L 101 102 0 TEXT "State Labels" | 112128,173499 1 0 0 "WT_CMD\n/17/" +S 100 6 69632 ELLIPSE "States" | 112674,196431 6500 6500 +L 99 100 0 TEXT "State Labels" | 112674,196431 1 0 0 "ST_S_CMD\n/18/" +I 96 0 2 Builtin OutPort | 149940,273023 "" "" +I 391 0 130 Builtin OutPort | 109748,219216 "" "" +L 390 391 0 TEXT "Labels" | 115748,219216 1 0 0 "respByte[7:0]" +L 389 388 0 TEXT "Labels" | 181327,240140 1 0 0 "dataByte1[7:0]" +I 388 0 130 Builtin Signal | 178327,240140 "" "" +L 387 386 0 TEXT "Labels" | 181327,235771 1 0 0 "dataByte2[7:0]" +I 386 0 130 Builtin Signal | 178327,235771 "" "" +L 385 384 0 TEXT "Labels" | 181070,231402 1 0 0 "dataByte3[7:0]" +I 384 0 130 Builtin Signal | 178070,231402 "" "" +C 123 106 0 TEXT "Conditions" | 113758,166364 1 0 0 "sendCmdReq == 1'b1" +L 122 121 0 TEXT "Labels" | 189826,245330 1 0 0 "rxDataRdyClr" +I 121 0 2 Builtin OutPort | 183826,245330 "" "" +L 118 117 0 TEXT "Labels" | 156520,254066 1 0 0 "txDataOut[7:0]" +I 117 0 130 Builtin OutPort | 150520,254066 "" "" +L 116 115 0 TEXT "Labels" | 191737,253793 1 0 0 "rxDataIn[7:0]" +I 115 0 130 Builtin InPort | 185737,253793 "" "" +L 112 111 0 TEXT "Labels" | 156520,249425 1 0 0 "txDataWen" +L 392 393 0 TEXT "Labels" | 155040,236450 1 0 0 "cmdByte_1[7:0]" +I 393 0 130 Builtin InPort | 149040,236450 "" "" +L 394 395 0 TEXT "Labels" | 155040,232130 1 0 0 "cmdByte_2[7:0]" +I 395 0 130 Builtin InPort | 149040,232130 "" "" +L 396 397 0 TEXT "Labels" | 115350,214850 1 0 0 "respTout" +I 397 0 2 Builtin OutPort | 109350,214850 "" "" +L 398 399 0 TEXT "Labels" | 156083,221028 1 0 0 "cmdByte[7:0]" +I 399 0 130 Builtin Signal | 153083,221028 "" "" +A 137 100 4 TEXT "Actions" | 132312,205914 1 0 0 "sendCmdRdy <= 1'b0;\ntxDataWen <= 1'b0;\ntxDataOut <= 8'h00;\nrxDataRdyClr <= 1'b0;\nrespByte <= 8'h00;\nrespTout <= 1'b0;\ntimeOutCnt <= 10'h000;" +A 138 102 4 TEXT "Actions" | 124218,176348 1 0 0 "sendCmdRdy <= 1'b1;" +A 139 106 16 TEXT "Actions" | 108893,161005 1 0 0 "sendCmdRdy <= 1'b0;\nrespTout <= 1'b0;" +L 400 401 0 TEXT "Labels" | 156156,216020 1 0 0 "timeOutCnt[9:0]" +I 401 0 130 Builtin Signal | 153156,216020 "" "" +L 407 408 0 TEXT "Labels" | 158650,240900 1 0 0 "txDataEmpty" +I 408 0 2 Builtin InPort | 152650,240900 "" "" +A 412 410 16 TEXT "Actions" | 187604,127904 1 0 0 "" +C 411 410 0 TEXT "Conditions" | 176525,34775 1 0 0 "txDataEmpty == 1'b1" +W 410 169 0 311 234 BEZIER "Transitions" | 129680,38771 133617,37459 138963,34462 145962,34024\ + 152962,33587 173088,34463 180556,35962 188025,37462\ + 197775,42588 199431,55306 201088,68025 197962,113775\ + 186681,128962 175400,144150 133400,159150 122119,165962\ + 110838,172775 107712,185025 107774,191306 107837,197587\ + 111213,210463 112150,219431 113087,228400 113463,251400\ + 114962,258243 116462,265087 122088,269463 125056,270025\ + 128025,270588 133111,267776 136236,266714 +L 420 421 0 TEXT "State Labels" | 197224,232320 1 0 0 "DEL\n/19/" +S 421 169 77824 ELLIPSE "States" | 197224,232320 6500 6500 +W 422 169 0 234 421 BEZIER "Transitions" | 147223,260243 159499,254229 180037,242591 192313,236577 +A 423 422 16 TEXT "Actions" | 153948,265428 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\ntimeOutCnt <= timeOutCnt + 1'b1;\nrxDataRdyClr <= 1'b1;" +W 424 169 0 421 237 BEZIER "Transitions" | 190754,232933 178974,233801 160757,232683 148977,233551 +A 425 424 16 TEXT "Actions" | 157420,238644 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" +L 167 168 0 TEXT "State Labels" | 111928,143426 1 0 0 "CMD" +S 168 6 73732 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111928,143426 6500 6500 +H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28668,29070 213168,277070 +S 176 169 65536 ELLIPSE "States" | 60614,226551 6500 6500 +A 177 176 4 TEXT "Actions" | 78632,227097 1 0 0 "txDataWen <= 1'b0;" +W 178 169 0 182 176 BEZIER "Transitions" | 85317,242783 68957,244509 60312,236489 60462,233017 +L 181 176 0 TEXT "State Labels" | 60614,226551 1 0 0 "CMD_BYTE_ST\n/16/" +S 182 169 8192 ELLIPSE "States" | 91419,245022 6500 6500 +L 183 182 0 TEXT "State Labels" | 91419,245558 1 0 0 "SEND_FF_FIN\n/2/" +I 184 169 0 Builtin Exit | 133914,177514 +I 185 169 0 Builtin Entry | 41073,271359 +L 193 194 0 TEXT "State Labels" | 61318,198350 1 0 0 "CMD_BYTE_FIN\n/3/" +S 194 169 12288 ELLIPSE "States" | 61318,198350 6500 6500 +W 197 169 0 176 194 BEZIER "Transitions" | 60038,220079 60241,216895 60646,208095 60689,204810 +C 200 197 0 TEXT "Conditions" | 62427,219576 1 0 0 "txDataFull == 1'b0" +A 201 197 16 TEXT "Actions" | 62131,214610 1 0 0 "txDataOut <= cmdByte;\ntxDataWen <= 1'b1;" +W 202 169 0 242 205 BEZIER "Transitions" | 65275,171028 65478,167844 67531,155583 67557,152187 +A 203 202 16 TEXT "Actions" | 55728,165182 1 0 0 "txDataOut <= dataByte1;\ntxDataWen <= 1'b1;" +C 204 202 0 TEXT "Conditions" | 67553,171135 1 0 0 "txDataFull == 1'b0" +S 205 169 16384 ELLIPSE "States" | 67858,145716 6500 6500 +L 206 205 0 TEXT "State Labels" | 67858,145716 1 0 0 "D_BYTE1_FIN\n/4/" +W 222 169 0 247 225 BEZIER "Transitions" | 52145,109346 52666,106042 53123,98876 53547,95545 +A 223 222 16 TEXT "Actions" | 54540,105067 1 0 0 "txDataOut <= dataByte2;\ntxDataWen <= 1'b1;" +C 224 222 0 TEXT "Conditions" | 54606,109737 1 0 0 "txDataFull == 1'b0" +S 225 169 0 ELLIPSE "States" | 54296,89091 6500 6500 +L 226 225 0 TEXT "State Labels" | 54296,89091 1 0 0 "D_BYTE2_FIN\n/0/" +L 233 234 0 TEXT "State Labels" | 141088,262390 1 0 0 "REQ_RESP_ST\n/5/" +S 234 169 20480 ELLIPSE "States" | 141088,262390 6500 6500 +L 236 237 0 TEXT "State Labels" | 142710,231828 1 0 0 "REQ_RESP_FIN\n/6/" +S 237 169 24576 ELLIPSE "States" | 142710,231828 6500 6500 +L 238 239 0 TEXT "State Labels" | 145411,207811 1 0 0 "CHK_RESP\n/7/" +S 239 169 28672 ELLIPSE "States" | 145411,207811 6500 6500 +C 255 253 0 TEXT "Conditions" | 150412,229033 1 0 0 "rxDataRdy == 1'b1" +W 253 169 0 237 239 BEZIER "Transitions" | 143448,225372 143908,221460 144298,218142 144670,214266 +S 247 169 4096 ELLIPSE "States" | 51517,115810 6500 6500 +L 246 247 0 TEXT "State Labels" | 51517,115810 1 0 0 "D_BYTE2_ST\n/1/" +W 245 169 0 194 242 BEZIER "Transitions" | 62217,191914 62763,188911 63074,186881 63620,183878 +A 243 205 4 TEXT "Actions" | 77303,148032 1 0 0 "txDataWen <= 1'b0;" +S 242 169 32768 ELLIPSE "States" | 64894,177508 6500 6500 +L 241 242 0 TEXT "State Labels" | 64894,177508 1 0 0 "D_BYTE1_ST\n/8/" +A 240 194 4 TEXT "Actions" | 71835,200982 1 0 0 "txDataWen <= 1'b0;" +W 264 169 3 239 234 BEZIER "Transitions" | 140148,211623 134593,217246 123512,226873 120971,232699\ + 118431,238525 119380,250586 121717,254311 124054,258037\ + 130485,259851 134685,261273 +C 263 262 0 TEXT "Conditions" | 112592,197061 1 0 0 "respByte[7] == 1'b0" +W 262 169 2 239 184 BEZIER "Transitions" | 143473,201609 142051,196460 135404,184680 133914,179562 +C 261 260 0 TEXT "Conditions" | 158534,204974 1 0 0 "timeOutCnt == 10'h200" +W 260 169 1 239 184 BEZIER "Transitions" | 151546,205667 157905,203655 172683,180675 136858,177514 +END Index: spimaster/trunk/Aldec/design0/src/spiCtrl.asf =================================================================== --- spimaster/trunk/Aldec/design0/src/spiCtrl.asf (nonexistent) +++ spimaster/trunk/Aldec/design0/src/spiCtrl.asf (revision 4) @@ -0,0 +1,141 @@ +VERSION=1.15 +HEADER +FILE="spiCtrl.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="spiCtrl" +FRAMES=ON +FREEOID=187 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// spiCtrl.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// Controls access to the 3 types of SPI access\n//// Direct SPI access, SD initialisation, and SD block read/write\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 99 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: spiCtrl" +A 5 0 1 TEXT "Actions" | 30673,274317 1 0 0 "-- diagram ACTION" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,232796 +L 7 6 0 TEXT "Labels" | 32486,211363 1 0 0 "spiCtrlSt" +L 8 9 0 TEXT "Labels" | 166432,268121 1 0 0 "spiTransCtrl" +I 9 0 2 Builtin InPort | 160432,268121 "" "" +L 10 11 0 TEXT "Labels" | 164257,264286 1 0 0 "spiTransSts" +I 11 0 2 Builtin OutPort | 158257,264286 "" "" +L 14 15 0 TEXT "Labels" | 166314,272204 1 0 0 "spiTransType[1:0]" +I 15 0 130 Builtin InPort | 160314,272204 "" "" +S 78 6 0 ELLIPSE "States" | 117132,210174 6500 6500 +L 77 78 0 TEXT "State Labels" | 117132,210174 1 0 0 "ST_S_CTRL\n/0/" +C 75 70 0 TEXT "Conditions" | 64251,212776 1 0 0 "rst == 1'b1" +I 74 0 2 Builtin InPort | 195973,268451 "" "" +L 73 74 0 TEXT "Labels" | 201973,268451 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +W 70 6 0 69 78 BEZIER "Transitions" | 55625,209356 74109,218718 92075,219949 111473,213370 +I 69 6 0 Builtin Reset | 54670,208387 +I 92 0 2 Builtin InPort | 99404,245269 "" "" +L 91 92 0 TEXT "Labels" | 105404,245269 1 0 0 "SDInitRdy" +I 90 0 2 Builtin OutPort | 97222,240694 "" "" +L 89 90 0 TEXT "Labels" | 103222,240694 1 0 0 "SDInitReq" +L 95 96 0 TEXT "State Labels" | 61517,181659 1 0 0 "WT_S_CTRL_REQ\n/1/" +S 96 6 4096 ELLIPSE "States" | 61517,181659 6500 6500 +W 97 6 0 78 96 BEZIER "Transitions" | 111858,206376 102862,186278 81827,184985 67818,183250 +L 98 99 0 TEXT "State Labels" | 61244,155715 1 0 0 "J1" +S 99 6 8196 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 61335,155624 3871 3871 +W 100 6 0 96 99 BEZIER "Transitions" | 61562,175246 61630,170469 58461,163807 60148,158618 +C 101 100 0 TEXT "Conditions" | 62422,174791 1 0 0 "spiTransCtrl == `TRANS_START" +A 102 100 16 TEXT "Actions" | 58411,169566 1 0 0 "spiTransSts <= `TRANS_BUSY;" +H 103 99 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 106 103 0 Builtin Entry | 96520,182880 +I 107 103 0 Builtin Exit | 144780,121920 +W 108 103 0 106 107 BEZIER "Transitions" | 100342,182880 105892,175161 136499,129639 142050,121920 +L 110 111 0 TEXT "State Labels" | 138174,125339 1 0 0 "DIR_ACC\n/3/" +S 111 6 16384 ELLIPSE "States" | 138174,125339 6500 6500 +W 113 6 0 99 111 BEZIER "Transitions" | 61166,151770 61234,146806 61130,137919 61640,134485\ + 62150,131051 64054,127243 73166,126223 82278,125203\ + 114404,125351 131676,125215 +C 115 113 0 TEXT "Conditions" | 67726,131051 1 0 0 "spiTransType == `DIRECT_ACCESS" +L 120 121 0 TEXT "Labels" | 46442,250017 1 0 0 "txDataWen" +I 121 0 2 Builtin OutPort | 40442,250017 "" "" +A 123 113 16 TEXT "Actions" | 94110,126699 1 0 0 "txDataWen <= 1'b1;\nspiCS_n <= 1'b0;" +A 125 111 4 TEXT "Actions" | 125118,137851 1 0 0 "txDataWen <= 1'b0;" +L 126 127 0 TEXT "State Labels" | 164014,125067 1 0 0 "WT_FIN1\n/2/" +S 127 6 12288 ELLIPSE "States" | 164014,125067 6500 6500 +W 128 6 0 111 127 BEZIER "Transitions" | 144619,124502 150739,124502 151363,124352 157533,124582 +W 136 6 0 127 96 BEZIER "Transitions" | 162717,131431 160337,140339 156330,157231 149122,163725\ + 141914,170219 117842,178379 106656,180181 95470,181983\ + 78345,181829 68009,181353 +C 137 136 0 TEXT "Conditions" | 156126,140571 1 0 0 "rxDataRdy == 1'b1" +A 138 136 16 TEXT "Actions" | 144158,151179 1 0 0 "rxDataRdyClr <= 1'b1;\nspiCS_n <= 1'b1;" +A 139 96 4 TEXT "Actions" | 42430,197963 1 0 0 "rxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;" +L 140 141 0 TEXT "State Labels" | 138990,98683 1 0 0 "INIT\n/4/" +S 141 6 20480 ELLIPSE "States" | 138990,98683 6500 6500 +W 142 6 0 99 141 BEZIER "Transitions" | 60786,151798 60378,142958 58886,126563 58818,120307\ + 58750,114051 59294,106707 60280,104225 61266,101743\ + 64666,99159 74118,98581 83570,98003 115288,98421\ + 132492,98557 +C 144 142 0 TEXT "Conditions" | 66910,103851 1 0 0 "spiTransType == `INIT_SD" +A 146 142 16 TEXT "Actions" | 93022,99499 1 0 0 "SDInitReq <= 1'b1;" +L 147 148 0 TEXT "State Labels" | 163742,99499 1 0 0 "WT_FIN2\n/5/" +S 148 6 24576 ELLIPSE "States" | 163742,99499 6500 6500 +W 149 6 0 141 148 BEZIER "Transitions" | 145474,99128 150302,99196 152415,99360 157243,99428 +A 150 141 4 TEXT "Actions" | 122126,110651 1 0 0 "SDInitReq <= 1'b0;" +W 151 6 0 148 96 BEZIER "Transitions" | 168589,103829 172805,107705 180470,114663 182272,121531\ + 184074,128399 182850,148119 177444,156007 172038,163895\ + 151638,175727 141812,179059 131986,182391 113082,183887\ + 103562,183887 94042,183887 77595,182762 68007,182014 +C 152 151 0 TEXT "Conditions" | 162382,115003 1 0 0 "SDInitRdy == 1'b1" +L 153 154 0 TEXT "State Labels" | 139806,74203 1 0 0 "RW\n/6/" +S 154 6 28672 ELLIPSE "States" | 139806,74203 6500 6500 +L 155 156 0 TEXT "State Labels" | 165374,73931 1 0 0 "WT_FIN3\n/7/" +S 156 6 32768 ELLIPSE "States" | 165374,73931 6500 6500 +W 161 6 0 99 154 BEZIER "Transitions" | 60982,151777 60302,133009 58070,97323 58546,87327\ + 59022,77331 62286,74883 71942,74271 81598,73659\ + 115628,74049 133308,74049 +W 162 6 0 99 154 BEZIER "Transitions" | 61169,151767 60217,127151 57526,79507 57832,66587\ + 58138,53667 62998,56357 73205,49463 83413,42570\ + 122689,61354 133487,72683 +W 163 6 0 154 156 BEZIER "Transitions" | 146246,75076 150598,74736 154569,75047 158921,74707 +C 165 161 0 TEXT "Conditions" | 65006,80459 1 0 0 "spiTransType == `RW_WRITE_SD_BLOCK" +C 166 162 0 TEXT "Conditions" | 61742,61486 1 0 0 "spiTransType == `RW_READ_SD_BLOCK" +A 167 161 16 TEXT "Actions" | 64462,75019 1 0 0 "readWriteSDBlockReq <= `WRITE_SD_BLOCK;" +A 168 162 16 TEXT "Actions" | 60862,54842 1 0 0 "readWriteSDBlockReq <= `READ_SD_BLOCK;" +A 169 154 4 TEXT "Actions" | 103358,87803 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;" +W 170 6 0 156 96 BEZIER "Transitions" | 171013,77161 178425,82737 192778,92291 196144,105313\ + 199510,118335 198150,159271 192336,170967 186522,182663\ + 164626,188511 153678,189531 142730,190551 120834,188783\ + 109886,187661 98938,186539 78902,183914 67954,182554 +C 171 170 0 TEXT "Conditions" | 168638,86715 1 0 0 "readWriteSDBlockRdy == 1'b1" +L 172 173 0 TEXT "Labels" | 46441,240515 1 0 0 "rxDataRdyClr" +I 173 0 2 Builtin OutPort | 40441,240515 "" "" +L 176 177 0 TEXT "Labels" | 133432,244833 1 0 0 "readWriteSDBlockReq[1:0]" +I 177 0 130 Builtin OutPort | 127432,244833 "" "" +L 178 179 0 TEXT "Labels" | 48477,245479 1 0 0 "rxDataRdy" +I 179 0 2 Builtin InPort | 42477,245479 "" "" +L 182 183 0 TEXT "Labels" | 135468,240330 1 0 0 "readWriteSDBlockRdy" +I 183 0 2 Builtin InPort | 129468,240330 "" "" +A 184 78 4 TEXT "Actions" | 131510,229116 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;\ntxDataWen <= 1'b0;\nSDInitReq <= 1'b0;\nrxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;\nspiCS_n <= 1'b1;" +L 185 186 0 TEXT "Labels" | 165711,256531 1 0 0 "spiCS_n" +I 186 0 2 Builtin OutPort | 159711,256531 "" "" +END Index: spimaster/trunk/Aldec/design0/fsm.set =================================================================== --- spimaster/trunk/Aldec/design0/fsm.set (nonexistent) +++ spimaster/trunk/Aldec/design0/fsm.set (revision 4) @@ -0,0 +1,5 @@ +FSMSET_CUTHEADER=1 +FSMSET_GENCOMMENTS=1 +FSMSET_USEDEFINE=1 +FSMSET_OMITGENNULL=0 +FSMSET_ENABLEPARSING=1 Index: spimaster/trunk/model/wb_master_model.v =================================================================== --- spimaster/trunk/model/wb_master_model.v (nonexistent) +++ spimaster/trunk/model/wb_master_model.v (revision 4) @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_master_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/wb_master_model.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + + parameter dwidth = 32; + parameter awidth = 32; + + input clk, rst; + output [awidth -1:0] adr; + input [dwidth -1:0] din; + output [dwidth -1:0] dout; + output cyc, stb; + output we; + output [dwidth/8 -1:0] sel; + input ack, err, rty; + + // Internal signals + reg [awidth -1:0] adr; + reg [dwidth -1:0] dout; + reg cyc, stb; + reg we; + reg [dwidth/8 -1:0] sel; + + reg [dwidth -1:0] q; + + // Memory Logic + initial + begin + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + end + + // Wishbone write cycle + task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end + endtask + + // Wishbone read cycle + task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end + endtask + + // Wishbone compare cycle (read data from location and compare with expected data) + task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end + endtask + +endmodule + Index: spimaster/trunk/model/sdModel.v =================================================================== --- spimaster/trunk/model/sdModel.v (nonexistent) +++ spimaster/trunk/model/sdModel.v (revision 4) @@ -0,0 +1,99 @@ +`include "timescale.v" + +module sdModel( + spiClk, + spiDataIn, + spiDataOut, + spiCS_n +); +input spiClk; +input spiDataIn; +output spiDataOut; +reg spiDataOut; +input spiCS_n; + +//local wires and regs +reg [7:0] rxByte; +reg [7:0] respByte; +reg [1:0] smSt; +reg [7:0] cnt; + +`define START 2'b00 +`define WAIT_FF 2'b01 +`define WAIT_FF_FIN 2'b10 + +initial +begin + smSt = `START; +end + + +// ------------------------------ txRxByte -------------------------- +task txRxByte; +input [7:0] txData; +output [7:0] rxData; + +integer i; +begin + spiDataOut <= txData[7]; + //@(negedge spiCS_n); + for (i=0;i<=7;i=i+1) begin + @(posedge spiClk); + rxData[0] <= spiDataIn; + rxData = rxData << 1; + @(negedge spiClk); + spiDataOut <= txData[6]; + txData = txData << 1; + end +end +endtask + + +//response state machine +always begin + case (smSt) + `START: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'hff) begin + smSt <= `WAIT_FF; + cnt <= 8'h00; + end + end + `WAIT_FF: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'hff) begin + cnt <= cnt + 1'b1; + if (cnt == 8'h04) begin + txRxByte(respByte, rxByte); + smSt <= `WAIT_FF_FIN; + end + end + else begin + smSt <= `START; + cnt <= 8'h00; + end + end + `WAIT_FF_FIN: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'h04) begin + cnt <= cnt + 1'b1; + if (cnt == 8'hff) begin + txRxByte(respByte, rxByte); + smSt <= `START; + end + end + else + smSt <= `START; + end + endcase +end + +// setRespByte +task setRespByte; + input [7:0] dataByte; + begin + respByte = dataByte; + end +endtask + +endmodule Index: spimaster/trunk/sim/run_icarus.bat =================================================================== --- spimaster/trunk/sim/run_icarus.bat (nonexistent) +++ spimaster/trunk/sim/run_icarus.bat (revision 4) @@ -0,0 +1,2 @@ +vvp testHarness + Index: spimaster/trunk/sim/filelist.icarus =================================================================== --- spimaster/trunk/sim/filelist.icarus (nonexistent) +++ spimaster/trunk/sim/filelist.icarus (revision 4) @@ -0,0 +1,22 @@ +../rtl/spiMaster.v +../rtl/sm_dpMem_dc.v +../rtl/sm_fifoRTL.v +../rtl/sm_RxFifoBI.v +../rtl/sm_TxFifoBI.v +../rtl/sm_RxFifo.v +../rtl/sm_TxFifo.v +../rtl/initSD.v +../rtl/readWriteSPIWireData.v +../rtl/readWriteSDBlock.v +../rtl/sendCmd.v +../rtl/spiCtrl.v +../rtl/spiTxRxData.v +../rtl/spiMasterWishBoneBI.v +../rtl/ctrlStsRegBI.v +../model/wb_master_model.v +../model/sdModel.v +../bench/testHarness.v +../bench/testCase0.v ++incdir+../rtl ++define+SIM_COMPILE + Index: spimaster/trunk/sim/wave.do =================================================================== --- spimaster/trunk/sim/wave.do (nonexistent) +++ spimaster/trunk/sim/wave.do (revision 4) @@ -0,0 +1,177 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider ctrlStsRegBI +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataIn +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/address +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/writeEn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/strobe_i +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/busClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiSysClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/ctrlStsRegSel +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransType +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatus +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxData +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromWire +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToBusClkOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkOut +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDAddr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiClkDelay +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/clk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstShift +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromBus +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxDataSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxDataSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransTypeSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkFirst +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlShift +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg1 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteErrorSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadErrorSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitErrorSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg1 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg2 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg3 +add wave -noupdate -divider spiTxRxData +add wave -noupdate -divider readWriteSPIWireData +add wave -noupdate -divider spiCtrl +add wave -noupdate -divider initSD +add wave -noupdate -divider sendCmd +add wave -noupdate -divider sdModel +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataIn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/rxByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/respByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/smSt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/cnt +add wave -noupdate -divider txFifo +add wave -noupdate -divider txFifoBI +add wave -noupdate -divider readWriteSDBlock +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/blockAddr +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/clk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockReq +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respByte +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respTout +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rst +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataIn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataEmpty +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataFull +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoData +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/checkSumByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/cmdByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte3 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte4 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readError +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdyClr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdReq +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoRen +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/writeError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_checkSumByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_cmdByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte3 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte4 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readError +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readWriteSDBlockRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxDataRdyClr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_sendCmdReq +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txFifoRen +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_writeError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/locRespByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_locRespByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/loopCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_loopCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/timeOutCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_timeOutCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/CurrState_rwBlkSt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/NextState_rwBlkSt +add wave -noupdate -divider sm_fifo +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataOut +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataIn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rdClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/wrClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoREn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoWEn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmptySyncToWrClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rstSyncToRdClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmptySyncToRdClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/rstSyncToWrClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/forceEmpty +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/numElementsInFifo +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndex +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/FIFO_DEPTH +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndexSyncToWrClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndex +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndexSyncToRdClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferInIndexToMem +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/ADDR_WIDTH +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/FIFO_WIDTH +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/dataFromMem +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoFull +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoREnDelayed +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/bufferOutIndexToMem +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_fifo/fifoEmpty +add wave -noupdate -divider TxFifoBI +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busDataIn +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/address +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/writeEn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/strobe_i +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/spiSysClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/rstSyncToBusClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/fifoSelect +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToBusClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/numElementsInFifo +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/fifoWEn +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/busDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToSpiClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptyShift +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmpty +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_sm_txFifo/u_sm_TxfifoBI/forceEmptySyncToSpiClkFirst +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {717201000 ps} 0} {{Cursor 2} {102093853 ps} 0} +configure wave -namecolwidth 456 +configure wave -valuecolwidth 73 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {7327222362 ps} {7443209350 ps} Index: spimaster/trunk/sim/run.do =================================================================== --- spimaster/trunk/sim/run.do (nonexistent) +++ spimaster/trunk/sim/run.do (revision 4) @@ -0,0 +1,5 @@ +vsim testCase0 testHarness +do wave.do +run -all + + Index: spimaster/trunk/sim/modelsim.ini =================================================================== --- spimaster/trunk/sim/modelsim.ini (nonexistent) +++ spimaster/trunk/sim/modelsim.ini (revision 4) @@ -0,0 +1,332 @@ +; Copyright 1991-2007 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Actel Primitive Libraries +; +; VHDL Section +; +;aact1 = $MODEL_TECH/../actel/vhdl/aact1 +;aact2 = $MODEL_TECH/../actel/vhdl/aact2 +;aact3 = $MODEL_TECH/../actel/vhdl/aact3 +;a3200dx = $MODEL_TECH/../actel/vhdl/a3200dx +;a40mx = $MODEL_TECH/../actel/vhdl/a40mx +;a42mx = $MODEL_TECH/../actel/vhdl/a42mx +;a54sxa = $MODEL_TECH/../actel/vhdl/a54sxa +; +; Verilog Section +; +;act1 = $MODEL_TECH/../actel/verilog/act1 +;act2 = $MODEL_TECH/../actel/verilog/act2 +;act3 = $MODEL_TECH/../actel/verilog/act3 +;3200dx = $MODEL_TECH/../actel/verilog/3200dx +;40mx = $MODEL_TECH/../actel/verilog/40mx +;42mx = $MODEL_TECH/../actel/verilog/42mx +;54sxa = $MODEL_TECH/../actel/verilog/54sxa + +work = work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both Index: spimaster/trunk/sim/compile.do =================================================================== --- spimaster/trunk/sim/compile.do (nonexistent) +++ spimaster/trunk/sim/compile.do (revision 4) @@ -0,0 +1,22 @@ + +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_dpMem_dc.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_fifoRTL.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_RxFifoBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_TxFifoBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_RxFifo.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sm_TxFifo.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/initSD.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSPIWireData.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSDBlock.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sendCmd.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiCtrl.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiTxRxData.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMaster.v +vlog +define+SIM_COMPILE +incdir+../rtl ../model/wb_master_model.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMasterWishBoneBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/ctrlStsRegBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../model/sdModel.v +vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testHarness.v +vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testCase0.v + + Index: spimaster/trunk/sim/build_icarus.bat =================================================================== --- spimaster/trunk/sim/build_icarus.bat (nonexistent) +++ spimaster/trunk/sim/build_icarus.bat (revision 4) @@ -0,0 +1,4 @@ +iverilog -o testHarness -cfilelist.icarus + +pause + Index: spimaster/trunk/syn/spiMaster.qsf =================================================================== --- spimaster/trunk/syn/spiMaster.qsf (nonexistent) +++ spimaster/trunk/syn/spiMaster.qsf (revision 4) @@ -0,0 +1,57 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# spiMaster_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY spiMaster +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:18 FEBRUARY 21, 2008" +set_global_assignment -name LAST_QUARTUS_VERSION 7.2 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace +set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBus_h.v +set_global_assignment -name VERILOG_FILE ../rtl/ctrlStsRegBI.v +set_global_assignment -name VERILOG_FILE ../rtl/dpMem_dc.v +set_global_assignment -name VERILOG_FILE ../rtl/fifoRTL.v +set_global_assignment -name VERILOG_FILE ../rtl/initSD.v +set_global_assignment -name VERILOG_FILE ../rtl/readWriteSDBlock.v +set_global_assignment -name VERILOG_FILE ../rtl/readWriteSPIWireData.v +set_global_assignment -name VERILOG_FILE ../rtl/RxFifo.v +set_global_assignment -name VERILOG_FILE ../rtl/RxFifoBI.v +set_global_assignment -name VERILOG_FILE ../rtl/sendCmd.v +set_global_assignment -name VERILOG_FILE ../rtl/spiCtrl.v +set_global_assignment -name VERILOG_FILE ../rtl/spiMaster.v +set_global_assignment -name VERILOG_FILE ../rtl/spiMaster_h.v +set_global_assignment -name VERILOG_FILE ../rtl/spiTxRxData.v +set_global_assignment -name VERILOG_FILE ../rtl/timescale.v +set_global_assignment -name VERILOG_FILE ../rtl/TxFifo.v +set_global_assignment -name VERILOG_FILE ../rtl/TxFifoBI.v +set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBI.v +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file Index: spimaster/trunk/syn/spiMaster.qpf =================================================================== --- spimaster/trunk/syn/spiMaster.qpf (nonexistent) +++ spimaster/trunk/syn/spiMaster.qpf (revision 4) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "7.2" +DATE = "14:03:18 February 21, 2008" + + +# Revisions + +PROJECT_REVISION = "spiMaster" Index: spimaster/trunk =================================================================== --- spimaster/trunk (nonexistent) +++ spimaster/trunk (revision 4)

spimaster/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: spimaster/web_uploads =================================================================== --- spimaster/web_uploads (nonexistent) +++ spimaster/web_uploads (revision 4)

spimaster/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: spimaster/branches =================================================================== --- spimaster/branches (nonexistent) +++ spimaster/branches (revision 4)

spimaster/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: spimaster/tags =================================================================== --- spimaster/tags (nonexistent) +++ spimaster/tags (revision 4)

spimaster/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##