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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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Rev 31 → Rev 30

/srdydrdy_lib/trunk/examples/bridge/rtl/allocator.v File deleted
/srdydrdy_lib/trunk/examples/bridge/rtl/control_pipe.v File deleted
/srdydrdy_lib/trunk/examples/bridge/rtl/packet_buffer.v File deleted
/srdydrdy_lib/trunk/examples/bridge/rtl/deallocator.v File deleted
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex2.v File deleted
/srdydrdy_lib/trunk/examples/bridge/rtl/sd_rx_gigmac.v
20,9 → 20,7
output rxg_srdy,
input rxg_drdy,
output [1:0] rxg_code,
output [7:0] rxg_data,
 
input cfg_check_crc
output [7:0] rxg_data
);
 
reg rxdv1, rxdv2;
157,7 → 155,7
begin
ic_srdy =1;
ic_data = pkt_crc[31:24];
if ((pkt_crc == crc) | !cfg_check_crc)
if (pkt_crc == crc)
begin
ic_code = `PCC_EOP;
end
/srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v
1,53 → 1,31
module port_macro
#(parameter port_num = 0,
parameter lpsz = 12,
parameter lpdsz = 13)
#(parameter port_num = 0)
(input clk,
input reset,
 
input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v
output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v
input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input drf_drdy, // To dealloc of deallocator.v
input [`LL_PG_ASZ-1:0] f2d_data, // To dealloc of deallocator.v
input f2d_srdy, // To dealloc of deallocator.v
input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
input lnp_drdy, // To alloc of allocator.v
input par_drdy, // To alloc of allocator.v
input [`LL_PG_ASZ-1:0] parr_page, // To alloc of allocator.v
input parr_srdy, // To alloc of allocator.v
input pbra_drdy, // To alloc of allocator.v
input pbrd_drdy, // To dealloc of deallocator.v
input [`PFW_SZ-1:0] pbrr_data, // To dealloc of deallocator.v
input pbrr_srdy, // To dealloc of deallocator.v
input pm2f_drdy, // To pm2f_join of sd_ajoin2.v
input rlp_drdy, // To dealloc of deallocator.v
input [`LL_PG_ASZ:0] rlpr_data, // To dealloc of deallocator.v
input rlpr_srdy, // To dealloc of deallocator.v
input fli_srdy, // To ring_tap of port_ring_tap.v
input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
input p2f_drdy, // To pkt_parse of pkt_parse.v
input rarb_ack, // To ring_tap of port_ring_tap.v
input ri_srdy, // To ring_tap of port_ring_tap.v
input ro_drdy, // To ring_tap of port_ring_tap.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [`LL_PG_ASZ*2-1:0] drf_page_list, // From dealloc of deallocator.v
output drf_srdy, // From dealloc of deallocator.v
output f2d_drdy, // From dealloc of deallocator.v
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
output [`LL_LNP_SZ-1:0] lnp_pnp, // From alloc of allocator.v
output lnp_srdy, // From alloc of allocator.v
output par_srdy, // From alloc of allocator.v
output parr_drdy, // From alloc of allocator.v
output [`PBR_SZ-1:0] pbra_data, // From alloc of allocator.v
output pbra_srdy, // From alloc of allocator.v
output [`PBR_SZ-1:0] pbrd_data, // From dealloc of deallocator.v
output pbrd_srdy, // From dealloc of deallocator.v
output pbrr_drdy, // From dealloc of deallocator.v
output [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data,// From pm2f_join of sd_ajoin2.v
output pm2f_srdy, // From pm2f_join of sd_ajoin2.v
output [`LL_PG_ASZ-1:0] rlp_rd_page, // From dealloc of deallocator.v
output rlp_srdy, // From dealloc of deallocator.v
output rlpr_drdy // From dealloc of deallocator.v
// End of automatics
 
output rarb_req,
output fli_drdy, // From ring_tap of port_ring_tap.v
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
output p2f_srdy, // From pkt_parse of pkt_parse.v
output ri_drdy, // From ring_tap of port_ring_tap.v
output ro_srdy // From ring_tap of port_ring_tap.v
);
 
wire [`RX_USG_SZ-1:0] rx_usage;
60,35 → 38,36
wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire a2f_drdy; // From pm2f_join of sd_ajoin2.v
wire [`LL_PG_ASZ-1:0] a2f_end; // From alloc of allocator.v
wire a2f_srdy; // From alloc of allocator.v
wire [`LL_PG_ASZ-1:0] a2f_start; // From alloc of allocator.v
wire crx_abort; // From con of concentrator.v
wire crx_commit; // From con of concentrator.v
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
wire crx_drdy; // From alloc of allocator.v
wire crx_srdy; // From con of concentrator.v
wire gmii_rx_reset; // From port_clocking of port_clocking.v
wire [`PAR_DATA_SZ-1:0] p2f_data; // From pkt_parse of pkt_parse.v
wire p2f_drdy; // From pm2f_join of sd_ajoin2.v
wire p2f_srdy; // From pkt_parse of pkt_parse.v
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
wire pdo_drdy; // From con of concentrator.v
wire pdo_srdy; // From pkt_parse of pkt_parse.v
wire ptx_drdy; // From dst of distributor.v
wire ptx_srdy; // From dealloc of deallocator.v
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
wire rxg_drdy; // From pkt_parse of pkt_parse.v
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
wire [1:0] txg_code; // From dst of distributor.v
wire [7:0] txg_data; // From dst of distributor.v
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
wire txg_srdy; // From dst of distributor.v
wire crx_abort; // From con of concentrator.v
wire crx_commit; // From con of concentrator.v
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
wire crx_drdy; // From fifo_rx of sd_fifo_b.v
wire crx_srdy; // From con of concentrator.v
wire ctx_abort; // From oflow of egr_oflow.v
wire ctx_commit; // From oflow of egr_oflow.v
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v
wire ctx_srdy; // From oflow of egr_oflow.v
wire gmii_rx_reset; // From port_clocking of port_clocking.v
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
wire pdo_drdy; // From con of concentrator.v
wire pdo_srdy; // From pkt_parse of pkt_parse.v
wire prx_drdy; // From ring_tap of port_ring_tap.v
wire prx_srdy; // From fifo_rx of sd_fifo_b.v
wire ptx_drdy; // From dst of distributor.v
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
wire rttx_drdy; // From oflow of egr_oflow.v
wire rttx_srdy; // From ring_tap of port_ring_tap.v
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
wire rxg_drdy; // From pkt_parse of pkt_parse.v
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
wire [1:0] txg_code; // From dst of distributor.v
wire [7:0] txg_data; // From dst of distributor.v
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
wire txg_srdy; // From dst of distributor.v
// End of automatics
 
 
95,11 → 74,11
port_clocking port_clocking
(/*AUTOINST*/
// Outputs
.gmii_rx_reset (gmii_rx_reset),
.gmii_rx_reset (gmii_rx_reset),
// Inputs
.clk (clk),
.reset (reset),
.gmii_rx_clk (gmii_rx_clk));
.clk (clk),
.reset (reset),
.gmii_rx_clk (gmii_rx_clk));
 
/* sd_rx_gigmac AUTO_TEMPLATE
(
109,19 → 88,17
);
*/
sd_rx_gigmac rx_gigmac
(
.cfg_check_crc (1'b0),
/*AUTOINST*/
(/*AUTOINST*/
// Outputs
.rxg_srdy (rxc_rxg_srdy), // Templated
.rxg_code (rxc_rxg_code[1:0]), // Templated
.rxg_data (rxc_rxg_data[7:0]), // Templated
.rxg_srdy (rxc_rxg_srdy), // Templated
.rxg_code (rxc_rxg_code[1:0]), // Templated
.rxg_data (rxc_rxg_data[7:0]), // Templated
// Inputs
.clk (gmii_rx_clk), // Templated
.reset (gmii_rx_reset), // Templated
.gmii_rx_dv (gmii_rx_dv),
.gmii_rxd (gmii_rxd[7:0]),
.rxg_drdy (rxc_rxg_drdy)); // Templated
.clk (gmii_rx_clk), // Templated
.reset (gmii_rx_reset), // Templated
.gmii_rx_dv (gmii_rx_dv),
.gmii_rxd (gmii_rxd[7:0]),
.rxg_drdy (rxc_rxg_drdy)); // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
(
138,36 → 115,35
sd_fifo_s #(8+2,16,1) rx_sync_fifo
(/*AUTOINST*/
// Outputs
.c_drdy (rxc_rxg_drdy), // Templated
.p_srdy (rxg_srdy), // Templated
.p_data ({rxg_code,rxg_data}), // Templated
.c_drdy (rxc_rxg_drdy), // Templated
.p_srdy (rxg_srdy), // Templated
.p_data ({rxg_code,rxg_data}), // Templated
// Inputs
.c_clk (gmii_rx_clk), // Templated
.c_reset (gmii_rx_reset), // Templated
.c_srdy (rxc_rxg_srdy), // Templated
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
.p_clk (clk), // Templated
.p_reset (reset), // Templated
.p_drdy (rxg_drdy)); // Templated
.c_clk (gmii_rx_clk), // Templated
.c_reset (gmii_rx_reset), // Templated
.c_srdy (rxc_rxg_srdy), // Templated
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
.p_clk (clk), // Templated
.p_reset (reset), // Templated
.p_drdy (rxg_drdy)); // Templated
 
pkt_parse #(port_num) pkt_parse
(
/*AUTOINST*/
(/*AUTOINST*/
// Outputs
.rxg_drdy (rxg_drdy),
.p2f_srdy (p2f_srdy),
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
.pdo_srdy (pdo_srdy),
.pdo_code (pdo_code[1:0]),
.pdo_data (pdo_data[7:0]),
.rxg_drdy (rxg_drdy),
.p2f_srdy (p2f_srdy),
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
.pdo_srdy (pdo_srdy),
.pdo_code (pdo_code[1:0]),
.pdo_data (pdo_data[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.rxg_srdy (rxg_srdy),
.rxg_code (rxg_code[1:0]),
.rxg_data (rxg_data[7:0]),
.p2f_drdy (p2f_drdy),
.pdo_drdy (pdo_drdy));
.clk (clk),
.reset (reset),
.rxg_srdy (rxg_srdy),
.rxg_code (rxg_code[1:0]),
.rxg_data (rxg_data[7:0]),
.p2f_drdy (p2f_drdy),
.pdo_drdy (pdo_drdy));
 
/* concentrator AUTO_TEMPLATE
(
178,102 → 154,120
concentrator con
(/*AUTOINST*/
// Outputs
.c_drdy (pdo_drdy), // Templated
.p_data (crx_data[`PFW_SZ-1:0]), // Templated
.p_srdy (crx_srdy), // Templated
.p_commit (crx_commit), // Templated
.p_abort (crx_abort), // Templated
.c_drdy (pdo_drdy), // Templated
.p_data (crx_data[`PFW_SZ-1:0]), // Templated
.p_srdy (crx_srdy), // Templated
.p_commit (crx_commit), // Templated
.p_abort (crx_abort), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_data (pdo_data[7:0]), // Templated
.c_code (pdo_code[1:0]), // Templated
.c_srdy (pdo_srdy), // Templated
.p_drdy (crx_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_data (pdo_data[7:0]), // Templated
.c_code (pdo_code[1:0]), // Templated
.c_srdy (pdo_srdy), // Templated
.p_drdy (crx_drdy)); // Templated
 
/* allocator AUTO_TEMPLATE
(
);
*/
allocator alloc
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
(
.p_abort (1'b0),
.p_commit (1'b0),
.c_usage (@_usage),
.p_usage (),
.c_\(.*\) (c@_\1),
.p_\(.*\) (p@_\1),
);
*/
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
(/*AUTOINST*/
// Outputs
.crx_drdy (crx_drdy),
.par_srdy (par_srdy),
.parr_drdy (parr_drdy),
.lnp_srdy (lnp_srdy),
.lnp_pnp (lnp_pnp[`LL_LNP_SZ-1:0]),
.pbra_data (pbra_data[`PBR_SZ-1:0]),
.pbra_srdy (pbra_srdy),
.a2f_start (a2f_start[`LL_PG_ASZ-1:0]),
.a2f_end (a2f_end[`LL_PG_ASZ-1:0]),
.a2f_srdy (a2f_srdy),
.c_drdy (crx_drdy), // Templated
.p_srdy (prx_srdy), // Templated
.p_data (prx_data), // Templated
.p_usage (), // Templated
.c_usage (rx_usage), // Templated
// Inputs
.clk (clk),
.reset (reset),
.crx_abort (crx_abort),
.crx_commit (crx_commit),
.crx_data (crx_data[`PFW_SZ-1:0]),
.crx_srdy (crx_srdy),
.par_drdy (par_drdy),
.parr_srdy (parr_srdy),
.parr_page (parr_page[`LL_PG_ASZ-1:0]),
.lnp_drdy (lnp_drdy),
.pbra_drdy (pbra_drdy),
.a2f_drdy (a2f_drdy));
.clk (clk),
.reset (reset),
.c_srdy (crx_srdy), // Templated
.c_commit (crx_commit), // Templated
.c_abort (crx_abort), // Templated
.c_data (crx_data), // Templated
.p_drdy (prx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
 
/* sd_ajoin2 AUTO_TEMPLATE
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
(/*AUTOINST*/
// Outputs
.c_drdy (ctx_drdy), // Templated
.p_srdy (ptx_srdy), // Templated
.p_data (ptx_data), // Templated
.p_usage (), // Templated
.c_usage (tx_usage), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (ctx_srdy), // Templated
.c_commit (ctx_commit), // Templated
.c_abort (ctx_abort), // Templated
.c_data (ctx_data), // Templated
.p_drdy (ptx_drdy), // Templated
.p_commit (1'b0), // Templated
.p_abort (1'b0)); // Templated
 
/* port_ring_tap AUTO_TEMPLATE
(
.c2_data ({a2f_end,a2f_start}),
.c1_\(.*\) (p2f_\1[]),
.c2_\(.*\) (a2f_\1[]),
.p_\(.*\) (pm2f_\1[]),
);
.ro_data (ro_data[`PRW_SZ-1:0]),
.ri_data (ri_data[`PRW_SZ-1:0]),
.prx_\(.*\) (prx_\1),
.ptx_\(.*\) (rttx_\1),
);
*/
sd_ajoin2 #(.c1_width(`PAR_DATA_SZ), .c2_width(`LL_PG_ASZ*2)) pm2f_join
port_ring_tap #(port_num) ring_tap
(/*AUTOINST*/
// Outputs
.c1_drdy (p2f_drdy), // Templated
.c2_drdy (a2f_drdy), // Templated
.p_srdy (pm2f_srdy), // Templated
.p_data (pm2f_data[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
.ri_drdy (ri_drdy),
.prx_drdy (prx_drdy), // Templated
.ro_srdy (ro_srdy),
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
.ptx_srdy (rttx_srdy), // Templated
.ptx_data (rttx_data), // Templated
.fli_drdy (fli_drdy),
.rarb_req (rarb_req),
// Inputs
.clk (clk),
.reset (reset),
.c1_srdy (p2f_srdy), // Templated
.c1_data (p2f_data[(`PAR_DATA_SZ)-1:0]), // Templated
.c2_srdy (a2f_srdy), // Templated
.c2_data ({a2f_end,a2f_start}), // Templated
.p_drdy (pm2f_drdy)); // Templated
.clk (clk),
.reset (reset),
.ri_srdy (ri_srdy),
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
.prx_srdy (prx_srdy), // Templated
.prx_data (prx_data), // Templated
.ro_drdy (ro_drdy),
.ptx_drdy (rttx_drdy), // Templated
.fli_srdy (fli_srdy),
.fli_data (fli_data[`NUM_PORTS-1:0]),
.rarb_ack (rarb_ack));
 
deallocator dealloc
/* egr_oflow AUTO_TEMPLATE
(
.c_\(.*\) (rttx_\1[]),
.p_\(.*\) (ctx_\1[]),
);
*/
egr_oflow oflow
(/*AUTOINST*/
// Outputs
.f2d_drdy (f2d_drdy),
.rlp_srdy (rlp_srdy),
.rlp_rd_page (rlp_rd_page[`LL_PG_ASZ-1:0]),
.rlpr_drdy (rlpr_drdy),
.drf_srdy (drf_srdy),
.drf_page_list (drf_page_list[`LL_PG_ASZ*2-1:0]),
.pbrd_data (pbrd_data[`PBR_SZ-1:0]),
.pbrd_srdy (pbrd_srdy),
.pbrr_drdy (pbrr_drdy),
.ptx_srdy (ptx_srdy),
.ptx_data (ptx_data[`PFW_SZ-1:0]),
.c_drdy (rttx_drdy), // Templated
.p_srdy (ctx_srdy), // Templated
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
.p_commit (ctx_commit), // Templated
.p_abort (ctx_abort), // Templated
// Inputs
.clk (clk),
.reset (reset),
.port_num (port_num[1:0]),
.f2d_srdy (f2d_srdy),
.f2d_data (f2d_data[`LL_PG_ASZ-1:0]),
.rlp_drdy (rlp_drdy),
.rlpr_srdy (rlpr_srdy),
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]),
.drf_drdy (drf_drdy),
.pbrd_drdy (pbrd_drdy),
.pbrr_srdy (pbrr_srdy),
.pbrr_data (pbrr_data[`PFW_SZ-1:0]),
.ptx_drdy (ptx_drdy));
.clk (clk),
.reset (reset),
.c_srdy (rttx_srdy), // Templated
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
.p_drdy (ctx_drdy)); // Templated
 
/* distributor AUTO_TEMPLATE
(
283,29 → 277,29
distributor dst
(/*AUTOINST*/
// Outputs
.ptx_drdy (ptx_drdy),
.p_srdy (txg_srdy), // Templated
.p_code (txg_code[1:0]), // Templated
.p_data (txg_data[7:0]), // Templated
.ptx_drdy (ptx_drdy),
.p_srdy (txg_srdy), // Templated
.p_code (txg_code[1:0]), // Templated
.p_data (txg_data[7:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.ptx_srdy (ptx_srdy),
.ptx_data (ptx_data[`PFW_SZ-1:0]),
.p_drdy (txg_drdy)); // Templated
.clk (clk),
.reset (reset),
.ptx_srdy (ptx_srdy),
.ptx_data (ptx_data[`PFW_SZ-1:0]),
.p_drdy (txg_drdy)); // Templated
 
sd_tx_gigmac tx_gmii
(/*AUTOINST*/
// Outputs
.gmii_tx_en (gmii_tx_en),
.gmii_txd (gmii_txd[7:0]),
.txg_drdy (txg_drdy),
.gmii_tx_en (gmii_tx_en),
.gmii_txd (gmii_txd[7:0]),
.txg_drdy (txg_drdy),
// Inputs
.clk (clk),
.reset (reset),
.txg_srdy (txg_srdy),
.txg_code (txg_code[1:0]),
.txg_data (txg_data[7:0]));
.clk (clk),
.reset (reset),
.txg_srdy (txg_srdy),
.txg_code (txg_code[1:0]),
.txg_data (txg_data[7:0]));
endmodule // port_macro
// Local Variables:
/srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup_fsm.v
1,15 → 1,15
module fib_lookup_fsm
(/*AUTOARG*/
// Outputs
lpp_drdy, ft_wdata, ft_rd_en, ft_wr_en, ft_addr, lout_start,
lout_srdy, lout_dst_vld, refup_srdy, refup_page, refup_count,
lpp_drdy, ft_wdata, ft_rd_en, ft_wr_en, ft_addr, lout_data,
lout_srdy, lout_dst_vld,
// Inputs
clk, reset, lpp_data, lpp_srdy, ft_rdata, lout_drdy, refup_drdy
clk, reset, lpp_data, lpp_srdy, ft_rdata, lout_drdy
);
 
input clk, reset;
input [`PM2F_SZ-1:0] lpp_data;
input [`PAR_DATA_SZ-1:0] lpp_data;
input lpp_srdy;
output reg lpp_drdy;
 
18,16 → 18,11
output reg ft_rd_en, ft_wr_en;
output reg [`FIB_ASZ-1:0] ft_addr;
output [`LL_PG_ASZ-1:0] lout_start;
output reg [`NUM_PORTS-1:0] lout_data;
output reg lout_srdy;
input lout_drdy;
output reg [`NUM_PORTS-1:0] lout_dst_vld;
output [`NUM_PORTS-1:0] lout_dst_vld;
output refup_srdy;
input refup_drdy;
output [`LL_PG_ASZ-1:0] refup_page;
output [`LL_REFSZ-1:0] refup_count;
 
wire [`FIB_ASZ-1:0] hf_out;
reg [47:0] hf_in;
 
34,36 → 29,10
wire [`NUM_PORTS-1:0] source_port_mask;
 
reg [`FIB_ASZ-1:0] init_ctr, nxt_init_ctr;
reg [5:0] state, nxt_state;
reg lrefup_srdy;
reg [`LL_REFSZ-1:0] lrefup_count;
 
reg [4:0] state, nxt_state;
assign source_port_mask = 1 << lpp_data[`PAR_SRCPORT];
 
//assign lrefup_count = count_bits (lout_dst_vld);
//assign refup_page = lpp_data[`A2F_STARTPG];
assign lout_start = lpp_data[`A2F_STARTPG];
function [`LL_REFSZ-1:0] count_bits;
input [`NUM_PORTS-1:0] dest;
integer i, count;
begin
count = 0;
for (i=0; i<4; i=i+1)
if (dest[i]) count = count + 1;
count_bits = count;
end
endfunction // for
 
sd_iohalf #(.width(`LL_PG_ASZ+`LL_REFSZ)) refup_buf
(.clk (clk), .reset (reset),
.c_srdy (lrefup_srdy),
.c_drdy (lrefup_drdy),
.c_data ({lrefup_count, lpp_data[`A2F_STARTPG]}),
.p_srdy (refup_srdy),
.p_drdy (refup_drdy),
.p_data ({refup_count, refup_page}));
basic_hashfunc #(48, `FIB_ENTRIES) hashfunc
(
// Outputs
72,10 → 41,13
.hf_in (hf_in));
 
localparam s_idle = 0, s_da_lookup = 1, s_sa_lookup = 2,
s_init0 = 3, s_init1 = 4, s_wait_refup = 5;
s_init0 = 3, s_init1 = 4;
localparam ns_idle = 1, ns_da_lookup = 2, ns_sa_lookup = 4,
ns_init0 = 8, ns_init1 = 16, ns_wait_refup = 1 << s_wait_refup;
ns_init0 = 8, ns_init1 = 16;
 
// send all results back to their originating port
assign lout_dst_vld = source_port_mask;
 
reg amux;
 
always @*
93,11 → 65,10
ft_rd_en = 0;
ft_wr_en = 0;
amux = 0;
lout_dst_vld = 0;
lout_data = 0;
lout_srdy = 0;
lpp_drdy = 0;
nxt_init_ctr = init_ctr;
lrefup_srdy = 0;
case (1'b1)
state[s_idle] :
108,7 → 79,7
if (lpp_data[`PAR_MACDA] & `MULTICAST)
begin
// flood the packet, don't bother to do DA lookup
lout_dst_vld = ~source_port_mask;
lout_data = ~source_port_mask;
lout_srdy = 1;
if (lout_drdy)
nxt_state = ns_sa_lookup;
130,11 → 101,11
// no match, flood packet
if (ft_rdata[`FIB_AGE] == 0)
begin
lout_dst_vld = ~source_port_mask;
lout_data = ~source_port_mask;
end
else
begin
lout_dst_vld = (1 << ft_rdata[`FIB_PORT]) & ~source_port_mask;
lout_data = (1 << ft_rdata[`FIB_PORT]) & ~source_port_mask;
end
lout_srdy = 1;
152,25 → 123,7
ft_wdata[`FIB_AGE] = `FIB_MAX_AGE;
ft_wdata[`FIB_PORT] = lpp_data[`PAR_SRCPORT];
nxt_state = ns_idle;
 
lrefup_srdy = 1;
if (lrefup_drdy)
begin
nxt_state = ns_idle;
lpp_drdy = 1;
end
else
nxt_state = ns_wait_refup;
end // case: state[s_sa_lookup]
 
state[s_wait_refup] :
begin
lrefup_srdy = 1;
if (lrefup_drdy)
begin
nxt_state = ns_idle;
lpp_drdy = 1;
end
lpp_drdy = 1;
end
 
state[s_init0] :
200,14 → 153,11
begin
init_ctr <= #1 0;
state <= #1 ns_init0;
lrefup_count <= #1 0;
end
else
begin
init_ctr <= #1 nxt_init_ctr;
state <= #1 nxt_state;
if (lout_srdy)
lrefup_count <= #1 count_bits (lout_dst_vld);
end
end
 
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge.vh
6,7 → 6,7
// We will have only 4 ports in our sample design
`define NUM_PORTS 4
 
// Data structure from parser to Allocator/FIB. Contains MAC DA,
// Data structure from parser to FIB. Contains MAC DA,
// MAC SA, and source port
`define PAR_DATA_SZ (48+48+4)
`define PAR_MACDA 47:0
13,13 → 13,6
`define PAR_MACSA 95:48
`define PAR_SRCPORT 99:96
 
// additional information from allocator to FIB
`define A2F_STARTPG 111:100
`define A2F_ENDPG 123:112
 
// total size of parser+allocator structure to FIB
`define PM2F_SZ 124
 
// number of entries in FIB table
`define FIB_ENTRIES 256
`define FIB_ASZ $clog2(`FIB_ENTRIES)
40,13 → 33,9
`define PCC_EOP 2'b10 // End of packet
`define PCC_BADEOP 2'b11 // End of packet w/ error
 
`define ANY_EOP(x) (( (x) == `PCC_EOP) || ( (x) == `PCC_BADEOP))
 
// Packet FIFO Word
`define PRW_DATA 63:0 // 64 bits of packet data
`define PRW_PCC 65:64 // packet control code
`define PRW_VALID 68:66 // # of valid bytes modulo 8
`define PFW_SZ 69
// uses same field definitions as Packet Ring Word, but no PVEC bit
`define PFW_SZ 69
 
// Port FIFO sizes
`define RX_FIFO_DEPTH 256
55,30 → 44,14
`define RX_USG_SZ $clog2(`RX_FIFO_DEPTH)+1
`define TX_USG_SZ $clog2(`TX_FIFO_DEPTH)+1
 
// Linked List Definitions
`define LL_PAGES 4096
`define LL_PG_ASZ $clog2(`LL_PAGES)
// Packet Ring Word
 
`define LL_ENDPAGE { 1'b1, {`LL_PG_ASZ{1'b0}} }
`define PRW_SZ 70
`define PRW_DATA 63:0 // 64 bits of packet data
`define PRW_PCC 65:64 // packet control code
`define PRW_VALID 68:66 // # of valid bytes modulo 8
`define PRW_PVEC 69 // indicates this is port vector word
 
`define LL_MAX_REF 16
`define LL_REFSZ 4
 
`define LL_LNP_SZ (`LL_PG_ASZ*2+1)
 
 
// Packet buffer size
`define PB_LINES_PER_PAGE 4
`define PB_DEPTH (`LL_PAGES*`PB_LINES_PER_PAGE)
`define PB_ASZ $clog2(`PB_DEPTH)
 
// Packet buffer request structure
`define PBR_DATA 68:0 // only valid for writes
`define PBR_ADDR 82:69
`define PBR_WRITE 83
`define PBR_PORT 87:84 // only valid for reads
`define PBR_SZ 88
 
// GMII definitions
`define GMII_PRE 8'h55
`define GMII_SFD 8'hD5
/srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup.v
4,33 → 4,29
module fib_lookup
(/*AUTOARG*/
// Outputs
refup_srdy, refup_page, refup_count, ppi_drdy, flo_data, flo_srdy,
ppi_drdy, flo_data, flo_srdy,
// Inputs
refup_drdy, ppi_srdy, clk, reset, ppi_data, flo_drdy
ppi_srdy, clk, reset, ppi_data, flo_drdy
);
 
input clk;
input reset;
 
input [`PM2F_SZ-1:0] ppi_data;
output [`LL_PG_ASZ-1:0] flo_data;
input [`PAR_DATA_SZ-1:0] ppi_data;
output [`NUM_PORTS-1:0] flo_data;
output [`NUM_PORTS-1:0] flo_srdy;
input [`NUM_PORTS-1:0] flo_drdy;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input ppi_srdy; // To port_parse_in of sd_input.v
input refup_drdy; // To fsm0 of fib_lookup_fsm.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output ppi_drdy; // From port_parse_in of sd_input.v
output [`LL_REFSZ-1:0] refup_count; // From fsm0 of fib_lookup_fsm.v
output [`LL_PG_ASZ-1:0] refup_page; // From fsm0 of fib_lookup_fsm.v
output refup_srdy; // From fsm0 of fib_lookup_fsm.v
// End of automatics
 
wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
wire [`PM2F_SZ-1:0] lpp_data;
wire [`PAR_DATA_SZ-1:0] lpp_data;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v
37,10 → 33,10
wire ft_rd_en; // From fsm0 of fib_lookup_fsm.v
wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v
wire ft_wr_en; // From fsm0 of fib_lookup_fsm.v
wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v
wire lout_drdy; // From fib_res_out of sd_mirror.v
wire [`NUM_PORTS-1:0] lout_dst_vld; // From fsm0 of fib_lookup_fsm.v
wire lout_srdy; // From fsm0 of fib_lookup_fsm.v
wire [`LL_PG_ASZ-1:0] lout_start; // From fsm0 of fib_lookup_fsm.v
wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v
wire lpp_srdy; // From port_parse_in of sd_input.v
// End of automatics
51,7 → 47,7
.ip_\(.*\) (lpp_\1),
);
*/
sd_input #(`PM2F_SZ) port_parse_in
sd_input #(`PAR_DATA_SZ) port_parse_in
(/*AUTOINST*/
// Outputs
.c_drdy (ppi_drdy), // Templated
91,31 → 87,24
.ft_rd_en (ft_rd_en),
.ft_wr_en (ft_wr_en),
.ft_addr (ft_addr[`FIB_ASZ-1:0]),
.lout_start (lout_start[`LL_PG_ASZ-1:0]),
.lout_data (lout_data[`NUM_PORTS-1:0]),
.lout_srdy (lout_srdy),
.lout_dst_vld (lout_dst_vld[`NUM_PORTS-1:0]),
.refup_srdy (refup_srdy),
.refup_page (refup_page[`LL_PG_ASZ-1:0]),
.refup_count (refup_count[`LL_REFSZ-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.lpp_data (lpp_data[`PM2F_SZ-1:0]),
.lpp_data (lpp_data[`PAR_DATA_SZ-1:0]),
.lpp_srdy (lpp_srdy),
.ft_rdata (ft_rdata[`FIB_ENTRY_SZ-1:0]),
.lout_drdy (lout_drdy),
.refup_drdy (refup_drdy));
.lout_drdy (lout_drdy));
 
/* sd_mirror AUTO_TEMPLATE
(
.c_data (lout_start[`LL_PG_ASZ-1:0]),
.c_\(.*\) (lout_\1),
.p_\(.*\) (flo_\1),
)
*/
sd_mirror #(// Parameters
.mirror (`NUM_PORTS),
.width (`LL_PG_ASZ)) fib_res_out
sd_mirror #(`NUM_PORTS, `NUM_PORTS) fib_res_out
(/*AUTOINST*/
// Outputs
.c_drdy (lout_drdy), // Templated
125,7 → 114,7
.clk (clk),
.reset (reset),
.c_srdy (lout_srdy), // Templated
.c_data (lout_start[`LL_PG_ASZ-1:0]), // Templated
.c_data (lout_data), // Templated
.c_dst_vld (lout_dst_vld), // Templated
.p_drdy (flo_drdy)); // Templated
 

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