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    from Rev 11 to Rev 12
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Rev 11 → Rev 12

/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v
21,7 → 21,10
input lptx_drdy,
input [rdp_sz-1:0] lri_data,
input lri_srdy,
input lro_drdy
input lro_drdy,
 
output rarb_req,
input rarb_ack
);
 
reg [4:0] state, nxt_state;
42,6 → 45,8
ns_rcopy = 4,
ns_rsink = 8,
ns_tdata = 16;
 
assign rarb_req = lfli_srdy & lprx_srdy | state[s_tdata];
always @*
begin
52,11 → 57,12
lptx_srdy = 0;
lri_drdy = 0;
lro_srdy = 0;
nxt_state = state;
case (1'b1)
state[s_idle] :
begin
if (lfli_srdy)
if (lfli_srdy & lprx_srdy & rarb_ack)
begin
if (lfli_data != 0)
begin
/srdydrdy_lib/trunk/examples/bridge/rtl/ring_arb.v
0,0 → 1,40
module ring_arb
(
input clk,
input reset,
 
input [`NUM_PORTS-1:0] rarb_req,
output reg [`NUM_PORTS-1:0] rarb_ack
);
integer i;
reg [`NUM_PORTS-1:0] nxt_rarb_ack;
reg [$clog2(`NUM_PORTS)-1:0] nxt_ack;
always @*
begin
nxt_rarb_ack = rarb_ack;
nxt_ack = 0;
 
if (rarb_req == 0)
nxt_rarb_ack = 0;
else if ((rarb_ack == 0) |
((rarb_req & rarb_ack) == 0))
begin
nxt_ack = 0;
for (i=`NUM_PORTS; i>0; i=i-1)
if (rarb_req[i-1])
nxt_ack = i-1;
nxt_rarb_ack = 1 << nxt_ack;
end
end // always @ *
 
always @(posedge clk)
begin
if (reset)
rarb_ack <= #1 0;
else
rarb_ack <= #1 nxt_rarb_ack;
end
 
endmodule // ring_arb
/srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v
13,10 → 13,12
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
input p2f_drdy, // To pkt_parse of pkt_parse.v
input rarb_ack, // To ring_tap of port_ring_tap.v
input ri_srdy, // To ring_tap of port_ring_tap.v
input ro_drdy, // To ring_tap of port_ring_tap.v
// End of automatics
 
output rarb_req,
output fli_drdy, // From ring_tap of port_ring_tap.v
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
54,6 → 56,7
wire prx_srdy; // From fifo_rx of sd_fifo_b.v
wire ptx_drdy; // From dst of distributor.v
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
wire rarb_req; // From ring_tap of port_ring_tap.v
wire rttx_drdy; // From oflow of egr_oflow.v
wire rttx_srdy; // From ring_tap of port_ring_tap.v
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
228,6 → 231,7
.ptx_srdy (rttx_srdy), // Templated
.ptx_data (rttx_data), // Templated
.fli_drdy (fli_drdy),
.rarb_req (rarb_req),
// Inputs
.clk (clk),
.reset (reset),
238,7 → 242,8
.ro_drdy (ro_drdy),
.ptx_drdy (rttx_drdy), // Templated
.fli_srdy (fli_srdy),
.fli_data (fli_data[`NUM_PORTS-1:0]));
.fli_data (fli_data[`NUM_PORTS-1:0]),
.rarb_ack (rarb_ack));
 
/* egr_oflow AUTO_TEMPLATE
(
/srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap.v
28,7 → 28,10
 
input fli_srdy,
output fli_drdy,
input [`NUM_PORTS-1:0] fli_data
input [`NUM_PORTS-1:0] fli_data,
 
output rarb_req,
input rarb_ack
);
 
wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v
38,16 → 41,16
wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire lfli_drdy; // From fsm of port_ring_tap_fsm.v
wire lfli_srdy; // From tc_fli of sd_input.v
wire lprx_drdy; // From fsm of port_ring_tap_fsm.v
wire lprx_srdy; // From tc_prx of sd_input.v
wire lptx_drdy; // From tc_ptx of sd_output.v
wire lptx_srdy; // From fsm of port_ring_tap_fsm.v
wire lri_drdy; // From fsm of port_ring_tap_fsm.v
wire lri_srdy; // From tc_ri of sd_input.v
wire lro_drdy; // From tc_ro of sd_output.v
wire lro_srdy; // From fsm of port_ring_tap_fsm.v
wire lfli_drdy; // From fsm of port_ring_tap_fsm.v
wire lfli_srdy; // From tc_fli of sd_input.v
wire lprx_drdy; // From fsm of port_ring_tap_fsm.v
wire lprx_srdy; // From tc_prx of sd_input.v
wire lptx_drdy; // From tc_ptx of sd_output.v
wire lptx_srdy; // From fsm of port_ring_tap_fsm.v
wire lri_drdy; // From fsm of port_ring_tap_fsm.v
wire lri_srdy; // From tc_ri of sd_input.v
wire lro_drdy; // From tc_ro of sd_output.v
wire lro_srdy; // From fsm of port_ring_tap_fsm.v
// End of automatics
/* sd_input AUTO_TEMPLATE "tc_\(.*\)"
60,63 → 63,65
sd_input #(rdp_sz) tc_ri
(/*AUTOINST*/
// Outputs
.c_drdy (ri_drdy), // Templated
.ip_srdy (lri_srdy), // Templated
.ip_data (lri_data), // Templated
.c_drdy (ri_drdy), // Templated
.ip_srdy (lri_srdy), // Templated
.ip_data (lri_data), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (ri_srdy), // Templated
.c_data (ri_data), // Templated
.ip_drdy (lri_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (ri_srdy), // Templated
.c_data (ri_data), // Templated
.ip_drdy (lri_drdy)); // Templated
sd_input #(pdp_sz) tc_prx
(/*AUTOINST*/
// Outputs
.c_drdy (prx_drdy), // Templated
.ip_srdy (lprx_srdy), // Templated
.ip_data (lprx_data), // Templated
.c_drdy (prx_drdy), // Templated
.ip_srdy (lprx_srdy), // Templated
.ip_data (lprx_data), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (prx_srdy), // Templated
.c_data (prx_data), // Templated
.ip_drdy (lprx_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (prx_srdy), // Templated
.c_data (prx_data), // Templated
.ip_drdy (lprx_drdy)); // Templated
sd_input #(`NUM_PORTS) tc_fli
(/*AUTOINST*/
// Outputs
.c_drdy (fli_drdy), // Templated
.ip_srdy (lfli_srdy), // Templated
.ip_data (lfli_data), // Templated
.c_drdy (fli_drdy), // Templated
.ip_srdy (lfli_srdy), // Templated
.ip_data (lfli_data), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (fli_srdy), // Templated
.c_data (fli_data), // Templated
.ip_drdy (lfli_drdy)); // Templated
.clk (clk),
.reset (reset),
.c_srdy (fli_srdy), // Templated
.c_data (fli_data), // Templated
.ip_drdy (lfli_drdy)); // Templated
 
port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm
(/*AUTOINST*/
// Outputs
.lfli_drdy (lfli_drdy),
.lprx_drdy (lprx_drdy),
.lptx_data (lptx_data[pdp_sz-1:0]),
.lptx_srdy (lptx_srdy),
.lri_drdy (lri_drdy),
.lro_data (lro_data[rdp_sz-1:0]),
.lro_srdy (lro_srdy),
.lfli_drdy (lfli_drdy),
.lprx_drdy (lprx_drdy),
.lptx_data (lptx_data[pdp_sz-1:0]),
.lptx_srdy (lptx_srdy),
.lri_drdy (lri_drdy),
.lro_data (lro_data[rdp_sz-1:0]),
.lro_srdy (lro_srdy),
.rarb_req (rarb_req),
// Inputs
.clk (clk),
.reset (reset),
.lfli_data (lfli_data[`NUM_PORTS-1:0]),
.lfli_srdy (lfli_srdy),
.lprx_data (lprx_data[pdp_sz-1:0]),
.lprx_srdy (lprx_srdy),
.lptx_drdy (lptx_drdy),
.lri_data (lri_data[rdp_sz-1:0]),
.lri_srdy (lri_srdy),
.lro_drdy (lro_drdy));
.clk (clk),
.reset (reset),
.lfli_data (lfli_data[`NUM_PORTS-1:0]),
.lfli_srdy (lfli_srdy),
.lprx_data (lprx_data[pdp_sz-1:0]),
.lprx_srdy (lprx_srdy),
.lptx_drdy (lptx_drdy),
.lri_data (lri_data[rdp_sz-1:0]),
.lri_srdy (lri_srdy),
.lro_drdy (lro_drdy),
.rarb_ack (rarb_ack));
 
/* sd_output AUTO_TEMPLATE "tc_\(.*\)"
(
128,28 → 133,28
sd_output #(pdp_sz) tc_ptx
(/*AUTOINST*/
// Outputs
.ic_drdy (lptx_drdy), // Templated
.p_srdy (ptx_srdy), // Templated
.p_data (ptx_data), // Templated
.ic_drdy (lptx_drdy), // Templated
.p_srdy (ptx_srdy), // Templated
.p_data (ptx_data), // Templated
// Inputs
.clk (clk),
.reset (reset),
.ic_srdy (lptx_srdy), // Templated
.ic_data (lptx_data), // Templated
.p_drdy (ptx_drdy)); // Templated
.clk (clk),
.reset (reset),
.ic_srdy (lptx_srdy), // Templated
.ic_data (lptx_data), // Templated
.p_drdy (ptx_drdy)); // Templated
 
sd_output #(rdp_sz) tc_ro
(/*AUTOINST*/
// Outputs
.ic_drdy (lro_drdy), // Templated
.p_srdy (ro_srdy), // Templated
.p_data (ro_data), // Templated
.ic_drdy (lro_drdy), // Templated
.p_srdy (ro_srdy), // Templated
.p_data (ro_data), // Templated
// Inputs
.clk (clk),
.reset (reset),
.ic_srdy (lro_srdy), // Templated
.ic_data (lro_data), // Templated
.p_drdy (ro_drdy)); // Templated
.clk (clk),
.reset (reset),
.ic_srdy (lro_srdy), // Templated
.ic_data (lro_data), // Templated
.p_drdy (ro_drdy)); // Templated
 
endmodule // port_ring_tap
// Local Variables:
/srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex1.v
55,6 → 55,8
wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrslow.v
wire ppi_drdy; // From fib_lookup of fib_lookup.v
wire ppi_srdy; // From fib_arb of sd_rrslow.v
wire [`NUM_PORTS-1:0] rarb_ack; // From ring_arb of ring_arb.v
wire [3:0] rarb_req; // From p0 of port_macro.v, ...
wire ri_drdy_0; // From p0 of port_macro.v
wire ri_drdy_1; // From p1 of port_macro.v
wire ri_drdy_2; // From p2 of port_macro.v
70,6 → 72,7
.clk (clk),
.reset (reset),
.ri_data (ri_data_@),
.rarb_\(.*\) (rarb_\1[@]),
.ro_\(.*\) (ri_\1_@"(% (+ 1 @) 4)"),
.p2f_srdy (p2f_srdy[@]),
.p2f_drdy (p2f_drdy[@]),
83,6 → 86,7
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_1), // Templated
.rarb_req (rarb_req[0]), // Templated
.fli_drdy (flo_drdy[0]), // Templated
.gmii_tx_en (gmii_tx_en_0), // Templated
.gmii_txd (gmii_txd_0[7:0]), // Templated
100,6 → 104,7
.gmii_rx_dv (gmii_rx_dv_0), // Templated
.gmii_rxd (gmii_rxd_0[7:0]), // Templated
.p2f_drdy (p2f_drdy[0]), // Templated
.rarb_ack (rarb_ack[0]), // Templated
.ri_srdy (ri_srdy_0), // Templated
.ro_drdy (ri_drdy_1)); // Templated
 
107,6 → 112,7
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_2), // Templated
.rarb_req (rarb_req[1]), // Templated
.fli_drdy (flo_drdy[1]), // Templated
.gmii_tx_en (gmii_tx_en_1), // Templated
.gmii_txd (gmii_txd_1[7:0]), // Templated
124,6 → 130,7
.gmii_rx_dv (gmii_rx_dv_1), // Templated
.gmii_rxd (gmii_rxd_1[7:0]), // Templated
.p2f_drdy (p2f_drdy[1]), // Templated
.rarb_ack (rarb_ack[1]), // Templated
.ri_srdy (ri_srdy_1), // Templated
.ro_drdy (ri_drdy_2)); // Templated
 
131,6 → 138,7
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_3), // Templated
.rarb_req (rarb_req[2]), // Templated
.fli_drdy (flo_drdy[2]), // Templated
.gmii_tx_en (gmii_tx_en_2), // Templated
.gmii_txd (gmii_txd_2[7:0]), // Templated
148,6 → 156,7
.gmii_rx_dv (gmii_rx_dv_2), // Templated
.gmii_rxd (gmii_rxd_2[7:0]), // Templated
.p2f_drdy (p2f_drdy[2]), // Templated
.rarb_ack (rarb_ack[2]), // Templated
.ri_srdy (ri_srdy_2), // Templated
.ro_drdy (ri_drdy_3)); // Templated
 
155,6 → 164,7
(/*AUTOINST*/
// Outputs
.ro_data (ri_data_0), // Templated
.rarb_req (rarb_req[3]), // Templated
.fli_drdy (flo_drdy[3]), // Templated
.gmii_tx_en (gmii_tx_en_3), // Templated
.gmii_txd (gmii_txd_3[7:0]), // Templated
172,6 → 182,7
.gmii_rx_dv (gmii_rx_dv_3), // Templated
.gmii_rxd (gmii_rxd_3[7:0]), // Templated
.p2f_drdy (p2f_drdy[3]), // Templated
.rarb_ack (rarb_ack[3]), // Templated
.ri_srdy (ri_srdy_3), // Templated
.ro_drdy (ri_drdy_0)); // Templated
 
211,6 → 222,15
.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
.ppi_srdy (ppi_srdy));
 
ring_arb ring_arb
(/*AUTOINST*/
// Outputs
.rarb_ack (rarb_ack[`NUM_PORTS-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.rarb_req (rarb_req[`NUM_PORTS-1:0]));
 
endmodule // bridge_ex1
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
/srdydrdy_lib/trunk/examples/bridge/env/bridge.vf
6,6 → 6,7
 
../rtl/basic_hashfunc.v
../rtl/bridge_ex1.v
../rtl/ring_arb.v
../rtl/concentrator.v
../rtl/distributor.v
../rtl/egr_oflow.v
/srdydrdy_lib/trunk/examples/bridge/env/env_top.v
33,7 → 33,7
driver3.send_packet (4, 1, 64);
join
 
#500;
#2000;
$finish;
end
 

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