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Rev 23 → Rev 24

/srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v
32,7 → 32,7
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
parameter asz=6) //log2(items))
(input clk,
input reset,
 
/srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard.v
19,7 → 19,7
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
parameter asz=6) //log2(items))
(input clk,
input reset,
 
37,7 → 37,8
output [width-1:0] p_data
);
 
localparam tot_in_sz = width*2+txid_sz+asz+1;
localparam tot_in_sz = ((use_mask)?width*2:width)+
((use_txid)?txid_sz:0)+asz+1;
wire ip_req_type; // 0=read, 1=write
wire [txid_sz-1:0] ip_txid;
49,9 → 50,9
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [asz-1:0] addr; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_in; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_out; // From sb_mem of behave1p_mem.v
wire [(asz)-1:0] addr; // From fsm of sd_scoreboard_fsm.v
wire [(width)-1:0] d_in; // From fsm of sd_scoreboard_fsm.v
wire [(width)-1:0] d_out; // From sb_mem of behave1p_mem.v
wire ic_drdy; // From outhold of sd_output.v
wire ic_srdy; // From fsm of sd_scoreboard_fsm.v
wire ip_drdy; // From fsm of sd_scoreboard_fsm.v
60,10 → 61,38
wire wr_en; // From fsm of sd_scoreboard_fsm.v
// End of automatics
 
wire [tot_in_sz-1:0] c_hold_data, p_hold_data;
generate if ((use_txid == 1) && (use_mask == 1))
begin : txid_and_mask
assign c_hold_data = {c_txid,c_req_type,c_itemid,c_mask,c_data};
assign {ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data} = p_hold_data;
end
else if ((use_txid == 0) && (use_mask == 1))
begin : no_txid_and_mask
assign c_hold_data = {c_req_type,c_itemid,c_mask,c_data};
assign {ip_req_type,ip_itemid,ip_mask,ip_data} = p_hold_data;
assign ip_mask = 0;
end
else if ((use_txid == 1) && (use_mask == 0))
begin : txid_and_no_mask
assign c_hold_data = {c_txid,c_req_type,c_itemid,c_data};
assign {ip_txid,ip_req_type,ip_itemid,ip_data} = p_hold_data;
assign ip_txid = 0;
end
else if ((use_txid == 0) && (use_mask == 0))
begin : no_txid_no_mask
assign c_hold_data = {c_req_type,c_itemid,c_data};
assign {ip_req_type,ip_itemid,ip_data} = p_hold_data;
assign ip_mask = 0;
assign ip_txid = 0;
end
endgenerate
sd_input #(.width(tot_in_sz)) inhold
(
.c_data ({c_txid,c_req_type,c_itemid,c_mask,c_data}),
.ip_data ({ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data}),
.c_data (c_hold_data),
.ip_data (p_hold_data),
/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
74,40 → 103,50
.c_srdy (c_srdy),
.ip_drdy (ip_drdy));
 
behave1p_mem #(.depth(items), .width(width)) sb_mem
behave1p_mem #(.depth(items),
.addr_sz (asz), /*AUTOINSTPARAM*/
// Parameters
.width (width)) sb_mem
(
.addr (addr[asz-1:0]),
/*AUTOINST*/
// Outputs
.d_out (d_out[width-1:0]),
.d_out (d_out[(width)-1:0]),
// Inputs
.wr_en (wr_en),
.rd_en (rd_en),
.clk (clk),
.d_in (d_in[width-1:0]));
.d_in (d_in[(width)-1:0]));
 
sd_scoreboard_fsm #(width,items,use_txid,use_mask,txid_sz) fsm
sd_scoreboard_fsm #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) fsm
(/*AUTOINST*/
// Outputs
.ip_drdy (ip_drdy),
.ic_srdy (ic_srdy),
.ic_txid (ic_txid[txid_sz-1:0]),
.ic_data (ic_data[width-1:0]),
.ic_txid (ic_txid[(txid_sz)-1:0]),
.ic_data (ic_data[(width)-1:0]),
.wr_en (wr_en),
.rd_en (rd_en),
.d_in (d_in[width-1:0]),
.addr (addr[asz-1:0]),
.d_in (d_in[(width)-1:0]),
.addr (addr[(asz)-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.ip_srdy (ip_srdy),
.ip_req_type (ip_req_type),
.ip_txid (ip_txid[txid_sz-1:0]),
.ip_mask (ip_mask[width-1:0]),
.ip_data (ip_data[width-1:0]),
.ip_itemid (ip_itemid[asz-1:0]),
.ip_txid (ip_txid[(txid_sz)-1:0]),
.ip_mask (ip_mask[(width)-1:0]),
.ip_data (ip_data[(width)-1:0]),
.ip_itemid (ip_itemid[(asz)-1:0]),
.ic_drdy (ic_drdy),
.d_out (d_out[width-1:0]));
.d_out (d_out[(width)-1:0]));
 
sd_output #(.width(width+txid_sz)) outhold
(
128,4 → 167,4
// verilog-library-directories:("." "../closure" "../memory")
// End:
 
/srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrmux.v
14,9 → 14,9
// When input deasserts, device will begin to hunt for a
// new input with data.
// Mode 2 : Continue to accept input until the incoming data
// matches a particular "end pattern". The trigger pattern
// is when (c_data & eod_mask) == eod_pattern. Once
// trigger pattern is seen, begin hunting for new input.
// matches a particular "end pattern". The end pattern
// is provided on the c_rearb (re-arbitrate) input. When
// c_rearb is high, will hunt for new inputs on next clock.
//
// This component also supports two arbitration modes: slow and fast.
// slow rotates the grant from requestor to requestor cycle by cycle,
51,8 → 51,6
#(parameter width=8,
parameter inputs=2,
parameter mode=0,
parameter eod_pattern=0,
parameter eod_mask=0,
parameter fast_arb=0)
(
input clk,
61,6 → 59,7
input [(width*inputs)-1:0] c_data,
input [inputs-1:0] c_srdy,
output [inputs-1:0] c_drdy,
input c_rearb, // for use with mode 2 only
 
output reg [width-1:0] p_data,
output [inputs-1:0] p_grant,
77,7 → 76,6
reg rr_locked;
genvar i;
integer j;
wire trig_pattern;
 
assign c_drdy = rr_state & {inputs{p_drdy}};
assign p_grant = rr_state;
108,7 → 106,6
begin : tp_gen
reg nxt_rr_locked;
assign trig_pattern = (rr_mux_grid[data_ind] & eod_mask) == eod_pattern;
always @*
begin
data_ind = 0;
120,7 → 117,7
 
if ((c_srdy & rr_state) & (!rr_locked))
nxt_rr_locked = 1;
else if ((c_srdy & rr_state) & p_drdy & trig_pattern )
else if ((c_srdy & rr_state & c_rearb) & p_drdy )
nxt_rr_locked = 0;
end
 
132,10 → 129,6
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
end
end // block: tp_gen
else
begin : ntp_gen
assign trig_pattern = 1'b0;
end
endgenerate
 
always @*
/srdydrdy_lib/trunk/examples/bridge/rtl/sd_rx_gigmac.v
25,104 → 25,32
 
reg rxdv1, rxdv2;
reg [7:0] rxd1, rxd2;
reg [31:0] calc_crc, nxt_calc_crc;
reg [31:0] pkt_crc, nxt_pkt_crc;
reg [31:0] pkt_crc;
reg [3:0] valid_bits, nxt_valid_bits;
reg [31:0] nxt_pkt_crc;
 
reg [5:0] state, nxt_state;
reg [6:0] state, nxt_state;
reg ic_srdy;
wire ic_drdy;
reg [1:0] ic_code;
reg [7:0] ic_data;
wire [31:0] crc;
 
wire [31:0] crc_comp_a, crc_comp_b;
reg crc_valid;
reg crc_clear;
mac_crc32 crc_chk
(
.clear (crc_clear),
.data (rxd2),
.valid (crc_valid),
 
assign crc_comp_a = { pkt_crc[23:0], rxd2 };
assign crc_comp_b = fixup_crc (calc_crc);
localparam CRC32_POLY = 32'h04C11DB7;
/*AUTOINST*/
// Outputs
.crc (crc[31:0]),
// Inputs
.clk (clk));
 
function [31:0] add_crc32;
input [7:0] add_byte;
input [31:0] prev_crc;
integer b, msb;
reg [31:0] tmp_crc;
begin
tmp_crc = prev_crc;
for (b = 0; b < 8; b = b + 1)
begin
msb = tmp_crc[31];
tmp_crc = tmp_crc << 1;
if (msb != add_byte[b])
begin
tmp_crc = tmp_crc ^ CRC32_POLY;
tmp_crc[0] = 1;
end
end
add_crc32 = tmp_crc;
end
endfunction // for
 
function [31:0] fixup_crc;
input [31:0] calc_crc;
reg [31:0] temp;
integer b;
begin
// Mirror:
for (b = 0; b < 32; b = b + 1)
temp[31-b] = calc_crc[b];
// Swap and Complement:
fixup_crc = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endfunction // for
 
/* -----\/----- EXCLUDED -----\/-----
// Copied from: http://www.mindspring.com/~tcoonan/gencrc.v
//
// Generate a (DOCSIS) CRC32.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter CRC32_POLY = 32'h04C11DB7;
// reg [ 7:0] crc32_packet[0:255];
// integer crc32_length;
//
// Globals modified:
// reg [31:0] crc32_result;
//
task gencrc32;
integer byte, bit;
reg msb;
reg [7:0] current_byte;
reg [31:0] temp;
begin
crc32_result = 32'hffffffff;
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
current_byte = crc32_packet[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_byte[bit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 32; bit = bit + 1)
temp[31-bit] = crc32_result[bit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
-----/\----- EXCLUDED -----/\----- */
 
always @(posedge clk)
begin
if (reset)
131,6 → 59,7
rxdv1 <= #1 0;
rxd2 <= #1 0;
rxdv2 <= #1 0;
pkt_crc <= #1 0;
end
else
begin
138,24 → 67,27
rxdv1 <= #1 gmii_rx_dv;
rxd2 <= #1 rxd1;
rxdv2 <= #1 rxdv1;
pkt_crc <= #1 nxt_pkt_crc;
end
end // always @ (posedge clk)
 
localparam s_idle = 0, s_preamble = 1, s_sop = 2, s_payload = 3, s_trunc = 4, s_sink = 5;
localparam s_idle = 0, s_preamble = 1, s_sop = 2, s_payload = 3, s_trunc = 4, s_sink = 5, s_eop = 6;
localparam ns_idle = 1, ns_preamble = 2, ns_sop = 4, ns_payload = 8, ns_trunc = 16, ns_sink = 32;
 
always @*
begin
nxt_calc_crc = calc_crc;
ic_srdy = 0;
ic_code = `PCC_DATA;
ic_data = 0;
nxt_valid_bits = valid_bits;
nxt_pkt_crc = pkt_crc;
crc_valid = 0;
crc_clear = 0;
 
case (1'b1)
state[s_idle] :
begin
nxt_calc_crc = {32{1'b1}};
crc_clear = 1;
nxt_pkt_crc = 0;
nxt_valid_bits = 0;
if (rxdv2 & (rxd2 == `GMII_SFD))
189,10 → 121,9
ic_srdy = 1;
ic_code = `PCC_SOP;
ic_data = rxd2;
crc_valid = 1;
nxt_pkt_crc = { rxd2, pkt_crc[31:8] };
nxt_state = ns_payload;
nxt_pkt_crc = { 24'h0, gmii_rxd };
nxt_valid_bits = 4'b0001;
//nxt_calc_crc = add_crc32 (gmii_rxd, calc_crc);
end
end // case: state[ns_payload]
 
202,18 → 133,12
nxt_state = ns_trunc;
else if (!rxdv1)
begin
nxt_state = ns_idle;
ic_srdy = 1;
//nxt_state = ns_idle;
ic_srdy = 0;
ic_data = rxd2;
//if ( { pkt_crc[23:0], rxd2 } == add_crc32 (rxd2, calc_crc))
`ifdef RX_CHECK_CRC
if ({ pkt_crc[23:0], rxd2 } == fixup_crc (calc_crc))
ic_code = `PCC_EOP;
else
ic_code = `PCC_BADEOP;
`else
ic_code = `PCC_EOP;
`endif
crc_valid = 1;
nxt_pkt_crc = { rxd2, pkt_crc[31:8] };
nxt_state = 1 << s_eop;
end
else
begin
220,13 → 145,27
ic_srdy = 1;
ic_code = `PCC_DATA;
ic_data = rxd2;
nxt_pkt_crc = { pkt_crc[23:0], rxd2 };
nxt_valid_bits = { valid_bits[2:0], 1'b1 };
if (valid_bits[2])
nxt_calc_crc = add_crc32 (pkt_crc[23:16], calc_crc);
crc_valid = 1;
nxt_pkt_crc = { rxd2, pkt_crc[31:8] };
end // else: !if(!rxdv1)
end // case: state[ns_payload]
 
 
state[s_eop] :
begin
ic_srdy =1;
ic_data = pkt_crc[31:24];
if (pkt_crc == crc)
begin
ic_code = `PCC_EOP;
end
else
ic_code = `PCC_BADEOP;
 
if (ic_drdy)
nxt_state = 1 << s_idle;
end
state[s_trunc] :
begin
ic_srdy = 1;
252,15 → 191,13
begin
state <= #1 1;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
calc_crc <= 32'h0;
pkt_crc <= 32'h0;
valid_bits <= 4'h0;
// End of automatics
// Beginning of autoreset for uninitialized flops
pkt_crc <= 32'h0;
valid_bits <= 4'h0;
// End of automatics
end
else
begin
calc_crc <= #1 nxt_calc_crc;
pkt_crc <= #1 nxt_pkt_crc;
state <= #1 nxt_state;
valid_bits <= #1 nxt_valid_bits;
/srdydrdy_lib/trunk/examples/bridge/rtl/sd_tx_gigmac.v
27,9 → 27,13
 
reg [7:0] nxt_gmii_txd;
reg nxt_gmii_tx_en;
reg [3:0] state, nxt_state;
reg [5:0] state, nxt_state;
 
localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3;
wire [31:0] crc;
reg clear;
reg crc_valid;
localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3, s_badcrc = 4, s_goodcrc = 5;
localparam ns_idle = 1, ns_preamble = 2, ns_payload = 4, ns_ipg = 8;
 
sd_input #(8+2) in_hold
45,6 → 49,17
.c_data ({txg_code,txg_data}),
.ip_drdy (ip_drdy));
 
mac_crc32 crcgen
(
.data (ip_data[7:0]),
.valid (crc_valid),
/*AUTOINST*/
// Outputs
.crc (crc[31:0]),
// Inputs
.clk (clk),
.clear (clear));
 
always @*
begin
ip_drdy = 0;
51,6 → 66,8
nxt_count = count;
nxt_gmii_tx_en = 0;
nxt_gmii_txd = gmii_txd;
clear = 0;
crc_valid = 0;
 
case (1'b1)
state[s_idle] :
61,6 → 78,7
nxt_gmii_txd = `GMII_PRE;
nxt_count = 1;
nxt_state = ns_preamble;
clear = 1;
end
else
begin
86,14 → 104,47
ip_drdy = 1;
nxt_gmii_tx_en = 1;
nxt_gmii_txd = ip_data;
crc_valid = 1;
if (!ip_srdy | ((ip_code == `PCC_EOP) | (ip_code == `PCC_BADEOP)))
begin
nxt_count = 0;
nxt_state = ns_ipg;
if (ip_code == `PCC_EOP)
nxt_state = 1 << s_goodcrc;
else
nxt_state = 1 << s_badcrc;
end
end // case: state[s_payload]
 
state[s_goodcrc] :
begin
nxt_count = count + 1;
nxt_gmii_tx_en = 1;
case (count)
0 : nxt_gmii_txd = crc[7:0];
1 : nxt_gmii_txd = crc[15:8];
2 : nxt_gmii_txd = crc[23:16];
3 : nxt_gmii_txd = crc[31:24];
endcase // case (count)
if (count == 3)
begin
nxt_state = 1 << s_ipg;
end
end
 
state[s_badcrc] :
begin
nxt_count = count + 1;
nxt_gmii_tx_en = 1;
nxt_gmii_txd = 8'h0;
if (count == 3)
begin
nxt_state = 1 << s_ipg;
end
end
 
state[s_ipg] :
begin
nxt_gmii_tx_en = 0;
/srdydrdy_lib/trunk/examples/bridge/rtl/mac_crc32.v
0,0 → 1,41
//----------------------------------------------------------------------
// 8-bit parallel CRC generator
//----------------------------------------------------------------------
 
module mac_crc32
(input clk,
input clear, // also functions as reset
input [7:0] data,
input valid,
 
output [31:0] crc);
 
reg [31:0] icrc;
reg [31:0] nxt_icrc;
integer i;
assign crc = ~icrc;
always @*
begin
nxt_icrc[7:0] = icrc[7:0] ^ data;
nxt_icrc[31:8] = icrc[31:8];
 
for (i=0; i<8; i=i+1)
begin
if (nxt_icrc[0])
nxt_icrc = nxt_icrc[31:1] ^ 32'hEDB88320;
else
nxt_icrc = nxt_icrc[31:1];
end
end // always @ *
always @(posedge clk)
begin
if (clear)
icrc <= #1 {32{1'b1}};
else if (valid)
icrc <= nxt_icrc;
end
 
endmodule
/srdydrdy_lib/trunk/examples/bridge/env/gmii_driver.v
21,6 → 21,35
forever rx_clk = #4 ~rx_clk;
end
 
task gencrc32;
input [7:0] length;
output [31:0] icrc;
reg [31:0] nxt_icrc;
integer i, len;
begin
icrc = {32{1'b1}};
for (len=0; len<length; len=len+1)
begin
nxt_icrc[7:0] = icrc[7:0] ^ rxbuf[len];
nxt_icrc[31:8] = icrc[31:8];
 
for (i=0; i<8; i=i+1)
begin
if (nxt_icrc[0])
nxt_icrc = nxt_icrc[31:1] ^ 32'hEDB88320;
else
nxt_icrc = nxt_icrc[31:1];
end
 
icrc = nxt_icrc;
end // for (len=0; len<length; len=len+1)
 
icrc = ~icrc;
end
endtask
/* -----\/----- EXCLUDED -----\/-----
// Copied from: http://www.mindspring.com/~tcoonan/gencrc.v
//
// Generate a (DOCSIS) CRC32.
66,6 → 95,7
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
-----/\----- EXCLUDED -----/\----- */
 
task print_packet;
input [31:0] length;
92,9 → 122,10
for (p=12; p<length; p=p+1)
rxbuf[p] = $random;
 
gencrc32 (length);
{ rxbuf[length-4], rxbuf[length-3],
rxbuf[length-2], rxbuf[length-1] } = crc32_result;
//gencrc32 (length);
gencrc32 (length, crc32_result);
{ rxbuf[length-1], rxbuf[length-2],
rxbuf[length-3], rxbuf[length-4] } = crc32_result;
 
$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length);
print_packet (length);
/srdydrdy_lib/trunk/examples/bridge/env/bridge.vf
19,6 → 19,7
../rtl/port_ring_tap.v
../rtl/sd_rx_gigmac.v
../rtl/sd_tx_gigmac.v
../rtl/mac_crc32.v
+libext+.v
-y ../../../rtl/verilog/buffers
-y ../../../rtl/verilog/closure

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