URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
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Rev 26 → Rev 27
/srdydrdy_lib/trunk/env/verilog/bpdrop/runsh
0,0 → 1,5
#!/bin/bash |
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iverilog -o bpdrop bench_bpdrop.v ../common/sd_seq_check.v ../common/sd_seq_gen.v ../../../rtl/verilog/utility/sd_bpdrop.v |
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/srdydrdy_lib/trunk/env/verilog/bpdrop/bench_bpdrop.v
0,0 → 1,87
`timescale 1ns/1ns |
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module bench_bpdrop; |
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reg clk, reset; |
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initial |
begin |
clk = 0; |
forever clk = #5 ~clk; |
end |
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wire a_srdy, a_drdy; |
wire [7:0] a_data; |
wire b_srdy, b_drdy; |
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wire fr_start, fr_end; |
assign fr_start = a_data[1:0] == 0; |
assign fr_end = a_data[1:0] == 3; |
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sd_seq_gen #(.width(8)) sgen |
( |
// Outputs |
.p_srdy (a_srdy), |
.p_data (a_data[7:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.p_drdy (a_drdy)); |
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sd_bpdrop #(.cnt_sz(4)) bpdrop |
( |
// Outputs |
.nc_drdy (a_drdy), |
.np_srdy (b_srdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.g_max_count (4'd5), |
.c_srdy (a_srdy), |
.c_fr_start (fr_start), |
.c_fr_end (fr_end), |
.p_drdy (b_drdy)); |
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sd_seq_check #(.width(8)) scheck |
( |
// Outputs |
.c_drdy (b_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (b_srdy), |
.c_data (a_data[7:0])); |
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initial |
begin |
`ifdef VCS |
$vcdpluson; |
`else |
$dumpfile("bench_bpdrop.vcd"); |
$dumpvars; |
`endif |
reset = 1; |
repeat (10) @(negedge clk); |
reset = 0; |
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// initial flow control to drop |
scheck.drdy_pat = 8'h1; |
sgen.send(64); |
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// still drop |
scheck.drdy_pat = 8'h7; |
sgen.send(64); |
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// pass |
scheck.drdy_pat = 8'h88; |
sgen.send(64); |
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#1000; |
$finish; |
end |
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endmodule // bench_bpdrop |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/utility/" "../common") |
// End: |