URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
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- This comparison shows the changes necessary to convert path
/srdydrdy_lib
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/rtl/verilog/forks/sd_mirror.v
36,7 → 36,8
input reset, |
|
input c_srdy, |
output reg c_drdy, |
//output reg c_drdy, |
output c_drdy, |
input [width-1:0] c_data, |
input [mirror-1:0] c_dst_vld, |
|
52,18 → 53,16
always @(posedge clk) |
if (load) |
p_data <= `SDLIB_DELAY c_data; |
|
|
assign c_drdy = (p_srdy == 0); |
|
always @* |
begin |
nxt_p_srdy = p_srdy; |
nxt_state = state; |
c_drdy = 0; |
load = 0; |
|
case (state) |
0 : |
if (p_srdy == {mirror{1'b0}}) |
begin |
c_drdy = 1'b1; |
if (c_srdy) |
begin |
if (c_dst_vld == {mirror{1'b0}}) |
70,21 → 69,13
nxt_p_srdy = {mirror{1'b1}}; |
else |
nxt_p_srdy = c_dst_vld; |
nxt_state = 1; |
load = 1; |
end |
end |
|
1 : |
begin |
nxt_p_srdy = p_srdy & ~p_drdy; |
|
if (p_srdy == {mirror{1'b0}}) |
begin |
nxt_state = 1'b0; |
end |
end |
endcase |
else |
begin |
nxt_p_srdy = p_srdy & ~p_drdy; |
end |
end |
|
always @(`SDLIB_CLOCKING) |
/trunk/rtl/verilog/buffers/sd_fifo_head_b.v
2,7 → 2,8
// Srdy/Drdy FIFO Head "B" |
// |
// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs |
// based around memories, with sizes that may not be a power of 2. |
// based around memories, with sizes that may not be a power of 2. This |
// FIFO has a limitation that at most (depth-1) entries may be used. |
// |
// The bound inputs allow multiple FIFO controllers to share a single |
// memory. The enable input is for arbitration between multiple FIFO |
54,7 → 55,7
reg full, nxt_full; |
reg [asz-1:0] nxt_com_wrptr; |
|
assign c_drdy = !full & enable; |
assign c_drdy = !nxt_full & enable; |
|
always @* |
begin |
65,14 → 66,24
else |
wrptr_p1 = cur_wrptr + 1; |
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empty = (cur_wrptr == rdptr) & !full; |
nxt_full = ((wrptr_p1 == rdptr) | (full & (cur_wrptr == rdptr))); |
//empty = (cur_wrptr == rdptr) & !full; |
empty = (cur_wrptr == rdptr); |
|
// special-case -- if we do abort on a full FIFO |
// force full flag to clear |
/* -----\/----- EXCLUDED -----\/----- |
if ((commit == 1) && c_abort && full) |
nxt_full = 0; |
else |
nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr))); |
-----/\----- EXCLUDED -----/\----- */ |
nxt_full = (wrptr_p1 == rdptr); |
|
if ((commit == 1) && c_abort) |
begin |
nxt_wrptr = com_wrptr; |
end |
else if (enable & c_srdy & !full) |
else if (enable & c_srdy & !nxt_full) |
begin |
nxt_wrptr = wrptr_p1; |
mem_we = 1; |
103,7 → 114,7
begin |
always @* |
begin |
if (enable & c_commit & !c_abort & c_srdy & !full) |
if (enable & c_commit & !c_abort & c_srdy & !nxt_full) |
nxt_com_wrptr = wrptr_p1; |
else |
nxt_com_wrptr = com_wrptr; |
/trunk/rtl/verilog/buffers/sd_fifo_s.v
37,7 → 37,7
input p_reset, |
output p_srdy, |
input p_drdy, |
output reg [width-1:0] p_data |
output [width-1:0] p_data |
); |
|
localparam asz = $clog2(depth); |
48,15 → 48,26
wire [asz:0] rdptr_tail, rdptr_tail_sync; |
wire wr_en; |
wire [asz:0] wrptr_head, wrptr_head_sync; |
reg dly_rd_en; |
wire [asz-1:0] rd_addr, wr_addr; |
|
/* -----\/----- EXCLUDED -----\/----- |
always @(posedge c_clk) |
if (wr_en) |
mem[wr_addr] <= `SDLIB_DELAY c_data; |
|
assign mem_rddata = mem[rd_addr]; |
-----/\----- EXCLUDED -----/\----- */ |
behave2p_mem #(width, depth) mem2p |
(.d_out (p_data), |
.wr_en (wr_en), |
.rd_en (rd_en), |
.wr_clk (c_clk), |
.wr_addr (wr_addr), |
.rd_clk (p_clk), |
.rd_addr (rd_addr), |
.d_in (c_data)); |
|
|
sd_fifo_head_s #(depth, async) head |
( |
// Outputs |
83,11 → 94,13
.wrptr_head (wrptr_head_sync), |
.p_drdy (p_drdy)); |
|
/* -----\/----- EXCLUDED -----\/----- |
always @(posedge p_clk) |
begin |
if (rd_en) |
p_data <= `SDLIB_DELAY mem_rddata; |
end |
-----/\----- EXCLUDED -----/\----- */ |
|
generate |
if (async) |
/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
228,7 → 228,7
|
always @* |
begin |
if (p_commit) |
if (p_commit & p_srdy & p_drdy) |
nxt_com_rdptr = p_rdaddr; |
else |
nxt_com_rdptr = com_rdptr; |
/trunk/env/verilog/bench_fifo_b.v
4,11 → 4,13
|
reg clk, reset; |
|
localparam width = 8, depth=256, asz=$clog2(depth); |
localparam width = 16, depth=32, asz=$clog2(depth); |
|
initial clk = 0; |
always #10 clk = ~clk; |
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reg gen_commit, gen_abort; |
reg chk_commit, chk_abort; |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [width-1:0] chk_data; // From fifo_s of sd_fifo_b.v |
25,7 → 27,7
.p_\(.*\) (gen_\1[]), |
); |
*/ |
sd_seq_gen gen |
sd_seq_gen #(width) gen |
(/*AUTOINST*/ |
// Outputs |
.p_srdy (gen_srdy), // Templated |
40,7 → 42,7
.c_\(.*\) (chk_\1[]), |
); |
*/ |
sd_seq_check chk |
sd_seq_check #(width) chk |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (chk_drdy), // Templated |
56,7 → 58,7
.c_\(.*\) (gen_\1[]), |
); |
*/ |
sd_fifo_b #(width, depth) fifo_s |
sd_fifo_b #(width, depth, 1, 1) fifo_s |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (gen_drdy), // Templated |
79,9 → 81,26
$dumpfile("fifo_b.vcd"); |
$dumpvars; |
reset = 1; |
gen.rep_count = 0; |
gen_commit = 0; |
gen_abort = 0; |
chk_commit = 1; |
chk_abort = 0; |
#100; |
reset = 0; |
repeat (5) @(posedge clk); |
|
//test1(); |
//test2(); |
test3(); |
end // initial begin |
|
// test basic overflow/underflow |
task test1; |
begin |
gen_commit = 1; |
gen.rep_count = 2000; |
|
// burst normal data for 50 cycles |
repeat (50) @(posedge clk); |
|
102,7 → 121,108
#5000; |
$finish; |
end |
endtask // test1 |
|
// test of write commit/abort behavior |
task test2; |
begin |
// first fill up entire FIFO |
gen.send (depth-1); |
#50; |
|
wait (gen_drdy == 0); |
@(posedge clk); |
gen_abort <= #1 1; |
|
@(posedge clk); |
gen_abort <= #1 0; |
#5; |
if (gen_drdy !== 1) |
begin |
$display ("ERROR -- drdy should be asserted on empty FIFO"); |
#100 $finish; |
end |
|
|
gen.send (depth-2); |
@(posedge clk); |
gen_commit <= 1; |
gen.send (1); |
gen_commit <= 0; |
|
repeat (depth+10) |
@(posedge clk); |
|
if (chk.last_seq != (depth*2-2)) |
begin |
$display ("ERROR -- last sequence number incorrect (%x)", chk.last_seq); |
$finish; |
end |
|
|
#5000; |
$finish; |
end |
endtask // test2 |
|
// test read/commit behavior |
task test3; |
begin |
// fill up FIFO |
gen_commit <= 1; |
chk_commit <= 0; |
chk_abort <= 0; |
|
@(negedge clk); |
chk.drdy_pat = 0; |
chk.c_drdy = 0; |
chk.nxt_c_drdy = 0; |
|
repeat (10) @(posedge clk); |
gen.send (depth-1); |
|
// read out contents of FIFO |
chk.drdy_pat = 8'h5A; |
|
repeat (depth*2+2) |
@(posedge clk); |
chk.drdy_pat = 0; |
|
// FIFO should be full at this point to write side, and empty to |
// read side |
if (gen_drdy || chk_srdy) |
begin |
$display ("ERROR -- c_drdy or p_srdy asserted"); |
#100 $finish; |
end |
|
// reset the read pointer and the expected value |
chk.last_seq = 0; |
chk_abort <= #1 1; |
@(posedge clk); |
chk_abort <= #1 0; |
|
// read out contents of FIFO again |
chk.drdy_pat = 8'hFF; |
|
@(posedge clk); |
repeat (depth-3) @(posedge clk); |
chk_commit <= #1 1; |
repeat (4) @(posedge clk); |
chk_commit <= #1 0; |
|
// All data has been committed, so drdy should be asserted |
if (gen_drdy) |
begin |
$display ("ERROR -- c_drdy not asserted"); |
#100 $finish; |
end |
#500; |
$finish; |
|
end |
endtask |
|
endmodule // bench_fifo_s |
// Local Variables: |
// verilog-library-directories:("." "../../rtl/verilog/buffers") |
/trunk/env/verilog/bench_fifo_s.v
82,6 → 82,8
#100; |
reset = 0; |
|
gen.rep_count = 1000; |
|
// burst normal data for 20 cycles |
repeat (20) @(posedge clk); |
|
/trunk/env/verilog/sd_seq_gen.v
31,6 → 31,7
|
reg [pat_dep-1:0] srdy_pat; |
integer spp, startup; |
integer rep_count; |
|
initial |
begin |
37,6 → 38,7
srdy_pat = {pat_dep{1'b1}}; |
spp = 0; |
startup = 0; |
rep_count = 0; |
end |
|
always @* |
44,12 → 46,10
nxt_p_data = p_data; |
nxt_p_srdy = p_srdy; |
|
if (startup < 10) |
if (p_srdy & p_drdy) |
begin |
end |
else if (p_srdy & p_drdy) |
begin |
if (srdy_pat[spp]) |
|
if (srdy_pat[spp] && (rep_count > 1)) |
begin |
nxt_p_data = p_data + 1; |
nxt_p_srdy = 1; |
56,8 → 56,8
end |
else |
nxt_p_srdy = 0; |
end |
else if (!p_srdy) |
end // if (p_srdy & p_drdy) |
else if (!p_srdy && (rep_count != 0)) |
begin |
if (srdy_pat[spp]) |
begin |
73,6 → 73,12
begin |
if ((p_srdy & p_drdy) | !p_srdy) |
spp = (spp + 1) % pat_dep; |
|
if (p_srdy & p_drdy) |
begin |
if (rep_count != -1) |
rep_count = rep_count - 1; |
end |
end |
|
always @(posedge clk) |
86,9 → 92,18
begin |
p_srdy <= `SDLIB_DELAY nxt_p_srdy; |
p_data <= `SDLIB_DELAY nxt_p_data; |
if (startup < 10) |
startup = startup + 1; |
end |
end // always @ (posedge clk) |
|
// simple blocking task to send N words and then wait until complete |
task send; |
input [31:0] amount; |
begin |
rep_count = amount; |
@(posedge clk); |
while (rep_count != 0) |
@(posedge clk); |
end |
endtask |
|
endmodule // sd_seq_gen |
/trunk/env/verilog/bench_fifo_s.vf
4,3 → 4,5
../../rtl/verilog/buffers/sd_fifo_s.v |
../../rtl/verilog/buffers/sd_fifo_head_s.v |
../../rtl/verilog/buffers/sd_fifo_tail_s.v |
../../rtl/verilog/memory/behave2p_mem.v |
|
/trunk/examples/bridge/env/run
3,12 → 3,11
TESTNAME=$1 |
shift |
|
which vcs &> /dev/null |
if [ "$?" == "-1" ]; then |
iverilog -f bridge.vf tests/$TESTNAME.v $* |
./a.out |
which iverilog &> /dev/null |
if [ "$?" == "0" ]; then |
iverilog -f bridge.vf tests/$TESTNAME.v $* |
./a.out |
else |
vcs -full64 +v2k -R -I -f bridge.vf tests/$TESTNAME.v $* |
#vcd2vpd env_top.vcd env_top.vpd |
vcs -full64 +v2k -R -I -f bridge.vf tests/$TESTNAME.v $* |
fi |
|