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Rev 17 → Rev 18

/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v
0,0 → 1,160
//----------------------------------------------------------------------
// Scoreboard FSM
//
// Keeps track of data regarding N items. Allows multiple entities
// to track data about a particular item. Supports masked writes,
// allowing only part of a record to be updated by a particular
// transaction.
//
// If masks are enabled,
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks. Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
`define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
`define SDLIB_DELAY #1
`endif
 
module sd_scoreboard_fsm
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
 
input ip_srdy,
output reg ip_drdy,
input ip_req_type, // 0=read, 1=write
input [txid_sz-1:0] ip_txid,
input [width-1:0] ip_mask,
input [width-1:0] ip_data,
input [asz-1:0] ip_itemid,
 
output reg ic_srdy,
input ic_drdy,
output reg [txid_sz-1:0] ic_txid,
output reg [width-1:0] ic_data,
 
input [width-1:0] d_out,
output reg wr_en,
output reg rd_en,
output reg [width-1:0] d_in,
output reg [asz-1:0] addr
);
 
localparam s_idle = 0, s_read = 1, s_rdmod = 2;
reg [2:0] state, nxt_state;
reg [txid_sz-1:0] txid, nxt_txid;
 
always @*
begin
ip_drdy = 0;
ic_srdy = 0;
ic_data = 0;
wr_en = 0;
rd_en = 0;
d_in = 0;
addr = ip_itemid;
nxt_state = state;
nxt_txid = txid;
if (use_txid)
ic_txid = txid;
else
ic_txid = 0;
 
nxt_state[s_read] = 0;
if (state[s_idle])
begin
if (ip_srdy & (ip_req_type==1))
begin
if ((use_mask==0) | (ip_mask=={width{1'b1}}))
begin
ip_drdy = 1;
wr_en = 1;
d_in = ip_data;
end
else
begin
rd_en = 1;
nxt_state[s_rdmod] = 1;
nxt_state[s_idle] = 0;
end
end
else if (ip_srdy & (ip_req_type==0) & (!state[s_read] | ic_drdy))
begin
rd_en = 1;
nxt_state[s_read] = 1;
nxt_txid = ip_txid;
ip_drdy = 1;
end
end // case: s_idle
 
if (state[s_read])
begin
ic_srdy = 1;
ic_data = d_out;
if (!ic_drdy)
begin
nxt_state[s_read] = 1;
//nxt_state[s_idle] = 1;
end
end // case: state[s_read]
 
if (state[s_rdmod])
begin
ip_drdy = 1;
d_in = (d_out & ~ip_mask) | (ip_data & ip_mask);
wr_en = 1;
 
nxt_state[s_rdmod] = 0;
nxt_state[s_idle] = 1;
end
end // always @ *
 
 
always @(`SDLIB_CLOCKING)
begin
if (reset)
begin
state <= `SDLIB_DELAY 1;
end
else
begin
state <= `SDLIB_DELAY nxt_state;
end
end // always @ (`SDLIB_CLOCKING)
 
generate
if (use_txid != 0)
begin : gen_txid_hold
always @(`SDLIB_CLOCKING)
begin
if (reset)
begin
txid <= `SDLIB_DELAY 0;
end
else
begin
txid <= `SDLIB_DELAY nxt_txid;
end
end // always @ (`SDLIB_CLOCKING)
end // block: gen_txid_hold
endgenerate
 
endmodule // sd_scoreboard_fsm
/trunk/rtl/verilog/utility/sd_scoreboard.v
0,0 → 1,131
//----------------------------------------------------------------------
// Scoreboard
//
// Keeps track of data regarding N items. Allows multiple entities
// to track data about a particular item. Supports masked writes,
// allowing only part of a record to be updated by a particular
// transaction.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
module sd_scoreboard
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
 
input c_srdy,
output c_drdy,
input c_req_type, // 0=read, 1=write
input [txid_sz-1:0] c_txid,
input [width-1:0] c_mask,
input [width-1:0] c_data,
input [asz-1:0] c_itemid,
 
output p_srdy,
input p_drdy,
output [txid_sz-1:0] p_txid,
output [width-1:0] p_data
);
 
localparam tot_in_sz = width*2+txid_sz+asz+1;
wire ip_req_type; // 0=read, 1=write
wire [txid_sz-1:0] ip_txid;
wire [width-1:0] ip_mask;
wire [width-1:0] ip_data;
wire [asz-1:0] ip_itemid;
wire [txid_sz-1:0] ic_txid;
wire [width-1:0] ic_data;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [asz-1:0] addr; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_in; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_out; // From sb_mem of behave1p_mem.v
wire ic_drdy; // From outhold of sd_output.v
wire ic_srdy; // From fsm of sd_scoreboard_fsm.v
wire ip_drdy; // From fsm of sd_scoreboard_fsm.v
wire ip_srdy; // From inhold of sd_input.v
wire rd_en; // From fsm of sd_scoreboard_fsm.v
wire wr_en; // From fsm of sd_scoreboard_fsm.v
// End of automatics
 
sd_input #(.width(tot_in_sz)) inhold
(
.c_data ({c_txid,c_req_type,c_itemid,c_mask,c_data}),
.ip_data ({ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data}),
/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
.ip_srdy (ip_srdy),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.ip_drdy (ip_drdy));
 
behave1p_mem #(.depth(items), .width(width)) sb_mem
(
.addr (addr[asz-1:0]),
/*AUTOINST*/
// Outputs
.d_out (d_out[width-1:0]),
// Inputs
.wr_en (wr_en),
.rd_en (rd_en),
.clk (clk),
.d_in (d_in[width-1:0]));
 
sd_scoreboard_fsm #(width,items,use_txid,use_mask,txid_sz) fsm
(/*AUTOINST*/
// Outputs
.ip_drdy (ip_drdy),
.ic_srdy (ic_srdy),
.ic_txid (ic_txid[txid_sz-1:0]),
.ic_data (ic_data[width-1:0]),
.wr_en (wr_en),
.rd_en (rd_en),
.d_in (d_in[width-1:0]),
.addr (addr[asz-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.ip_srdy (ip_srdy),
.ip_req_type (ip_req_type),
.ip_txid (ip_txid[txid_sz-1:0]),
.ip_mask (ip_mask[width-1:0]),
.ip_data (ip_data[width-1:0]),
.ip_itemid (ip_itemid[asz-1:0]),
.ic_drdy (ic_drdy),
.d_out (d_out[width-1:0]));
 
sd_output #(.width(width+txid_sz)) outhold
(
.p_data ({p_txid,p_data}),
.ic_data ({ic_txid,ic_data}),
/*AUTOINST*/
// Outputs
.ic_drdy (ic_drdy),
.p_srdy (p_srdy),
// Inputs
.clk (clk),
.reset (reset),
.ic_srdy (ic_srdy),
.p_drdy (p_drdy));
 
endmodule // sd_scoreboard
// Local Variables:
// verilog-library-directories:("." "../closure" "../memory")
// End:
 
/trunk/rtl/verilog/utility/sd_ring_node.v
0,0 → 1,153
//----------------------------------------------------------------------
// Single Cycle RING Node [sd_ring_node]
//
// Halts timing on all interfaces, no combinational passthrough
// Inputs are used unregistered
// All outputs are registered
// Four Interfaces
// RP -> Ring Previous : Ring data arrives on this interface
// RP -> Ring Next : Ring Data leaves on this interface
// P -> Producer : Destination offload interface
// C -> Consumer : Data Injection Interface
//----------------------------------------------------------------------
//
// Author: Awais Nemat
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
module sd_ring_node
#(parameter data_width = 8,
parameter addr_width = 8,
parameter my_addr = 8'h1)
(
input clk,
input reset,
 
input rp_srdy,
output rp_drdy,
input [data_width-1:0] rp_data,
input [addr_width-1:0] rp_addr,
 
output rn_srdy,
input rn_drdy,
output [data_width-1:0] rn_data,
output [addr_width-1:0] rn_addr,
 
input c_srdy,
output c_drdy,
input [data_width-1:0] c_data,
input [addr_width-1:0] c_addr,
output p_srdy,
input p_drdy,
output [data_width-1:0] p_data,
output [addr_width-1:0] p_addr
);
 
// All Combinational Signals
// reg's are functions of other signals
// NOT registered though
wire rp_srdy_o;
reg rp_drdy_i;
wire [data_width-1:0] rp_data_o;
wire [addr_width-1:0] rp_addr_o;
 
reg rn_srdy_i;
wire rn_drdy_o;
 
wire s_srdy_o;
reg s_drdy_i;
wire [data_width-1:0] s_data_o;
wire [addr_width-1:0] s_addr_o;
reg d_srdy_i;
wire d_drdy_o;
wire [data_width-1:0] d_data_i = rp_data_o;
wire [addr_width-1:0] d_addr_i = rp_addr_o;
 
reg d; // Asserted if address matches
reg [data_width-1:0] data_o; // Mux Selected Data, S:RP
reg [addr_width-1:0] addr_o; // Mux Selected Adda, S:RP
always @*
begin
// Compute if this module is the Destination
d = rp_srdy_o & (rp_addr_o == my_addr);
 
// Pop data from RP destined to this instance when space is available in 'D'
// OR when not destined to this instance and space is available in RN
rp_drdy_i = (d) ? d_drdy_o : rn_drdy_o ;
 
// Indicate data availability to RN, when S has data OR when RP has
// data that is NOT Destined to D
rn_srdy_i = s_srdy_o | (rp_srdy_o & ~d);
 
// Indicate data availability to D, when it becomes available in RP
// and it is destined to this instance
d_srdy_i = rp_srdy_o & d;
 
// Indicate space availability to S, when it becomes available is RN
// and there is not Data in RP that needs to be passed on to RN.
 
if ( d & rp_srdy_o & rn_drdy_o ) s_drdy_i = 1;
// Exception: When data in RP is destined to this instance and
// space in RN is available, S could transmit to RN
else if ( rp_srdy_o & rn_drdy_o ) s_drdy_i = 0;
// When Data is present in RP and is NOT destined to this instance
// S cannot transmit to RN. RP has absolute priority over S
else if (rn_drdy_o) s_drdy_i = 1;
// No Data is Present in RP and RN has space, S could transmit
else s_drdy_i = 0;
// this is the default behaviour <MAY CHANGE; DEADLOCK?>
 
// Mux the Data and the Address
data_o = (s_drdy_i) ? s_data_o : rp_data_o;
addr_o = (s_drdy_i) ? s_addr_o : rp_addr_o;
 
end
 
// Instantiate the primitives
 
sd_output #(.width (data_width+addr_width))
RN_i0 (.clk(clk),
.reset (reset),
.srdy_in(rn_srdy_i),
.drdy_in(rn_drdy_o),
.data_in({addr_o,data_o}),
.srdy_out(rn_srdy),
.drdy_out(rn_drdy),
.data_out({rn_addr,rn_data}));
sd_output #(.width (data_width+addr_width))
D_i0 (.clk(clk),
.reset (reset),
.srdy_in(d_srdy_i),
.drdy_in(d_drdy_o),
.data_in({d_addr_i,d_data_i}),
.srdy_out(p_srdy),
.drdy_out(p_drdy),
.data_out({p_addr,p_data}));
sd_input #(.width (data_width+addr_width))
RP_i0 (.clk(clk),
.reset (reset),
.srdy_in(rp_srdy),
.drdy_in(rp_drdy),
.data_in({rp_addr,rp_data}),
.srdy_out(rp_srdy_o),
.drdy_out(rp_drdy_i),
.data_out({rp_addr_o,rp_data_o}));
sd_input #(.width (data_width+addr_width))
S_i0 (.clk(clk),
.reset (reset),
.srdy_in(c_srdy),
.drdy_in(c_drdy),
.data_in({c_addr,c_data}),
.srdy_out(s_srdy_o),
.drdy_out(s_drdy_i),
.data_out({s_addr_o,s_data_o}));
 
endmodule
/trunk/rtl/verilog/forks/sd_rrslow.v
51,6 → 51,7
output [inputs-1:0] c_drdy,
 
output reg [width-1:0] p_data,
output [inputs-1:0] p_grant,
output reg p_srdy,
input p_drdy
);
67,6 → 68,7
wire trig_pattern;
 
assign c_drdy = rr_state & {inputs{p_drdy}};
assign p_grant = rr_state;
generate
for (i=0; i<inputs; i=i+1)
/trunk/rtl/verilog/forks/sd_ajoin2.v
0,0 → 1,95
//----------------------------------------------------------------------
// Srdy/drdy assymetric join
//
// Performs assymetric join of 2 inputs by concatination. Efficiency
// of 0.5.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks. Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
`define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
`define SDLIB_DELAY #1
`endif
 
module sd_ajoin2
#(parameter c1_width=8,
parameter c2_width=8)
(
input clk;
input reset,
input c1_srdy,
output c1_drdy,
input [c1_width-1:0] c1_data,
 
input c2_srdy,
output c2_drdy,
input [c2_width-1:0] c2_data,
output p_srdy,
input p_drdy,
output reg [c1_width+c2_width-1:0] p_data
);
reg [c1_width+c2_width-1:0] nxt_p_data;
 
reg [1:0] in_drdy, nxt_in_drdy;
 
assign {c2_drdy,c1_drdy} = in_drdy;
 
always @*
begin
nxt_p_data = p_data;
nxt_in_drdy = in_drdy;
if (in_drdy[0])
begin
if (c1_srdy)
begin
nxt_in_drdy[0] = 0;
nxt_p_data[c1_width-1:0] = c1_data;
end
end
else if (p_srdy & p_drdy)
nxt_in_drdy[0] = 1;
 
if (in_drdy[1])
begin
if (c2_srdy)
begin
nxt_in_drdy[1] = 0;
nxt_p_data[c2_width+c1_width-1:c1_width] = c2_data;
end
end
else if (p_srdy & p_drdy)
nxt_in_drdy[1] = 1;
end
always @(`SDLIB_CLOCKING)
begin
if (reset)
begin
in_drdy <= `SDLIB_DELAY 2'b11;
p_data <= `SDLIB_DELAY 0;
end
else
begin
in_drdy <= `SDLIB_DELAY nxt_in_drdy;
p_data <= `SDLIB_DELAY nxt_p_data;
end // else: !if(reset)
end // always @ (posedge clk)
 
assign p_srdy = & (~in_drdy);
endmodule // it_output
/trunk/env/verilog/scoreboard/sb_monitor.v
0,0 → 1,52
// combination refmodel/monitor for scoreboard
 
module sb_monitor
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
 
input c_srdy,
input c_drdy,
input c_req_type, // 0=read, 1=write
input [txid_sz-1:0] c_txid,
input [width-1:0] c_mask,
input [width-1:0] c_data,
input [asz-1:0] c_itemid,
 
input p_srdy,
output reg p_drdy,
input [txid_sz-1:0] p_txid,
input [width-1:0] p_data
);
 
reg [width-1:0] sbmem [0:items-1];
 
always @(posedge clk)
begin
if (c_srdy & c_drdy & (c_req_type == 1))
begin
sbmem[c_itemid] <= #20 (sbmem[c_itemid] & ~c_mask) | (c_data & c_mask);
end
 
if (p_srdy & p_drdy)
begin
if (p_data != sbmem[p_txid])
begin
$display ("%t: ERROR: sb returned %x, expected %x",
$time, p_data, sbmem[p_txid]);
end
end
end
initial
begin
p_drdy = 1;
end
 
endmodule // sb_monitor
/trunk/env/verilog/scoreboard/sb_driver.v
0,0 → 1,147
//----------------------------------------------------------------------
// Srdy/Drdy sequence generator
//
// Simplistic traffic generator for srdy/drdy blocks. Generates an
// incrementing data sequence.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
`define SDLIB_DELAY #1
`endif
 
module sb_driver
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
output reg p_srdy,
input p_drdy,
output reg p_req_type, // 0=read, 1=write
output reg [txid_sz-1:0] p_txid,
output reg [width-1:0] p_mask,
output reg [asz-1:0] p_itemid,
output reg [width-1:0] p_data);
 
/* -----\/----- EXCLUDED -----\/-----
parameter pat_dep = 8;
 
reg [pat_dep-1:0] srdy_pat;
integer spp, startup;
integer rep_count;
 
initial
begin
srdy_pat = {pat_dep{1'b1}};
spp = 0;
startup = 0;
rep_count = 0;
end
 
always @*
begin
nxt_p_data = p_data;
nxt_p_srdy = p_srdy;
nxt_p_req_type = p_req_type;
if (p_srdy & p_drdy)
begin
 
if (srdy_pat[spp] && (rep_count > 1))
begin
nxt_p_data = p_data + 1;
nxt_p_srdy = 1;
end
else
nxt_p_srdy = 0;
end // if (p_srdy & p_drdy)
else if (!p_srdy && (rep_count != 0))
begin
if (srdy_pat[spp])
begin
nxt_p_data = p_data + 1;
nxt_p_srdy = 1;
end
else
nxt_p_srdy = 0;
end
end // always @ *
 
always @(posedge clk)
begin
if ((p_srdy & p_drdy) | !p_srdy)
spp = (spp + 1) % pat_dep;
 
if (p_srdy & p_drdy)
begin
if (rep_count != -1)
rep_count = rep_count - 1;
end
end
 
always @(posedge clk)
begin
if (reset)
begin
p_srdy <= `SDLIB_DELAY 0;
p_data <= `SDLIB_DELAY 0;
end
else
begin
p_srdy <= `SDLIB_DELAY nxt_p_srdy;
p_data <= `SDLIB_DELAY nxt_p_data;
end
end // always @ (posedge clk)
-----/\----- EXCLUDED -----/\----- */
 
initial
begin
p_srdy <= #1 0;
p_req_type <= #1 0;
p_txid <= #1 0;
p_mask <= #1 0;
p_itemid <= #1 0;
p_data <= #1 0;
end
 
task send;
input req_type;
//input [txid_sz-1:0] txid;
input [width-1:0] mask;
input [width-1:0] data;
input [asz-1:0] itemid;
begin
p_srdy <= #1 1;
//input p_drdy,
p_req_type <= #1 req_type;
p_txid <= #1 itemid;
p_mask <= #1 mask;
p_itemid <= #1 itemid;
p_data <= #1 data;
@(negedge clk);
if (p_drdy)
begin
@(posedge clk);
p_srdy <= #1 0;
end
else
begin
while (!p_drdy)
@(posedge clk);
p_srdy <= #1 0;
end
end
endtask
 
endmodule // sb_driver
/trunk/env/verilog/scoreboard/run
0,0 → 1,11
#!/bin/bash
 
which iverilog &> /dev/null
if [ "$?" == "0" ]; then
rm -f a.out
iverilog -f scoreboard.vf $*
./a.out -lxt
else
vcs -full64 +v2k -R -I -f scoreboard.vf $*
fi
 
/trunk/env/verilog/scoreboard/sb_bench.v
0,0 → 1,179
`timescale 1ns/1ns
 
module sb_bench;
 
localparam width = 32;
localparam items = 32;
localparam use_txid = 1;
localparam use_mask = 1;
localparam asz=$clog2(items);
localparam txid_sz = asz;
 
reg clk, reset;
wire p_drdy = 1'b1;
 
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] c_data; // From driver of sb_driver.v
wire c_drdy; // From sboard of sd_scoreboard.v
wire [asz-1:0] c_itemid; // From driver of sb_driver.v
wire [width-1:0] c_mask; // From driver of sb_driver.v
wire c_req_type; // From driver of sb_driver.v
wire c_srdy; // From driver of sb_driver.v
wire [txid_sz-1:0] c_txid; // From driver of sb_driver.v
wire [width-1:0] p_data; // From sboard of sd_scoreboard.v
wire p_srdy; // From sboard of sd_scoreboard.v
wire [txid_sz-1:0] p_txid; // From sboard of sd_scoreboard.v
// End of automatics
 
/* sb_driver AUTO_TEMPLATE
(
.p_\(.*\) (c_\1[]),
);
*/
sb_driver #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) driver
(/*AUTOINST*/
// Outputs
.p_srdy (c_srdy), // Templated
.p_req_type (c_req_type), // Templated
.p_txid (c_txid[txid_sz-1:0]), // Templated
.p_mask (c_mask[width-1:0]), // Templated
.p_itemid (c_itemid[asz-1:0]), // Templated
.p_data (c_data[width-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.p_drdy (c_drdy)); // Templated
/* sd_scoreboard AUTO_TEMPLATE
(
);
*/
sd_scoreboard #(
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz)) sboard
(/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_drdy (p_drdy));
 
sb_monitor #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) monitor
(/*AUTOINST*/
// Outputs
.p_drdy (p_drdy),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_drdy (c_drdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]));
 
/* -----\/----- EXCLUDED -----\/-----
task send;
input req_type;
input [txid_sz-1:0] txid;
input [width-1:0] mask;
input [width-1:0] data;
input [asz-1:0] itemid;
-----/\----- EXCLUDED -----/\----- */
integer i, entry;
integer op;
initial
begin
`ifdef VCS
$vcdpluson;
`else
$dumpfile ("sb.lxt");
$dumpvars;
`endif
reset = 1;
#200;
reset = 0;
 
repeat (5) @(posedge clk);
 
// fill up scoreboard with random data
for (i=0; i<items; i=i+1)
begin
driver.send (1, {width{1'b1}}, $random, i);
end
 
// request random entries from scoreboard
for (i=0; i<64; i=i+1)
begin
entry = {$random} % items;
driver.send (0, 0, 0, entry);
end
 
// mix updates with requests
for (i=0; i<1024; i=i+1)
begin
entry = {$random} % items;
 
op = {$random} % 8;
 
if (op == 0)
driver.send (1, {width{1'b1}}, $random, entry);
else if (op == 1)
driver.send (1, $random, $random, entry);
else
driver.send (0, 0, 0, entry);
end
#500;
$finish;
end
endmodule // sb_bench
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/utility")
// End:
 
/trunk/env/verilog/scoreboard/scoreboard.vf
0,0 → 1,9
sb_bench.v
sb_driver.v
sb_monitor.v
../../../rtl/verilog/utility/sd_scoreboard.v
../../../rtl/verilog/utility/sd_scoreboard_fsm.v
+libext+.v
-y ../../../rtl/verilog/closure/
-y ../../../rtl/verilog/memory
 

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