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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib
    from Rev 18 to Rev 19
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Rev 18 → Rev 19

/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v
81,7 → 81,11
if (state[s_idle])
begin
if (ip_srdy & (ip_req_type==1))
if (state[s_read] & !ic_drdy)
begin
// output is busy, stall
end
else if (ip_srdy & (ip_req_type==1))
begin
if ((use_mask==0) | (ip_mask=={width{1'b1}}))
begin
96,7 → 100,7
nxt_state[s_idle] = 0;
end
end
else if (ip_srdy & (ip_req_type==0) & (!state[s_read] | ic_drdy))
else if (ip_srdy & (ip_req_type==0))
begin
rd_en = 1;
nxt_state[s_read] = 1;
/trunk/rtl/verilog/memory/behave1p_mem.v
38,4 → 38,15
 
assign d_out = array[r_addr];
 
genvar g;
 
generate
for (g=0; g<depth; g=g+1)
begin : breakout
wire [width-1:0] brk;
 
assign brk=array[g];
end
endgenerate
 
endmodule
/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v
57,7 → 57,7
output reg mem_re,
input mem_we,
 
output reg [usz:0] p_usage,
output reg [usz-1:0] p_usage,
output p_srdy,
input p_drdy,
105,8 → 105,6
nxt_cur_rdptr = com_rdptr;
mem_re = 0;
end
// else if (enable & !empty & (!valid_a | (!prev_re & !valid_b) |
// (valid_a & valid_b & p_drdy)))
else if (enable & !empty & ip_drdy)
begin
nxt_cur_rdptr = cur_rdptr_p1;
126,42 → 124,9
p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
end // always @ *
 
/* -----\/----- EXCLUDED -----\/-----
// alternate usage calc
reg [asz-1:0] prev_wr;
reg [asz:0] usage2, nxt_usage2;
wire lcl_wr_en;
//assign lcl_wr_en = (prev_wr0 != wrptr[0]);
always @(posedge clk)
begin
if (reset)
begin
/-*AUTORESET*-/
// Beginning of autoreset for uninitialized flops
usage2 <= {(1+(asz)){1'b0}};
// End of automatics
end
else
begin
usage2 <= #1 nxt_usage2;
end
end
always @*
begin
if (mem_re & !mem_we)
nxt_usage2 = usage2 - 1;
else if (!mem_re & mem_we)
nxt_usage2 = usage2 + 1;
else
nxt_usage2 = usage2;
end
-----/\----- EXCLUDED -----/\----- */
 
always @(posedge clk)
begin
if (reset)
cur_rdptr <= `SDLIB_DELAY bound_low;
else
cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
/trunk/rtl/verilog/buffers/sd_fifo_b.v
25,7 → 25,8
parameter depth=256,
parameter rd_commit=0,
parameter wr_commit=0,
parameter asz=$clog2(depth)
parameter asz=$clog2(depth),
parameter usz=$clog2(depth+1)
)
(
input clk,
43,8 → 44,8
input p_abort,
output [width-1:0] p_data,
 
output [asz:0] p_usage,
output [asz:0] c_usage
output [usz-1:0] p_usage,
output [usz-1:0] c_usage
);
 
wire [asz-1:0] com_rdptr; // From tail of sd_fifo_tail_b.v
54,7 → 55,6
wire [width-1:0] mem_rd_data;
wire mem_re; // From tail of sd_fifo_tail_b.v
wire mem_we; // From head of sd_fifo_head_b.v
wire [asz:0] usage; // From tail of sd_fifo_tail_b.v
wire [asz-1:0] bound_high;
 
assign bound_high = depth-1;
/trunk/doc/component_descriptions.txt
107,10 → 107,32
 
4.0 Utility
 
This section is currently empty, but is intended for blocks which do not fit
into one of the above categories. Utility blocks could be items like a switch
fabric, packet ring, or a scoreboard.
This is intended for blocks which do not fit into one of the above categories.
Utility blocks could be items like a switch fabric, packet ring, or a scoreboard.
 
4.1 sd_ring_node
 
This is a building block for a unidirectional ring. Data is placed on the ring
using the consumer interface and is removed on the producer interface. sd_ring_node
supports only point-to-point single-transaction processing (single transaction meaning
that subsequent requests from the same source are treated as independent, and other
requests from other nodes may be interleaved at the destination).
 
4.2 sd_scoreboard
 
This implements a "scoreboard", or centralized repository of information about a number
of items. The scoreboard has a single consumer and producer interface. The user
is expected to use a pipeline join block (such as sd_rrslow) to serialize requests.
 
The scoreboard has a transaction id that it carries with each read request that can be
used to steer the results back to the requestor. For example, the "p_grant" output from
rrslow can be connected to the c_txid input, and the p_txid output can be connected to
the c_dst_vld input of sd_mirror, giving multi-read/multi-write capability.
 
The scoreboard supports both read and write, where write can also use a mask to implement
partial updates. If the mask is set to anything other than all 1's, the scoreboard performs
a read-modify-write to change only the unmasked portion of the data.
 
5.0 Memory
 
Contains synthesizable memories implemented as flops. These correspond to the
/trunk/env/verilog/scoreboard/sb_monitor.v
24,22 → 24,70
input [width-1:0] p_data
);
 
localparam pat_dep = 8;
 
reg [width-1:0] sbmem [0:items-1];
reg [7:0] drdy_pat;
integer dpp;
reg nxt_p_drdy;
 
reg [width-1:0] outbuf[0:items-1];
 
initial
begin
drdy_pat = {pat_dep{1'b1}};
dpp = 0;
end
 
always @*
begin
nxt_p_drdy = p_drdy;
 
if (p_srdy & p_drdy)
begin
if (drdy_pat[dpp])
begin
nxt_p_drdy = 1;
end
else
nxt_p_drdy = 0;
end
else if (!p_drdy)
begin
if (drdy_pat[dpp])
begin
nxt_p_drdy = 1;
end
else
nxt_p_drdy = 0;
end
end // always @ *
 
always @(posedge clk)
begin
if ((c_srdy & p_drdy) | !p_drdy)
dpp = (dpp + 1) % pat_dep;
 
p_drdy <= #1 nxt_p_drdy;
end
 
always @(posedge clk)
begin
if (c_srdy & c_drdy & (c_req_type == 1))
begin
sbmem[c_itemid] <= #20 (sbmem[c_itemid] & ~c_mask) | (c_data & c_mask);
sbmem[c_itemid] <= #18 (sbmem[c_itemid] & ~c_mask) | (c_data & c_mask);
end
else if (c_srdy & c_drdy & (c_req_type == 0))
begin
outbuf[c_itemid] = sbmem[c_itemid];
end
 
if (p_srdy & p_drdy)
begin
if (p_data != sbmem[p_txid])
if (p_data != outbuf[p_txid])
begin
$display ("%t: ERROR: sb returned %x, expected %x",
$time, p_data, sbmem[p_txid]);
$time, p_data, outbuf[p_txid]);
end
end
end
/trunk/env/verilog/scoreboard/sb_bench.v
10,7 → 10,6
localparam txid_sz = asz;
 
reg clk, reset;
wire p_drdy = 1'b1;
 
initial
begin
20,16 → 19,17
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] c_data; // From driver of sb_driver.v
wire c_drdy; // From sboard of sd_scoreboard.v
wire [asz-1:0] c_itemid; // From driver of sb_driver.v
wire [width-1:0] c_mask; // From driver of sb_driver.v
wire c_req_type; // From driver of sb_driver.v
wire c_srdy; // From driver of sb_driver.v
wire [txid_sz-1:0] c_txid; // From driver of sb_driver.v
wire [width-1:0] p_data; // From sboard of sd_scoreboard.v
wire p_srdy; // From sboard of sd_scoreboard.v
wire [txid_sz-1:0] p_txid; // From sboard of sd_scoreboard.v
wire [width-1:0] c_data; // From driver of sb_driver.v
wire c_drdy; // From sboard of sd_scoreboard.v
wire [asz-1:0] c_itemid; // From driver of sb_driver.v
wire [width-1:0] c_mask; // From driver of sb_driver.v
wire c_req_type; // From driver of sb_driver.v
wire c_srdy; // From driver of sb_driver.v
wire [txid_sz-1:0] c_txid; // From driver of sb_driver.v
wire [width-1:0] p_data; // From sboard of sd_scoreboard.v
wire p_drdy; // From monitor of sb_monitor.v
wire p_srdy; // From sboard of sd_scoreboard.v
wire [txid_sz-1:0] p_txid; // From sboard of sd_scoreboard.v
// End of automatics
 
/* sb_driver AUTO_TEMPLATE
38,25 → 38,25
);
*/
sb_driver #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) driver
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) driver
(/*AUTOINST*/
// Outputs
.p_srdy (c_srdy), // Templated
.p_req_type (c_req_type), // Templated
.p_txid (c_txid[txid_sz-1:0]), // Templated
.p_mask (c_mask[width-1:0]), // Templated
.p_itemid (c_itemid[asz-1:0]), // Templated
.p_data (c_data[width-1:0]), // Templated
.p_srdy (c_srdy), // Templated
.p_req_type (c_req_type), // Templated
.p_txid (c_txid[txid_sz-1:0]), // Templated
.p_mask (c_mask[width-1:0]), // Templated
.p_itemid (c_itemid[asz-1:0]), // Templated
.p_data (c_data[width-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.p_drdy (c_drdy)); // Templated
.clk (clk),
.reset (reset),
.p_drdy (c_drdy)); // Templated
/* sd_scoreboard AUTO_TEMPLATE
(
71,45 → 71,45
.txid_sz (txid_sz)) sboard
(/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]),
.c_drdy (c_drdy),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_drdy (p_drdy));
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_drdy (p_drdy));
 
sb_monitor #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) monitor
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) monitor
(/*AUTOINST*/
// Outputs
.p_drdy (p_drdy),
.p_drdy (p_drdy),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_drdy (c_drdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]));
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_drdy (c_drdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]));
 
/* -----\/----- EXCLUDED -----\/-----
task send;
151,15 → 151,31
end
 
// mix updates with requests
for (i=0; i<1024; i=i+1)
for (i=0; i<4096; i=i+1)
begin
entry = {$random} % items;
// choose random entry but space requests apart
//entry = {$random} % items;
case (i%2)
0 : entry = {$random} % (items/2);
1 : entry = {$random} % (items/2) + items/2;
//2 : entry = {$random} % (items/4) + 2*(items/4);
//3 : entry = {$random} % (items/4) + 3*(items/4);
endcase
 
op = {$random} % 8;
 
case (i)
512 : monitor.drdy_pat = 8'h55;
1024 : monitor.drdy_pat = 8'h0F;
1500 : monitor.drdy_pat = 8'h82;
2000 : monitor.drdy_pat = 8'hFE;
endcase
 
if (op == 0)
driver.send (1, {width{1'b1}}, $random, entry);
else if (op == 1)
driver.send (1, 32'h0000FFFF, $random, entry);
else if (op == 2)
driver.send (1, $random, $random, entry);
else
driver.send (0, 0, 0, entry);
/trunk/examples/bridge/env/run
6,8 → 6,8
which iverilog &> /dev/null
if [ "$?" == "0" ]; then
rm -f a.out
iverilog -f bridge.vf tests/$TESTNAME.v $*
./a.out -lxt
iverilog -f bridge.vf tests/$TESTNAME.v $* |& tee compile.log
./a.out -lxt | tee run.log
else
vcs -full64 +v2k -R -I -f bridge.vf tests/$TESTNAME.v $*
fi

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