URL
https://opencores.org/ocsvn/srl_fifo/srl_fifo/trunk
Subversion Repositories srl_fifo
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Rev 4 → Rev 5
/trunk/rtl/tb_srl_fifo_64.vhd
0,0 → 1,326
---------------------------------------------------------------------------- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- Implementation of srl_fifo IP core according to ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------------- |
-- ---- |
-- CVS Revision History ---- |
-- ---- |
-- $Log: not supported by cvs2svn $ ---- |
-- ---- |
-- |
-- quick description |
-- |
-- Based upon the using a shift register as a fifo which has been |
-- around for years ( decades ), but really came of use to VHDL |
-- when the Xilinx FPGA's started having SRL's. |
-- |
-- In my view, the definitive article on shift register logic fifo's |
-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO |
-- tecXeclusive article, which as at early 2008, Xilinx have |
-- removed. |
-- |
-- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.std_logic_unsigned.all; |
USE ieee.numeric_std.ALL; |
|
ENTITY tb_srl_fifo_64_vhd IS |
END tb_srl_fifo_64_vhd; |
|
ARCHITECTURE behavior OF tb_srl_fifo_64_vhd IS |
|
constant width_tb : integer := 8; |
|
-- Component Declaration for the Unit Under Test (UUT) |
COMPONENT srl_fifo_64 |
GENERIC ( width : integer := width_tb ); -- set to how wide fifo is to be |
PORT( |
data_in : IN std_logic_vector(width_tb - 1 downto 0); |
reset : IN std_logic; |
write : IN std_logic; |
read : IN std_logic; |
clk : IN std_logic; |
data_out : OUT std_logic_vector(width_tb -1 downto 0); |
full : OUT std_logic; |
half_full : OUT std_logic; |
data_present : OUT std_logic |
); |
END COMPONENT; |
|
--Inputs |
SIGNAL reset : std_logic := '0'; |
SIGNAL write : std_logic := '0'; |
SIGNAL read : std_logic := '0'; |
SIGNAL clk : std_logic := '0'; |
SIGNAL data_in : std_logic_vector(width_tb - 1 downto 0) := (others=>'0'); |
|
--Outputs |
SIGNAL data_out : std_logic_vector(width_tb -1 downto 0); |
SIGNAL full : std_logic; |
SIGNAL half_full : std_logic; |
SIGNAL data_present : std_logic; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: srl_fifo_64 |
GENERIC MAP ( |
width => width_tb |
) |
PORT MAP( |
data_in => data_in, |
data_out => data_out, |
reset => reset, |
write => write, |
read => read, |
full => full, |
half_full => half_full, |
data_present => data_present, |
clk => clk |
); |
|
tb : PROCESS |
BEGIN |
|
|
|
-- Wait 100 ns for global reset to finish |
wait for 100 ns; |
|
wait until clk = '0'; |
reset <= '0'; |
|
-- Place stimulus here |
|
wait until clk = '0'; -- 0 |
data_in <= X"AA"; |
write <= '1'; |
|
wait until clk = '0'; -- 1 |
data_in <= X"55"; |
|
wait until clk = '0'; -- 2 |
data_in <= X"02"; |
wait until clk = '0'; -- 3 |
data_in <= X"03"; |
wait until clk = '0'; -- 4 |
data_in <= X"04"; |
wait until clk = '0'; -- 5 |
data_in <= X"05"; |
wait until clk = '0'; -- 6 |
data_in <= X"06"; |
wait until clk = '0'; -- 7 |
data_in <= X"07"; |
wait until clk = '0'; -- 8 |
data_in <= X"08"; |
wait until clk = '0'; -- 9 |
data_in <= X"09"; |
wait until clk = '0'; -- A |
data_in <= X"A0"; |
wait until clk = '0'; -- B |
data_in <= X"B0"; |
wait until clk = '0'; -- C |
data_in <= X"C0"; |
wait until clk = '0'; -- D |
data_in <= X"D0"; |
wait until clk = '0'; -- E |
data_in <= X"E0"; |
wait until clk = '0'; -- F |
data_in <= X"F0"; |
wait until clk = '0'; -- 10 |
data_in <= X"10"; |
wait until clk = '0'; -- 11 |
data_in <= X"11"; |
wait until clk = '0'; -- 12 |
data_in <= X"12"; |
wait until clk = '0'; -- 13 |
data_in <= X"13"; |
wait until clk = '0'; -- 14 |
data_in <= X"14"; |
wait until clk = '0'; -- 15 |
data_in <= X"15"; |
wait until clk = '0'; -- 16 |
data_in <= X"16"; |
wait until clk = '0'; -- 17 |
data_in <= X"17"; |
wait until clk = '0'; -- 18 |
data_in <= X"18"; |
wait until clk = '0'; -- 19 |
data_in <= X"19"; |
wait until clk = '0'; -- 1A |
data_in <= X"1A"; |
wait until clk = '0'; -- 1B |
data_in <= X"1B"; |
wait until clk = '0'; -- 1C |
data_in <= X"1C"; |
wait until clk = '0'; -- 1D |
data_in <= X"1D"; |
wait until clk = '0'; -- 1E |
data_in <= X"1E"; |
wait until clk = '0'; -- 1F |
data_in <= X"1F"; |
|
-- |
|
wait until clk = '0'; -- 20 |
data_in <= X"20"; |
write <= '1'; |
|
wait until clk = '0'; -- 21 |
data_in <= X"21"; |
|
wait until clk = '0'; -- 22 |
data_in <= X"22"; |
wait until clk = '0'; -- 23 |
data_in <= X"23"; |
wait until clk = '0'; -- 24 |
data_in <= X"24"; |
wait until clk = '0'; -- 25 |
data_in <= X"25"; |
wait until clk = '0'; -- 26 |
data_in <= X"26"; |
wait until clk = '0'; -- 27 |
data_in <= X"27"; |
wait until clk = '0'; -- 28 |
data_in <= X"28"; |
wait until clk = '0'; -- 29 |
data_in <= X"29"; |
wait until clk = '0'; -- 2A |
data_in <= X"2A"; |
wait until clk = '0'; -- 2B |
data_in <= X"2B"; |
wait until clk = '0'; -- 2C |
data_in <= X"2C"; |
wait until clk = '0'; -- 2D |
data_in <= X"2D"; |
wait until clk = '0'; -- 2E |
data_in <= X"2E"; |
wait until clk = '0'; -- 2F |
data_in <= X"2F"; |
wait until clk = '0'; -- 30 |
data_in <= X"30"; |
wait until clk = '0'; -- 31 |
data_in <= X"31"; |
wait until clk = '0'; -- 32 |
data_in <= X"32"; |
wait until clk = '0'; -- 33 |
data_in <= X"33"; |
wait until clk = '0'; -- 34 |
data_in <= X"34"; |
wait until clk = '0'; -- 35 |
data_in <= X"35"; |
wait until clk = '0'; -- 36 |
data_in <= X"36"; |
wait until clk = '0'; -- 37 |
data_in <= X"37"; |
wait until clk = '0'; -- 38 |
data_in <= X"38"; |
wait until clk = '0'; -- 39 |
data_in <= X"39"; |
wait until clk = '0'; -- 3A |
data_in <= X"3A"; |
wait until clk = '0'; -- 3B |
data_in <= X"3B"; |
wait until clk = '0'; -- 3C |
data_in <= X"3C"; |
wait until clk = '0'; -- 3D |
data_in <= X"3D"; |
wait until clk = '0'; -- 3E |
data_in <= X"3E"; |
wait until clk = '0'; -- 3F |
data_in <= X"3F"; |
|
|
|
wait until clk = '0'; -- no write |
data_in <= X"FF"; |
|
wait until clk = '0'; -- write and read on full, reads first out |
data_in <= X"EE"; |
read <= '1'; |
|
wait until clk = '0'; -- no read or write |
data_in <= X"AB"; |
read <= '0'; |
write <= '0'; |
|
|
-- read untill empty |
|
wait until clk = '0'; |
|
read <= '1'; |
for i in 0 to 61 loop -- read out 62 more |
wait until clk = '0'; |
end loop; |
|
read <= '0'; |
wait until clk = '0'; -- dont read, |
|
read <= '1'; |
wait until clk = '0'; -- read last - 1 out |
|
|
read <= '0'; |
wait until clk = '0'; -- dont read, |
|
read <= '1'; |
wait until clk = '0'; -- read last out |
|
|
read <= '0'; -- stop reading |
|
wait; -- will wait forever |
END PROCESS; |
|
-- clock gen process |
process |
begin |
wait for 1 ns; |
clk <= '0'; |
wait for 1 ns; |
clk <= '1'; |
end process; |
|
|
|
END; |
/trunk/rtl/srl_fifo_32.vhd
1,51 → 1,51
---------------------------------------------------------------------------- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- Implementation of srl_fifo IP core according to ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------------- |
-- ---- |
-- CVS Revision History ---- |
-- ---- |
-- $Log: not supported by cvs2svn $ ---- |
-- ---- |
-- |
---- ---- |
-- CVS Revision History ---- |
---- ---- |
-- $Log: not supported by cvs2svn $ ---- |
---- ---- |
---- ---- |
-- quick description |
-- |
-- Based upon the using a shift register as a fifo which has been |
57,10 → 57,16
-- tecXeclusive article, which as at early 2008, Xilinx have |
-- removed. |
-- |
-- This version is for 'later' devices that have an inherent shift |
-- register of 32 bits. |
-- |
|
-- using Xilinx ISE 10.1 and later, the tools are getting real clever. |
-- In previous version of ISE, SRL inferance was not this clever. |
-- now if one infers a 32 bit srl in a device that has inherantly 16 |
-- bit srls, then an srl and a series of registers was created. |
-- In 10,1 and later, if you infer a 32 bit srl for a device with |
-- 16 bit srls in, then you end up with the cascaded srls as expected. |
-- |
-- Well done Xilinx.. |
-- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use ieee.NUMERIC_STD.all; |
/trunk/rtl/srl_fifo_16.vhd
1,51 → 1,51
---------------------------------------------------------------------------- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- Implementation of srl_fifo IP core according to ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------------- |
-- ---- |
-- CVS Revision History ---- |
-- ---- |
-- $Log: not supported by cvs2svn $ ---- |
-- ---- |
-- |
---- ---- |
-- CVS Revision History ---- |
---- ---- |
-- $Log: not supported by cvs2svn $ ---- |
---- ---- |
---- ---- |
-- quick description |
-- |
-- Based upon the using a shift register as a fifo which has been |
57,9 → 57,16
-- tecXeclusive article, which as at early 2008, Xilinx have |
-- removed. |
-- |
-- This version is for 'earlier' devices that have an inherent shift |
-- register of 16 bits. |
-- |
-- using Xilinx ISE 10.1 and later, the tools are getting real clever. |
-- In previous version of ISE, SRL inferance was not this clever. |
-- now if one infers a 32 bit srl in a device that has inherantly 16 |
-- bit srls, then an srl and a series of registers was created. |
-- In 10,1 and later, if you infer a 32 bit srl for a device with |
-- 16 bit srls in, then you end up with the cascaded srls as expected. |
-- |
-- Well done Xilinx.. |
-- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
/trunk/rtl/srl_fifo_64.vhd
0,0 → 1,206
---------------------------------------------------------------------------- |
---- ---- |
---- ---- |
---- This file is part of the srl_fifo project ---- |
---- http://www.opencores.org/cores/srl_fifo ---- |
---- ---- |
---- Description ---- |
---- Implementation of srl_fifo IP core according to ---- |
---- srl_fifo IP core specification document. ---- |
---- ---- |
---- To Do: ---- |
---- NA ---- |
---- ---- |
---- Author(s): ---- |
---- Andrew Mulcock, amulcock@opencores.org ---- |
---- ---- |
---------------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2008 Authors and OPENCORES.ORG ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------------- |
---- ---- |
-- CVS Revision History ---- |
---- ---- |
-- $Log: not supported by cvs2svn $ ---- |
---- ---- |
---- ---- |
-- quick description |
-- |
-- Based upon the using a shift register as a fifo which has been |
-- around for years ( decades ), but really came of use to VHDL |
-- when the Xilinx FPGA's started having SRL's. |
-- |
-- In my view, the definitive article on shift register logic fifo's |
-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO |
-- tecXeclusive article, which as at early 2008, Xilinx have |
-- removed. |
-- |
-- |
-- using Xilinx ISE 10.1 and later, the tools are getting real clever. |
-- In previous version of ISE, SRL inferance was not this clever. |
-- now if one infers a 32 bit srl in a device that has inherantly 16 |
-- bit srls, then an srl and a series of registers was created. |
-- In 10,1 and later, if you infer a 32 bit srl for a device with |
-- 16 bit srls in, then you end up with the cascaded srls as expected. |
-- |
-- Well done Xilinx.. |
-- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use ieee.NUMERIC_STD.all; |
|
entity srl_fifo_64 is |
generic ( width : integer := 8 ); -- set to how wide fifo is to be |
port( |
data_in : in std_logic_vector (width -1 downto 0); |
data_out : out std_logic_vector (width -1 downto 0); |
reset : in std_logic; |
write : in std_logic; |
read : in std_logic; |
full : out std_logic; |
half_full : out std_logic; |
data_present : out std_logic; |
clk : in std_logic |
); |
|
-- Declarations |
|
end srl_fifo_64 ; |
-- |
------------------------------------------------------------------------------------ |
-- |
architecture rtl of srl_fifo_64 is |
-- |
------------------------------------------------------------------------------------ |
-- |
|
|
|
------------------------------------------------------------------------------------ |
-- |
------------------------------------------------------------------------------------ |
-- |
|
constant srl_length : integer := 64; -- set to 16, 32, 64 etc. |
constant pointer_vec : integer := 6; -- set to number of bits needed to store pointer = log2(srl_length) |
|
type srl_array is array ( srl_length - 1 downto 0 ) of STD_LOGIC_VECTOR ( WIDTH - 1 downto 0 ); |
signal fifo_store : srl_array; |
|
signal pointer : integer range 0 to srl_length - 1; |
|
signal pointer_zero : std_logic; |
signal pointer_full : std_logic; |
signal valid_write : std_logic; |
signal half_full_int : std_logic_vector( pointer_vec - 1 downto 0); |
|
signal empty : std_logic := '1'; |
signal valid_count : std_logic ; |
|
------------------------------------------------------------------------------------ |
-- |
------------------------------------------------------------------------------------ |
-- |
begin |
|
|
-- Valid write, high when valid to write data to the store. |
valid_write <= '1' when ( read = '1' and write = '1' ) |
or ( write = '1' and pointer_full = '0' ) else '0'; |
|
-- data store SRL's |
data_srl :process( clk ) |
begin |
if rising_edge( clk ) then |
if valid_write = '1' then |
fifo_store <= fifo_store( fifo_store'left - 1 downto 0) & data_in; |
end if; |
end if; |
end process; |
|
data_out <= fifo_store( pointer ); |
|
|
process( clk) |
begin |
if rising_edge( clk ) then |
if reset = '1' then |
empty <= '1'; |
elsif empty = '1' and write = '1' then |
empty <= '0'; |
elsif pointer_zero = '1' and read = '1' and write = '0' then |
empty <= '1'; |
end if; |
end if; |
end process; |
|
|
|
-- W R Action |
-- 0 0 pointer <= pointer |
-- 0 1 pointer <= pointer - 1 Read, but no write, so less data in counter |
-- 1 0 pointer <= pointer + 1 Write, but no read, so more data in fifo |
-- 1 1 pointer <= pointer Read and write, so same number of words in fifo |
-- |
|
valid_count <= '1' when ( |
(write = '1' and read = '0' and pointer_full = '0' and empty = '0' ) |
or |
(write = '0' and read = '1' and pointer_zero = '0' ) |
) else '0'; |
process( clk ) |
begin |
if rising_edge( clk ) then |
if valid_count = '1' then |
if write = '1' then |
pointer <= pointer + 1; |
else |
pointer <= pointer - 1; |
end if; |
end if; |
end if; |
end process; |
|
|
-- Detect when pointer is zero and maximum |
pointer_zero <= '1' when pointer = 0 else '0'; |
pointer_full <= '1' when pointer = srl_length - 1 else '0'; |
|
|
|
|
-- assign internal signals to outputs |
full <= pointer_full; |
half_full_int <= std_logic_vector(to_unsigned(pointer, pointer_vec)); |
half_full <= half_full_int(half_full_int'left); |
data_present <= not( empty ); |
|
end rtl; |
|
------------------------------------------------------------------------------------ |
-- |
------------------------------------------------------------------------------------ |
|
|