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https://opencores.org/ocsvn/ssp_slv/ssp_slv/trunk
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- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/RTL/SSPx_Slv.v
1,28 → 1,39
// ------------------------- CONFIDENTIAL ------------------------------------ |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright 2008-2011 by Michael A. Morris, dba M. A. Morris & Associates |
// Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates |
// |
// All rights reserved. No part of this source code may be reproduced or |
// transmitted in any form or by any means, electronic or mechanical, |
// including photocopying, recording, or any information storage and |
// retrieval system, without permission in writing from Michael A. Morris, |
// dba M. A. Morris & Associates. |
// All rights reserved. The source code contained herein is publicly released |
// under the terms and conditions of the GNU Lesser Public License. No part of |
// this source code may be reproduced or transmitted in any form or by any |
// means, electronic or mechanical, including photocopying, recording, or any |
// information storage and retrieval system in violation of the license under |
// which the source code is released. |
// |
// The source code contained herein is free; it may be redistributed and/or |
// modified in accordance with the terms of the GNU Lesser General Public |
// License as published by the Free Software Foundation; either version 2.1 of |
// the GNU Lesser General Public License, or any later version. |
// |
// The source code contained herein is freely released WITHOUT ANY WARRANTY; |
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for |
// more details.) |
// |
// A copy of the GNU Lesser General Public License should have been received |
// along with the source code contained herein; if not, a copy can be obtained |
// by writing to: |
// |
// Free Software Foundation, Inc. |
// 51 Franklin Street, Fifth Floor |
// Boston, MA 02110-1301 USA |
// |
// Further, no use of this source code is permitted in any form or means |
// without a valid, written license agreement with Michael A. Morris, dba |
// M. A. Morris & Associates. |
// without inclusion of this banner prominently in any derived works. |
// |
// Michael A. Morris |
// dba M. A. Morris & Associates |
// 164 Raleigh Way |
// Huntsville, AL 35811, USA |
// Ph. +1 256 508 5869 |
// Huntsville, AL |
// |
// Licensed To: DopplerTech, Inc. (DTI) |
// 9345 E. South Frontage Rd. |
// Yuma, AZ 85365 |
// |
// ---------------------------------------------------------------------------- |
//////////////////////////////////////////////////////////////////////////////// |
|
`timescale 1ns / 1ps |
|
31,10 → 42,10
// Engineer: Michael A. Morris |
// |
// Create Date: 07:33 05/10/2008 |
// Design Name: LTAS |
// Module Name: C:/XProjects/ISE10.1i/LTAS/LTAS_Top.v |
// Project Name: LTAS |
// Target Devices: XC3S700AN-5FFG484I |
// Design Name: Synchronous Serial Peripheral (SSP) Interface UART |
// Module Name: ../VerilogCoponentsLib/SSP_UART/SSPx_Slv.v |
// Project Name: Verilog Components Library |
// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I |
// Tool versions: ISE 10.1i SP3 |
// |
// Description: |
67,11 → 78,33
// RA[0] into RA[2:0] address port and a WnR command |
// port. This makes the operation of the SSP/SPI I/F |
// more clear. |
// |
// |
// 2.10 13G06 MAM Changed the asynchronous reset generated by ~SSEL. |
// Previously, a number of internal circuits were |
// reset asynchronously on system reset, Rst, or ~SSEL. |
// Added a FF, clocked on posedge SCK, that is asyn- |
// chronously reset as before, but synchronously de- |
// asserts on first rising edge of SCK. This signal, |
// SSP_Rst, is used to asynchronously reset the same |
// circuits as before: BC, EOC, and RDI. SPI Modes 0 or |
// 3 are still supported. |
// |
// 2.20 14D25 MAM Encountered an issue whereby RA[2] held in reset |
// after SSEL deasserted and then reasserted. The |
// asynchronous reset on the signal SSP_Rst, a FF |
// clocked on the falling edge of SCK, was changed to |
// the combinatorial signal Rst_SSP. Rst_SSP is the |
// source of the asynchronous reset of the SSP_Rst FF. |
// The additional delay in the SSP_Rst signal caused |
// RA[2] to be kept in reset at the start of a new |
// SSP transfer cycle. Also added two additional CE |
// signals while tracking down this issue: CE_RA and |
// CE_WnR. They were previously driven directly by the |
// bit counter. |
// |
// Additional Comments: |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
|
module SSPx_Slv( |
input Rst, // System Reset |
99,6 → 132,8
reg [15:1] RDI; // Serial Input Shift Register |
reg [11:0] rDO; // output data register |
|
reg SSP_Rst; |
|
/////////////////////////////////////////////////////////////////////////////// |
// |
// Implementation |
108,12 → 143,20
|
assign Rst_SSP = (Rst | ~SSEL); |
|
always @(posedge SCK or posedge Rst_SSP) |
begin |
if(Rst_SSP) |
SSP_Rst <= #1 ~0; |
else |
SSP_Rst <= #1 0; |
end |
|
// Bit Counter, count from 0 to 15 |
// Clock on negedge SCK to align MISO in bit cell |
|
always @(negedge SCK or posedge Rst_SSP) |
always @(negedge SCK or posedge SSP_Rst) |
begin |
if(Rst_SSP) |
if(SSP_Rst) |
BC <= #1 4'd0; |
else |
BC <= #1 (BC + 1); |
122,9 → 165,9
// End-Of-Cycle, asserted during last bit of transfer (bit 15) |
// Clock on negedge SCK to center rising edge in bit cell |
|
always @(negedge SCK or posedge Rst_SSP) |
always @(negedge SCK or posedge SSP_Rst) |
begin |
if(Rst_SSP) |
if(SSP_Rst) |
EOC <= #1 1'b0; |
else |
EOC <= #1 (BC == 14); |
143,67 → 186,50
RDI <= #1 15'b0; |
else |
case(BC) |
4'b0000 : RDI[15] <= #1 MOSI; |
4'b0001 : RDI[14] <= #1 MOSI; |
4'b0010 : RDI[13] <= #1 MOSI; |
4'b0011 : RDI[12] <= #1 MOSI; |
4'b0100 : RDI[11] <= #1 MOSI; |
4'b0101 : RDI[10] <= #1 MOSI; |
4'b0110 : RDI[ 9] <= #1 MOSI; |
4'b0111 : RDI[ 8] <= #1 MOSI; |
4'b1000 : RDI[ 7] <= #1 MOSI; |
4'b1001 : RDI[ 6] <= #1 MOSI; |
4'b1010 : RDI[ 5] <= #1 MOSI; |
4'b1011 : RDI[ 4] <= #1 MOSI; |
4'b1100 : RDI[ 3] <= #1 MOSI; |
4'b1101 : RDI[ 2] <= #1 MOSI; |
4'b1110 : RDI[ 1] <= #1 MOSI; |
4'b0000 : RDI[15] <= #1 MOSI; |
4'b0001 : RDI[14] <= #1 MOSI; |
4'b0010 : RDI[13] <= #1 MOSI; |
4'b0011 : RDI[12] <= #1 MOSI; |
4'b0100 : RDI[11] <= #1 MOSI; |
4'b0101 : RDI[10] <= #1 MOSI; |
4'b0110 : RDI[ 9] <= #1 MOSI; |
4'b0111 : RDI[ 8] <= #1 MOSI; |
4'b1000 : RDI[ 7] <= #1 MOSI; |
4'b1001 : RDI[ 6] <= #1 MOSI; |
4'b1010 : RDI[ 5] <= #1 MOSI; |
4'b1011 : RDI[ 4] <= #1 MOSI; |
4'b1100 : RDI[ 3] <= #1 MOSI; |
4'b1101 : RDI[ 2] <= #1 MOSI; |
4'b1110 : RDI[ 1] <= #1 MOSI; |
default : RDI <= #1 RDI; |
endcase |
end |
|
// Assign RA, WnR, and DI bus from RDI and MOSI |
|
//always @(posedge SCK or posedge Rst) |
//begin |
// if(Rst) |
// RA <= #1 0; |
// else if(BC == 2) |
// RA <= #1 {RDI[15:14], MOSI}; |
//end |
// |
//always @(posedge SCK or posedge Rst) |
//begin |
// if(Rst) |
// WnR <= #1 0; |
// else if(BC == 3) |
// WnR <= #1 MOSI; |
//end |
assign CE_RA = (BC == 2); |
|
always @(negedge SCK or posedge Rst) |
always @(negedge SCK or posedge Rst_SSP) |
begin |
if(Rst) |
if(Rst_SSP) |
RA <= #1 0; |
else if(BC == 2) |
else if(CE_RA) |
RA <= #1 RDI[15:13]; |
end |
|
always @(negedge SCK or posedge Rst) |
assign CE_WnR = (BC == 3); |
|
always @(negedge SCK or posedge Rst_SSP) |
begin |
if(Rst) |
if(Rst_SSP) |
WnR <= #1 0; |
else if(EOC) |
WnR <= #1 0; |
else if(BC == 3) |
else if(CE_WnR) |
WnR <= #1 RDI[12]; |
end |
|
always @(posedge SCK or posedge Rst) |
begin |
if(Rst) |
DI <= #1 0; |
else if(EOC) |
DI <= #1 {RDI[11:1], MOSI}; |
end |
always @(*) DI <= {RDI[11:1], MOSI}; |
|
always @(negedge SCK or posedge Rst) |
begin |
215,7 → 241,7
|
// Generate MISO: multiplex MOSI and DO using En and BC |
|
always @(BC or rDO or MOSI) |
always @(*) |
begin |
case(BC) |
4'b0000 : MISO <= MOSI; |