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URL https://opencores.org/ocsvn/ssp_uart/ssp_uart/trunk

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Rev 3 → Rev 4

/trunk/RTL/SSP_UART.v
45,7 → 45,7
// Design Name: Synchronous Serial Peripheral (SSP) Interface UART
// Module Name: ../VerilogCoponentsLib/SSP_UART/SSP_UART.v
// Project Name: Verilog Components Library
// Target Devices: XC3S50A-4VQG100I, XC3S20A-4VQG100I, XC3S700AN-4FFG484I
// Target Devices: XC3S50A-4VQG100I, XC3S200A-4VQG100I, XC3S700AN-4FFG484I
// Tool versions: ISE 10.1i SP3
//
// Description: This module integrates the various elements of a simplified
92,7 → 92,7
// RAM.
//
// 1.11 08G27 MAM Modified the organization of the SPR window status
// registers to match Table 5 in the 17000-0403C SSP
// registers to match Table 5 in the 1700-0403C SSP
// UART specification.
//
// 1.20 08G27 MAM Modified Tx signal path to include a FF that will
152,23 → 152,23
// the Additional Comments section.
//
// 2.40 13G21 MAM Added asynchronous reset to several functions in
// order to correctly simulate in ISim.
//
// 2.50 13G28 MAM Corrected issue with polling of the Receive Data
// Register. A race condition was found. Corrected by
// registering the data on the SCK clock domain and
// by requiring that the read pulse for the receive
// FIFO is only generated if the empty flag status is
// present on the SCK clock domain. This prevents the
// same race condition as found when polling the UART
// Status Register. Examining the condition/flags of
// these registers, without polling via the SSP inter-
// face, avoids these issues. Given the limited I/O
// resources of the M16C5x, examining the condition/
// flags bits directly without polling is not a viable
// option. Therefore, corrected the race condition. If
// examining the condition/flags directly is an option,
// then that is the preferred method from a performance
// order to correctly simulate in ISim.
//
// 2.50 13G28 MAM Corrected issue with polling of the Receive Data
// Register. A race condition was found. Corrected by
// registering the data on the SCK clock domain and
// by requiring that the read pulse for the receive
// FIFO is only generated if the empty flag status is
// present on the SCK clock domain. This prevents the
// same race condition as found when polling the UART
// Status Register. Examining the condition/flags of
// these registers, without polling via the SSP inter-
// face, avoids these issues. Given the limited I/O
// resources of the M16C5x, examining the condition/
// flags bits directly without polling is not a viable
// option. Therefore, corrected the race condition. If
// examining the condition/flags directly is an option,
// then that is the preferred method from a performance
// perspective.
//
// Additional Comments:
189,7 → 189,7
//
// The Synchronous Serial Peripheral of the ARM is configured to send 16 bits.
// The result is that the 3 most significant bits are interpreted as an regis-
// ter select. Bit 12, the fourth transmitted bit, set the write/read mode of
// ter select. Bit 12, the fourth transmitted bit, sets the write/read mode of
// transfer. The remaining twelve bits, bits 11...0, are data bits. In this
// manner, the SSP UART minimizes the number of serial transfers required to
// send and receive serial data from the SSP UART. The reads from the TDR/RDR
242,7 → 242,7
// 11:8 - PS : Baud Rate Prescaler (see table below) - load with (M - 1)
// 7:0 - Div : Baud Rate Divider (see table below) - load with (N - 1)
//
// {PS, Div} : Baud Rate = (Clk / 16) / ((M - 1) * (N - 1))
// {PS, Div} : Baud Rate = (Clk / 16) / ((PS + 1) * (Div + 1))
//
// Transmit Data Register - TDR (RA = 3'b010)
//
314,8 → 314,8
 
// FIFO Configuration Parameters
 
parameter pTF_Depth = 0, // Tx FIFO Depth: 2**(TF_Depth + 4)
parameter pRF_Depth = 3, // Rx FIFO Depth: 2**(RF_Depth + 4)
parameter pTF_Depth = 2, // Tx FIFO Depth: 2**(TF_Depth + 4)
parameter pRF_Depth = 2, // Rx FIFO Depth: 2**(RF_Depth + 4)
parameter pTF_Init = "Src/UART_TF.coe", // Tx FIFO Memory Initialization
parameter pRF_Init = "Src/UART_RF.coe" // Rx FIFO Memory Initialization
)(
421,7 → 421,6
wire [(pRF_Depth + 4):0] RFCnt; // RX FIFO Count
reg [ 7:0] TDR; // Transmit Data Register
// wire [11:0] RDR; // Receive Data Register, UART Status Reg
reg [11:0] RDR; // Receive Data Register, UART Status Reg
reg [11:0] UCR, USR, SPR; // UART Control, Status, & Scratch Pad Regs
reg [ 7:0] RTFThr; // UART Rx/Tx FIFO Threshold Register
576,14 → 575,14
// Baud Rate Generator's PS and Div for defined Baud Rates (48 MHz Osc)
//
// Profibus Baud Rates
//
//
// {PS, Div} <= {4'h0, 8'h00}; // PS= 1; Div= 1; BR=3.0M
// {PS, Div} <= {4'h0, 8'h01}; // PS= 1; Div= 2; BR=1.5M
// {PS, Div} <= {4'h0, 8'h05}; // PS= 1; Div= 6; BR=500.0k
// {PS, Div} <= {4'h0, 8'h0F}; // PS= 1; Div= 16; BR=187.5k
//
//
// Standard Baud Rates
//
//
// {PS, Div} <= {4'hC, 8'h00}; // PS=13; Div= 1; BR=230.4k
// {PS, Div} <= {4'hC, 8'h01}; // PS=13; Div= 2; BR=115.2k
// {PS, Div} <= {4'hC, 8'h02}; // PS=13; Div= 3; BR= 76.8k
598,15 → 597,15
// {PS, Div} <= {4'hC, 8'hBF}; // PS=13; Div=192; BR= 1.2k
//
// Baud Rate Generator's PS and Div for defined Baud Rates (29.4912 MHz)
//
// Extended Baud Rates
//
// Extended Baud Rates
//
// {PS, Div} <= {4'h0, 8'h00}; // PS= 1; Div= 1; BR=1843.2k
// {PS, Div} <= {4'h0, 8'h01}; // PS= 1; Div= 2; BR= 921.6k
// {PS, Div} <= {4'h0, 8'h01}; // PS= 1; Div= 2; BR= 921.6k
// {PS, Div} <= {4'h0, 8'h02}; // PS= 1; Div= 3; BR= 614.4k
// {PS, Div} <= {4'h0, 8'h03}; // PS= 1; Div= 4; BR= 460.8k
// {PS, Div} <= {4'h0, 8'h05}; // PS= 1; Div= 6; BR= 307.2k
// {PS, Div} <= {4'h0, 8'h07}; // PS= 1; Div= 8; BR= 230.4k
// {PS, Div} <= {4'h0, 8'h07}; // PS= 1; Div= 8; BR= 230.4k
// {PS, Div} <= {4'h0, 8'h0B}; // PS= 1; Div= 12; BR= 153.6k
//
// Standard Baud Rates
613,7 → 612,7
//
// {PS, Div} <= {4'h0, 8'h0F}; // PS= 1; Div= 16; BR= 115.2k
// {PS, Div} <= {4'h0, 8'h17}; // PS= 1; Div= 24; BR= 76.8k
// {PS, Div} <= {4'h0, 8'h1F}; // PS= 1; Div= 32; BR= 57.6k
// {PS, Div} <= {4'h0, 8'h1F}; // PS= 1; Div= 32; BR= 57.6k
// {PS, Div} <= {4'h0, 8'h2F}; // PS= 1; Div= 48; BR= 38.4k
// {PS, Div} <= {4'h0, 8'h3F}; // PS= 1; Div= 64; BR= 28.8k
// {PS, Div} <= {4'h0, 8'h5F}; // PS= 1; Div= 96; BR= 19.2k
811,20 → 810,20
assign TRDY = ~TF_FF;
assign RRDY = ~RF_EF;
assign RTO = RcvTimeout;
assign RERR = RHR[8];
 
assign RERR = RHR[8];
 
// Capture and Hold Receive Data Register on SCK clock domain
 
always @(posedge SCK or posedge Rst)
begin
if(Rst)
RDR <= #1 0;
else if(~SSP_En)
RDR <= #1 {TRDY, RRDY, RTO, RERR, RHR[7:0]};
end
always @(posedge SCK or posedge Rst)
begin
if(Rst)
RDR <= #1 0;
else if(~SSP_En)
RDR <= #1 {TRDY, RRDY, RTO, RERR, RHR[7:0]};
end
 
// Read Receive Holding Register
// Generate RE_RHR read pulse only when the captured value indicates that
// Read Receive Holding Register
// Generate RE_RHR read pulse only when the captured value indicates that
// RDR contains data because there is data in the Receive FIFO, i.e. RHR.
 
assign RE_RDR = Sel_RDR & ~SSP_WnR & (SSP_En & ~En) & RDR[10];

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