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URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/steelcore/trunk/bench/tb_control_unit.v
73,6 → 73,7
reg FUNCT7_5;
reg [2:0] FUNCT3;
reg [1:0] IADDER_OUT_1_TO_0;
reg TRAP_TAKEN;
wire [3:0] ALU_OPCODE;
wire MEM_WR_REQ;
94,7 → 95,8
.OPCODE(OPCODE),
.FUNCT7_5(FUNCT7_5),
.FUNCT3(FUNCT3),
.IADDER_OUT_1_TO_0(IADDER_OUT_1_TO_0),
.IADDER_OUT_1_TO_0(IADDER_OUT_1_TO_0),
.TRAP_TAKEN(TRAP_TAKEN),
.ALU_OPCODE(ALU_OPCODE),
.MEM_WR_REQ(MEM_WR_REQ),
.LOAD_SIZE(LOAD_SIZE),
127,6 → 129,7
opcode_6_to_2 = `OPCODE_OP;
OPCODE = {opcode_6_to_2, 2'b11};
IADDER_OUT_1_TO_0 = 2'b00;
TRAP_TAKEN = 1'b0;
#10;
if(MEM_WR_REQ != 1'b0)
877,6 → 880,15
$finish;
end
TRAP_TAKEN = 1'b1;
#10;
if(MEM_WR_REQ != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
TRAP_TAKEN = 1'b0;
$display("STORE control signals common to all instructions successfully tested.");
$display("Testing signal MISALIGNED_STORE for SB...");
/steelcore/trunk/bench/tb_machine_mode.v
107,6 → 107,8
wire FLUSH;
wire TRAP_TAKEN;
machine_control dut(
 
.CLK(CLK),
145,7 → 147,9
.PC_SRC(PC_SRC),
.FLUSH(FLUSH)
.FLUSH(FLUSH),
.TRAP_TAKEN(TRAP_TAKEN)
 
);
164,6 → 168,8
ILLEGAL_INSTR = 1'b0;
MISALIGNED_INSTR = 1'b0;
MISALIGNED_LOAD = 1'b0;
MISALIGNED_STORE = 1'b0;
OPCODE_6_TO_2 = `OPCODE_OP;
FUNCT3 = `FUNCT3_ADD;
1267,6 → 1273,253
$display("Test OK.");
$display("Testing TRAP_TAKEN signal...");
OPCODE_6_TO_2 = `OPCODE_OP;
FUNCT3 = `FUNCT3_ADD;
FUNCT7 = `FUNCT7_ADD;
RS1_ADDR = 5'b00000;
RS2_ADDR = 5'b00000;
RD_ADDR = 5'b00000;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
OPCODE_6_TO_2 = `OPCODE_SYSTEM;
FUNCT3 = `FUNCT3_EBREAK;
FUNCT7 = `FUNCT7_EBREAK;
RS1_ADDR = `RS1_EBREAK;
RS2_ADDR = `RS2_EBREAK;
RD_ADDR = `RD_EBREAK;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
OPCODE_6_TO_2 = `OPCODE_OP;
FUNCT3 = `FUNCT3_ADD;
FUNCT7 = `FUNCT7_ADD;
RS1_ADDR = 5'b00000;
RS2_ADDR = 5'b00000;
RD_ADDR = 5'b00000;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
OPCODE_6_TO_2 = `OPCODE_SYSTEM;
FUNCT3 = `FUNCT3_ECALL;
FUNCT7 = `FUNCT7_ECALL;
RS1_ADDR = `RS1_ECALL;
RS2_ADDR = `RS2_ECALL;
RD_ADDR = `RD_ECALL;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
OPCODE_6_TO_2 = `OPCODE_OP;
FUNCT3 = `FUNCT3_ADD;
FUNCT7 = `FUNCT7_ADD;
RS1_ADDR = 5'b00000;
RS2_ADDR = 5'b00000;
RD_ADDR = 5'b00000;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
ILLEGAL_INSTR = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
ILLEGAL_INSTR = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_INSTR = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_INSTR = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_LOAD = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_LOAD = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_STORE = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MISALIGNED_STORE = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MIE = 1'b1;
MEIE = 1'b1;
MTIE = 1'b1;
MSIE = 1'b1;
E_IRQ = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
E_IRQ = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
T_IRQ = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
T_IRQ = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
S_IRQ = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
S_IRQ = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MEIP = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MEIP = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MTIP = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MTIP = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
MSIP = 1'b1;
#20;
if(TRAP_TAKEN != 1'b1)
begin
$display("FAIL. Check the results.");
$finish;
end
MSIP = 1'b0;
#20;
if(TRAP_TAKEN != 1'b0)
begin
$display("FAIL. Check the results.");
$finish;
end
$display("Machine Mode Control module successfully tested.");
end
/steelcore/trunk/control_unit.v
72,6 → 72,7
input wire FUNCT7_5,
input wire [2:0] FUNCT3,
input wire [1:0] IADDER_OUT_1_TO_0,
input wire TRAP_TAKEN,
output wire [3:0] ALU_OPCODE,
output wire MEM_WR_REQ,
155,7 → 156,7
assign misaligned = mal_word | mal_half;
assign MISALIGNED_STORE = is_store & misaligned;
assign MISALIGNED_LOAD = is_load & misaligned;
assign MEM_WR_REQ = is_store & ~misaligned;
assign MEM_WR_REQ = is_store & ~misaligned & ~TRAP_TAKEN;
endmodule
/steelcore/trunk/machine_control.v
114,7 → 114,10
output reg [1:0] PC_SRC,
// to pipeline stage 2 register
output reg FLUSH
output reg FLUSH,
// to Control Unit
output wire TRAP_TAKEN
 
);
138,14 → 141,11
wire RS1_ADDR_zero;
wire RS2_ADDR_zero;
wire rd_zero;
wire RS2_ADDR_wfi;
wire RS2_ADDR_mret;
wire RS2_ADDR_ebreak;
wire FUNCT3_zero;
wire FUNCT7_zero;
wire FUNCT7_wfi;
wire FUNCT7_mret;
wire wfi;
wire csr;
wire mret;
wire ecall;
165,7 → 165,6
assign RS2_ADDR_wfi = ~RS2_ADDR[4] & ~RS2_ADDR[3] & RS2_ADDR[2] & ~RS2_ADDR[1] & RS2_ADDR[0];
assign RS2_ADDR_mret = ~RS2_ADDR[4] & ~RS2_ADDR[3] & ~RS2_ADDR[2] & RS2_ADDR[1] & ~RS2_ADDR[0];
assign RS2_ADDR_ebreak = ~RS2_ADDR[4] & ~RS2_ADDR[3] & ~RS2_ADDR[2] & ~RS2_ADDR[1] & RS2_ADDR[0];
assign wfi = is_system & FUNCT7_wfi & RS2_ADDR_wfi & RS1_ADDR_zero & FUNCT3_zero & rd_zero;
assign mret = is_system & FUNCT7_mret & RS2_ADDR_mret & RS1_ADDR_zero & FUNCT3_zero & rd_zero;
assign ecall = is_system & FUNCT7_zero & RS2_ADDR_zero & RS1_ADDR_zero & FUNCT3_zero & rd_zero;
assign ebreak = is_system & FUNCT7_zero & RS2_ADDR_ebreak & RS1_ADDR_zero & FUNCT3_zero & rd_zero;
175,6 → 174,7
assign sip = MSIE & (S_IRQ | MSIP);
assign ip = eip | tip | sip;
assign exception = ILLEGAL_INSTR | MISALIGNED_INSTR | MISALIGNED_LOAD | MISALIGNED_STORE;
assign TRAP_TAKEN = (MIE & ip) | exception | ecall | ebreak;
always @*
begin
182,7 → 182,7
STATE_RESET:
next_state = STATE_OPERATING;
STATE_OPERATING:
if((MIE & ip) | exception | ecall | ebreak) next_state = STATE_TRAP_TAKEN;
if(TRAP_TAKEN) next_state = STATE_TRAP_TAKEN;
else if(mret) next_state = STATE_TRAP_RETURN;
else next_state = STATE_OPERATING;
STATE_TRAP_TAKEN:
/steelcore/trunk/steel_top.v
15,6 → 15,7
// csr_file.v
// imm_generator.v
// load_unit.v
// store_unit.v
//
// Version 0.01
//
176,6 → 177,7
wire [31:0] SU_D_ADDR;
wire [3:0] SU_WR_MASK;
wire SU_WR_REQ;
wire TRAP_TAKEN;
// ---------------------------------
// PIPELINE STAGE 1
236,6 → 238,7
.FUNCT7_5(FUNCT7[5]),
.FUNCT3(FUNCT3),
.IADDER_OUT_1_TO_0(IADDER_OUT[1:0]),
.TRAP_TAKEN(TRAP_TAKEN),
.ALU_OPCODE(ALU_OPCODE),
.MEM_WR_REQ(MEM_WR_REQ),
377,7 → 380,9
.PC_SRC(PC_SRC),
.FLUSH(FLUSH)
.FLUSH(FLUSH),
.TRAP_TAKEN(TRAP_TAKEN)
 
);
/steelcore/steel_docs.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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