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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

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Rev 18 → Rev 19

/storm_core/templates/MEMORY.vhd File deleted \ No newline at end of file
/storm_core/rtl/REG_FILE.vhd
29,8 → 29,9
-- ###############################################################################################
 
CTRL_I : in STD_LOGIC_VECTOR(CTRL_MSB downto 0); -- control lines
OP_ADR_I : in STD_LOGIC_VECTOR(14 downto 0); -- operand addresses
MODE_I : in STD_LOGIC_VECTOR(04 downto 0); -- current operation mode
OP_ADR_I : in STD_LOGIC_VECTOR(14 downto 0); -- operand addresses
MODE_I : in STD_LOGIC_VECTOR(04 downto 0); -- current operation mode
USR_RD_I : in STD_LOGIC; -- use USR bank
 
-- ###############################################################################################
-- ## Operand Connection ##
67,7 → 68,7
 
-- Address Busses --
signal R_ADR_PORT_A, R_ADR_PORT_B, R_ADR_PORT_C : STD_LOGIC_VECTOR(4 downto 0);
signal W_ADR_PORT : STD_LOGIC_VECTOR(4 downto 0);
signal W_ADR_PORT, MODE_INT : STD_LOGIC_VECTOR(4 downto 0);
 
-- Address Translator --
component ADR_TRANSLATION_UNIT
108,6 → 109,9
 
-- Register File Read Access ----------------------------------------------------------------------
-- ---------------------------------------------------------------------------------------------------
--- Force USR bank read ---
MODE_INT <= MODE_I when (USR_RD_I = '0') else User32_MODE;
 
--- Read Access Port A ---
read_access_port_a:
114,7 → 118,7
ADR_TRANSLATION_UNIT
port map (
REG_ADR_I => OP_ADR_I(OP_A_ADR_3 downto OP_A_ADR_0),
MODE_I => MODE_I,
MODE_I => MODE_INT,
ADR_O => R_ADR_PORT_A
);
 
123,7 → 127,7
ADR_TRANSLATION_UNIT
port map (
REG_ADR_I => OP_ADR_I(OP_B_ADR_3 downto OP_B_ADR_0),
MODE_I => MODE_I,
MODE_I => MODE_INT,
ADR_O => R_ADR_PORT_B
);
 
132,7 → 136,7
ADR_TRANSLATION_UNIT
port map (
REG_ADR_I => OP_ADR_I(OP_C_ADR_3 downto OP_C_ADR_0),
MODE_I => MODE_I,
MODE_I => MODE_INT,
ADR_O => R_ADR_PORT_C
);
 
/storm_core/rtl/CORE.vhd
268,6 → 268,7
CTRL_I => WB_CTRL, -- stage control
OP_ADR_I => OP_ADR, -- operand addresses
MODE_I => CMSR(SREG_MODE_4 downto SREG_MODE_0), -- current processor mode
USR_RD_I => OF_CTRL(CTRL_RD_USR), -- read data from USR reg bank
WB_DATA_I => WB_DATA_LINE, -- write back bus
REG_PC_I => REG_PC, -- PC for manual operations
OP_A_O => OF_OP_A, -- register A output
/storm_core/rtl/CORE_PKG.vhd
103,30 → 103,32
constant CTRL_MEM_DQ_1 : natural := 24; -- '0' = see above, '1' = halfword
constant CTRL_MEM_SE : natural := 25; -- '0' = no sign extension, '1' = sign extension
constant CTRL_MEM_RW : natural := 26; -- '0' = read, '1' = write
constant CTRL_MEM_USER : natural := 27; -- '1' = access memory with "user_mode" output
 
constant CTRL_MREG_ACC : natural := 28; -- '1' = Access machine register file
constant CTRL_MREG_M : natural := 29; -- '0' = CMSR, '1' = SMSR
constant CTRL_MREG_RW : natural := 30; -- '0' = read, '1' = write
constant CTRL_MREG_FA : natural := 31; -- '0' = whole access, '1' = flag access
constant CTRL_RD_USR : natural := 27; -- '1' = read data from USR reg bank
constant CTRL_WR_USR : natural := 28; -- '1' = write fata to USR reg bank
 
constant CTRL_CP_ACC : natural := 32; -- '1' coprocessor access
constant CTRL_CP_RW : natural := 33; -- '0' read, '1' = write
constant CTRL_CP_REG_0 : natural := 34; -- cp register address bit 0
constant CTRL_CP_REG_1 : natural := 35; -- cp register address bit 1
constant CTRL_CP_REG_2 : natural := 36; -- cp register address bit 2
constant CTRL_CP_REG_3 : natural := 37; -- cp register address bit 3
constant CTRL_MREG_ACC : natural := 29; -- '1' = Access machine register file
constant CTRL_MREG_M : natural := 30; -- '0' = CMSR, '1' = SMSR
constant CTRL_MREG_RW : natural := 31; -- '0' = read, '1' = write
constant CTRL_MREG_FA : natural := 32; -- '0' = whole access, '1' = flag access
 
constant CTRL_SHIFT_M_0 : natural := 38; -- shift mode bit 0
constant CTRL_SHIFT_M_1 : natural := 39; -- shift mode bit 1
constant CTRL_SHIFT_V_0 : natural := 40; -- shift value bit 0
constant CTRL_SHIFT_V_1 : natural := 41; -- shift value bit 1
constant CTRL_SHIFT_V_2 : natural := 42; -- shift value bit 2
constant CTRL_SHIFT_V_3 : natural := 43; -- shift value bit 3
constant CTRL_SHIFT_V_4 : natural := 44; -- shift value bit 4
constant CTRL_MSB : natural := 44; -- size of control bus
constant CTRL_CP_ACC : natural := 33; -- '1' coprocessor access
constant CTRL_CP_RW : natural := 34; -- '0' read, '1' = write
constant CTRL_CP_REG_0 : natural := 35; -- cp register address bit 0
constant CTRL_CP_REG_1 : natural := 36; -- cp register address bit 1
constant CTRL_CP_REG_2 : natural := 37; -- cp register address bit 2
constant CTRL_CP_REG_3 : natural := 38; -- cp register address bit 3
 
constant CTRL_SHIFT_M_0 : natural := 39; -- shift mode bit 0
constant CTRL_SHIFT_M_1 : natural := 40; -- shift mode bit 1
constant CTRL_SHIFT_V_0 : natural := 41; -- shift value bit 0
constant CTRL_SHIFT_V_1 : natural := 42; -- shift value bit 1
constant CTRL_SHIFT_V_2 : natural := 43; -- shift value bit 2
constant CTRL_SHIFT_V_3 : natural := 44; -- shift value bit 3
constant CTRL_SHIFT_V_4 : natural := 45; -- shift value bit 4
 
constant CTRL_MSB : natural := 45; -- size of control bus
 
-- Progress Redefinitions --
constant CTRL_MODE_0 : natural := CTRL_AF; -- mode bit 0
constant CTRL_MODE_1 : natural := CTRL_ALU_FS_0; -- mode bit 1
252,6 → 254,7
-- Matt Kennon - The Call
-- Brad Paisley - Letter To Me
-- Montgomery Gentry - Where I Come From
-- Dixie Chicks - Ready To Run
 
-- INTERNAL MNEMONICS ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
354,6 → 357,7
CTRL_I : in STD_LOGIC_VECTOR(CTRL_MSB downto 0);
OP_ADR_I : in STD_LOGIC_VECTOR(14 downto 0);
MODE_I : in STD_LOGIC_VECTOR(04 downto 0);
USR_RD_I : in STD_LOGIC;
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
REG_PC_I : in STD_LOGIC_VECTOR(31 downto 0);
OP_A_O : out STD_LOGIC_VECTOR(31 downto 0);
/storm_core/rtl/LOAD_STORE_UNIT.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Load/Store Unit for Data Memory Access #
-- # *************************************************** #
-- # Last modified: 05.10.2011 #
-- # Last modified: 25.01.2012 #
-- #######################################################
 
library IEEE;
158,11 → 158,7
XMEM_ACC_REQ_O <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_MEM_ACC);
 
--- Mode for MEM access --
if (CTRL_I(CTRL_MEM_USER) = '1') then
XMEM_MODE_O <= User32_MODE; -- force user_mode
else
XMEM_MODE_O <= MODE_I; -- current processor mode
end if;
XMEM_MODE_O <= MODE_I; -- current processor mode
 
end process MEM_DATA_INTERFACE;
 
/storm_core/rtl/FLOW_CTRL.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Operation Flow Control Unit #
-- # *************************************************** #
-- # Last modified: 07.01.2012 #
-- # Last modified: 25.01.2012 #
-- #######################################################
 
library IEEE;
459,7 → 459,12
WB_CTRL <= (others => '0');
elsif (G_HALT_I = '0') then
WB_CTRL <= MEM_CTRL;
WB_CTRL(CTRL_MODE_4 downto CTRL_MODE_0) <= SREG_I(SREG_MODE_4 downto SREG_MODE_0);
--- Write back to USER register bank ---
if (MEM_CTRL(CTRL_WR_USR) = '1') then
WB_CTRL(CTRL_MODE_4 downto CTRL_MODE_0) <= User32_MODE;
else
WB_CTRL(CTRL_MODE_4 downto CTRL_MODE_0) <= SREG_I(SREG_MODE_4 downto SREG_MODE_0);
end if;
end if;
end if;
end process STAGE_BUFFER_5;
/storm_core/rtl/OPCODE_DECODER.vhd
3,7 → 3,7
-- # *************************************************** #
-- # ARM-Native OPCODE Decoding Unit #
-- # *************************************************** #
-- # Last modified: 07.01.2012 #
-- # Last modified: 25.01.2012 #
-- #######################################################
 
library IEEE;
73,6 → 73,7
variable block_t_en_v : std_logic;
variable block_t_radr_v : std_logic_vector(03 downto 0);
variable block_t_tmp_v : std_logic_vector(15 downto 0);
variable pc_in_list_v : std_logic;
begin
 
--- DEFAULT CONTROL ---
182,7 → 183,6
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ
DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN
DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode
NEXT_DUAL_OP(0) <= '1';
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA
REG_SEL(OP_A_IS_REG) <= '1';
230,7 → 230,6
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE
DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN
DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode
NEXT_DUAL_OP(0) <= '1';
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA
REG_SEL(OP_A_IS_REG) <= '1';
558,6 → 557,14
NEXT_DUAL_OP(4 downto 1) <= Std_Logic_Vector(unsigned(DUAL_OP(4 downto 1)) + 1);
end if;
 
pc_in_list_v := '0';
if (block_t_radr_v = C_PC_ADR) then
pc_in_list_v := '1';
end if;
DEC_CTRL(CTRL_RD_USR) <= (not INSTR_REG(20)) and INSTR_REG(22); -- read reg in USR mode
DEC_CTRL(CTRL_WR_USR) <= INSTR_REG(20) and INSTR_REG(22) and (not pc_in_list_v); -- write reg in USR mode
DEC_CTRL(CTRL_AF) <= INSTR_REG(20) and INSTR_REG(22) and pc_in_list_v; -- SMSR -> CMSR
 
temp_6 := block_t_en_v & INSTR_REG(20) & INSTR_REG(24) & INSTR_REG(21);
case temp_6 is -- L_P_W
 
596,7 → 603,6
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '0'; -- MEM_READ
DEC_CTRL(CTRL_WB_EN) <= '1'; -- WB EN
DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode
NEXT_DUAL_OP(0) <= '1';
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA
REG_SEL(OP_C_IS_REG) <= '0';
636,7 → 642,6
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE
DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN
DEC_CTRL(CTRL_MEM_USER) <= INSTR_REG(21); -- access in pseudo-user-mode
NEXT_DUAL_OP(0) <= '1';
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassA; -- ALU_CTRL = PassA
REG_SEL(OP_C_IS_REG) <= '1';
/storm_core/doc/STORM CORE datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/sim/STORM_core_TB.vhd
0,0 → 1,264
-- #######################################################
-- # < STORM Core Processor by Stephan Nolting > #
-- # *************************************************** #
-- # STORM Core / STORM SoC Testbench #
-- # *************************************************** #
-- # Last modified: 31.01.2012 #
-- #######################################################
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity STORM_core_TB is
end STORM_core_TB;
 
architecture Structure of STORM_core_TB is
 
-- Architecture Constants ---------------------------------------------------------
-- -----------------------------------------------------------------------------------
constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
constant INT_MEM_SIZE_C : natural := 2048; -- bytes
constant BOOT_VECTOR_C : STD_LOGIC_VECTOR(31 downto 0) := INT_MEM_BASE_C;
constant I_CACHE_PAGES_C : natural := 8; -- number of pages in I cache
constant I_CACHE_PAGE_SIZE_C : natural := 64; -- page size in I cache
constant D_CACHE_PAGES_C : natural := 8; -- number of pages in D cache
constant D_CACHE_PAGE_SIZE_C : natural := 1; -- page size in D cache
 
 
-- Global Signals -----------------------------------------------------------------
-- -----------------------------------------------------------------------------------
 
-- Global Clock & Reset --
signal EXT_RST : STD_LOGIC;
signal MAIN_RST : STD_LOGIC;
signal SYS_RST : STD_LOGIC;
signal CORE_CLK : STD_LOGIC := '0';
signal BUS_CLK : STD_LOGIC := '0';
signal STORM_IRQ : STD_LOGIC;
signal STORM_FIQ : STD_LOGIC;
 
-- Wishbone Core Bus --
signal CORE_WB_ADR_O : STD_LOGIC_VECTOR(31 downto 0); -- address
signal CORE_WB_CTI_O : STD_LOGIC_VECTOR(02 downto 0); -- cycle type
signal CORE_WB_TGC_O : STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
signal CORE_WB_SEL_O : STD_LOGIC_VECTOR(03 downto 0); -- byte select
signal CORE_WB_WE_O : STD_LOGIC; -- write enable
signal CORE_WB_DATA_O : STD_LOGIC_VECTOR(31 downto 0); -- data out
signal CORE_WB_DATA_I : STD_LOGIC_VECTOR(31 downto 0); -- data in
signal CORE_WB_STB_O : STD_LOGIC; -- valid transfer
signal CORE_WB_CYC_O : STD_LOGIC; -- valid cycle
signal CORE_WB_ACK_I : STD_LOGIC; -- acknowledge
signal CORE_WB_HALT_I : STD_LOGIC; -- halt request
 
 
-- Component interface ------------------------------------------------------------
-- -----------------------------------------------------------------------------------
 
-- Internal Working Memory --
signal INT_MEM_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal INT_MEM_STB_I : STD_LOGIC;
signal INT_MEM_ACK_O : STD_LOGIC;
signal INT_MEM_HALT_O : STD_LOGIC;
 
 
-- Logarithm duales ---------------------------------------------------------------
-- -----------------------------------------------------------------------------------
function log2(temp : natural) return natural is
begin
for i in 0 to integer'high loop
if (2**i >= temp) then
return i;
end if;
end loop;
return 0;
end function log2;
 
 
-- STORM Core Top Entity ----------------------------------------------------------
-- -----------------------------------------------------------------------------------
component STORM_TOP
generic (
I_CACHE_PAGES : natural := 4; -- number of pages in I cache
I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
D_CACHE_PAGES : natural := 8; -- number of pages in D cache
D_CACHE_PAGE_SIZE : natural := 4; -- page size in D cache
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0) := x"00000000" -- boot address
);
port (
-- Global Control --
CORE_CLK_I : in STD_LOGIC; -- core clock input
BUS_CLK_I : in STD_LOGIC; -- bus clock input
RST_I : in STD_LOGIC; -- global reset input
F_RST_O : out STD_LOGIC; -- force system reset
 
-- Wishbone Bus --
WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- address
WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0); -- cycle type
WB_TGC_O : out STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); -- byte select
WB_WE_O : out STD_LOGIC; -- write enable
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data out
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data in
WB_STB_O : out STD_LOGIC; -- valid transfer
WB_CYC_O : out STD_LOGIC; -- valid cycle
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_HALT_I : in STD_LOGIC; -- halt request
 
-- Interrupt Request Lines --
IRQ_I : in STD_LOGIC; -- interrupt request
FIQ_I : in STD_LOGIC -- fast interrupt request
);
end component;
 
 
-- Internal Working Memory --------------------------------------------------------
-- -----------------------------------------------------------------------------------
component MEMORY
generic (
MEM_SIZE : natural := 256; -- memory cells
LOG2_MEM_SIZE : natural := 8 -- log2(memory cells)
);
port (
-- Wishbone Bus --
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
WB_WE_I : in STD_LOGIC; -- write enable
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC -- throttle master
);
end component;
 
 
begin
 
-- #################################################################################################################################
-- ### STORM CORE PROCESSOR ###
-- #################################################################################################################################
 
-- CLOCK/RESET GENERATOR -------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
-- Clock Generator --
CORE_CLK <= not CORE_CLK after 20 ns; -- 50MHz
BUS_CLK <= not BUS_CLK after 40 ns; -- 25MHz
 
-- Reset System --
EXT_RST <= '1', '0' after 400 ns;
MAIN_RST <= EXT_RST or SYS_RST;
 
-- Interrupt Generator --
STORM_IRQ <= '0', '1' after 2000 ns, '0' after 2020 ns;
STORM_FIQ <= '0';
 
 
 
-- STORM CORE PROCESSOR --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
STORM_TOP_INST: STORM_TOP
generic map (
I_CACHE_PAGES => I_CACHE_PAGES_C, -- number of pages in I cache
I_CACHE_PAGE_SIZE => I_CACHE_PAGE_SIZE_C, -- page size in I cache
D_CACHE_PAGES => D_CACHE_PAGES_C, -- number of pages in D cache
D_CACHE_PAGE_SIZE => D_CACHE_PAGE_SIZE_C, -- page size in D cache
BOOT_VECTOR => BOOT_VECTOR_C -- startup boot address
)
port map (
-- Global Control --
CORE_CLK_I => CORE_CLK, -- core clock input
BUS_CLK_I => BUS_CLK, -- bus clock input
RST_I => MAIN_RST, -- global reset input
F_RST_O => SYS_RST, -- force system reset
 
-- Wishbone Bus --
WB_ADR_O => CORE_WB_ADR_O, -- address
WB_CTI_O => CORE_WB_CTI_O, -- cycle type
WB_TGC_O => CORE_WB_TGC_O, -- cycle tag
WB_SEL_O => CORE_WB_SEL_O, -- byte select
WB_WE_O => CORE_WB_WE_O, -- write enable
WB_DATA_O => CORE_WB_DATA_O, -- data out
WB_DATA_I => CORE_WB_DATA_I, -- data in
WB_STB_O => CORE_WB_STB_O, -- valid transfer
WB_CYC_O => CORE_WB_CYC_O, -- valid cycle
WB_ACK_I => CORE_WB_ACK_I, -- acknowledge
WB_HALT_I => CORE_WB_HALT_I, -- halt request
 
-- Interrupt Request Lines --
IRQ_I => STORM_IRQ, -- interrupt request
FIQ_I => STORM_FIQ -- fast interrupt request
);
 
 
 
-- #################################################################################################################################
-- ### WISHBONE FABRIC ###
-- #################################################################################################################################
 
-- Read-Back Data Selector -----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_DATA_I <=
INT_MEM_DATA_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else
-- DUMMY0_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else
-- DUMMY1_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else
x"00000000";
 
 
-- Acknowledge Terminal --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_ACK_I <= INT_MEM_ACK_O or
-- DUMMY0_ACK_O or
-- DUMMY1_ACK_O or
'0';
 
 
-- Halt Terminal ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_HALT_I <= INT_MEM_HALT_O or
-- DUMMY0_HALT_O or
-- DUMMY1_HALT_O or
'0';
 
 
-- Valid Transfer Signal Terminal ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INT_MEM_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else '0';
-- DUMMY0_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else '0';
-- DUMMY1_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else '0';
 
 
 
-- #################################################################################################################################
-- ### SYSTEM COMPONENTS ###
-- #################################################################################################################################
 
-- Internal Working Memory -----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INTERNAL_MEMORY: MEMORY
generic map (
MEM_SIZE => INT_MEM_SIZE_C/4, -- memory size in 32-bit cells
LOG2_MEM_SIZE => log2(INT_MEM_SIZE_C/4) -- log2 memory size in 32-bit cells
)
port map(
WB_CLK_I => BUS_CLK,
WB_RST_I => MAIN_RST,
WB_CTI_I => CORE_WB_CTI_O,
WB_TGC_I => CORE_WB_TGC_O,
WB_ADR_I => CORE_WB_ADR_O(log2(INT_MEM_SIZE_C/4)+1 downto 2), -- word boundary access
WB_DATA_I => CORE_WB_DATA_O,
WB_DATA_O => INT_MEM_DATA_O,
WB_SEL_I => CORE_WB_SEL_O,
WB_WE_I => CORE_WB_WE_O,
WB_STB_I => INT_MEM_STB_I,
WB_ACK_O => INT_MEM_ACK_O,
WB_HALT_O => INT_MEM_HALT_O
);
 
 
end Structure;
/storm_core/sim/MEMORY.vhd
0,0 → 1,144
-- ######################################################
-- # < STORM CORE SYSTEM by Stephan Nolting > #
-- # ************************************************** #
-- # Internal Working Memory #
-- # ************************************************** #
-- # Version 3.0, 25.11.2011, PipeWB compatible #
-- ######################################################
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
library work;
use work.STORM_core_package.ALL;
 
entity MEMORY is
generic (
MEM_SIZE : natural := 256; -- memory cells
LOG2_MEM_SIZE : natural := 8 -- log2(memory cells)
);
port (
-- Wishbone Bus --
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
WB_WE_I : in STD_LOGIC; -- write enable
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC -- throttle master
);
end MEMORY;
 
architecture Behavioral of MEMORY is
 
--- Are we simulating? ---
constant IS_SIM : boolean := TRUE;
 
--- Ack Buffer --
signal WB_ACK_O_INT : STD_LOGIC;
 
--- Memory Type ---
type RAM_8 is array(0 to MEM_SIZE - 1) of STD_LOGIC_VECTOR(7 downto 0);
type RAM_32 is array(3 downto 0) of RAM_8;
type RAM_IMAGE_TYPE is array (0 to MEM_SIZE - 1) of STD_LOGIC_VECTOR(31 downto 0);
--- INIT MEMORY IMAGE ---
-----------------------------------------------------------------
constant RAM_IMAGE : RAM_IMAGE_TYPE :=
(
-- ############################################
-- # PLACE YOUR PROGRAM HERE #
-- ############################################
);
-----------------------------------------------------------------
 
--- Init RAM function ---
function load_mem(IMAGE : RAM_IMAGE_TYPE; j : natural) return RAM_8 is
variable TEMP_MEM : RAM_8;
begin
for i in 0 to MEM_SIZE - 1 loop
TEMP_MEM(i) := IMAGE(i)(8*j+7 downto 8*j);
end loop;
return TEMP_MEM;
end load_mem;
 
--- Internal Working Memory ---
signal MEM_FILE_HH : RAM_8 := load_mem(RAM_IMAGE, 3);
signal MEM_FILE_HL : RAM_8 := load_mem(RAM_IMAGE, 2);
signal MEM_FILE_LH : RAM_8 := load_mem(RAM_IMAGE, 1);
signal MEM_FILE_LL : RAM_8 := load_mem(RAM_IMAGE, 0);
 
--- Dummy memory for simulation ---
signal SIM_MEM : RAM_IMAGE_TYPE;
 
begin
 
-- STORM data/instruction memory -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
MEM_FILE_ACCESS: process(WB_CLK_I)
begin
--- Sync Write ---
if rising_edge(WB_CLK_I) then
if (WB_RST_I = '1') then
WB_ACK_O_INT <= '0';
else
 
--- Data Read/Write ---
if (WB_STB_I = '1') then
if (WB_WE_I = '1') then
if (WB_SEL_I(0) = '1') then
MEM_FILE_LL(to_integer(unsigned(WB_ADR_I))) <= WB_DATA_I(8*0+7 downto 8*0);
end if;
if (WB_SEL_I(1) = '1') then
MEM_FILE_LH(to_integer(unsigned(WB_ADR_I))) <= WB_DATA_I(8*1+7 downto 8*1);
end if;
if (WB_SEL_I(2) = '1') then
MEM_FILE_HL(to_integer(unsigned(WB_ADR_I))) <= WB_DATA_I(8*2+7 downto 8*2);
end if;
if (WB_SEL_I(3) = '1') then
MEM_FILE_HH(to_integer(unsigned(WB_ADR_I))) <= WB_DATA_I(8*3+7 downto 8*3);
end if;
end if;
WB_DATA_O(8*0+7 downto 8*0) <= MEM_FILE_LL(to_integer(unsigned(WB_ADR_I)));
WB_DATA_O(8*1+7 downto 8*1) <= MEM_FILE_LH(to_integer(unsigned(WB_ADR_I)));
WB_DATA_O(8*2+7 downto 8*2) <= MEM_FILE_HL(to_integer(unsigned(WB_ADR_I)));
WB_DATA_O(8*3+7 downto 8*3) <= MEM_FILE_HH(to_integer(unsigned(WB_ADR_I)));
end if;
 
--- ACK Control ---
if (WB_CTI_I = "000") or (WB_CTI_I = "111") then
WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT);
else
WB_ACK_O_INT <= WB_STB_I;
end if;
end if;
end if;
end process MEM_FILE_ACCESS;
 
--- ACK Signal ---
WB_ACK_O <= WB_ACK_O_INT;
 
--- Throttle ---
WB_HALT_O <= '0'; -- yeay, we're at full speed!
 
 
 
-- Dummy memory for simulation -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- use this memory dummy for simulation output
DEBUG_SIM_MEM:
if (IS_SIM = TRUE) generate
GEN_DEBUG_MEM:
for i in 0 to MEM_SIZE - 1 generate
SIM_MEM(i) <= MEM_FILE_HH(i) & MEM_FILE_HL(i) & MEM_FILE_LH(i) & MEM_FILE_LL(i);
end generate;
end generate;
 
 
end Behavioral;
/storm_core/sim/Xilinx ISIM/storm_core_debug_wave.wcfg
0,0 → 1,395
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="N:/N/STORM Core/syn_xilinx/STORM_core_TB_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="storm_core_package" />
<top_module name="storm_core_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="43" />
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore globals</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/core_clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">core_clk_i</obj_property>
<obj_property name="ObjectShortName">core_clk_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/bus_clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_clk_i</obj_property>
<obj_property name="ObjectShortName">bus_clk_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/halt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">halt</obj_property>
<obj_property name="ObjectShortName">halt</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/f_rst_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">f_rst_o</obj_property>
<obj_property name="ObjectShortName">f_rst_o</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore interrupt</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/ext_int_req_sync" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ext_int_req_sync[3:0]</obj_property>
<obj_property name="ObjectShortName">ext_int_req_sync[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cont_exe" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">cont_exe</obj_property>
<obj_property name="ObjectShortName">cont_exe</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/new_mode" type="array" db_ref_id="1">
<obj_property name="ElementShortName">new_mode[4:0]</obj_property>
<obj_property name="ObjectShortName">new_mode[4:0]</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore pipeline</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/of_ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">of_ctrl_o[45:0]</obj_property>
<obj_property name="ObjectShortName">of_ctrl_o[45:0]</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/ms_ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ms_ctrl_o[45:0]</obj_property>
<obj_property name="ObjectShortName">ms_ctrl_o[45:0]</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/ex1_ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ex1_ctrl_o[45:0]</obj_property>
<obj_property name="ObjectShortName">ex1_ctrl_o[45:0]</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/mem_ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mem_ctrl_o[45:0]</obj_property>
<obj_property name="ObjectShortName">mem_ctrl_o[45:0]</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/wb_ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">wb_ctrl_o[45:0]</obj_property>
<obj_property name="ObjectShortName">wb_ctrl_o[45:0]</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore registers</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file" type="array" db_ref_id="1">
<obj_property name="ElementShortName">reg_file[0:31]</obj_property>
<obj_property name="ObjectShortName">reg_file[0:31]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">reg_file[0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">reg_file[1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">reg_file[2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">reg_file[3]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">reg_file[4]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[5]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">reg_file[5]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[6]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">reg_file[6]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[7]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">reg_file[7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[8]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">reg_file[8]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[9]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">reg_file[9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[10]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">reg_file[10]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[11]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">reg_file[11]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[12]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">reg_file[12]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[13]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">reg_file[13]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[14]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">reg_file[14]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[15]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">reg_file[15]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[16]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[16]</obj_property>
<obj_property name="ObjectShortName">reg_file[16]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[17]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[17]</obj_property>
<obj_property name="ObjectShortName">reg_file[17]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[18]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[18]</obj_property>
<obj_property name="ObjectShortName">reg_file[18]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[19]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[19]</obj_property>
<obj_property name="ObjectShortName">reg_file[19]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[20]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[20]</obj_property>
<obj_property name="ObjectShortName">reg_file[20]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[21]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[21]</obj_property>
<obj_property name="ObjectShortName">reg_file[21]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[22]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[22]</obj_property>
<obj_property name="ObjectShortName">reg_file[22]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[23]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[23]</obj_property>
<obj_property name="ObjectShortName">reg_file[23]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[24]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[24]</obj_property>
<obj_property name="ObjectShortName">reg_file[24]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[25]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[25]</obj_property>
<obj_property name="ObjectShortName">reg_file[25]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[26]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[26]</obj_property>
<obj_property name="ObjectShortName">reg_file[26]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[27]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[27]</obj_property>
<obj_property name="ObjectShortName">reg_file[27]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[28]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[28]</obj_property>
<obj_property name="ObjectShortName">reg_file[28]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[29]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[29]</obj_property>
<obj_property name="ObjectShortName">reg_file[29]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[30]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[30]</obj_property>
<obj_property name="ObjectShortName">reg_file[30]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Register_File/reg_file[31]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[31]</obj_property>
<obj_property name="ObjectShortName">reg_file[31]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/mcr_pc" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mcr_pc[31:0]</obj_property>
<obj_property name="ObjectShortName">mcr_pc[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ff0000</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Operation_Flow_Control/instr_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">instr_reg[31:0]</obj_property>
<obj_property name="ObjectShortName">instr_reg[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#0000ff</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/mcr_cmsr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mcr_cmsr[31:0]</obj_property>
<obj_property name="ObjectShortName">mcr_cmsr[31:0]</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffffff</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">DATA CACHE</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_ll" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_ll[0:7]</obj_property>
<obj_property name="ObjectShortName">cache_mem_ll[0:7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_lh" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_lh[0:7]</obj_property>
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