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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

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Rev 20 → Rev 21

/storm_core/rtl/CACHE.vhd
9,7 → 9,7
-- # A cache line contains a complete word (32-bit). #
-- # The cache is fully associative. #
-- # *************************************************** #
-- # Last modified: 04.01.2012 #
-- # Last modified: 15.02.2012 #
-- #######################################################
 
library IEEE;
24,11 → 24,10
-- ## Cache Configuration ##
-- ################################################################################################################
generic (
CACHE_PAGES : natural := 4;
LOG2_CACHE_PAGES : natural := 2;
PAGE_SIZE : natural := 4; -- #words
LOG2_PAGE_SIZE : natural := 2;
READ_ONLY : boolean := FALSE
CACHE_PAGES : natural := 8;
LOG2_CACHE_PAGES : natural := 3;
PAGE_SIZE : natural := 2; -- #words
LOG2_PAGE_SIZE : natural := 1
);
port (
-- ################################################################################################################
36,7 → 35,6
-- ################################################################################################################
 
CORE_CLK_I : in STD_LOGIC; -- core clock, all triggering on rising edge
BUS_CLK_I : in STD_LOGIC; -- bus clock, all triggering on rising edge
RST_I : in STD_LOGIC; -- global reset, high active, sync
HALT_I : in STD_LOGIC; -- global storm halt signal
 
59,17 → 57,17
B_ADR_I : in STD_LOGIC_VECTOR(31 downto 0); -- address input
B_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data input
B_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data output
B_DQ_I : in STD_LOGIC_VECTOR(01 downto 0); -- data quantity
B_WE_I : in STD_LOGIC; -- write enable
B_PG_SEL_I : in STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
B_DRT_SEL_O : out STD_LOGIC; -- dirty bit of selected page
B_BSA_O : out STD_LOGIC_VECTOR(31 downto 0); -- base adr of selected page
B_DRT_ACK_I : in STD_LOGIC; -- dirty acknowledged
B_MSS_ACK_I : in STD_LOGIC; -- miss acknowledged
B_IO_ACC_I : in STD_LOGIC; -- IO access
 
-- ################################################################################################################
-- ## Cache Control Port ##
-- ################################################################################################################
 
C_UPDATE_I : in STD_LOGIC; -- bus unit takes control
C_FRESH_I : in STD_LOGIC; -- refresh accessed page
C_FLUSH_I : in STD_LOGIC; -- flush cache
C_CLEAR_I : in STD_LOGIC; -- clear cache
C_MISS_O : out STD_LOGIC; -- cache miss access
81,71 → 79,71
 
architecture Behavioral of CACHE is
 
-- Are we simulating? --
constant IS_SIM : boolean := FALSE;
-- Cache Arbiter --
type ARB_STATE_TYPE is (STORM_ACCESS, MISS_STATE, IO_REQUEST, IO_PIPE_RESYNC, IO_PIPE_RESYNC_END, DIRTY_STATE, PIPE_RESYNC);
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE;
signal ADR_BUF, ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal DAT_BUF, DAT_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal HST_BUF, HST_BUF_NXT : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal BIT_BUF, BIT_BUF_NXT : STD_LOGIC;
 
-- Cache Memory --
type cache_base_type is array(0 to (CACHE_PAGES*PAGE_SIZE)-1) of STD_LOGIC_VECTOR(07 downto 0);
type sim_mem_type is array(0 to (CACHE_PAGES*PAGE_SIZE)-1) of STD_LOGIC_VECTOR(31 downto 0);
signal CACHE_MEM_LL : cache_base_type := (others => (others => '0'));
signal CACHE_MEM_LH : cache_base_type := (others => (others => '0'));
signal CACHE_MEM_HL : cache_base_type := (others => (others => '0'));
signal CACHE_MEM_HH : cache_base_type := (others => (others => '0'));
signal CACHE_WE : STD_LOGIC;
signal CACHE_ADR : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES+(LOG2_PAGE_SIZE-1) downto 0);
signal CACHE_R_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal CACHE_W_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal ADR_INT : STD_LOGIC_VECTOR(31 downto 0);
signal DQ_INT : STD_LOGIC_VECTOR(01 downto 0);
type cache_mem_type is array(0 to (CACHE_PAGES*PAGE_SIZE)-1) of STD_LOGIC_VECTOR(07 downto 0);
signal CACHE_MEM_LL : cache_mem_type := (others => (others => '0'));
signal CACHE_MEM_LH : cache_mem_type := (others => (others => '0'));
signal CACHE_MEM_HL : cache_mem_type := (others => (others => '0'));
signal CACHE_MEM_HH : cache_mem_type := (others => (others => '0'));
type sim_mem_type is array(0 to (CACHE_PAGES*PAGE_SIZE)-1) of STD_LOGIC_VECTOR(31 downto 0);
signal SIM_MEM : sim_mem_type;
signal CACHE_ADR : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES+(LOG2_PAGE_SIZE-1) downto 0);
 
-- Page Base Memory --
type page_base_type is array(0 to CACHE_PAGES-1) of STD_LOGIC_VECTOR(31 downto LOG2_PAGE_SIZE+2);
type page_base_type is array(0 to CACHE_PAGES-1) of STD_LOGIC_VECTOR(31 downto LOG2_PAGE_SIZE+2);
signal PAGE_BASE_ADR : page_base_type;
signal SET_NEW_BAS : STD_LOGIC;
 
-- Status Flags --
signal VALID_FLAG : STD_LOGIC_VECTOR(CACHE_PAGES-1 downto 0);
signal CLR_CUR_VAL : STD_LOGIC;
signal SET_CUR_VAL : STD_LOGIC;
signal CLR_ALL_VAL : STD_LOGIC;
signal DIRTY_FLAG : STD_LOGIC_VECTOR(CACHE_PAGES-1 downto 0);
signal CACHE_DIRTY : STD_LOGIC;
signal CLR_CUR_DRT : STD_LOGIC;
signal SET_CUR_DRT : STD_LOGIC;
signal SET_ALL_DRT : STD_LOGIC;
 
-- Cache Access History --
type cache_hist_mem is array(CACHE_PAGES-1 downto 0) of STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal HIST_MEM : cache_hist_mem;
signal NEW_ENTRY_ADR : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal ACCESS_SREG : STD_LOGIC_VECTOR(03 downto 0);
signal UPDATE_HISTORY : STD_LOGIC;
signal UPDATE_HIST_FF : STD_LOGIC;
 
-- Page Selector --
signal PAGE_SELECT : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal PAGE_SELECT_FF : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal PAGE_TRANSLATE : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal NEW_ENTRY_PAGE : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
signal B_BASE_O_SEL : STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
 
-- Read-Back Buffer --
signal RB_BUFFER : STD_LOGIC_VECTOR(31 downto 0);
signal RB_DATA : STD_LOGIC_VECTOR(31 downto 0);
signal RB_BUFF_EN : STD_LOGIC;
 
-- Internal Access Signals --
signal DATA_INT : STD_LOGIC_VECTOR(31 downto 0);
signal ADR_INT : STD_LOGIC_VECTOR(31 downto 0);
signal DQ_INT : STD_LOGIC_VECTOR(01 downto 0);
signal WE_INT : STD_LOGIC;
signal CS_INT : STD_LOGIC;
 
-- Internal Control --
signal CACHE_HIT : STD_LOGIC;
signal CACHE_MISS : STD_LOGIC;
signal BYTE_SEL : STD_LOGIC_VECTOR(03 downto 0);
signal P_DATA_O_SEL : STD_LOGIC;
signal P_DATA_O_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal P_DATA_O_INT : STD_LOGIC_VECTOR(31 downto 0);
 
-- Cache Coherency Control --
signal DRT_CNT : STD_LOGIC_VECTOR(02 downto 0);
 
begin
 
-- Access Control --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ADR_INT <= P_ADR_I when (C_UPDATE_I = '0') else B_ADR_I; -- access address
DATA_INT <= P_DATA_I when (C_UPDATE_I = '0') else B_DATA_I; -- input data
DQ_INT <= P_DQ_I when (C_UPDATE_I = '0') else B_DQ_I; -- data quantity
WE_INT <= P_WE_I when (C_UPDATE_I = '0') else B_WE_I; -- write enable
CS_INT <= P_CS_I when (C_UPDATE_I = '0') else B_CS_I; -- chip select
 
 
 
-- Page Base Address System ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
PAGE_ADR_SYS: process(CORE_CLK_I, PAGE_BASE_ADR, B_PG_SEL_I)
PAGE_ADR_SYS: process(CORE_CLK_I, PAGE_BASE_ADR, B_BASE_O_SEL)
begin
-- Update Base Adr Register --
if rising_edge(CORE_CLK_I) then
153,24 → 151,69
for i in 0 to CACHE_PAGES-1 loop
PAGE_BASE_ADR(i) <= (others => '0');
end loop;
elsif (CS_INT = '1') and (WE_INT = '1') and (C_UPDATE_I = '1') then
PAGE_BASE_ADR(to_integer(unsigned(NEW_ENTRY_ADR))) <= ADR_INT(31 downto LOG2_PAGE_SIZE+2);
elsif (SET_NEW_BAS = '1') then
PAGE_BASE_ADR(to_integer(unsigned(NEW_ENTRY_PAGE))) <= ADR_INT(31 downto LOG2_PAGE_SIZE+2);
end if;
end if;
 
-- Bus unit Base Adr request --
--if rising_edge(CLK_I) then
--if (RST_I = '0') then
--B_BSA_O <= (others => '0');
--else
B_BSA_O <= (others => '0');
B_BSA_O(31 downto LOG2_PAGE_SIZE+2) <= PAGE_BASE_ADR(to_integer(unsigned(B_PG_SEL_I)));
--end if;
--end if;
-- Base ADR output for bus unit --
B_BSA_O <= (others => '0');
B_BSA_O(31 downto LOG2_PAGE_SIZE+2) <= PAGE_BASE_ADR(to_integer(unsigned(B_BASE_O_SEL)));
end process PAGE_ADR_SYS;
 
 
 
-- Cache Access History --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CACHE_ACCESS_HIST_BUF: process(CORE_CLK_I)
begin
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
PAGE_SELECT_FF <= (others => '0');
UPDATE_HIST_FF <= '0';
else
PAGE_SELECT_FF <= PAGE_SELECT_FF;
UPDATE_HIST_FF <= UPDATE_HISTORY;
end if;
end if;
end process CACHE_ACCESS_HIST_BUF;
 
 
CACHE_ACCESS_HISTORY: process(HIST_MEM, PAGE_SELECT_FF, CORE_CLK_I)
variable hist_mem_ce_v : std_logic_vector(CACHE_PAGES-1 downto 0);
begin
--- CE signal hierarchy comparator ---
hist_mem_ce_v := (others => '1');
for i in 0 to CACHE_PAGES-1 loop
if (HIST_MEM(CACHE_PAGES-1-i) = PAGE_SELECT_FF) then
exit;
else
hist_mem_ce_v(CACHE_PAGES-1-i) := '0'; -- compare hit
end if;
end loop;
 
--- Sync update ---
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
for i in 0 to CACHE_PAGES-1 loop
HIST_MEM(i) <= std_logic_vector(to_unsigned(i, LOG2_CACHE_PAGES));
end loop;
elsif (UPDATE_HIST_FF = '1') then
for i in 0 to CACHE_PAGES-1 loop
if (hist_mem_ce_v(CACHE_PAGES-1-i) = '1') then
if (i = CACHE_PAGES-1) then
HIST_MEM(CACHE_PAGES-1-i) <= PAGE_SELECT_FF;
else
HIST_MEM(CACHE_PAGES-1-i) <= HIST_MEM(CACHE_PAGES-1-i-1);
end if;
end if;
end loop;
end if;
end if;
end process CACHE_ACCESS_HISTORY;
 
 
 
-- Page Validation System ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
PAGE_VALID_SYS: process(CORE_CLK_I)
177,12 → 220,14
begin
-- Update Valid Status Flag --
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') or (C_CLEAR_I = '1') then
if (RST_I = '1') or (CLR_ALL_VAL = '1') then
for i in 0 to CACHE_PAGES-1 loop
VALID_FLAG(i) <= '0';
end loop;
elsif (CS_INT = '1') and (WE_INT = '1') and (C_UPDATE_I = '1') then
VALID_FLAG(to_integer(unsigned(NEW_ENTRY_ADR))) <= '1';
elsif (CLR_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
end if;
end if;
end process PAGE_VALID_SYS;
189,52 → 234,229
 
 
 
-- Page Modification Flag ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
DIRTY_REG: process(CORE_CLK_I, DIRTY_FLAG, VALID_FLAG)
variable temp_v : std_logic;
begin
-- Sync update --
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '0';
end loop;
elsif (SET_ALL_DRT = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '1';
end loop;
else
if (CLR_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
end if;
end if;
end if;
 
-- Any dirty bits? --
temp_v := '0';
for i in 0 to CACHE_PAGES-1 loop
temp_v := temp_v or (DIRTY_FLAG(i) and VALID_FLAG(i));
end loop;
CACHE_DIRTY <= temp_v;
end process DIRTY_REG;
 
 
 
-- HIT / MISS Detector ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CONTENT_DETECTOR: process(ADR_INT, PAGE_BASE_ADR, VALID_FLAG, P_CS_I, C_UPDATE_I, NEW_ENTRY_ADR)
CONTENT_DETECTOR: process(ADR_INT, PAGE_BASE_ADR, VALID_FLAG, P_CS_I)
variable miss_v : std_logic;
begin
miss_v := '1';
for i in 0 to CACHE_PAGES-1 loop
PAGE_SELECT <= std_logic_vector(to_unsigned(i, LOG2_CACHE_PAGES));
if (PAGE_BASE_ADR(i) = ADR_INT(31 downto LOG2_PAGE_SIZE+2)) then
if (VALID_FLAG(i) = '1') then
miss_v := '0';
exit;
end if;
PAGE_TRANSLATE <= std_logic_vector(to_unsigned(i, LOG2_CACHE_PAGES));
if (PAGE_BASE_ADR(i) = ADR_INT(31 downto LOG2_PAGE_SIZE+2)) and (VALID_FLAG(i) = '1') then
miss_v := '0';
exit;
end if;
end loop;
 
-- Only STORM access can cause a hit/miss
CACHE_HIT <= (not miss_v) and P_CS_I;
C_MISS_O <= miss_v and P_CS_I;
C_HIT_O <= (not miss_v) and P_CS_I;
CACHE_HIT <= not miss_v;
CACHE_MISS <= miss_v;
C_HIT_O <= (not miss_v) and P_CS_I; -- Output for statistic generator
end process CONTENT_DETECTOR;
 
 
 
-- Cache Access History --------------------------------------------------------------------------------
-- Cache Arbiter ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CACHE_ACCESS_HISTORY: process(CORE_CLK_I) -- 0, 1, 2, 3, ... older ones
CACHE_ARBITER_SYNC: process(CORE_CLK_I)
begin
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
for i in 0 to CACHE_PAGES-1 loop
HIST_MEM(i) <= std_logic_vector(to_unsigned((CACHE_PAGES-1)-i, LOG2_CACHE_PAGES));
end loop;
elsif (CACHE_HIT = '1') and (C_UPDATE_I = '0') then -- Cache access
if (HIST_MEM(0) /= PAGE_SELECT) then
HIST_MEM <= HIST_MEM(CACHE_PAGES-2 downto 0) & PAGE_SELECT;
end if;
ARB_STATE <= STORM_ACCESS;
ADR_BUF <= (others => '0');
DAT_BUF <= (others => '0');
HST_BUF <= (others => '0');
BIT_BUF <= '0';
else
ARB_STATE <= ARB_STATE_NXT;
ADR_BUF <= ADR_BUF_NXT;
DAT_BUF <= DAT_BUF_NXT;
HST_BUF <= HST_BUF_NXT;
BIT_BUF <= BIT_BUF_NXT;
end if;
end if;
end process CACHE_ACCESS_HISTORY;
end process CACHE_ARBITER_SYNC;
 
-- New Entry address is least used cache page --
NEW_ENTRY_ADR <= HIST_MEM(CACHE_PAGES-1);
 
 
CACHE_ARBITER: process(ARB_STATE, HIST_MEM, PAGE_TRANSLATE, ADR_BUF, DAT_BUF, HST_BUF, BIT_BUF, CACHE_R_DATA, DIRTY_FLAG,
CACHE_MISS, CACHE_DIRTY, C_FRESH_I, C_CLEAR_I, C_FLUSH_I, CACHE_HIT, C_WTHRU_I,
P_ADR_I, P_DATA_I, P_CS_I, P_WE_I, P_DQ_I,
B_ADR_I, B_DATA_I, B_CS_I, B_WE_I, B_IO_ACC_I, B_MSS_ACK_I, B_DRT_ACK_I)
begin
--- Arbiter ---
ARB_STATE_NXT <= ARB_STATE;
ADR_BUF_NXT <= ADR_BUF;
DAT_BUF_NXT <= DAT_BUF;
HST_BUF_NXT <= HST_BUF;
BIT_BUF_NXT <= BIT_BUF;
 
--- Cache Control ---
CACHE_WE <= '0';
CACHE_W_DATA <= P_DATA_I; -- (others => '0');
CACHE_ADR <= (others => '0');
ADR_INT <= P_ADR_I; -- (others => '0');
DQ_INT <= DQ_WORD;
PAGE_SELECT <= PAGE_TRANSLATE;
 
--- Cache History ---
UPDATE_HISTORY <= '0';
NEW_ENTRY_PAGE <= HST_BUF; -- (others => '0');
 
--- Cache Status ---
CLR_CUR_DRT <= '0';
SET_CUR_DRT <= '0';
SET_ALL_DRT <= C_FLUSH_I;
CLR_CUR_VAL <= '0';
SET_CUR_VAL <= '0';
CLR_ALL_VAL <= C_CLEAR_I;
SET_NEW_BAS <= '0';
 
--- STORM ---
P_DATA_O_INT <= CACHE_R_DATA; -- (others => '0');
 
--- Bus Unit ---
B_DATA_O <= CACHE_R_DATA; -- (others => '0');
C_DIRTY_O <= '0';
C_MISS_O <= '0';
B_BASE_O_SEL <= HIST_MEM(CACHE_PAGES-1);
 
--- State machine ---
case (ARB_STATE) is
 
when STORM_ACCESS => -- STORM can use the cache
----------------------------------------------------------------
ADR_INT <= P_ADR_I;
DQ_INT <= P_DQ_I;
PAGE_SELECT <= PAGE_TRANSLATE;
CACHE_ADR <= PAGE_TRANSLATE & P_ADR_I((LOG2_PAGE_SIZE-1)+2 downto 2);
CACHE_W_DATA <= P_DATA_I;
CACHE_WE <= P_CS_I and CACHE_HIT and P_WE_I and (not B_IO_ACC_I);
CLR_CUR_VAL <= C_FRESH_I and CACHE_HIT and P_CS_I and (not B_IO_ACC_I);
SET_CUR_DRT <= P_CS_I and CACHE_HIT and P_WE_I and (not B_IO_ACC_I);
UPDATE_HISTORY <= P_CS_I and CACHE_HIT and (not B_IO_ACC_I);
P_DATA_O_INT <= CACHE_R_DATA;
DAT_BUF_NXT <= P_DATA_I;
ADR_BUF_NXT <= P_ADR_I;
HST_BUF_NXT <= HIST_MEM(CACHE_PAGES-1); -- next page for writing
BIT_BUF_NXT <= P_CS_I and P_WE_I;
if (C_WTHRU_I = '0') and (DIRTY_FLAG(to_integer(unsigned(HIST_MEM(CACHE_PAGES-1)))) = '1') then
ARB_STATE_NXT <= DIRTY_STATE;
elsif (B_IO_ACC_I = '1') and (P_CS_I = '1') then
ARB_STATE_NXT <= IO_REQUEST;
elsif ((CACHE_MISS = '1') or (C_FRESH_I = '1')) and (P_CS_I = '1') then
ARB_STATE_NXT <= MISS_STATE;
elsif ((CACHE_DIRTY = '1') and (C_WTHRU_I = '1')) then -- write through
ARB_STATE_NXT <= DIRTY_STATE;
end if;
 
when IO_REQUEST => -- IO Access
----------------------------------------------------------------
B_DATA_O <= DAT_BUF;
if (B_MSS_ACK_I = '1') or (B_DRT_ACK_I = '1') then
DAT_BUF_NXT <= B_DATA_I;
if (BIT_BUF = '1') then -- write
ARB_STATE_NXT <= IO_PIPE_RESYNC_END;
else -- read
ARB_STATE_NXT <= IO_PIPE_RESYNC;
end if;
end if;
when IO_PIPE_RESYNC => -- IO Pipeline Re-Sync
P_DATA_O_INT <= DAT_BUF;
ARB_STATE_NXT <= IO_PIPE_RESYNC_END;
when IO_PIPE_RESYNC_END => -- IO Pipeline Re-Sync finished
P_DATA_O_INT <= DAT_BUF;
ARB_STATE_NXT <= STORM_ACCESS;
 
when MISS_STATE => -- Cache miss
----------------------------------------------------------------
C_MISS_O <= '1'; -- we're missing something
ADR_INT <= B_ADR_I;
DQ_INT <= DQ_WORD;
PAGE_SELECT <= HST_BUF;
CACHE_ADR <= HST_BUF & B_ADR_I((LOG2_PAGE_SIZE-1)+2 downto 2);
CACHE_W_DATA <= B_DATA_I;
CACHE_WE <= B_CS_I;-- and B_WE_I;
SET_CUR_VAL <= B_CS_I;-- and B_WE_I;
CLR_CUR_DRT <= B_CS_I;-- and B_WE_I;
SET_CUR_DRT <= BIT_BUF;
SET_NEW_BAS <= B_CS_I;-- and B_WE_I;
UPDATE_HISTORY <= B_CS_I;-- and B_WE_I;
B_DATA_O <= CACHE_R_DATA;
NEW_ENTRY_PAGE <= HST_BUF;
if (B_MSS_ACK_I = '1') then
ARB_STATE_NXT <= PIPE_RESYNC;
end if;
 
when DIRTY_STATE => -- Cache dirty
----------------------------------------------------------------
C_DIRTY_O <= '1';
if (C_WTHRU_I = '1') then
B_BASE_O_SEL <= PAGE_SELECT;
end if;
ADR_INT <= B_ADR_I;
DQ_INT <= DQ_WORD;
PAGE_SELECT <= PAGE_TRANSLATE;--HST_BUF;
CACHE_ADR <= PAGE_TRANSLATE & B_ADR_I((LOG2_PAGE_SIZE-1)+2 downto 2);--HST_BUF & B_ADR_I((LOG2_PAGE_SIZE-1)+2 downto 2);
CLR_CUR_DRT <= B_CS_I;-- and B_WE_I;
--UPDATE_HISTORY <= B_CS_I;-- and B_WE_I;
B_DATA_O <= CACHE_R_DATA;
if (B_DRT_ACK_I = '1') then
ARB_STATE_NXT <= PIPE_RESYNC;
end if;
 
when PIPE_RESYNC => -- Re-sync Pipeline
----------------------------------------------------------------
ADR_INT <= ADR_BUF;
DQ_INT <= DQ_WORD;
PAGE_SELECT <= PAGE_TRANSLATE;
CACHE_ADR <= PAGE_TRANSLATE & ADR_BUF((LOG2_PAGE_SIZE-1)+2 downto 2);
CACHE_W_DATA <= DAT_BUF;
CACHE_WE <= BIT_BUF;
P_DATA_O_INT <= CACHE_R_DATA;
if (CACHE_DIRTY = '1') and (C_WTHRU_I = '1') then -- write through
ARB_STATE_NXT <= DIRTY_STATE;
else
ARB_STATE_NXT <= STORM_ACCESS;
end if;
 
end case;
end process CACHE_ARBITER;
 
 
 
-- Data Quantity Decoder ----------------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
DQ_DECODER: process(DQ_INT, ADR_INT(1 downto 0))
277,158 → 499,68
 
 
 
-- Cache Read/Write Access -----------------------------------------------------------------------------
-- Cache Memory Access ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
 
-- Cache Access Address --
CACHE_ADR <= (NEW_ENTRY_ADR & ADR_INT((LOG2_PAGE_SIZE-1)+2 downto 2)) when ((C_UPDATE_I = '1') and (B_WE_I = '1')) else (PAGE_SELECT & ADR_INT((LOG2_PAGE_SIZE-1)+2 downto 2));
 
-- Sync Cache Read/Write --
CACHE_ACCESS: process(CORE_CLK_I, CS_INT, CACHE_HIT, C_UPDATE_I)
variable cache_mem_cs_int_v : std_logic;
CACHE_ACCESS: process(CORE_CLK_I)
begin
 
-- Cache select --
cache_mem_cs_int_v := CS_INT and (CACHE_HIT or C_UPDATE_I);
 
-- Sync Write--
if rising_edge(CORE_CLK_I) then
if (cache_mem_cs_int_v = '1') then
if (WE_INT = '1') then -- cache write access
if (BYTE_SEL(0) = '1') then
CACHE_MEM_LL(to_integer(unsigned(CACHE_ADR))) <= DATA_INT(07 downto 00);
end if;
if (BYTE_SEL(1) = '1') then
CACHE_MEM_LH(to_integer(unsigned(CACHE_ADR))) <= DATA_INT(15 downto 08);
end if;
if (BYTE_SEL(2) = '1') then
CACHE_MEM_HL(to_integer(unsigned(CACHE_ADR))) <= DATA_INT(23 downto 16);
end if;
if (BYTE_SEL(3) = '1') then
CACHE_MEM_HH(to_integer(unsigned(CACHE_ADR))) <= DATA_INT(31 downto 24);
end if;
if (CACHE_WE = '1') then -- cache write access
if (BYTE_SEL(0) = '1') then
CACHE_MEM_LL(to_integer(unsigned(CACHE_ADR))) <= CACHE_W_DATA(0*8+7 downto 0*8);
end if;
RB_DATA(07 downto 00) <= CACHE_MEM_LL(to_integer(unsigned(CACHE_ADR)));
RB_DATA(15 downto 08) <= CACHE_MEM_LH(to_integer(unsigned(CACHE_ADR)));
RB_DATA(23 downto 16) <= CACHE_MEM_HL(to_integer(unsigned(CACHE_ADR)));
RB_DATA(31 downto 24) <= CACHE_MEM_HH(to_integer(unsigned(CACHE_ADR)));
if (BYTE_SEL(1) = '1') then
CACHE_MEM_LH(to_integer(unsigned(CACHE_ADR))) <= CACHE_W_DATA(1*8+7 downto 1*8);
end if;
if (BYTE_SEL(2) = '1') then
CACHE_MEM_HL(to_integer(unsigned(CACHE_ADR))) <= CACHE_W_DATA(2*8+7 downto 2*8);
end if;
if (BYTE_SEL(3) = '1') then
CACHE_MEM_HH(to_integer(unsigned(CACHE_ADR))) <= CACHE_W_DATA(3*8+7 downto 3*8);
end if;
end if;
CACHE_R_DATA(07 downto 00) <= CACHE_MEM_LL(to_integer(unsigned(CACHE_ADR)));
CACHE_R_DATA(15 downto 08) <= CACHE_MEM_LH(to_integer(unsigned(CACHE_ADR)));
CACHE_R_DATA(23 downto 16) <= CACHE_MEM_HL(to_integer(unsigned(CACHE_ADR)));
CACHE_R_DATA(31 downto 24) <= CACHE_MEM_HH(to_integer(unsigned(CACHE_ADR)));
end if;
end process CACHE_ACCESS;
 
 
 
-- Dummy memory for simulation -----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
DEBUG_SIM_MEM:
if (IS_SIM = TRUE) generate
GEN_DEBUG_MEM:
for i in 0 to (CACHE_PAGES*PAGE_SIZE) - 1 generate
SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i);
end generate;
-- Dummy for simulation --
GEN_DEBUG_MEM:
for i in 0 to (CACHE_PAGES*PAGE_SIZE)-1 generate
SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i);
end generate;
 
 
 
-- Page Modification Flag ------------------------------------------------------------------------------
-- Read-Access Synchronizer ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
DIRTY_REG: process(CORE_CLK_I)
R_ACC_SYNC: process(CORE_CLK_I, HALT_I, ARB_STATE)
variable sel_v : std_logic;
begin
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '0';
end loop;
elsif (C_FLUSH_I = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '1';
end loop;
else
if ((B_CS_I and C_UPDATE_I and (not B_WE_I)) = '1') then -- bus unit write access
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0'; -- cache re-sync
elsif ((CACHE_HIT and P_WE_I) = '1') then -- processor write access
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1'; -- processor modified cache
end if;
end if;
sel_v := '0';
if (HALT_I = '1') and (ARB_STATE = STORM_ACCESS) then
sel_v := '1';
end if;
end process DIRTY_REG;
 
--- Bus unit Dirty_Flag_Reg Access ---
B_DRT_SEL_O <= DIRTY_FLAG(to_integer(unsigned(B_PG_SEL_I))) and VALID_FLAG(to_integer(unsigned(B_PG_SEL_I)));
 
 
 
-- Global Dirty Flag -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CACHE_DIRTY_DETECTOR: process(CORE_CLK_I, DIRTY_FLAG, VALID_FLAG)
variable dirty_tmp_v : std_logic;
begin
-- global dirty bit --
dirty_tmp_v := '0';
if (READ_ONLY = FALSE) then
for i in 0 to CACHE_PAGES-1 loop
if ((DIRTY_FLAG(i) and VALID_FLAG(i)) = '1') then
dirty_tmp_v := '1';
exit;
end if;
end loop;
end if;
 
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
C_DIRTY_O <= '0';
--B_DRT_SEL_O <= '0';
P_DATA_O_SEL <= '0';
P_DATA_O_BUF <= (others => '0');
else
--B_DRT_SEL_O <= DIRTY_FLAG(to_integer(unsigned(B_PG_SEL_I))) and VALID_FLAG(to_integer(unsigned(B_PG_SEL_I)));
if (C_WTHRU_I = '0') then
if (dirty_tmp_v = '0') then
C_DIRTY_O <= '0';
elsif (HIST_MEM(0) /= PAGE_SELECT) then
C_DIRTY_O <= dirty_tmp_v;
end if;
else
C_DIRTY_O <= dirty_tmp_v;
P_DATA_O_SEL <= sel_v;
if (P_DATA_O_SEL = '0') then
P_DATA_O_BUF <= P_DATA_O_INT;
end if;
end if;
end if;
end process CACHE_DIRTY_DETECTOR;
end process R_ACC_SYNC;
 
--- Data output buffer ---
P_DATA_O <= P_DATA_O_INT when (P_DATA_O_SEL = '0') else P_DATA_O_BUF;
 
TIMEOUT_COUNTER: process(CORE_CLK_I)
begin
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
DRT_CNT <= (others => '1');
elsif ((P_CS_I and P_WE_I) = '1') and (HIST_MEM(0) = PAGE_SELECT) then
DRT_CNT <= "000";
elsif (DRT_CNT /= "111") then
DRT_CNT <= Std_Logic_Vector(unsigned(DRT_CNT) + 1);
end if;
end if;
end process TIMEOUT_COUNTER;
 
 
 
-- Cache Read Buffer -----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CACHE_R_BUFFER: process(CORE_CLK_I)
begin
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
RB_BUFFER <= (others => '0');
RB_BUFF_EN <= '0';
else
RB_BUFF_EN <= HALT_I;
if (RB_BUFF_EN = '0') then
RB_BUFFER <= RB_DATA;
end if;
end if;
end if;
end process CACHE_R_BUFFER;
 
-- readback buffer select --
P_DATA_O <= RB_BUFFER when (RB_BUFF_EN = '1') else RB_DATA;
B_DATA_O <= RB_DATA;
 
 
 
end Behavioral;
/storm_core/rtl/STORM_TOP.vhd
21,7 → 21,7
-- # - LOAD_STORE_UNIT.vhd | Download at http://opencores.org/project,storm_core #
-- # - OPCODE_DECODER.vhd | #
-- # ***************************************************************************************************** #
-- # Last modified: 04.01.2012 =/\= #
-- # Last modified: 15.02.2012 =/\= #
-- #########################################################################################################
 
library IEEE;
37,11 → 37,13
-- ## System Architecture Configuration ##
-- ###############################################################################################
 
I_CACHE_PAGES : natural := 4; -- number of pages in I cache
I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
D_CACHE_PAGES : natural := 8; -- number of pages in D cache
D_CACHE_PAGE_SIZE : natural := 4; -- page size in D cache
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0) := x"00000000" -- boot address
I_CACHE_PAGES : natural := 4; -- number of pages in I cache
I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
D_CACHE_PAGES : natural := 8; -- number of pages in D cache
D_CACHE_PAGE_SIZE : natural := 1; -- page size in D cache
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; -- boot address
IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; -- io begin address
IO_UC_END : STD_LOGIC_VECTOR(31 downto 0) := x"00000000" -- io end address
);
-- ###############################################################################################
-- ## Global Interface ##
48,9 → 50,9
-- ###############################################################################################
port (
CORE_CLK_I : in STD_LOGIC; -- core clock input
BUS_CLK_I : in STD_LOGIC; -- bus clock input
RST_I : in STD_LOGIC; -- global reset input
F_RST_O : out STD_LOGIC; -- force system reset
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
 
-- ###############################################################################################
-- ## Wishbone Interface ##
58,15 → 60,15
 
WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- address
WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0); -- cycle type
WB_TGC_O : out STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_TGC_O : out STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); -- byte select
WB_WE_O : out STD_LOGIC; -- write enable
WB_WE_O : out STD_LOGIC; -- write enable
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data out
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data in
WB_STB_O : out STD_LOGIC; -- valid transfer
WB_CYC_O : out STD_LOGIC; -- valid cycle
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_HALT_I : in STD_LOGIC; -- halt request
WB_STB_O : out STD_LOGIC; -- valid transfer
WB_CYC_O : out STD_LOGIC; -- valid cycle
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_HALT_I : in STD_LOGIC; -- halt request
 
-- ###############################################################################################
-- ## Interrupt Lines ##
92,11 → 94,10
return 0;
end function log2;
 
-- special processor lines --
-- Special processor lines --
signal ST_HALT : STD_LOGIC;
signal ST_MODE : STD_LOGIC_VECTOR(04 downto 0);
signal C_WTHRU : STD_LOGIC;
signal C_BGWB : STD_LOGIC;
signal C_BUS_CYCC : STD_LOGIC_VECTOR(15 downto 0);
 
-- STORM D-Cache Interface --
109,6 → 110,8
signal ST_DC_CLEAR : STD_LOGIC;
signal ST_DC_FLUSH : STD_LOGIC;
signal ST_DC_HIT : STD_LOGIC;
signal ST_DC_FRESH : STD_LOGIC;
signal ST_DC_CIO : STD_LOGIC;
 
-- Bus Unit D-Cache Interface --
signal BS_DC_CS : STD_LOGIC;
115,14 → 118,13
signal BS_DC_ADR : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DATA_I : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DQ : STD_LOGIC_VECTOR(01 downto 0);
signal BS_DC_WE : STD_LOGIC;
signal BS_DC_UPDATE : STD_LOGIC;
signal BS_DC_DIRTY : STD_LOGIC;
signal BS_DC_MISS : STD_LOGIC;
signal BS_DC_PG_SEL : STD_LOGIC_VECTOR((log2(D_CACHE_PAGES))-1 downto 0);
signal BS_DC_DRT_SEL : STD_LOGIC;
signal BS_DC_BSA_SEL : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DRT_ACK : STD_LOGIC;
signal BS_DC_MSS_ACK : STD_LOGIC;
signal BS_DC_IO_ACC : STD_LOGIC;
 
-- STORM I-Cache Interface --
signal ST_IC_REQ : STD_LOGIC;
130,16 → 132,15
signal ST_IC_RD_DTA : STD_LOGIC_VECTOR(31 downto 0);
signal ST_IC_CLEAR : STD_LOGIC;
signal ST_IC_HIT : STD_LOGIC;
signal ST_IC_FRESH : STD_LOGIC;
 
-- Bus Unit I-Cache Interface --
signal BS_IC_CS : STD_LOGIC;
signal BS_IC_ADR : STD_LOGIC_VECTOR(31 downto 0);
signal BS_IC_DATA_I : STD_LOGIC_VECTOR(31 downto 0);
signal BS_IC_DQ : STD_LOGIC_VECTOR(01 downto 0);
signal BS_IC_WE : STD_LOGIC;
signal BS_IC_UPDATE : STD_LOGIC;
signal BS_IC_MISS : STD_LOGIC;
signal BS_IC_PG_SEL : STD_LOGIC_VECTOR((log2(I_CACHE_PAGES))-1 downto 0);
signal BS_IC_MSS_ACK : STD_LOGIC;
 
-- Abort Signals --
signal D_ABORT : STD_LOGIC;
156,7 → 157,6
port map (
-- Global Control --
RES => RST_I, -- global reset input (high active)
F_RST => F_RST_O, -- force system reset
CLK => CORE_CLK_I, -- global clock input
 
-- Special Control --
175,6 → 175,8
D_CACHE_FLUSH => ST_DC_FLUSH, -- flush d-cache
D_CACHE_MISS => BS_DC_MISS, -- d-cache miss
D_CACHE_HIT => ST_DC_HIT, -- d-cache hit
D_CACHE_FRESH => ST_DC_FRESH, -- refresh d-cache
D_CACHE_CIO => ST_DC_CIO, -- en cached IO
 
-- Instruction Cache Interface --
I_CACHE_REQ => ST_IC_REQ, -- memory access in next cycle
184,11 → 186,13
I_CACHE_CLEAR => ST_IC_CLEAR, -- clear i-cache
I_CACHE_MISS => BS_IC_MISS, -- i-cache miss
I_CACHE_HIT => ST_IC_HIT, -- i-cache hit
I_CACHE_FRESH => ST_IC_FRESH, -- refresh i-cache
 
-- General Control Lines --
C_BUS_CYCC_O => C_BUS_CYCC, -- max bus cycle length
C_WTHRU_O => C_WTHRU, -- cache write through
C_BGWB_O => C_BGWB, -- background write-back
IO_PORT_OUT => IO_PORT_O, -- direct output
IO_PORT_IN => IO_PORT_I, -- direct input
 
-- Interrupt Request Lines --
IRQ => IRQ_I, -- interrupt request
204,13 → 208,11
CACHE_PAGES => I_CACHE_PAGES,
LOG2_CACHE_PAGES => log2(I_CACHE_PAGES),
PAGE_SIZE => I_CACHE_PAGE_SIZE,
LOG2_PAGE_SIZE => log2(I_CACHE_PAGE_SIZE),
READ_ONLY => TRUE
LOG2_PAGE_SIZE => log2(I_CACHE_PAGE_SIZE)
)
port map (
-- Global Control --
CORE_CLK_I => CORE_CLK_I, -- core clock, all triggering on rising edge
BUS_CLK_I => BUS_CLK_I, -- bus clock, all triggering on rising edge
RST_I => RST_I, -- global reset, high active, sync
HALT_I => ST_HALT, -- global storm halt signal
 
227,14 → 229,14
B_ADR_I => BS_IC_ADR, -- address input
B_DATA_I => BS_IC_DATA_I, -- data input
B_DATA_O => open, -- data output
B_DQ_I => BS_IC_DQ, -- data quantity
B_WE_I => BS_IC_WE, -- write enable
B_PG_SEL_I => BS_IC_PG_SEL, -- bus unit page select
B_DRT_SEL_O => open, -- dirty bit of selected page
B_BSA_O => open, -- base adr of selected page
B_DRT_ACK_I => '1', -- dirty acknowledged
B_MSS_ACK_I => BS_IC_MSS_ACK, -- miss acknowledged
B_IO_ACC_I => '0', -- IO access
 
-- Cache Control --
C_UPDATE_I => BS_IC_UPDATE, -- bus unit takes control
C_FRESH_I => ST_IC_FRESH, -- refresh accessed page
C_FLUSH_I => '0', -- flush cache
C_CLEAR_I => ST_IC_CLEAR, -- clear cache
C_MISS_O => BS_IC_MISS, -- cache miss access
242,7 → 244,6
C_DIRTY_O => open, -- cache modified
C_WTHRU_I => '0' -- write through
);
BS_IC_PG_SEL <= (others => '0'); -- dummy signal
 
 
 
253,13 → 254,11
CACHE_PAGES => D_CACHE_PAGES,
LOG2_CACHE_PAGES => log2(D_CACHE_PAGES),
PAGE_SIZE => D_CACHE_PAGE_SIZE,
LOG2_PAGE_SIZE => log2(D_CACHE_PAGE_SIZE),
READ_ONLY => FALSE
LOG2_PAGE_SIZE => log2(D_CACHE_PAGE_SIZE)
)
port map (
-- Global Control --
CORE_CLK_I => CORE_CLK_I, -- core clock, all triggering on rising edge
BUS_CLK_I => BUS_CLK_I, -- bus clock, all triggering on rising edge
RST_I => RST_I, -- global reset, high active, sync
HALT_I => ST_HALT, -- global storm halt signal
 
276,14 → 275,14
B_ADR_I => BS_DC_ADR, -- address input
B_DATA_I => BS_DC_DATA_I, -- data input
B_DATA_O => BS_DC_DATA_O, -- data output
B_DQ_I => BS_DC_DQ, -- data quantity
B_WE_I => BS_DC_WE, -- write enable
B_PG_SEL_I => BS_DC_PG_SEL, -- bus unit page select
B_DRT_SEL_O => BS_DC_DRT_SEL, -- dirty bit of selected page
B_BSA_O => BS_DC_BSA_SEL, -- base adr of selected page
B_DRT_ACK_I => BS_DC_DRT_ACK, -- dirty acknowledged
B_MSS_ACK_I => BS_DC_MSS_ACK, -- miss acknowledged
B_IO_ACC_I => BS_DC_IO_ACC, -- IO access
 
-- Cache Control --
C_UPDATE_I => BS_DC_UPDATE, -- bus unit takes control
C_FRESH_I => ST_DC_FRESH, -- refresh accessed page
C_FLUSH_I => ST_DC_FLUSH, -- flush cache
C_CLEAR_I => ST_DC_CLEAR, -- clear cache
C_MISS_O => BS_DC_MISS, -- cache miss access
306,12 → 305,13
D_CACHE_PAGES => D_CACHE_PAGES, -- number of pages in D cache
LOG2_D_CACHE_PAGES => log2(D_CACHE_PAGES), -- log2 of page count
D_CACHE_PAGE_SIZE => D_CACHE_PAGE_SIZE, -- page size in D cache
LOG2_D_CACHE_PAGE_SIZE => log2(D_CACHE_PAGE_SIZE) -- log2 of page size
LOG2_D_CACHE_PAGE_SIZE => log2(D_CACHE_PAGE_SIZE), -- log2 of page size
IO_UC_BEGIN => IO_UC_BEGIN, -- begin of uncachable IO area
IO_UC_END => IO_UC_END -- end of uncachable IO area
)
port map (
-- Global Control --
CORE_CLK_I => CORE_CLK_I, -- core clock signal, rising edge
BUS_CLK_I => BUS_CLK_I, -- bus clock signal, rising edge
RST_I => RST_I, -- reset signal, sync, active high
FREEZE_STORM_O => ST_HALT, -- freeze processor
STORM_MODE_I => ST_MODE, -- current processor mode
318,32 → 318,33
D_ABORT_O => D_ABORT, -- bus error during data transfer
I_ABORT_O => I_ABORT, -- bus error during instruction transfer
C_BUS_CYCC_I => C_BUS_CYCC, -- max bus cycle length
C_BGWB_I => C_BGWB, -- background write-back
CACHED_IO_I => ST_DC_CIO, -- enable cached IO
 
-- Data Cache Interface --
DC_CS_O => BS_DC_CS, -- chip select
DC_P_ADR_I => ST_DC_ADR, -- processor address
DC_P_CS_I => ST_DC_REQ, -- processor cache request
DC_P_WE_I => ST_DC_RW, -- processor write enable
DC_ADR_O => BS_DC_ADR, -- cache address
DC_DATA_O => BS_DC_DATA_I, -- data outut
DC_DATA_I => BS_DC_DATA_O, -- data input
DC_DQ_O => BS_DC_DQ, -- data quantity
DC_WE_O => BS_DC_WE, -- write enable
DC_UPDATE_O => BS_DC_UPDATE, -- bus unit takes control
DC_MISS_I => BS_DC_MISS, -- cache miss access
DC_DIRTY_I => BS_DC_DIRTY, -- cache modified
DC_PG_SEL_O => BS_DC_PG_SEL, -- bus unit page selector
DC_DRT_SEL_I => BS_DC_DRT_SEL, -- dirty bit of selected page
DC_BSA_I => BS_DC_BSA_SEL, -- base address of selected page
DC_DRT_ACK_O => BS_DC_DRT_ACK, -- dirty acknowledged
DC_MSS_ACK_O => BS_DC_MSS_ACK, -- miss acknowledged
DC_IO_ACC_O => BS_DC_IO_ACC, -- IO access
 
-- Instruction Cache Interface --
IC_CS_O => BS_IC_CS, -- chip select
IC_P_ADR_I => ST_IC_ADR, -- processor address
IC_P_CS_I => ST_IC_REQ, -- processor cache request
IC_ADR_O => BS_IC_ADR, -- cache address
IC_DATA_O => BS_IC_DATA_I, -- data output
IC_DQ_O => BS_IC_DQ, -- data quantity
IC_WE_O => BS_IC_WE, -- write enable
IC_UPDATE_O => BS_IC_UPDATE, -- bus unit takes control
IC_MISS_I => BS_IC_MISS, -- cache miss access
IC_MSS_ACK_O => BS_IC_MSS_ACK, -- miss acknowledged
 
-- Wishbone Bus --
WB_ADR_O => WB_ADR_O, -- address
/storm_core/rtl/BUS_UNIT.vhd
9,7 → 9,7
-- # Note: I-Cache is read-only for the processor and #
-- # write-only for the bus unit. #
-- # ************************************************** #
-- # Last modified: 23.01.2012 #
-- # Last modified: 15.02.2012 #
-- ######################################################
 
library IEEE;
25,14 → 25,16
-- ## Cache Configuration ##
-- ################################################################################################################
 
I_CACHE_PAGES : natural; -- number of pages in I cache
LOG2_I_CACHE_PAGES : natural; -- log2 of page count
I_CACHE_PAGE_SIZE : natural; -- page size in I cache
LOG2_I_CACHE_PAGE_SIZE : natural; -- log2 of page size
D_CACHE_PAGES : natural; -- number of pages in D cache
LOG2_D_CACHE_PAGES : natural; -- log2 of page count
D_CACHE_PAGE_SIZE : natural; -- page size in D cache
LOG2_D_CACHE_PAGE_SIZE : natural -- log2 of page size
I_CACHE_PAGES : natural; -- number of pages in I cache
LOG2_I_CACHE_PAGES : natural; -- log2 of page count
I_CACHE_PAGE_SIZE : natural; -- page size in I cache
LOG2_I_CACHE_PAGE_SIZE : natural; -- log2 of page size
D_CACHE_PAGES : natural; -- number of pages in D cache
LOG2_D_CACHE_PAGES : natural; -- log2 of page count
D_CACHE_PAGE_SIZE : natural; -- page size in D cache
LOG2_D_CACHE_PAGE_SIZE : natural; -- log2 of page size
IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0); -- begin of uncachable IO area
IO_UC_END : STD_LOGIC_VECTOR(31 downto 0) -- end of uncachable IO area
);
port (
-- ################################################################################################################
40,7 → 42,6
-- ################################################################################################################
 
CORE_CLK_I : in STD_LOGIC; -- core clock signal, rising edge
BUS_CLK_I : in STD_LOGIC; -- bus clock signal, rising edge
RST_I : in STD_LOGIC; -- reset signal, sync, active high
FREEZE_STORM_O : out STD_LOGIC; -- freeze processor
STORM_MODE_I : in STD_LOGIC_VECTOR(04 downto 0); -- current processor mode
47,7 → 48,7
D_ABORT_O : out STD_LOGIC; -- bus error during data transfer
I_ABORT_O : out STD_LOGIC; -- bus error during instruction transfer
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0); -- max bus cycle length
C_BGWB_I : in STD_LOGIC; -- background write-back
CACHED_IO_I : in STD_LOGIC; -- enable cached IO
 
-- ################################################################################################################
-- ## STORM Data Cache Interface ##
55,17 → 56,18
 
DC_CS_O : out STD_LOGIC; -- chip select
DC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0); -- processor address
DC_P_CS_I : in STD_LOGIC; -- processor cache request
DC_P_WE_I : in STD_LOGIC; -- processor write enable
DC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- cache address
DC_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data output
DC_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data input
DC_DQ_O : out STD_LOGIC_VECTOR(01 downto 0); -- data quantity
DC_WE_O : out STD_LOGIC; -- write enable
DC_UPDATE_O : out STD_LOGIC; -- bus unit takes control
DC_MISS_I : in STD_LOGIC; -- cache miss access
DC_DIRTY_I : in STD_LOGIC; -- cache modified
DC_PG_SEL_O : out STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0);
DC_DRT_SEL_I : in STD_LOGIC; -- dirty bit of selected page
DC_BSA_I : in STD_LOGIC_VECTOR(31 downto 0); -- base address of selected page
DC_DRT_ACK_O : out STD_LOGIC; -- dirty acknowledged
DC_MSS_ACK_O : out STD_LOGIC; -- miss acknowledged
DC_IO_ACC_O : out STD_LOGIC; -- IO access
 
-- ################################################################################################################
-- ## STORM Instruction Cache Interface ##
73,12 → 75,12
 
IC_CS_O : out STD_LOGIC; -- chip select
IC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0); -- processor address
IC_P_CS_I : in STD_LOGIC; -- processor cache request
IC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- cache address
IC_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data outut
IC_DQ_O : out STD_LOGIC_VECTOR(01 downto 0); -- data quantity
IC_WE_O : out STD_LOGIC; -- write enable
IC_UPDATE_O : out STD_LOGIC; -- bus unit takes control
IC_MISS_I : in STD_LOGIC; -- cache miss access
IC_MSS_ACK_O : out STD_LOGIC; -- miss acknowledged
 
-- ################################################################################################################
-- ## Wishbone Bus ##
88,7 → 90,7
WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0); -- cycle type
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data
WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); -- byte select
WB_TGC_O : out STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_TGC_O : out STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_WE_O : out STD_LOGIC; -- read/write
WB_CYC_O : out STD_LOGIC; -- cycle
WB_STB_O : out STD_LOGIC; -- strobe
110,27 → 112,31
constant WB_BST_END_CYC : STD_LOGIC_VECTOR(2 downto 0) := "111"; -- burst end
 
-- Arbiter FSM --
type ARB_STATE_TYPE is (IDLE, ASSIGN_D_PAGE, UPLOAD_D_PAGE, DOWNLOAD_I_PAGE, DOWNLOAD_D_PAGE, END_TRANSFER);
type ARB_STATE_TYPE is (IDLE, UPLOAD_D_PAGE, IO_REQUEST, DOWNLOAD_I_PAGE, DOWNLOAD_D_PAGE, END_TRANSFER);
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE;
 
-- Address Buffer --
signal IC_ADR_BUF, IC_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal DC_ADR_BUF, DC_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ADR_BUF, WB_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal BASE_BUF, BASE_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal PAGE_SEL, PAGE_SEL_NXT : STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0);
signal IC_ADR_BUF, IC_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal DC_ADR_BUF, DC_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ADR_BUF, WB_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal DC_P_ADR_BUF, IC_P_ADR_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal BASE_BUF, BASE_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
 
-- Wishbone Syncs --
signal WB_DATA_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ACK_BUF : STD_LOGIC;
signal VA_CYC_BUF, VA_CYC_BUF_NXT : STD_LOGIC;
signal WB_DATA_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ACK_BUF : STD_LOGIC;
signal VA_CYC_BUF, VA_CYC_BUF_NXT : STD_LOGIC;
signal WE_FLAG, WE_FLAG_NXT : STD_LOGIC;
 
-- Access System --
signal IO_ACCESS : STD_LOGIC;
 
-- Local Signals --
signal FREEZE_FLAG, FREEZE_FLAG_NXT : STD_LOGIC; -- freeze flag
signal FREEZE_DIS, FREEZE_DIS_NXT : STD_LOGIC; -- freeze disable
signal FREEZE_FLAG, FREEZE_FLAG_NXT : STD_LOGIC; -- freeze flag
signal FREEZE_DIS, FREEZE_DIS_NXT : STD_LOGIC; -- freeze disable
 
-- Timeout System --
signal TIMEOUT_CNT, TIMEOUT_CNT_NXT : STD_LOGIC_VECTOR(15 downto 0);
signal TIMEOUT_CNT, TIMEOUT_CNT_NXT : STD_LOGIC_VECTOR(15 downto 0);
 
begin
 
159,55 → 165,59
--- D-Cache ---
DC_DATA_O <= WB_DATA_BUF;
DC_ADR_O <= DC_ADR_BUF;
DC_DQ_O <= DQ_WORD; -- update cache entry = word
DC_PG_SEL_O <= PAGE_SEL; -- bus unit page select
 
--- I-Cache ---
IC_DATA_O <= WB_DATA_BUF;
IC_ADR_O <= IC_ADR_BUF;
IC_DQ_O <= DQ_WORD; -- update cache entry = word
IC_WE_O <= '1'; -- processor cannot change i-cache, no readback necessary
 
--- Wishbone Bus ---
WB_SEL_O <= "1111"; -- cache entry = word
WB_ADR_O <= WB_ADR_BUF;
WB_DATA_O <= DC_DATA_I;
WB_DATA_O <= x"00000000" when (ARB_STATE = IDLE) else DC_DATA_I;
WB_WE_O <= WE_FLAG;
 
--- IO Access ---
IO_ACCESS <= '1' when (DC_P_ADR_I >= IO_UC_BEGIN) and (DC_P_ADR_I <= IO_UC_END) and (CACHED_IO_I = '0') else '0';
DC_IO_ACC_O <= IO_ACCESS;
 
 
 
-- Arbiter State Machine (Sync) ---------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
ARBITER_SYNC: process(BUS_CLK_I)
ARBITER_SYNC: process(CORE_CLK_I)
begin
if rising_edge(BUS_CLK_I) then
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
ARB_STATE <= IDLE;
TIMEOUT_CNT <= (others => '0');
WB_DATA_BUF <= (others => '0');
WB_ACK_BUF <= '0';
VA_CYC_BUF <= '0';
--WB_DATA_O <= (others => '0');
IC_ADR_BUF <= (others => '0');
DC_ADR_BUF <= (others => '0');
WB_ADR_BUF <= (others => '0');
BASE_BUF <= (others => '0');
PAGE_SEL <= (others => '0');
ARB_STATE <= IDLE;
TIMEOUT_CNT <= (others => '0');
WB_DATA_BUF <= (others => '0');
WB_ACK_BUF <= '0';
WE_FLAG <= '0';
VA_CYC_BUF <= '0';
IC_ADR_BUF <= (others => '0');
DC_ADR_BUF <= (others => '0');
WB_ADR_BUF <= (others => '0');
BASE_BUF <= (others => '0');
DC_P_ADR_BUF <= (others => '0');
IC_P_ADR_BUF <= (others => '0');
else
-- Arbiter CTRL --
ARB_STATE <= ARB_STATE_NXT;
TIMEOUT_CNT <= TIMEOUT_CNT_NXT;
ARB_STATE <= ARB_STATE_NXT;
TIMEOUT_CNT <= TIMEOUT_CNT_NXT;
DC_P_ADR_BUF <= DC_P_ADR_I;
IC_P_ADR_BUF <= IC_P_ADR_I;
WE_FLAG <= WE_FLAG_NXT;
if (WB_HALT_I = '0') then
-- Wishbone Sync --
WB_DATA_BUF <= WB_DATA_I;
WB_ACK_BUF <= WB_ACK_I;
VA_CYC_BUF <= VA_CYC_BUF_NXT;
--WB_DATA_O <= DC_DATA_I;
-- Address Buffer --
IC_ADR_BUF <= IC_ADR_BUF_NXT;
DC_ADR_BUF <= DC_ADR_BUF_NXT;
WB_ADR_BUF <= WB_ADR_BUF_NXT;
BASE_BUF <= BASE_BUF_NXT;
PAGE_SEL <= PAGE_SEL_NXT;
end if;
end if;
end if;
217,18 → 227,17
 
-- Arbiter State Machine (Async) --------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, PAGE_SEL, TIMEOUT_CNT,
DC_ADR_BUF, DC_P_ADR_I, DC_DIRTY_I, DC_MISS_I, DC_DRT_SEL_I, DC_BSA_I,
IC_ADR_BUF, IC_P_ADR_I, IC_MISS_I,
WB_ADR_BUF, WB_ACK_BUF, VA_CYC_BUF, C_BUS_CYCC_I, C_BGWB_I)
variable IF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
variable DF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, WE_FLAG,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, DC_DIRTY_I, DC_MISS_I, DC_BSA_I, DC_P_WE_I, DC_P_CS_I,
IC_ADR_BUF, IC_P_ADR_BUF, IC_MISS_I,
WB_ADR_BUF, WB_ACK_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
variable IF_BASE_ADR_V, DF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
begin
--- Base Address Word Alignment ---
IF_BASE_ADR_V := (others => '0');
IF_BASE_ADR_V(31 downto LOG2_I_CACHE_PAGE_SIZE+2) := IC_P_ADR_I(31 downto LOG2_I_CACHE_PAGE_SIZE+2);
IF_BASE_ADR_V(31 downto LOG2_I_CACHE_PAGE_SIZE+2) := IC_P_ADR_BUF(31 downto LOG2_I_CACHE_PAGE_SIZE+2);
DF_BASE_ADR_V := (others => '0');
DF_BASE_ADR_V(31 downto LOG2_D_CACHE_PAGE_SIZE+2) := DC_P_ADR_I(31 downto LOG2_D_CACHE_PAGE_SIZE+2);
DF_BASE_ADR_V(31 downto LOG2_D_CACHE_PAGE_SIZE+2) := DC_P_ADR_BUF(31 downto LOG2_D_CACHE_PAGE_SIZE+2);
 
--- Arbiter Defaults ---
ARB_STATE_NXT <= ARB_STATE;
239,26 → 248,27
FREEZE_FLAG_NXT <= FREEZE_FLAG;
FREEZE_DIS_NXT <= '0';
BASE_BUF_NXT <= BASE_BUF;
PAGE_SEL_NXT <= PAGE_SEL;
VA_CYC_BUF_NXT <= '0';
TIMEOUT_CNT_NXT <= (others => '0');
WE_FLAG_NXT <= WE_FLAG;
 
--- Wishbone Bus Defaults ---
WB_CTI_O <= WB_CLASSIC_CYC;
WB_TGC_O <= '0' & STORM_MODE_I;
WB_WE_O <= '0';
WB_CYC_O <= '0';
WB_STB_O <= '0';
WB_CTI_O <= WB_CLASSIC_CYC;
WB_TGC_O <= "00" & STORM_MODE_I;
WB_CYC_O <= '0';
WB_STB_O <= '0';
 
--- D-Cache Interface Defaults ---
DC_CS_O <= '0';
DC_WE_O <= '0';
DC_UPDATE_O <= '0';
D_ABORT_O <= '0';
 
DC_CS_O <= '0';
DC_WE_O <= '0';
D_ABORT_O <= '0';
DC_DRT_ACK_O <= '0';
DC_MSS_ACK_O <= '0';
--- I-Cache Interface Defaults ---
IC_CS_O <= '0';
IC_UPDATE_O <= '0';
I_ABORT_O <= '0';
IC_CS_O <= '0';
I_ABORT_O <= '0';
IC_MSS_ACK_O <= '0';
 
--- State Machine ---
case (ARB_STATE) is
267,35 → 277,45
-------------------------------------------------------------------------------
IC_ADR_BUF_NXT <= IF_BASE_ADR_V;
DC_ADR_BUF_NXT <= DF_BASE_ADR_V;
TIMEOUT_CNT_NXT <= (others => '0');
if (IC_MISS_I = '1') then -- i-cache miss -> reload cache page
if (IO_ACCESS = '1') and (DC_P_CS_I = '1') then -- IO access
ARB_STATE_NXT <= IO_REQUEST;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DC_P_ADR_I;
WE_FLAG_NXT <= DC_P_WE_I;
elsif (IC_MISS_I = '1') then -- i-cache miss -> reload cache page
ARB_STATE_NXT <= DOWNLOAD_I_PAGE;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= IF_BASE_ADR_V;
BASE_BUF_NXT <= IF_BASE_ADR_V;
WE_FLAG_NXT <= '0'; -- bus read
elsif (DC_MISS_I = '1') then -- d-cache miss -> reload cache page
ARB_STATE_NXT <= DOWNLOAD_D_PAGE;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DF_BASE_ADR_V;
BASE_BUF_NXT <= DF_BASE_ADR_V;
WE_FLAG_NXT <= '0'; -- bus read
elsif (DC_DIRTY_I = '1') then -- d-cache modification -> copy page to main memory
ARB_STATE_NXT <= ASSIGN_D_PAGE;
DC_ADR_BUF_NXT <= DC_BSA_I;
WB_ADR_BUF_NXT <= DC_BSA_I;
BASE_BUF_NXT <= DC_BSA_I;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
WE_FLAG_NXT <= '1'; -- bus write
FREEZE_FLAG_NXT <= '1';
PAGE_SEL_NXT <= (others => '0');
end if;
 
when DOWNLOAD_I_PAGE => -- get new i-cache page
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '1'; -- indicate instruction transfer
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
IC_UPDATE_O <= '1'; -- i-cache update
WB_TGC_O(5) <= '1'; -- indicate instruction transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (IC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + I_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
elsif (WB_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) - 4 + I_CACHE_PAGE_SIZE*4)) then
WB_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(WB_ADR_BUF) + 4); -- inc counter
end if;
307,6 → 327,7
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
I_ABORT_O <= '1';
FREEZE_DIS_NXT <= '1';
end if;
313,17 → 334,18
 
when DOWNLOAD_D_PAGE => -- get new d-cache page
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
DC_UPDATE_O <= '1'; -- d-cache update
DC_WE_O <= '1'; -- cache write access
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
DC_WE_O <= '1'; -- cache write access
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (DC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
elsif (WB_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) - 4 + D_CACHE_PAGE_SIZE*4)) then
WB_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(WB_ADR_BUF) + 4); -- inc counter
end if;
335,46 → 357,62
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
D_ABORT_O <= '1';
FREEZE_DIS_NXT <= '1';
end if;
 
when ASSIGN_D_PAGE => -- find dirty page in cache and get base address
when IO_REQUEST => -- read/write IO location (single 32-bit word)
-------------------------------------------------------------------------------
if (DC_DRT_SEL_I = '1') then
FREEZE_FLAG_NXT <= '1';
DC_ADR_BUF_NXT <= DC_BSA_I;
WB_ADR_BUF_NXT <= DC_BSA_I;
BASE_BUF_NXT <= DC_BSA_I;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
else
PAGE_SEL_NXT <= Std_Logic_Vector(unsigned(PAGE_SEL) + 1); -- analyse next page
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '1'; -- io access
WB_CTI_O <= WB_CON_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
DC_WE_O <= '1'; -- dummy cache write access
DC_ADR_BUF_NXT <= WB_ADR_BUF;
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
DC_MSS_ACK_O <= '1'; -- ack of pseudo miss signal
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
DC_MSS_ACK_O <= '1'; -- ack of pseudo miss signal
D_ABORT_O <= '1';
FREEZE_DIS_NXT <= '1';
end if;
 
when UPLOAD_D_PAGE => -- copy d-cache page to main memory
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= VA_CYC_BUF; -- valid cycle, delayed one cycle
WB_STB_O <= VA_CYC_BUF; -- valid transfer, delayed one cycle
WB_WE_O <= '1'; -- wishbone write access
DC_UPDATE_O <= '1'; -- d-cache update
DC_CS_O <= '1'; -- enable data read back
DC_WE_O <= '0'; -- cache read access
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (DC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
FREEZE_FLAG_NXT <= '1';
else
WB_ADR_BUF_NXT <= DC_ADR_BUF;
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc counter
VA_CYC_BUF_NXT <= '1';
WB_ADR_BUF_NXT <= DC_ADR_BUF;
VA_CYC_BUF_NXT <= '1';
if (WB_ADR_BUF = Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
if (WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of dirty signal
VA_CYC_BUF_NXT <= '0';
end if;
end if;
if (DC_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc pointer
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack dirty signal
D_ABORT_O <= '1';
FREEZE_DIS_NXT <= '1';
end if;
381,11 → 419,11
 
when END_TRANSFER => -- terminate cycle
-------------------------------------------------------------------------------
TIMEOUT_CNT_NXT <= (others => '0');
if (DC_DIRTY_I = '1') then -- another dirty page in cache
ARB_STATE_NXT <= ASSIGN_D_PAGE;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
else -- finish transfer
FREEZE_FLAG_NXT <= '0';
FREEZE_DIS_NXT <= '0';
ARB_STATE_NXT <= IDLE;
end if;
 
/storm_core/rtl/CORE.vhd
21,7 → 21,7
-- # | -> stnolting@googlemail.com #
-- # | -> stnolting@web.de #
-- # *************************************************************************************************** #
-- # Last modified: 10.01.2012 #
-- # Last modified: 08.02.2012 #
-- #######################################################################################################
 
library IEEE;
44,7 → 44,6
-- ###############################################################################################
 
RES : in STD_LOGIC; -- global reset input (high active)
F_RST : out STD_LOGIC; -- force system reset
CLK : in STD_LOGIC; -- global clock input
 
-- ###############################################################################################
69,6 → 68,8
D_CACHE_FLUSH : out STD_LOGIC; -- flush d-cache
D_CACHE_MISS : in STD_LOGIC; -- d-cache miss
D_CACHE_HIT : in STD_LOGIC; -- d-cache hit
D_CACHE_FRESH : out STD_LOGIC; -- refresh d-cache
D_CACHE_CIO : out STD_LOGIC; -- enable cached IO
 
-- ###############################################################################################
-- ## Instruction Cache Interface ##
81,6 → 82,7
I_CACHE_CLEAR : out STD_LOGIC; -- clear i-cache
I_CACHE_MISS : in STD_LOGIC; -- i-cache miss
I_CACHE_HIT : in STD_LOGIC; -- i-cache hit
I_CACHE_FRESH : out STD_LOGIC; -- refresh i-cache
 
-- ###############################################################################################
-- ## General Control Lines ##
88,7 → 90,8
 
C_BUS_CYCC_O : out STD_LOGIC_VECTOR(15 downto 0); -- max bus cycle length
C_WTHRU_O : out STD_LOGIC; -- write through
C_BGWB_O : out STD_LOGIC; -- background write-back
IO_PORT_OUT : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_IN : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
 
-- ###############################################################################################
-- ## Interrupt Interface ##
155,7 → 158,6
signal MCR_STOP_IF : STD_LOGIC; -- stop instruction fetch
signal PIPE_EMPTY : STD_LOGIC; -- pipeline is empty
signal D_MEM_MODE : STD_LOGIC_VECTOR(04 downto 0); -- mode for data mem access
signal MR_FREEZE : STD_LOGIC; -- freeze core until reset
 
begin
-- Global CLOCK, RESET and HALT Networks -----------------------------------------------------
162,7 → 164,7
-- ----------------------------------------------------------------------------------------------
gCLK <= CLK;
gRES <= RES;
G_HALT <= HALT or MR_FREEZE; -- maybe try clock gating?!
G_HALT <= HALT; -- maybe try clock gating?!
 
 
 
218,7 → 220,6
CLK_I => gCLK, -- global clock net
G_HALT_I => G_HALT, -- global halt signal
RST_I => gRES, -- global active high reset
F_RST_O => F_RST, -- force system reset
CTRL_I => EX1_CTRL, -- stage control
HALT_I => PC_HALT, -- halt program counter
PEND_XI_REQ_O => MCR_STOP_IF, -- pending ext. int request
241,12 → 242,15
DC_CLEAR_O => D_CACHE_CLEAR, -- clear d-cache
DC_HIT_I => D_CACHE_HIT, -- d-cache hit access
DC_MISS_I => D_CACHE_MISS, -- d-cache miss acess
DC_FRESH_O => D_CACHE_FRESH, -- d-cache auto-refresh
IC_FRESH_O => I_CACHE_FRESH, -- i-cache auto-refresh
IC_CLEAR_O => I_CACHE_CLEAR, -- clear i-cache
IC_HIT_I => I_CACHE_HIT, -- i-cache hit access
IC_MISS_I => I_CACHE_MISS, -- i-cache miss accessear i-cache
C_WTHRU_O => C_WTHRU_O, -- write through
C_BGWB_O => C_BGWB_O, -- background write-back
SC_FREEZE_O => MR_FREEZE -- freeze core until reset
CACHED_IO_O => D_CACHE_CIO, -- en cached IO
IO_PORT_O => IO_PORT_OUT, -- direct output
IO_PORT_I => IO_PORT_IN -- direct input
);
 
 
/storm_core/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and #
-- # system parameters for the STORM Core processor. #
-- # +-------------------------------------------------+ #
-- # Last modified: 21.01.2012 #
-- # Last modified: 15.02.2012 #
-- #######################################################
 
library IEEE;
167,65 → 167,74
constant CP_CSTAT : natural := 8; -- cache statistics register
constant CP_TIME_THRES : natural := 9; -- Internal timer, threshold value
constant CP_TIME_COUNT : natural := 10; -- Internal timer, counter
constant CP_LFSR_POLY : natural := 12; -- Internal lfsr, polynomial
constant CP_LFSR_DATA : natural := 13; -- Internal lfsr, shift register
constant CP_LFSR_POLY : natural := 11; -- Internal lfsr, polynomial
constant CP_LFSR_DATA : natural := 12; -- Internal lfsr, shift register
constant CP_IO_PORT : natural := 13; -- Internal IO port
 
-- INTERNAL IO PORT REGISTER --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant CP_IO_O_LSB : natural := 0; -- output LSB
constant CP_IO_O_MSB : natural := 15; -- output MSB
constant CP_IO_I_LSB : natural := 16; -- input LSB
constant CP_IO_I_MSB : natural := 31; -- input MSB
 
-- INTERNAL COPROCESSOR, SYSTEM CONTROL REGISTER 0 ----------------------------------------
-- -------------------------------------------------------------------------------------------
constant CSCR0_FDC : natural := 0; -- flush d-cache
constant CSCR0_CDC : natural := 1; -- clear d-cache
constant CSCR0_CIC : natural := 2; -- flush i-cache
constant CSCR0_CWT : natural := 3; -- cache write-thru enable
constant CSCR0_CBG : natural := 4; -- cache background write-back
constant CSCR0_RST : natural := 5; -- force system reset
constant CSCR0_FRZ : natural := 6; -- freeze processor until reset
constant CSCR0_TEN : natural := 7; -- internal timer enable
constant CSCR0_TIE : natural := 8; -- internal timer interrupt enable
constant CSCR0_TIM : natural := 9; -- internal timer interrupt mode (0:IRQ/1:FIQ)
constant CSCR0_LFSRE : natural := 10; -- internal LFSR enable
constant CSCR0_LFSRM : natural := 11; -- internal LFSR update mode (0:auto/1:access)
constant CSCR0_LFSRD : natural := 12; -- internal LFSR direction (0:right/1:left))
constant CSCR0_CWT : natural := 3; -- d-cache write-thru enable
constant CSCR0_DAR : natural := 4; -- auto pre-refresh d-cache for new access
constant CSCR0_IAR : natural := 5; -- auto pre-refresh i-cache for new access
constant CSCR0_CIO : natural := 6; -- enable cached IO
 
constant CSCR0_TEN : natural := 10; -- internal timer enable
constant CSCR0_TIE : natural := 11; -- internal timer interrupt enable
constant CSCR0_TIM : natural := 12; -- internal timer interrupt mode (0:IRQ/1:FIQ)
constant CSCR0_LFSRE : natural := 13; -- internal LFSR enable
constant CSCR0_LFSRM : natural := 14; -- internal LFSR update mode (0:auto/1:access)
constant CSCR0_LFSRD : natural := 15; -- internal LFSR direction (0:right/1:left))
constant CSCR0_MBC_0 : natural := 16; -- max bus cycle length bit 0
constant CSCR0_MBC_15 : natural := 31; -- max bus cycle length bit 15
 
-- INTERRUPT VECTORS ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant RES_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- hardware reset
constant UND_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- going to Undefined32_MODE
constant SWI_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- going to Supervisor32_MODE
constant PRF_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- going to Abort32_MODE
constant DAT_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- going to Abort32_MODE
constant IRQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11000"; -- going to IRQ32_MODE
constant FIQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11100"; -- going to FIQ32_MODE
constant RES_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00000"; -- hardware reset
constant UND_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "00100"; -- going to Undefined32_MODE
constant SWI_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01000"; -- going to Supervisor32_MODE
constant PRF_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "01100"; -- going to Abort32_MODE
constant DAT_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "10000"; -- going to Abort32_MODE
constant IRQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11000"; -- going to IRQ32_MODE
constant FIQ_INT_VEC : STD_LOGIC_VECTOR(4 downto 0) := "11100"; -- going to FIQ32_MODE
 
-- PROCESSOR MODE CODES -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant User32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10000";
constant FIQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10001";
constant IRQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10010";
constant Supervisor32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10011";
constant Abort32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10111";
constant Undefined32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "11011";
constant System32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "11111";
constant User32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10000";
constant FIQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10001";
constant IRQ32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10010";
constant Supervisor32_MODE: STD_LOGIC_VECTOR(4 downto 0) := "10011";
constant Abort32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "10111";
constant Undefined32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "11011";
constant System32_MODE : STD_LOGIC_VECTOR(4 downto 0) := "11111";
 
-- CONDITION OPCODES ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant COND_EQ : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant COND_NE : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant COND_CS : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant COND_CC : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant COND_MI : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant COND_PL : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant COND_VS : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant COND_VC : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant COND_HI : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant COND_LS : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant COND_GE : STD_LOGIC_VECTOR(3 downto 0) := "1010";
constant COND_LT : STD_LOGIC_VECTOR(3 downto 0) := "1011";
constant COND_GT : STD_LOGIC_VECTOR(3 downto 0) := "1100";
constant COND_LE : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant COND_AL : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant COND_NV : STD_LOGIC_VECTOR(3 downto 0) := "1111";
constant COND_EQ : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant COND_NE : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant COND_CS : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant COND_CC : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant COND_MI : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant COND_PL : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant COND_VS : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant COND_VC : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant COND_HI : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant COND_LS : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant COND_GE : STD_LOGIC_VECTOR(3 downto 0) := "1010";
constant COND_LT : STD_LOGIC_VECTOR(3 downto 0) := "1011";
constant COND_GT : STD_LOGIC_VECTOR(3 downto 0) := "1100";
constant COND_LE : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant COND_AL : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant COND_NV : STD_LOGIC_VECTOR(3 downto 0) := "1111";
 
-- COOL WORKING MUSIC ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
255,6 → 264,8
-- Brad Paisley - Letter To Me
-- Montgomery Gentry - Where I Come From
-- Dixie Chicks - Ready To Run
-- Eagle-Eye Cherry - Skull Tattoo
-- Jake Owen - Barefoot Blue Jean Night
 
-- INTERNAL MNEMONICS ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
292,7 → 303,6
CLK_I : in STD_LOGIC;
G_HALT_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
F_RST_O : out STD_LOGIC;
CTRL_I : in STD_LOGIC_VECTOR(CTRL_MSB downto 0);
HALT_I : in STD_LOGIC;
PEND_XI_REQ_O : out STD_LOGIC;
315,12 → 325,15
DC_CLEAR_O : out STD_LOGIC;
DC_HIT_I : in STD_LOGIC;
DC_MISS_I : in STD_LOGIC;
DC_FRESH_O : out STD_LOGIC;
IC_FRESH_O : out STD_LOGIC;
IC_CLEAR_O : out STD_LOGIC;
IC_HIT_I : in STD_LOGIC;
IC_MISS_I : in STD_LOGIC;
C_WTHRU_O : out STD_LOGIC;
C_BGWB_O : out STD_LOGIC;
SC_FREEZE_O : out STD_LOGIC
CACHED_IO_O : out STD_LOGIC;
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0);
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0)
);
end component;
 
526,12 → 539,10
CACHE_PAGES : natural := 4;
LOG2_CACHE_PAGES : natural := 2;
PAGE_SIZE : natural := 64; -- #words
LOG2_PAGE_SIZE : natural := 6;
READ_ONLY : boolean := FALSE
LOG2_PAGE_SIZE : natural := 6
);
port (
CORE_CLK_I : in STD_LOGIC;
BUS_CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
HALT_I : in STD_LOGIC;
P_CS_I : in STD_LOGIC;
544,12 → 555,12
B_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
B_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
B_DATA_O : out STD_LOGIC_VECTOR(31 downto 0);
B_DQ_I : in STD_LOGIC_VECTOR(01 downto 0);
B_WE_I : in STD_LOGIC;
B_PG_SEL_I : in STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
B_DRT_SEL_O : out STD_LOGIC;
B_BSA_O : out STD_LOGIC_VECTOR(31 downto 0);
C_UPDATE_I : in STD_LOGIC;
B_DRT_ACK_I : in STD_LOGIC;
B_MSS_ACK_I : in STD_LOGIC;
B_IO_ACC_I : in STD_LOGIC;
C_FRESH_I : in STD_LOGIC;
C_FLUSH_I : in STD_LOGIC;
C_CLEAR_I : in STD_LOGIC;
C_MISS_O : out STD_LOGIC;
570,11 → 581,12
D_CACHE_PAGES : natural;
LOG2_D_CACHE_PAGES : natural;
D_CACHE_PAGE_SIZE : natural;
LOG2_D_CACHE_PAGE_SIZE : natural
LOG2_D_CACHE_PAGE_SIZE : natural;
IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0);
IO_UC_END : STD_LOGIC_VECTOR(31 downto 0)
);
port (
CORE_CLK_I : in STD_LOGIC;
BUS_CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
FREEZE_STORM_O : out STD_LOGIC;
STORM_MODE_I : in STD_LOGIC_VECTOR(04 downto 0);
581,33 → 593,34
D_ABORT_O : out STD_LOGIC;
I_ABORT_O : out STD_LOGIC;
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0);
C_BGWB_I : in STD_LOGIC;
CACHED_IO_I : in STD_LOGIC;
DC_CS_O : out STD_LOGIC;
DC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_P_CS_I : in STD_LOGIC;
DC_P_WE_I : in STD_LOGIC;
DC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0);
DC_DATA_O : out STD_LOGIC_VECTOR(31 downto 0);
DC_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_DQ_O : out STD_LOGIC_VECTOR(01 downto 0);
DC_WE_O : out STD_LOGIC;
DC_UPDATE_O : out STD_LOGIC;
DC_MISS_I : in STD_LOGIC;
DC_DIRTY_I : in STD_LOGIC;
DC_PG_SEL_O : out STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0);
DC_DRT_SEL_I : in STD_LOGIC;
DC_BSA_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_DRT_ACK_O : out STD_LOGIC;
DC_MSS_ACK_O : out STD_LOGIC;
DC_IO_ACC_O : out STD_LOGIC;
IC_CS_O : out STD_LOGIC;
IC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
IC_P_CS_I : in STD_LOGIC;
IC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0);
IC_DATA_O : out STD_LOGIC_VECTOR(31 downto 0);
IC_DQ_O : out STD_LOGIC_VECTOR(01 downto 0);
IC_WE_O : out STD_LOGIC;
IC_UPDATE_O : out STD_LOGIC;
IC_MISS_I : in STD_LOGIC;
IC_MSS_ACK_O : out STD_LOGIC;
WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0);
WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0);
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0);
WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0);
WB_TGC_O : out STD_LOGIC_VECTOR(05 downto 0);
WB_TGC_O : out STD_LOGIC_VECTOR(06 downto 0);
WB_WE_O : out STD_LOGIC;
WB_CYC_O : out STD_LOGIC;
WB_STB_O : out STD_LOGIC;
625,7 → 638,6
);
port (
RES : in STD_LOGIC;
F_RST : out STD_LOGIC;
CLK : in STD_LOGIC;
HALT : in STD_LOGIC;
MODE : out STD_LOGIC_VECTOR(04 downto 0);
640,6 → 652,8
D_CACHE_FLUSH : out STD_LOGIC;
D_CACHE_MISS : in STD_LOGIC;
D_CACHE_HIT : in STD_LOGIC;
D_CACHE_FRESH : out STD_LOGIC;
D_CACHE_CIO : out STD_LOGIC;
I_CACHE_REQ : out STD_LOGIC;
I_CACHE_ADR : out STD_LOGIC_VECTOR(31 downto 0);
I_CACHE_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0);
647,9 → 661,11
I_CACHE_CLEAR : out STD_LOGIC;
I_CACHE_MISS : in STD_LOGIC;
I_CACHE_HIT : in STD_LOGIC;
I_CACHE_FRESH : out STD_LOGIC;
C_BUS_CYCC_O : out STD_LOGIC_VECTOR(15 downto 0);
C_WTHRU_O : out STD_LOGIC;
C_BGWB_O : out STD_LOGIC;
IO_PORT_OUT : out STD_LOGIC_VECTOR(15 downto 0);
IO_PORT_IN : in STD_LOGIC_VECTOR(15 downto 0);
IRQ : in STD_LOGIC;
FIQ : in STD_LOGIC
);
/storm_core/rtl/FLOW_CTRL.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Operation Flow Control Unit #
-- # *************************************************** #
-- # Last modified: 25.01.2012 #
-- # Last modified: 09.02.2012 #
-- #######################################################
 
library IEEE;
205,17 → 205,19
INSTR_REG <= NOP_CMD;
INSTR_BUF <= NOP_CMD;
INS_BUF_SEL <= '0';
elsif (WR_IR_EN = '1') and (G_HALT_I = '0') then
INS_BUF_SEL <= INS_BUF_SEL_NXT;
if (INS_BUF_SEL = '0') then
INSTR_BUF <= INSTR_I;
end if;
if (IR_HALT = '0') then
else
if (WR_IR_EN = '1') and (G_HALT_I = '0') then
INS_BUF_SEL <= INS_BUF_SEL_NXT;
if (INS_BUF_SEL = '0') then
INSTR_REG <= INSTR_I;
else
INSTR_REG <= INSTR_BUF;
INSTR_BUF <= INSTR_I;
end if;
if (IR_HALT = '0') then
if (INS_BUF_SEL = '0') then
INSTR_REG <= INSTR_I;
else
INSTR_REG <= INSTR_BUF;
end if;
end if;
end if;
end if;
end if;
/storm_core/rtl/MC_SYS.vhd
1,9 → 1,9
-- #######################################################
-- # < STORM CORE PROCESSOR by Stephan Nolting > #
-- # *************************************************** #
-- # Machine Control Register System #
-- # Machine Control System #
-- # *************************************************** #
-- # Last modified: 23.01.2012 #
-- # Last modified: 15.02.2012 #
-- #######################################################
 
library IEEE;
27,7 → 27,6
CLK_I : in STD_LOGIC; -- global clock line
G_HALT_I : in STD_LOGIC; -- global halt line
RST_I : in STD_LOGIC; -- global reset line, high active
F_RST_O : out STD_LOGIC; -- force system reset
 
-- ###############################################################################################
-- ## Global Control ##
72,17 → 71,21
DC_CLEAR_O : out STD_LOGIC; -- clear d-cache
DC_HIT_I : in STD_LOGIC; -- d-cache hit access
DC_MISS_I : in STD_LOGIC; -- d-cache miss acess
DC_FRESH_O : out STD_LOGIC; -- d-cache auto-refresh
IC_FRESH_O : out STD_LOGIC; -- i-cache auto-refresh
IC_CLEAR_O : out STD_LOGIC; -- clear i-cache
IC_HIT_I : in STD_LOGIC; -- i-cache hit access
IC_MISS_I : in STD_LOGIC; -- i-cache miss access
C_WTHRU_O : out STD_LOGIC; -- write through
C_BGWB_O : out STD_LOGIC; -- background write-back
CACHED_IO_O : out STD_LOGIC; -- en cached IO
 
-- ###############################################################################################
-- ## System Control ##
-- ###############################################################################################
 
SC_FREEZE_O : out STD_LOGIC -- freeze processor until reset
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0) -- direct input
 
);
end MC_SYS;
 
142,15 → 145,15
begin
if rising_edge(CLK_I) then
if (RST_I = '1') then
FIQ_TAKEN <= '0';
IRQ_TAKEN <= '0';
DAB_TAKEN <= '0';
IAB_TAKEN <= '0';
FIQ_TAKEN <= '0';
IRQ_TAKEN <= '0';
DAB_TAKEN <= '0';
IAB_TAKEN <= '0';
elsif (G_HALT_I = '0')then
FIQ_TAKEN <= FIQ_TAKEN_NXT and (not FIQ_TAKEN);
IRQ_TAKEN <= IRQ_TAKEN_NXT and (not IRQ_TAKEN);
DAB_TAKEN <= DAB_TAKEN_NXT and (not DAB_TAKEN);
IAB_TAKEN <= IAB_TAKEN_NXT and (not IAB_TAKEN);
FIQ_TAKEN <= FIQ_TAKEN_NXT and (not FIQ_TAKEN);
IRQ_TAKEN <= IRQ_TAKEN_NXT and (not IRQ_TAKEN);
DAB_TAKEN <= DAB_TAKEN_NXT and (not DAB_TAKEN);
IAB_TAKEN <= IAB_TAKEN_NXT and (not IAB_TAKEN);
end if;
end if;
end process EXT_INT_SYNC_REG;
274,32 → 277,42
FLAG_BUS(SREG_DAB_DIS) <= MCR_CMSR(SREG_DAB_DIS); -- keep current interrupt settings
FLAG_BUS(SREG_IAB_DIS) <= MCR_CMSR(SREG_IAB_DIS); -- keep current interrupt settings
 
-- interrupt hirarchie / priority list --
if (DAB_TAKEN = '1') then -- data fetch abort
--- Priority 1: Data Fetch Abort ---
if (DAB_TAKEN = '1') then
INT_VEC <= DAT_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Abort32_MODE;
NEW_MODE <= Abort32_MODE;
FLAG_BUS(SREG_DAB_DIS) <= '1'; -- disable DAB
elsif (FIQ_TAKEN = '1') then -- fast interrupt request
 
--- Priority 2: Fast Interrupt Request ---
elsif (FIQ_TAKEN = '1') then
INT_VEC <= FIQ_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= FIQ32_MODE;
NEW_MODE <= FIQ32_MODE;
FLAG_BUS(SREG_FIQ_DIS) <= '1'; -- disable FIQ
elsif (IRQ_TAKEN = '1') then -- interrupt request
 
--- Priority 3: Interrupt Request ---
elsif (IRQ_TAKEN = '1') then
INT_VEC <= IRQ_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= IRQ32_MODE;
NEW_MODE <= IRQ32_MODE;
FLAG_BUS(SREG_IRQ_DIS) <= '1'; -- disable IRQ
elsif (IAB_TAKEN = '1') then -- instruction fetch abort
 
--- Priority 4: Instruction Fetch Abort ---
elsif (IAB_TAKEN = '1') then
INT_VEC <= PRF_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Abort32_MODE;
NEW_MODE <= Abort32_MODE;
FLAG_BUS(SREG_IAB_DIS) <= '1'; -- disable IAB
elsif (UND_TAKEN = '1') then -- undefined instruction
 
--- Priority 5: Undefined Instruction ---
elsif (UND_TAKEN = '1') then
INT_VEC <= UND_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Undefined32_MODE;
NEW_MODE <= Undefined32_MODE;
elsif (SWI_TAKEN = '1') then -- software interrupt
 
--- Priority 6: Software I nterrupt ---
elsif (SWI_TAKEN = '1') then
INT_VEC <= SWI_INT_VEC;
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Supervisor32_MODE;
NEW_MODE <= Supervisor32_MODE;
342,13 → 355,13
if rising_edge(CLK_I) then
if (RST_I = '1') then
MCR_PC <= BOOT_VEC; -- start-up address
MCR_CMSR <= x"000001FF"; -- INTs disabled and we're in SYSTEM32 mode
SMSR_FIQ <= x"000001F0"; -- INTs disabled and return to USER32 mode
SMSR_SVC <= x"000001F0"; -- INTs disabled and return to USER32 mode
SMSR_ABT <= x"000001F0"; -- INTs disabled and return to USER32 mode
SMSR_IRQ <= x"000001F0"; -- INTs disabled and return to USER32 mode
SMSR_UND <= x"000001F0"; -- INTs disabled and return to USER32 mode
SMSR_SYS <= x"000001F0"; -- INTs disabled and return to USER32 mode
MCR_CMSR <= x"000003DF"; -- INTs disabled and we're in SYSTEM32 mode
SMSR_FIQ <= x"000003D0"; -- INTs disabled and return to USER32 mode
SMSR_SVC <= x"000003D0"; -- INTs disabled and return to USER32 mode
SMSR_ABT <= x"000003D0"; -- INTs disabled and return to USER32 mode
SMSR_IRQ <= x"000003D0"; -- INTs disabled and return to USER32 mode
SMSR_UND <= x"000003D0"; -- INTs disabled and return to USER32 mode
SMSR_SYS <= x"000003D0"; -- INTs disabled and return to USER32 mode
elsif (G_HALT_I = '0') then
 
 
402,44 → 415,6
 
 
---- SAVED MACHINE STATUS REGISTER -------------------------------------------------
-- if (CONT_EXE = '1') then -- context up change
-- case (NEW_MODE) is
-- when FIQ32_MODE => SMSR_FIQ <= MCR_CMSR;
-- when Supervisor32_MODE => SMSR_SVC <= MCR_CMSR;
-- when Abort32_MODE => SMSR_ABT <= MCR_CMSR;
-- when IRQ32_MODE => SMSR_IRQ <= MCR_CMSR;
-- when Undefined32_MODE => SMSR_UND <= MCR_CMSR;
-- when System32_MODE => SMSR_SYS <= MCR_CMSR;
-- when others => NULL;
-- end case;
-- elsif (CTRL_I(CTRL_EN) and mwr_smsr_v) = '1' then -- manual data write
-- if (CTRL_I(CTRL_MREG_FA) = '1') then
-- -- flag access only --
-- case (current_mode_v) is
-- when FIQ32_MODE => SMSR_FIQ(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when Supervisor32_MODE => SMSR_SVC(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when Abort32_MODE => SMSR_ABT(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when IRQ32_MODE => SMSR_IRQ(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when Undefined32_MODE => SMSR_UND(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when System32_MODE => SMSR_SYS(31 downto 28) <= MCR_DATA_I(31 downto 28);
-- when others => NULL;
-- end case;
-- else
-- -- full SMSR access --
-- case (current_mode_v) is
-- when FIQ32_MODE => SMSR_FIQ <= MCR_DATA_I;
-- when Supervisor32_MODE => SMSR_SVC <= MCR_DATA_I;
-- when Abort32_MODE => SMSR_ABT <= MCR_DATA_I;
-- when IRQ32_MODE => SMSR_IRQ <= MCR_DATA_I;
-- when Undefined32_MODE => SMSR_UND <= MCR_DATA_I;
-- when System32_MODE => SMSR_SYS <= MCR_DATA_I;
-- when others => NULL;
-- end case;
-- end if;
-- end if;
 
 
---- SAVED MACHINE STATUS REGISTER -------------------------------------------------
smsr_acc_case_v := CONT_EXE & (CTRL_I(CTRL_EN) and mwr_smsr_v) & CTRL_I(CTRL_MREG_FA);
case (smsr_acc_case_v) is
-- Content up-change --
492,9 → 467,9
-- System Coprocessor Write Access ----------------------------------------------------------------
-- ---------------------------------------------------------------------------------------------------
SYS_CP_ACC: process(CLK_I, CTRL_I, MCR_CMSR)
variable is_priv_mode_v : std_logic;
variable cr_r_acc_v, cr_w_acc_v : std_logic;
variable cp_adr_v : integer range 0 to 15;
variable is_priv_mode_v : std_logic;
variable cr_r_acc_v, cr_w_acc_v : std_logic;
variable cp_adr_v : integer range 0 to 15;
begin
-- Is Priviliged mode? --
is_priv_mode_v := '1';
517,10 → 492,10
if rising_edge(CLK_I) then
if (RST_I = '1') then
CP_REG_FILE <= (others => (others => '0')); -- clear all
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0116"; -- core update data
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;)
CP_REG_FILE(CP_SYS_CTRL_0) <= x"01000010"; -- system control register 0
CP_REG_FILE(CP_ID_REG_0) <= x"07DC020F"; -- core update date
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;)
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length
else
 
-- System Control Register 0 --------------------------------------------------
527,10 → 502,9
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_SYS_CTRL_0) then
CP_REG_FILE(CP_SYS_CTRL_0) <= MCR_DATA_I;
else
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_FDC) <= '0';
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CDC) <= '0';
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIC) <= '0';
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_RST) <= '0';
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_FDC) <= '0'; -- auto-reset flush d-cache
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CDC) <= '0'; -- auto-reset clear d-cache
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIC) <= '0'; -- auto-reset clear i-cache
end if;
 
-- Cache Statistic Register ---------------------------------------------------
570,7 → 544,7
elsif (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_LFSRE) = '1') then
if ((CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_LFSRM) = '1') and (cr_r_acc_v = '1')) or
(CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_LFSRM) = '0') then
if (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_LFSRD) = '1') then -- right shift
if (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_LFSRD) = '0') then -- right shift
CP_REG_FILE(CP_LFSR_DATA) <= LFSR_DN & CP_REG_FILE(CP_LFSR_DATA)(31 downto 1);
else -- left shift
CP_REG_FILE(CP_LFSR_DATA) <= CP_REG_FILE(CP_LFSR_DATA)(30 downto 0) & LFSR_DN;
578,6 → 552,12
end if;
end if;
 
-- Internal IO Register -------------------------------------------
CP_REG_FILE(CP_IO_PORT)(CP_IO_I_MSB downto CP_IO_I_LSB) <= IO_PORT_I;
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_TIME_COUNT) then
CP_REG_FILE(CP_IO_PORT)(CP_IO_O_MSB downto CP_IO_O_LSB) <= MCR_DATA_I(CP_IO_O_MSB downto CP_IO_O_LSB);
end if;
 
end if;
end if;
end process SYS_CP_ACC;
585,12 → 565,13
--- System Control Processor Output ---
DC_FLUSH_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_FDC);
DC_CLEAR_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CDC);
DC_FRESH_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_DAR);
CACHED_IO_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIO);
IC_FRESH_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_IAR);
IC_CLEAR_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIC);
C_WTHRU_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CWT);
C_BGWB_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CBG);
F_RST_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_RST);
SC_FREEZE_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_FRZ);
BUS_CYCC_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0);
IO_PORT_O <= CP_REG_FILE(CP_IO_PORT)(CP_IO_O_MSB downto CP_IO_O_LSB);
 
--- Internal Timer Interrupt ---
INT_TIMER_IRQ: process(CLK_I)
/storm_core/rtl/OPCODE_DECODER.vhd
18,11 → 18,11
-- ###############################################################################################
 
entity OPCODE_DECODER is
Port (
OPCODE_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
OPCODE_CTRL_I : in STD_LOGIC_VECTOR(15 downto 0);
OPCODE_CTRL_O : out STD_LOGIC_VECTOR(CTRL_MSB downto 0);
OPCODE_MISC_O : out STD_LOGIC_VECTOR(99 downto 0)
port (
OPCODE_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
OPCODE_CTRL_I : in STD_LOGIC_VECTOR(15 downto 0);
OPCODE_CTRL_O : out STD_LOGIC_VECTOR(CTRL_MSB downto 0);
OPCODE_MISC_O : out STD_LOGIC_VECTOR(99 downto 0)
);
end OPCODE_DECODER;
 
56,8 → 56,7
OPCODE_MISC_O(44 downto 33) <= OP_ADR_OUT;
OPCODE_MISC_O(47 downto 45) <= REG_SEL;
OPCODE_MISC_O(79 downto 48) <= IMM_OUT;
OPCODE_MISC_O(81 downto 80) <= (others => '0');
OPCODE_MISC_O(86 downto 82) <= (others => '0');
OPCODE_MISC_O(86 downto 80) <= (others => '0');
OPCODE_MISC_O(91 downto 87) <= NEXT_DUAL_OP;
OPCODE_MISC_O(99 downto 93) <= (others => '0'); -- unused
 
201,7 → 200,7
 
when "010" => -- store, pre indexing, no write back
----------------------------------------------------------------------------------
DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= "0000"; -- R_DEST wayne
DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST <WAYNE>
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE
DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN
467,7 → 466,7
 
when "010" => -- store, pre indexing, no write back
----------------------------------------------------------------------------------
DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= "0000"; -- R_DEST
DEC_CTRL(CTRL_RD_3 downto CTRL_RD_0) <= INSTR_REG(19 downto 16); -- R_DEST <WAYNE>
DEC_CTRL(CTRL_MEM_ACC) <= '1'; -- MEM_ACCESS
DEC_CTRL(CTRL_MEM_RW) <= '1'; -- MEM_WRITE
DEC_CTRL(CTRL_WB_EN) <= '0'; -- WB EN
531,7 → 530,6
 
else -- Block Data Transfer
----------------------------------------------------------------------------------
DEC_CTRL(CTRL_UND) <= INSTR_REG(22); -- undefined instruction when S-bit set
OP_ADR_OUT(OP_A_ADR_3 downto OP_A_ADR_0) <= INSTR_REG(19 downto 16); -- BASE
REG_SEL(OP_A_IS_REG) <= '1'; -- BASE is always a register
IMM_OUT(31 downto 0) <= x"00000004"; -- offset immediate
/storm_core/doc/STORM CORE datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/sim/STORM_core_TB.vhd
3,7 → 3,7
-- # *************************************************** #
-- # STORM Core / STORM SoC Testbench #
-- # *************************************************** #
-- # Last modified: 31.01.2012 #
-- # Last modified: 16.02.2012 #
-- #######################################################
 
library IEEE;
15,15 → 15,23
 
architecture Structure of STORM_core_TB is
 
-- Memory Map ---------------------------------------------------------------------
-- -----------------------------------------------------------------------------------
constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
constant INT_MEM_SIZE_C : natural := 1024; -- bytes
constant GP_IO_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020";
constant GP_IO_SIZE_C : natural := 8; -- bytes
 
 
-- Architecture Constants ---------------------------------------------------------
-- -----------------------------------------------------------------------------------
constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
constant INT_MEM_SIZE_C : natural := 2048; -- bytes
constant BOOT_VECTOR_C : STD_LOGIC_VECTOR(31 downto 0) := INT_MEM_BASE_C;
constant I_CACHE_PAGES_C : natural := 8; -- number of pages in I cache
constant I_CACHE_PAGE_SIZE_C : natural := 64; -- page size in I cache
constant D_CACHE_PAGES_C : natural := 8; -- number of pages in D cache
constant D_CACHE_PAGE_SIZE_C : natural := 1; -- page size in D cache
constant IO_BEGIN_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020"; -- first addr of IO area
constant IO_END_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE024"; -- last addr of IO area
constant I_CACHE_PAGES_C : natural := 4; -- number of pages in I cache
constant I_CACHE_PAGE_SIZE_C : natural := 32; -- page size in I cache
constant D_CACHE_PAGES_C : natural := 4; -- number of pages in D cache
constant D_CACHE_PAGE_SIZE_C : natural := 2; -- page size in D cache
 
 
-- Global Signals -----------------------------------------------------------------
32,9 → 40,7
-- Global Clock & Reset --
signal EXT_RST : STD_LOGIC;
signal MAIN_RST : STD_LOGIC;
signal SYS_RST : STD_LOGIC;
signal CORE_CLK : STD_LOGIC := '0';
signal BUS_CLK : STD_LOGIC := '0';
signal MAIN_CLK : STD_LOGIC := '0';
signal STORM_IRQ : STD_LOGIC;
signal STORM_FIQ : STD_LOGIC;
 
41,7 → 47,7
-- Wishbone Core Bus --
signal CORE_WB_ADR_O : STD_LOGIC_VECTOR(31 downto 0); -- address
signal CORE_WB_CTI_O : STD_LOGIC_VECTOR(02 downto 0); -- cycle type
signal CORE_WB_TGC_O : STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
signal CORE_WB_TGC_O : STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
signal CORE_WB_SEL_O : STD_LOGIC_VECTOR(03 downto 0); -- byte select
signal CORE_WB_WE_O : STD_LOGIC; -- write enable
signal CORE_WB_DATA_O : STD_LOGIC_VECTOR(31 downto 0); -- data out
56,12 → 62,20
-- -----------------------------------------------------------------------------------
 
-- Internal Working Memory --
signal INT_MEM_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal INT_MEM_STB_I : STD_LOGIC;
signal INT_MEM_ACK_O : STD_LOGIC;
signal INT_MEM_HALT_O : STD_LOGIC;
signal INT_MEM_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal INT_MEM_STB_I : STD_LOGIC;
signal INT_MEM_ACK_O : STD_LOGIC;
signal INT_MEM_HALT_O : STD_LOGIC;
 
-- General Purpose IO Controller --
signal GP_IO_CTRL_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal GP_IO_CTRL_STB_I : STD_LOGIC;
signal GP_IO_CTRL_ACK_O : STD_LOGIC;
signal GP_IO_CTRL_HALT_O : STD_LOGIC;
signal GP_IO_OUT_PORT : STD_LOGIC_VECTOR(31 downto 0);
signal GP_IO_IN_PORT : STD_LOGIC_VECTOR(31 downto 0);
 
 
-- Logarithm duales ---------------------------------------------------------------
-- -----------------------------------------------------------------------------------
function log2(temp : natural) return natural is
83,19 → 97,21
I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
D_CACHE_PAGES : natural := 8; -- number of pages in D cache
D_CACHE_PAGE_SIZE : natural := 4; -- page size in D cache
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0) := x"00000000" -- boot address
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0); -- boot address
IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0); -- begin of uncachable IO area
IO_UC_END : STD_LOGIC_VECTOR(31 downto 0) -- end of uncachable IO area
);
port (
-- Global Control --
CORE_CLK_I : in STD_LOGIC; -- core clock input
BUS_CLK_I : in STD_LOGIC; -- bus clock input
RST_I : in STD_LOGIC; -- global reset input
F_RST_O : out STD_LOGIC; -- force system reset
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
 
-- Wishbone Bus --
WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- address
WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0); -- cycle type
WB_TGC_O : out STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_TGC_O : out STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); -- byte select
WB_WE_O : out STD_LOGIC; -- write enable
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data out
124,7 → 140,7
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
137,6 → 153,33
end component;
 
 
-- General Purpose IO Controller --------------------------------------------------
-- -----------------------------------------------------------------------------------
component GP_IO_CTRL
port (
-- Wishbone Bus --
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC; -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
WB_WE_I : in STD_LOGIC; -- write enable
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC; -- throttle master
 
-- IO Port --
GP_IO_O : out STD_LOGIC_VECTOR(31 downto 00);
GP_IO_I : in STD_LOGIC_VECTOR(31 downto 00);
 
-- Input Change INT --
IO_IRQ_O : out STD_LOGIC
);
end component;
 
begin
 
-- #################################################################################################################################
147,12 → 190,11
-- --------------------------------------------------------------------------------------------------------
 
-- Clock Generator --
CORE_CLK <= not CORE_CLK after 20 ns; -- 50MHz
BUS_CLK <= not BUS_CLK after 40 ns; -- 25MHz
MAIN_CLK <= not MAIN_CLK after 20 ns; -- 50MHz
 
-- Reset System --
EXT_RST <= '1', '0' after 400 ns;
MAIN_RST <= EXT_RST or SYS_RST;
MAIN_RST <= EXT_RST;
 
-- Interrupt Generator --
STORM_IRQ <= '0', '1' after 2000 ns, '0' after 2020 ns;
168,14 → 210,16
I_CACHE_PAGE_SIZE => I_CACHE_PAGE_SIZE_C, -- page size in I cache
D_CACHE_PAGES => D_CACHE_PAGES_C, -- number of pages in D cache
D_CACHE_PAGE_SIZE => D_CACHE_PAGE_SIZE_C, -- page size in D cache
BOOT_VECTOR => BOOT_VECTOR_C -- startup boot address
BOOT_VECTOR => BOOT_VECTOR_C, -- startup boot address
IO_UC_BEGIN => IO_BEGIN_C, -- begin of uncachable IO area
IO_UC_END => IO_END_C -- end of uncachable IO area
)
port map (
-- Global Control --
CORE_CLK_I => CORE_CLK, -- core clock input
BUS_CLK_I => BUS_CLK, -- bus clock input
CORE_CLK_I => MAIN_CLK, -- core clock input
RST_I => MAIN_RST, -- global reset input
F_RST_O => SYS_RST, -- force system reset
IO_PORT_O => open, -- direct output
IO_PORT_I => x"0000", -- direct input
 
-- Wishbone Bus --
WB_ADR_O => CORE_WB_ADR_O, -- address
204,33 → 248,45
-- Read-Back Data Selector -----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_DATA_I <=
INT_MEM_DATA_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else
-- DUMMY0_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else
-- DUMMY1_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else
INT_MEM_DATA_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else
GP_IO_CTRL_DATA_O when (CORE_WB_ADR_O(31 downto log2(GP_IO_SIZE_C)) = GP_IO_BASE_C( 31 downto log2(GP_IO_SIZE_C))) else
-- DUMMY0_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else
-- DUMMY1_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else
x"00000000";
 
-- Use this style of data read-back terminal for pipelined Wishbone systems.
-- You have to ensure, that all not selected IO devices set their data output to 0.
-- CORE_WB_DATA_I <= INT_MEM_DATA_O or
-- GP_IO_CTRL_DATA_O or
-- DUMMY0_DATA_O or
-- DUMMY1_DATA_O or
-- x"00000000";
 
 
-- Acknowledge Terminal --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_ACK_I <= INT_MEM_ACK_O or
-- DUMMY0_ACK_O or
-- DUMMY1_ACK_O or
CORE_WB_ACK_I <= INT_MEM_ACK_O or
GP_IO_CTRL_ACK_O or
-- DUMMY0_ACK_O or
-- DUMMY1_ACK_O or
'0';
 
 
-- Halt Terminal ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_HALT_I <= INT_MEM_HALT_O or
-- DUMMY0_HALT_O or
-- DUMMY1_HALT_O or
CORE_WB_HALT_I <= INT_MEM_HALT_O or
GP_IO_CTRL_HALT_O or
-- DUMMY0_HALT_O or
-- DUMMY1_HALT_O or
'0';
 
 
-- Valid Transfer Signal Terminal ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INT_MEM_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else '0';
-- DUMMY0_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else '0';
-- DUMMY1_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else '0';
INT_MEM_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else '0';
GP_IO_CTRL_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(GP_IO_SIZE_C)) = GP_IO_BASE_C( 31 downto log2(GP_IO_SIZE_C))) else '0';
-- DUMMY0_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else '0';
-- DUMMY1_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else '0';
 
 
 
246,7 → 302,7
LOG2_MEM_SIZE => log2(INT_MEM_SIZE_C/4) -- log2 memory size in 32-bit cells
)
port map(
WB_CLK_I => BUS_CLK,
WB_CLK_I => MAIN_CLK,
WB_RST_I => MAIN_RST,
WB_CTI_I => CORE_WB_CTI_O,
WB_TGC_I => CORE_WB_TGC_O,
261,4 → 317,34
);
 
 
 
-- General Purpose IO ----------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
IO_CONTROLLER: GP_IO_CTRL
port map (
-- Wishbone Bus --
WB_CLK_I => MAIN_CLK,
WB_RST_I => MAIN_RST,
WB_CTI_I => CORE_WB_CTI_O,
WB_TGC_I => CORE_WB_TGC_O,
WB_ADR_I => CORE_WB_ADR_O(2),
WB_DATA_I => CORE_WB_DATA_O,
WB_DATA_O => GP_IO_CTRL_DATA_O,
WB_SEL_I => CORE_WB_SEL_O,
WB_WE_I => CORE_WB_WE_O,
WB_STB_I => GP_IO_CTRL_STB_I,
WB_ACK_O => GP_IO_CTRL_ACK_O,
WB_HALT_O => GP_IO_CTRL_HALT_O,
 
-- IO Port --
GP_IO_O => GP_IO_OUT_PORT,
GP_IO_I => GP_IO_IN_PORT,
 
-- Input Change INT --
IO_IRQ_O => open
);
 
-- Dummy input --
GP_IO_IN_PORT <= "00000000001100111100110000000000";
 
end Structure;
/storm_core/sim/GP_IO_CTRL.vhd
0,0 → 1,148
-- #######################################################
-- # < STORM System on Chip by Stephan Nolting > #
-- # *************************************************** #
-- # General Purpose 32-bit IO Controller #
-- # *************************************************** #
-- # Last modified: 16.02.2012 #
-- #######################################################
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity GP_IO_CTRL is
port (
-- Wishbone Bus --
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC; -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
WB_WE_I : in STD_LOGIC; -- write enable
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC; -- throttle master
 
-- IO Port --
GP_IO_O : out STD_LOGIC_VECTOR(31 downto 00);
GP_IO_I : in STD_LOGIC_VECTOR(31 downto 00);
 
-- Input Change INT --
IO_IRQ_O : out STD_LOGIC
);
end GP_IO_CTRL;
 
architecture Structure of GP_IO_CTRL is
 
-- Input / Output Sync Register --
signal IO_I_SYNC, IO_O_SYNC, IRQ_SYNC : STD_LOGIC_VECTOR(31 downto 0);
 
-- internal Buffer --
signal WB_ACK_O_INT : STD_LOGIC;
-- Memory Map (word boundary)
-- ADR_I = 0 : Access to OUTPUT register
-- ADR_I = 1 : Access to INPUT register
 
begin
 
-- Wishbone Input Interface ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
WB_W_ACCESS: process(WB_CLK_I)
begin
if rising_edge(WB_CLK_I) then
if (WB_RST_I = '1') then
IO_O_SYNC <= (others => '0');
elsif (WB_STB_I = '1') and (WB_WE_I = '1') and (WB_ADR_I = '0') then -- valid write access
for i in 0 to 3 loop
if (WB_SEL_I(i) = '1') then
IO_O_SYNC(8*i+7 downto 8*i) <= WB_DATA_I(8*i+7 downto 8*i);
end if;
end loop;
end if;
end if;
end process WB_W_ACCESS;
 
--- Out-Port ---
GP_IO_O <= IO_O_SYNC;
 
 
 
-- Wishbone Output Interface ---------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
WB_R_ACCESS: process(WB_CLK_I)
begin
if rising_edge(WB_CLK_I) then
if (WB_RST_I = '1') then
WB_DATA_O <= (others => '0');
WB_ACK_O_INT <= '0';
else
--- Data Output ---
if (WB_STB_I = '1') and (WB_WE_I = '0') then -- valid read request
if (WB_ADR_I = '0') then
WB_DATA_O <= IO_O_SYNC;
else
WB_DATA_O <= IO_I_SYNC;
end if;
else
WB_DATA_O <= (others => '0');
end if;
 
--- ACK Control ---
if (WB_CTI_I = "000") or (WB_CTI_I = "111") then
WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT);
else
WB_ACK_O_INT <= WB_STB_I; -- data is valid one cycle later
end if;
end if;
end if;
end process WB_R_ACCESS;
 
--- ACK Signal ---
WB_ACK_O <= WB_ACK_O_INT;
 
--- Throttle ---
WB_HALT_O <= '0'; -- yeay, we're at full speed!
 
 
 
-- Synchronize Input -------------------------------------------------
-- ----------------------------------------------------------------------
SYNC_INPUT: process(WB_CLK_I)
begin
if rising_edge(WB_CLK_I) then
if (WB_RST_I = '1') then
IO_I_SYNC <= (others => '0');
IRQ_SYNC <= (others => '0');
else
IO_I_SYNC <= GP_IO_I;
IRQ_SYNC <= IO_I_SYNC;
end if;
end if;
end process SYNC_INPUT;
 
 
 
-- Input Change IRQ --------------------------------------------------
-- ----------------------------------------------------------------------
INPUT_CHANGE_IRQ: process(WB_CLK_I)
begin
if rising_edge(WB_CLK_I) then
if (WB_RST_I = '1') then
IO_IRQ_O <= '0';
else
if (IRQ_SYNC /= IO_I_SYNC) then
IO_IRQ_O <= '1';
else
IO_IRQ_O <= '0';
end if;
end if;
end if;
end process INPUT_CHANGE_IRQ;
 
 
 
end Structure;
/storm_core/sim/MEMORY.vhd
3,7 → 3,7
-- # ************************************************** #
-- # Internal Working Memory #
-- # ************************************************** #
-- # Version 3.0, 25.11.2011, PipeWB compatible #
-- # Last modified: 16.02.2012 #
-- ######################################################
 
library IEEE;
23,7 → 23,7
WB_CLK_I : in STD_LOGIC; -- memory master clock
WB_RST_I : in STD_LOGIC; -- high active sync reset
WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
WB_TGC_I : in STD_LOGIC_VECTOR(05 downto 0); -- cycle tag
WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
52,9 → 52,104
-----------------------------------------------------------------
constant RAM_IMAGE : RAM_IMAGE_TYPE :=
(
-- ############################################
-- # PLACE YOUR PROGRAM HERE #
-- ############################################
000000 => x"EA000012",
000001 => x"E59FF014",
000002 => x"E59FF014",
000003 => x"E59FF014",
000004 => x"E59FF014",
000005 => x"E1A00000",
000006 => x"E51FFFF0",
000007 => x"E59FF010",
000008 => x"00000038",
000009 => x"0000003C",
000010 => x"00000040",
000011 => x"00000044",
000012 => x"00000048",
000013 => x"0000004C",
000014 => x"EAFFFFFE",
000015 => x"EAFFFFFE",
000016 => x"EAFFFFFE",
000017 => x"EAFFFFFE",
000018 => x"EAFFFFFE",
000019 => x"EAFFFFFE",
000020 => x"E59F00C8",
000021 => x"E10F1000",
000022 => x"E3C1107F",
000023 => x"E38110DB",
000024 => x"E129F001",
000025 => x"E1A0D000",
000026 => x"E2400080",
000027 => x"E10F1000",
000028 => x"E3C1107F",
000029 => x"E38110D7",
000030 => x"E129F001",
000031 => x"E1A0D000",
000032 => x"E2400080",
000033 => x"E10F1000",
000034 => x"E3C1107F",
000035 => x"E38110D1",
000036 => x"E129F001",
000037 => x"E1A0D000",
000038 => x"E2400080",
000039 => x"E10F1000",
000040 => x"E3C1107F",
000041 => x"E38110D2",
000042 => x"E129F001",
000043 => x"E1A0D000",
000044 => x"E2400080",
000045 => x"E10F1000",
000046 => x"E3C1107F",
000047 => x"E38110D3",
000048 => x"E129F001",
000049 => x"E1A0D000",
000050 => x"E2400080",
000051 => x"E10F1000",
000052 => x"E3C1107F",
000053 => x"E38110DF",
000054 => x"E129F001",
000055 => x"E1A0D000",
000056 => x"E3A00000",
000057 => x"E59F1038",
000058 => x"E59F2038",
000059 => x"E1510002",
000060 => x"0A000001",
000061 => x"34810004",
000062 => x"3AFFFFFB",
000063 => x"E3A00000",
000064 => x"E1A01000",
000065 => x"E1A02000",
000066 => x"E1A0B000",
000067 => x"E1A07000",
000068 => x"E59FA014",
000069 => x"E1A0E00F",
000070 => x"E1A0F00A",
000071 => x"EAFFFFFE",
000072 => x"00000A00",
000073 => x"00000184",
000074 => x"00000184",
000075 => x"00000130",
000076 => x"E3E03A01",
000077 => x"E3A02000",
000078 => x"E52DE004",
000079 => x"E5032FDF",
000080 => x"E3A0E001",
000081 => x"E5032FDF",
000082 => x"E1A0100E",
000083 => x"E1A0000E",
000084 => x"E1A02000",
000085 => x"EA000000",
000086 => x"E3A0E001",
000087 => x"E2820001",
000088 => x"E08EC001",
000089 => x"E5031FDF",
000090 => x"E350001E",
000091 => x"E3A01000",
000092 => x"E1A02001",
000093 => x"CAFFFFF7",
000094 => x"E1A0100E",
000095 => x"E1A0E00C",
000096 => x"EAFFFFF2",
others => x"F0013007"
);
-----------------------------------------------------------------
 
109,6 → 204,8
WB_DATA_O(8*1+7 downto 8*1) <= MEM_FILE_LH(to_integer(unsigned(WB_ADR_I)));
WB_DATA_O(8*2+7 downto 8*2) <= MEM_FILE_HL(to_integer(unsigned(WB_ADR_I)));
WB_DATA_O(8*3+7 downto 8*3) <= MEM_FILE_HH(to_integer(unsigned(WB_ADR_I)));
-- else
-- WB_DATA_O <= (others => '0');
end if;
 
--- ACK Control ---
/storm_core/sim/Xilinx ISIM/storm_core_debug_wave.wcfg
12,7 → 12,7
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="43" />
<WVObjectSize size="53" />
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore globals</obj_property>
<obj_property name="DisplayName">label</obj_property>
36,10 → 36,6
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/f_rst_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">f_rst_o</obj_property>
<obj_property name="ObjectShortName">f_rst_o</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">STORMcore interrupt</obj_property>
<obj_property name="DisplayName">label</obj_property>
278,6 → 274,90
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="CustomSignalColor">#ffffff</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cp_reg_file[15:0]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[15:0]</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[15]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[15]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[15]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[14]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[14]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[14]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[13]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[13]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[13]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[12]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[12]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[12]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[11]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[11]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[11]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[10]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[10]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[10]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[9]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[9]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[8]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[8]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[8]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[7]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[6]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[6]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[5]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[5]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[4]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[3]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/Machine_Control_System/cp_reg_file[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">cp_reg_file[0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">DATA CACHE</obj_property>
<obj_property name="DisplayName">label</obj_property>
285,25 → 365,63
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_ll" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_ll[0:7]</obj_property>
<obj_property name="ObjectShortName">cache_mem_ll[0:7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/arb_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">arb_state</obj_property>
<obj_property name="ObjectShortName">arb_state</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_lh" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_lh[0:7]</obj_property>
<obj_property name="ObjectShortName">cache_mem_lh[0:7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/b_cs_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">b_cs_i</obj_property>
<obj_property name="ObjectShortName">b_cs_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_hl" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_hl[0:7]</obj_property>
<obj_property name="ObjectShortName">cache_mem_hl[0:7]</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/p_adr_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">p_adr_i[31:0]</obj_property>
<obj_property name="ObjectShortName">p_adr_i[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/cache_mem_hh" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_hh[0:7]</obj_property>
<obj_property name="ObjectShortName">cache_mem_hh[0:7]</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sim_mem[0:7]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0:7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">sim_mem[1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">sim_mem[2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">sim_mem[3]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">sim_mem[4]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[5]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">sim_mem[5]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[6]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">sim_mem[6]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/D_CACHE_INST/sim_mem[7]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">sim_mem[7]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">INSTRUCTION CACHE</obj_property>
312,26 → 430,655
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/cache_mem_ll" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_ll[0:511]</obj_property>
<obj_property name="ObjectShortName">cache_mem_ll[0:511]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/arb_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">arb_state</obj_property>
<obj_property name="ObjectShortName">arb_state</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/cache_mem_lh" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_lh[0:511]</obj_property>
<obj_property name="ObjectShortName">cache_mem_lh[0:511]</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sim_mem[0:127]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0:127]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem[1]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">sim_mem[1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">sim_mem[2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">sim_mem[3]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/sim_mem[4]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">sim_mem[4]</obj_property>
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<obj_property name="ElementShortName">[123]</obj_property>
<obj_property name="ObjectShortName">sim_mem[123]</obj_property>
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<obj_property name="ElementShortName">[124]</obj_property>
<obj_property name="ObjectShortName">sim_mem[124]</obj_property>
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<obj_property name="ElementShortName">[125]</obj_property>
<obj_property name="ObjectShortName">sim_mem[125]</obj_property>
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<obj_property name="ObjectShortName">sim_mem[126]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="ElementShortName">[127]</obj_property>
<obj_property name="ObjectShortName">sim_mem[127]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="ElementShortName">cache_mem_hl[0:511]</obj_property>
<obj_property name="ObjectShortName">cache_mem_hl[0:511]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/I_CACHE_INST/cache_mem_hh" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cache_mem_hh[0:511]</obj_property>
<obj_property name="ObjectShortName">cache_mem_hh[0:511]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">BUS UNIT</obj_property>
<obj_property name="DisplayName">label</obj_property>
339,10 → 1086,31
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/timeout_cnt" type="array" db_ref_id="1">
<obj_property name="ElementShortName">timeout_cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">timeout_cnt[15:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/arb_state" type="other" db_ref_id="1">
<obj_property name="ElementShortName">arb_state</obj_property>
<obj_property name="ObjectShortName">arb_state</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/io_access" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">io_access</obj_property>
<obj_property name="ObjectShortName">io_access</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/dc_miss_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dc_miss_i</obj_property>
<obj_property name="ObjectShortName">dc_miss_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/dc_dirty_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">dc_dirty_i</obj_property>
<obj_property name="ObjectShortName">dc_dirty_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/BUS_UNIT_INST/freeze_storm_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">freeze_storm_o</obj_property>
<obj_property name="ObjectShortName">freeze_storm_o</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">WISHBONE BUS</obj_property>
<obj_property name="DisplayName">label</obj_property>
388,8 → 1156,1322
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/wb_stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_stb_i</obj_property>
<obj_property name="ObjectShortName">wb_stb_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/wb_ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_ack_o</obj_property>
<obj_property name="ObjectShortName">wb_ack_o</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sim_mem[0:511]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0:511]</obj_property>
<obj_property name="ElementShortName">sim_mem[0:255]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0:255]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[0]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">sim_mem[0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">sim_mem[1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[2]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">sim_mem[2]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[3]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">sim_mem[3]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="ElementShortName">[226]</obj_property>
<obj_property name="ObjectShortName">sim_mem[226]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[227]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[227]</obj_property>
<obj_property name="ObjectShortName">sim_mem[227]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[228]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[228]</obj_property>
<obj_property name="ObjectShortName">sim_mem[228]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[229]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[229]</obj_property>
<obj_property name="ObjectShortName">sim_mem[229]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[230]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[230]</obj_property>
<obj_property name="ObjectShortName">sim_mem[230]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[231]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[231]</obj_property>
<obj_property name="ObjectShortName">sim_mem[231]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[232]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[232]</obj_property>
<obj_property name="ObjectShortName">sim_mem[232]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[233]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[233]</obj_property>
<obj_property name="ObjectShortName">sim_mem[233]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[234]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[234]</obj_property>
<obj_property name="ObjectShortName">sim_mem[234]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[235]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[235]</obj_property>
<obj_property name="ObjectShortName">sim_mem[235]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[236]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[236]</obj_property>
<obj_property name="ObjectShortName">sim_mem[236]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[237]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[237]</obj_property>
<obj_property name="ObjectShortName">sim_mem[237]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[238]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[238]</obj_property>
<obj_property name="ObjectShortName">sim_mem[238]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[239]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[239]</obj_property>
<obj_property name="ObjectShortName">sim_mem[239]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[240]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[240]</obj_property>
<obj_property name="ObjectShortName">sim_mem[240]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[241]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[241]</obj_property>
<obj_property name="ObjectShortName">sim_mem[241]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[242]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[242]</obj_property>
<obj_property name="ObjectShortName">sim_mem[242]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[243]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[243]</obj_property>
<obj_property name="ObjectShortName">sim_mem[243]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[244]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[244]</obj_property>
<obj_property name="ObjectShortName">sim_mem[244]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[245]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[245]</obj_property>
<obj_property name="ObjectShortName">sim_mem[245]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[246]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[246]</obj_property>
<obj_property name="ObjectShortName">sim_mem[246]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[247]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[247]</obj_property>
<obj_property name="ObjectShortName">sim_mem[247]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[248]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[248]</obj_property>
<obj_property name="ObjectShortName">sim_mem[248]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[249]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[249]</obj_property>
<obj_property name="ObjectShortName">sim_mem[249]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[250]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[250]</obj_property>
<obj_property name="ObjectShortName">sim_mem[250]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[251]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[251]</obj_property>
<obj_property name="ObjectShortName">sim_mem[251]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[252]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[252]</obj_property>
<obj_property name="ObjectShortName">sim_mem[252]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[253]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[253]</obj_property>
<obj_property name="ObjectShortName">sim_mem[253]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[254]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[254]</obj_property>
<obj_property name="ObjectShortName">sim_mem[254]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/INTERNAL_MEMORY/sim_mem[255]" type="array" db_ref_id="1">
<obj_property name="ElementShortName">[255]</obj_property>
<obj_property name="ObjectShortName">sim_mem[255]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">IO Controller</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">#3e3e3e</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/IO_CONTROLLER/wb_stb_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_stb_i</obj_property>
<obj_property name="ObjectShortName">wb_stb_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/IO_CONTROLLER/wb_ack_o" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wb_ack_o</obj_property>
<obj_property name="ObjectShortName">wb_ack_o</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/IO_CONTROLLER/io_o_sync" type="array" db_ref_id="1">
<obj_property name="ElementShortName">io_o_sync[31:0]</obj_property>
<obj_property name="ObjectShortName">io_o_sync[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/IO_CONTROLLER/io_o_sync" type="array" db_ref_id="1">
<obj_property name="ElementShortName">io_o_sync[31:0]</obj_property>
<obj_property name="ObjectShortName">io_o_sync[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>
/storm_core/software/C/build/storm_startup_code.S
129,10 → 129,12
ldr r1,=_etext // -> ROM data start
ldr r2,=_data // -> data start
ldr r3,=_edata // -> end of data
1: cmp r2,r3 // check if data to move
x01: cmp r2,r3 // check if data to move
beq y01
ldrlo r0,[r1],#4 // copy it
strlo r0,[r2],#4
blo 1b // loop until done
blo x01 // loop until done
y01:
#endif
// Clear .bss
// ----------
139,14 → 141,14
mov r0,#0 // get a zero
ldr r1,=__bss_start // -> bss start
ldr r2,=__bss_end__ // -> bss end
2: cmp r1,r2 // check if data to clear
beq leer
x02: cmp r1,r2 // check if data to clear
beq y02
strlo r0,[r1],#4 // clear 4 bytes
blo 2b // loop until done
 
blo x02 // loop until done
y02:
// Call main program: main(0)
// --------------------------
leer: mov r0,#0 // no arguments (argc = 0)
mov r0,#0 // no arguments (argc = 0)
mov r1,r0
mov r2,r0
mov fp,r0 // null frame pointer
/storm_core/software/C/storm_core.h
5,10 → 5,12
// storm_core.h - STORM Core internal definitions
//
// Created by Stephan Nolting (stnolting@googlemail.com)
// Last modified 22. Jan. 2012
// http://www.opencores.com/project,storm_core
// Last modified 15. Feb. 2012
////////////////////////////////////////////////////////////////////////////////
 
/* Internal System Coprocessor Register Set */
#define SYS_CP 15 // system coprocessor #
#define ID_REG_0 0 // ID register 0
#define ID_REG_1 1 // ID register 1
#define ID_REG_2 2 // ID register 2
22,21 → 24,24
#define TIME_COUNT 10 // Internal timer, counter
#define LFSR_POLY 11 // Internal LFSR, polynomial
#define LFSR_DATA 12 // Internal LFSR, shift register
#define SYS_IO 13 // System IO ports
 
/* CP_SYS_CTRL_0 */
#define FDC 0 // flush d-cache
#define CDC 1 // clear d-cache
#define CIC 2 // flush i-cache
#define CWT 3 // cache write-thru enable
#define RST 5 // force system reset
#define FRZ 6 // freeze processor until reset
#define TEN 7 // internal timer enable
#define TIE 8 // internal timer interrupt enable
#define TIM 9 // internal timer interrupt mode (0:IRQ/1:FIQ)
#define LFSRE 10 // LFSR enable
#define LFSRM 11 // LFSR update on 0:clock/1:access
#define LFSRD 12 // LFSR shift direction (0:R/1:L)
#define MBC_0 16 // max bus cycle length bit 0
#define MBC_15 31 // max bus cycle length bit 15
#define DC_FLUSH 0 // flush d-cache
#define DC_CLEAR 1 // clear d-cache
#define IC_CLEAR 2 // flush i-cache
#define DC_WTHRU 3 // cache write-thru enable
#define DC_AUTOPR 4 // auto pre-reload d-cache page
#define IC_AUTOPR 5 // auto pre-reload i-cache page
#define TIME_EN 10 // enable internal timer
#define TIME_INT 11 // int timer interrupt enable
#define TIME_M 12 // int timer interrupt mode
#define LFSR_EN 13 // enable lfsr
#define LFSR_M 14 // lfsr update mode
#define LFSR_D 15 // lfsr shift direction
#define MBC_0 16 // max bus cycle length bit 0
#define MBC_LSB 16
#define MBC_15 31 // max bus cycle length bit 15
#define MBC_MSB 31
 
#endif // storm_core_h
/storm_core/software/C/main.c
1,39 → 1,38
#include "storm_core.h"
 
//GPIO_OUT is a port-expander connected to the wishbone bus
#define REG32 (volatile unsigned int*)
#define GPIO_OUT (*(REG32 (0xFFFFE028)))
/*----------------------------------------
STORM Core Demo SoC Program
by Stephan Nolting
 
This program outputs the first 30
Fibonacci numbers on the IO.O port.
----------------------------------------*/
 
// simple delay function
static void delay(void)
{
static int i;
#define REG32 (volatile unsigned int*)
 
for (i=0; i<200001; i++)
{
asm volatile ("NOP");
}
}
/* ---- IO Device Locations ---- */
#define GPIO_OUT (*(REG32 (0xFFFFFE020)))
#define GPIO_IN (*(REG32 (0xFFFFFE024)))
 
 
// main program
int main(void)
{
int i;
int test_array[14] = {1,2,4,8,16,32,64,128,64,32,16,8,4,2};
int i, num_a, num_b, tmp;
 
GPIO_OUT = 0;
GPIO_OUT = 0; // clear output
 
while(1)
{
for(i=0; i<14; i++)
{
delay();
GPIO_OUT = test_array[i];
num_a = 0;
num_b = 1;
 
for(i=0; i<31; i++)
{
GPIO_OUT = num_a;
tmp = num_a + num_b;
num_a = num_b;
num_b = tmp;
}
}
 
return 0;
}
 

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