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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

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    from Rev 23 to Rev 24
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Rev 23 → Rev 24

/storm_core/trunk/rtl/REG_FILE.vhd
4,7 → 4,7
-- # 30x32-Bit Banked 1w3r Register File #
-- # (+ address translation unit) #
-- # *************************************************** #
-- # Last modified: 28.05.2011 #
-- # Last modified: 18.02.2012 #
-- #######################################################
 
library IEEE;
224,13 → 224,13
 
case (MODE_I) is
 
when User32_MODE =>
when User32_MODE | System32_MODE =>
REAL_REG_SEL(14 downto 08) := VIRT_REG_SEL(14 downto 08);
 
when FIQ32_MODE =>
REAL_REG_SEL(21 downto 15) := VIRT_REG_SEL(14 downto 08);
 
when Supervisor32_MODE | System32_MODE =>
when Supervisor32_MODE =>
REAL_REG_SEL(12 downto 08) := VIRT_REG_SEL(12 downto 08);
REAL_REG_SEL(23 downto 22) := VIRT_REG_SEL(14 downto 13);
 
/storm_core/trunk/rtl/STORM_TOP.vhd
68,6 → 68,7
WB_STB_O : out STD_LOGIC; -- valid transfer
WB_CYC_O : out STD_LOGIC; -- valid cycle
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_ERR_I : in STD_LOGIC; -- abnormal cycle termination
WB_HALT_I : in STD_LOGIC; -- halt request
 
-- ###############################################################################################
357,6 → 358,7
WB_STB_O => WB_STB_O, -- strobe
WB_DATA_I => WB_DATA_I, -- data
WB_ACK_I => WB_ACK_I, -- acknowledge
WB_ERR_I => WB_ERR_I, -- abnormal termination
WB_HALT_I => WB_HALT_I -- halt
);
 
/storm_core/trunk/rtl/BUS_UNIT.vhd
96,6 → 96,7
WB_STB_O : out STD_LOGIC; -- strobe
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_ERR_I : in STD_LOGIC; -- abnormal termination
WB_HALT_I : in STD_LOGIC -- halt
);
end BUS_UNIT;
125,6 → 126,7
-- Wishbone Syncs --
signal WB_DATA_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ACK_BUF : STD_LOGIC;
signal WB_ERR_BUF : STD_LOGIC;
signal VA_CYC_BUF, VA_CYC_BUF_NXT : STD_LOGIC;
signal WE_FLAG, WE_FLAG_NXT : STD_LOGIC;
 
193,6 → 195,7
TIMEOUT_CNT <= (others => '0');
WB_DATA_BUF <= (others => '0');
WB_ACK_BUF <= '0';
WB_ERR_BUF <= '0';
WE_FLAG <= '0';
VA_CYC_BUF <= '0';
IC_ADR_BUF <= (others => '0');
212,6 → 215,7
-- Wishbone Sync --
WB_DATA_BUF <= WB_DATA_I;
WB_ACK_BUF <= WB_ACK_I;
WB_ERR_BUF <= WB_ERR_I;
VA_CYC_BUF <= VA_CYC_BUF_NXT;
-- Address Buffer --
IC_ADR_BUF <= IC_ADR_BUF_NXT;
230,7 → 234,7
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, WE_FLAG,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, DC_DIRTY_I, DC_MISS_I, DC_BSA_I, DC_P_WE_I, DC_P_CS_I,
IC_ADR_BUF, IC_P_ADR_BUF, IC_MISS_I,
WB_ADR_BUF, WB_ACK_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
WB_ADR_BUF, WB_ACK_BUF, WB_ERR_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
variable IF_BASE_ADR_V, DF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
begin
--- Base Address Word Alignment ---
324,7 → 328,8
IC_CS_O <= '1';
IC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(IC_ADR_BUF) + 4); -- inc counter
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
354,7 → 359,8
DC_CS_O <= '1';
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc counter
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
377,7 → 383,8
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
DC_MSS_ACK_O <= '1'; -- ack of pseudo miss signal
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
409,7 → 416,8
if (DC_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc pointer
end if;
if (TIMEOUT_CNT >= C_BUS_CYCC_I) then
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack dirty signal
/storm_core/trunk/rtl/CORE_PKG.vhd
255,7 → 255,6
-- Collin Raye - I Can Still Feel You
-- Jason Aldean - She's Country
-- Kellie Pickler - Best Days Of Your Life
-- Rascal Flatts - Stand
-- Hunter Hayes - STORM Warning (lol, the core's theme xD)
-- Keith Urban - You Gonna Fly
-- Big And Rich - Lost In The Moment
266,6 → 265,8
-- Dixie Chicks - Ready To Run
-- Eagle-Eye Cherry - Skull Tattoo
-- Jake Owen - Barefoot Blue Jean Night
-- Keith Urban - You Gonna Fly
-- Miranda Lambert - Baggage Claim
 
-- INTERNAL MNEMONICS ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
626,6 → 627,7
WB_STB_O : out STD_LOGIC;
WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
WB_ACK_I : in STD_LOGIC;
WB_ERR_I : in STD_LOGIC;
WB_HALT_I : in STD_LOGIC
);
end component;
/storm_core/trunk/rtl/MC_SYS.vhd
492,7 → 492,7
if rising_edge(CLK_I) then
if (RST_I = '1') then
CP_REG_FILE <= (others => (others => '0')); -- clear all
CP_REG_FILE(CP_ID_REG_0) <= x"07DC020F"; -- core update date
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0214"; -- core update date
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;)
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length
/storm_core/trunk/doc/STORM CORE datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/sim/STORM_core_TB.vhd
1,9 → 1,9
-- #######################################################
-- # < STORM Core Processor by Stephan Nolting > #
-- # *************************************************** #
-- # STORM Core / STORM SoC Testbench #
-- # STORM Core / STORM Demo SoC Testbench #
-- # *************************************************** #
-- # Last modified: 16.02.2012 #
-- # Last modified: 21.02.2012 #
-- #######################################################
 
library IEEE;
15,7 → 15,7
 
architecture Structure of STORM_core_TB is
 
-- Memory Map ---------------------------------------------------------------------
-- Address Map --------------------------------------------------------------------
-- -----------------------------------------------------------------------------------
constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
constant INT_MEM_SIZE_C : natural := 1024; -- bytes
55,6 → 55,7
signal CORE_WB_STB_O : STD_LOGIC; -- valid transfer
signal CORE_WB_CYC_O : STD_LOGIC; -- valid cycle
signal CORE_WB_ACK_I : STD_LOGIC; -- acknowledge
signal CORE_WB_ERR_I : STD_LOGIC; -- abnormal termination
signal CORE_WB_HALT_I : STD_LOGIC; -- halt request
 
 
65,6 → 66,7
signal INT_MEM_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal INT_MEM_STB_I : STD_LOGIC;
signal INT_MEM_ACK_O : STD_LOGIC;
signal INT_MEM_ERR_O : STD_LOGIC;
signal INT_MEM_HALT_O : STD_LOGIC;
 
-- General Purpose IO Controller --
71,6 → 73,7
signal GP_IO_CTRL_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
signal GP_IO_CTRL_STB_I : STD_LOGIC;
signal GP_IO_CTRL_ACK_O : STD_LOGIC;
signal GP_IO_CTRL_ERR_O : STD_LOGIC;
signal GP_IO_CTRL_HALT_O : STD_LOGIC;
signal GP_IO_OUT_PORT : STD_LOGIC_VECTOR(31 downto 0);
signal GP_IO_IN_PORT : STD_LOGIC_VECTOR(31 downto 0);
119,6 → 122,7
WB_STB_O : out STD_LOGIC; -- valid transfer
WB_CYC_O : out STD_LOGIC; -- valid cycle
WB_ACK_I : in STD_LOGIC; -- acknowledge
WB_ERR_I : in STD_LOGIC; -- abnormal cycle termination
WB_HALT_I : in STD_LOGIC; -- halt request
 
-- Interrupt Request Lines --
148,7 → 152,8
WB_WE_I : in STD_LOGIC; -- write enable
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC -- throttle master
WB_HALT_O : out STD_LOGIC; -- throttle master
WB_ERR_O : out STD_LOGIC -- abnormal cycle termination
);
end component;
 
170,6 → 175,7
WB_STB_I : in STD_LOGIC; -- valid cycle
WB_ACK_O : out STD_LOGIC; -- acknowledge
WB_HALT_O : out STD_LOGIC; -- throttle master
WB_ERR_O : out STD_LOGIC; -- abnormal termination
 
-- IO Port --
GP_IO_O : out STD_LOGIC_VECTOR(31 downto 00);
232,6 → 238,7
WB_STB_O => CORE_WB_STB_O, -- valid transfer
WB_CYC_O => CORE_WB_CYC_O, -- valid cycle
WB_ACK_I => CORE_WB_ACK_I, -- acknowledge
WB_ERR_I => CORE_WB_ERR_I, -- abnormal cycle termination
WB_HALT_I => CORE_WB_HALT_I, -- halt request
 
-- Interrupt Request Lines --
281,6 → 288,15
'0';
 
 
-- Halt Terminal ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_ERR_I <= INT_MEM_ERR_O or
GP_IO_CTRL_ERR_O or
-- DUMMY0_ERR_O or
-- DUMMY1_ERR_O or
'0';
 
 
-- Valid Transfer Signal Terminal ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INT_MEM_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else '0';
313,6 → 329,7
WB_WE_I => CORE_WB_WE_O,
WB_STB_I => INT_MEM_STB_I,
WB_ACK_O => INT_MEM_ACK_O,
WB_ERR_O => INT_MEM_ERR_O,
WB_HALT_O => INT_MEM_HALT_O
);
 
335,6 → 352,7
WB_STB_I => GP_IO_CTRL_STB_I,
WB_ACK_O => GP_IO_CTRL_ACK_O,
WB_HALT_O => GP_IO_CTRL_HALT_O,
WB_ERR_O => GP_IO_CTRL_ERR_O,
 
-- IO Port --
GP_IO_O => GP_IO_OUT_PORT,
/storm_core/trunk/sim/Xilinx ISIM/storm_core_debug_wave.wcfg
24,10 → 24,6
<obj_property name="ElementShortName">core_clk_i</obj_property>
<obj_property name="ObjectShortName">core_clk_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/bus_clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">bus_clk_i</obj_property>
<obj_property name="ObjectShortName">bus_clk_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/STORM_TOP_INST/PROCESSOR_CORE/halt" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">halt</obj_property>
<obj_property name="ObjectShortName">halt</obj_property>
1149,6 → 1145,10
<obj_property name="ElementShortName">core_wb_halt_i</obj_property>
<obj_property name="ObjectShortName">core_wb_halt_i</obj_property>
</wvobject>
<wvobject fp_name="/storm_core_tb/core_wb_err_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">core_wb_err_i</obj_property>
<obj_property name="ObjectShortName">core_wb_err_i</obj_property>
</wvobject>
<wvobject fp_name="divider7" type="divider">
<obj_property name="label">INTERNAL MEMORY</obj_property>
<obj_property name="DisplayName">label</obj_property>

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