URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/storm_core/trunk/rtl/CACHE.vhd
9,7 → 9,7
-- # A cache line contains a complete word (32-bit). # |
-- # The cache is fully associative. # |
-- # *************************************************** # |
-- # Last modified: 15.02.2012 # |
-- # Last modified: 24.02.2012 # |
-- ####################################################### |
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library IEEE; |
79,6 → 79,9
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architecture Behavioral of CACHE is |
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-- Is Simulation? -- |
constant IS_SIM : boolean := FALSE; |
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-- Cache Arbiter -- |
type ARB_STATE_TYPE is (STORM_ACCESS, MISS_STATE, IO_REQUEST, IO_PIPE_RESYNC, IO_PIPE_RESYNC_END, DIRTY_STATE, PIPE_RESYNC); |
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE; |
172,7 → 175,7
PAGE_SELECT_FF <= (others => '0'); |
UPDATE_HIST_FF <= '0'; |
else |
PAGE_SELECT_FF <= PAGE_SELECT_FF; |
PAGE_SELECT_FF <= PAGE_SELECT; |
UPDATE_HIST_FF <= UPDATE_HISTORY; |
end if; |
end if; |
424,7 → 427,7
---------------------------------------------------------------- |
C_DIRTY_O <= '1'; |
if (C_WTHRU_I = '1') then |
B_BASE_O_SEL <= PAGE_SELECT; |
B_BASE_O_SEL <= PAGE_TRANSLATE; |
end if; |
ADR_INT <= B_ADR_I; |
DQ_INT <= DQ_WORD; |
529,7 → 532,7
-- Dummy for simulation -- |
GEN_DEBUG_MEM: |
for i in 0 to (CACHE_PAGES*PAGE_SIZE)-1 generate |
SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i); |
SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i) when (IS_SIM = TRUE) else x"00000000"; |
end generate; |
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