URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 25 to Rev 26
- ↔ Reverse comparison
Rev 25 → Rev 26
/storm_core/trunk/rtl/WB_UNIT.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Data Write Back Selector & MEM Read Input # |
-- # *************************************************** # |
-- # Last modified: 05.10.2011 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
192,12 → 192,16
-- Data Write Back Enabled -- |
WB_FW_O(FWD_WB) <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_WB_EN); |
-- Mode bits modification -- |
WB_FW_O(FWD_MCR_MOD) <= '0'; -- not needed here |
WB_FW_O(FWD_MCR_MOD) <= '0'; -- not needed here |
-- Flag bits modification -- |
WB_FW_O(FWD_FLAG_MOD) <= '0'; -- not needed here |
WB_FW_O(FWD_FLAG_MOD) <= '0'; -- not needed here |
-- MCR Read Access -- |
WB_FW_O(FWD_MCR_R_ACC) <= '0'; -- not needed here |
-- Memory Read Access -- |
WB_FW_O(FWD_MEM_R_ACC) <= '0'; -- not needed here |
-- Memory-Pc Load -- |
WB_FW_O(FWD_MEM_PC_LD) <= '0'; -- not needed here |
|
|
|
end Structure; |
/storm_core/trunk/rtl/MS_UNIT.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Multiply/Shift Unit # |
-- # *************************************************** # |
-- # Last modified: 05.10.2011 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
157,6 → 157,9
-- Memory Read Access -- |
MSU_FW_O(FWD_MEM_R_ACC) <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_MEM_ACC) and (not CTRL_I(CTRL_MEM_RW)); |
|
-- Memory-Pc Load -- |
MSU_FW_O(FWD_MEM_PC_LD) <= '1' when (CTRL_I(CTRL_RD_3 downto CTRL_RD_0) = C_PC_ADR) and (CTRL_I(CTRL_EN) = '1') and (CTRL_I(CTRL_MEM_ACC) = '1') and (CTRL_I(CTRL_MEM_RW) = '0') else '0'; |
|
|
|
end Structural; |
/storm_core/trunk/rtl/ALU.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Arithmetical/Logical/MCR_Access Unit # |
-- # *************************************************** # |
-- # Last modified: 05.10.2011 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
257,6 → 257,8
ALU_FW_O(FWD_MCR_R_ACC) <= CTRL_I(CTRL_EN) and ((CTRL_I(CTRL_MREG_ACC) and (not CTRL_I(CTRL_MREG_RW))) or (CTRL_I(CTRL_CP_ACC) and (not CTRL_I(CTRL_CP_RW)))); |
-- Memory Read Access -- |
ALU_FW_O(FWD_MEM_R_ACC) <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_MEM_ACC) and (not CTRL_I(CTRL_MEM_RW)); |
-- Memory-Pc Load -- |
ALU_FW_O(FWD_MEM_PC_LD) <= '0'; -- not needed here |
|
|
|
/storm_core/trunk/rtl/OPERAND_UNIT.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Operand Fetch & Data Dependency Detector # |
-- # *************************************************** # |
-- # Last modified: 03.12.2011 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
206,7 → 206,8
|
elsif ((MSU_MATCH = '1') and (MSU_FW_I(FWD_MCR_R_ACC) = '1')) or -- Data dependency OF <-> MA (MCR access) |
((ALU_MATCH = '1') and (ALU_FW_I(FWD_MEM_R_ACC) = '1')) or -- Data dependency OF <-> WB (mem read) from EX |
(MSU_FW_I(FWD_MCR_MOD) = '1') then |
(MSU_FW_I(FWD_MEM_PC_LD) = '1') or -- we're loading the pc from memory |
(MSU_FW_I(FWD_MCR_MOD) = '1') then -- mcr may get modified |
HOLD_BUS_O(2 downto 1) <= "01"; -- 2 cycles |
HOLD_BUS_O(0) <= '1'; -- enable |
|
/storm_core/trunk/rtl/BUS_UNIT.vhd
9,7 → 9,7
-- # Note: I-Cache is read-only for the processor and # |
-- # write-only for the bus unit. # |
-- # ************************************************** # |
-- # Last modified: 15.02.2012 # |
-- # Last modified: 01.03.2012 # |
-- ###################################################### |
|
library IEEE; |
281,12 → 281,7
------------------------------------------------------------------------------- |
IC_ADR_BUF_NXT <= IF_BASE_ADR_V; |
DC_ADR_BUF_NXT <= DF_BASE_ADR_V; |
if (IO_ACCESS = '1') and (DC_P_CS_I = '1') then -- IO access |
ARB_STATE_NXT <= IO_REQUEST; |
FREEZE_FLAG_NXT <= '1'; |
WB_ADR_BUF_NXT <= DC_P_ADR_I; |
WE_FLAG_NXT <= DC_P_WE_I; |
elsif (IC_MISS_I = '1') then -- i-cache miss -> reload cache page |
if (IC_MISS_I = '1') then -- i-cache miss -> reload cache page |
ARB_STATE_NXT <= DOWNLOAD_I_PAGE; |
FREEZE_FLAG_NXT <= '1'; |
WB_ADR_BUF_NXT <= IF_BASE_ADR_V; |
298,6 → 293,11
WB_ADR_BUF_NXT <= DF_BASE_ADR_V; |
BASE_BUF_NXT <= DF_BASE_ADR_V; |
WE_FLAG_NXT <= '0'; -- bus read |
elsif (IO_ACCESS = '1') and (DC_P_CS_I = '1') then -- IO access |
ARB_STATE_NXT <= IO_REQUEST; |
FREEZE_FLAG_NXT <= '1'; |
WB_ADR_BUF_NXT <= DC_P_ADR_I; |
WE_FLAG_NXT <= DC_P_WE_I; |
elsif (DC_DIRTY_I = '1') then -- d-cache modification -> copy page to main memory |
DC_ADR_BUF_NXT <= DC_BSA_I; |
WB_ADR_BUF_NXT <= DC_BSA_I; |
/storm_core/trunk/rtl/CORE.vhd
21,7 → 21,7
-- # | -> stnolting@googlemail.com # |
-- # | -> stnolting@web.de # |
-- # *************************************************************************************************** # |
-- # Last modified: 08.02.2012 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################################################################### |
|
library IEEE; |
158,6 → 158,7
signal MCR_STOP_IF : STD_LOGIC; -- stop instruction fetch |
signal PIPE_EMPTY : STD_LOGIC; -- pipeline is empty |
signal D_MEM_MODE : STD_LOGIC_VECTOR(04 downto 0); -- mode for data mem access |
signal PC_INJECT : STD_LOGIC; -- load pc with data from wb stage |
|
begin |
-- Global CLOCK, RESET and HALT Networks ----------------------------------------------------- |
199,6 → 200,7
STOP_IF_I => MCR_STOP_IF, -- stop new instruction fetch |
HOLD_BUS_I => HALT_BUS, -- number of bubbles |
EMPTY_PIPE_O => PIPE_EMPTY, -- pipeline is empty |
PC_INJECT_O => PC_INJECT, -- pc load from memory |
OP_ADR_O => OP_ADR, -- operand register addresses |
IMM_O => IMMEDIATE, -- immediate output |
OF_CTRL_O => OF_CTRL, -- stage control OF |
233,6 → 235,8
INF_PC_O => INF_PC, -- PC value for instruction fetch |
MCR_DATA_I => MCR_DTA_WR, -- mcr write data input |
MCR_DATA_O => MCR_DTA_RD, -- mcr read data output |
PC_INJECT_I => PC_INJECT, -- pc load from memory |
PC_INJECT_D_I => WB_DATA_LINE, -- write back data |
EX_FIQ_I => FIQ, -- external fast interrupt request |
EX_IRQ_I => IRQ, -- external interrupt request |
EX_DAB_I => D_CACHE_ABORT, -- external D memory abort request |
/storm_core/trunk/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and # |
-- # system parameters for the STORM Core processor. # |
-- # +-------------------------------------------------+ # |
-- # Last modified: 15.02.2012 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
67,7 → 67,8
constant FWD_FLAG_MOD : natural := 38; -- sreg flags will be modified |
constant FWD_MCR_R_ACC : natural := 39; -- MCR Read Access |
constant FWD_MEM_R_ACC : natural := 40; -- Memory Read Access |
constant FWD_MSB : natural := 40; -- width of forwarding bus |
constant FWD_MEM_PC_LD : natural := 41; -- pc load from memory |
constant FWD_MSB : natural := 41; -- width of forwarding bus |
|
-- CTRL BUS LOCATIONS --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
165,8 → 166,7
constant CP_SYS_CTRL_0 : natural := 6; -- system control register 0 |
constant CP_SYS_CTRL_1 : natural := 7; -- system control register 1 |
constant CP_CSTAT : natural := 8; -- cache statistics register |
constant CP_TIME_THRES : natural := 9; -- Internal timer, threshold value |
constant CP_TIME_COUNT : natural := 10; -- Internal timer, counter |
|
constant CP_LFSR_POLY : natural := 11; -- Internal lfsr, polynomial |
constant CP_LFSR_DATA : natural := 12; -- Internal lfsr, shift register |
constant CP_IO_PORT : natural := 13; -- Internal IO port |
188,9 → 188,6
constant CSCR0_IAR : natural := 5; -- auto pre-refresh i-cache for new access |
constant CSCR0_CIO : natural := 6; -- enable cached IO |
|
constant CSCR0_TEN : natural := 10; -- internal timer enable |
constant CSCR0_TIE : natural := 11; -- internal timer interrupt enable |
constant CSCR0_TIM : natural := 12; -- internal timer interrupt mode (0:IRQ/1:FIQ) |
constant CSCR0_LFSRE : natural := 13; -- internal LFSR enable |
constant CSCR0_LFSRM : natural := 14; -- internal LFSR update mode (0:auto/1:access) |
constant CSCR0_LFSRD : natural := 15; -- internal LFSR direction (0:right/1:left)) |
254,7 → 251,6
-- Dixie Chicks - Wide Open Spaces |
-- Collin Raye - I Can Still Feel You |
-- Jason Aldean - She's Country |
-- Kellie Pickler - Best Days Of Your Life |
-- Hunter Hayes - STORM Warning (lol, the core's theme xD) |
-- Keith Urban - You Gonna Fly |
-- Big And Rich - Lost In The Moment |
267,6 → 263,7
-- Jake Owen - Barefoot Blue Jean Night |
-- Keith Urban - You Gonna Fly |
-- Miranda Lambert - Baggage Claim |
-- Diamond Rio - Meet In The Middle |
|
-- INTERNAL MNEMONICS --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
317,6 → 314,8
INF_PC_O : out STD_LOGIC_VECTOR(31 downto 0); |
MCR_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); |
MCR_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); |
PC_INJECT_I : in STD_LOGIC; |
PC_INJECT_D_I : in STD_LOGIC_VECTOR(31 downto 0); |
EX_FIQ_I : in STD_LOGIC; |
EX_IRQ_I : in STD_LOGIC; |
EX_DAB_I : in STD_LOGIC; |
435,6 → 434,7
STOP_IF_I : in STD_LOGIC; |
HOLD_BUS_I : in STD_LOGIC_VECTOR(02 downto 0); |
EMPTY_PIPE_O : out STD_LOGIC; |
PC_INJECT_O : out STD_LOGIC; |
OP_ADR_O : out STD_LOGIC_VECTOR(14 downto 0); |
IMM_O : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); |
OF_CTRL_O : out STD_LOGIC_VECTOR(CTRL_MSB downto 0); |
/storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Load/Store Unit for Data Memory Access # |
-- # *************************************************** # |
-- # Last modified: 25.01.2012 # |
-- # Last modified: 02.03.2012 # |
-- ####################################################### |
|
library IEEE; |
58,7 → 58,7
); |
end LOAD_STORE_UNIT; |
|
architecture LOAD_STORE_UNIT_STRUCTURE of LOAD_STORE_UNIT is |
architecture Structure of LOAD_STORE_UNIT is |
|
-- Pipeline Regs -- |
signal DATA_BUFFER : STD_LOGIC_VECTOR(31 downto 0); |
89,8 → 89,6
|
-- Address Output -- |
ADR_O <= ADR_BUFFER; |
|
-- Data MEM Address -- |
XMEM_ADR_O <= ADR_BUFFER; |
|
|
97,6 → 95,7
|
-- Bypass Multiplexer --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
|
-- bypass multiplexer for link operations -- |
BP_O <= LNK_PC_I when (CTRL_I(CTRL_LINK) = '1') else DATA_BUFFER; |
-- Memory Write Data -- |
104,9 → 103,9
|
|
|
|
-- Forwarding Path ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
|
-- Forwarding Data-- |
LDST_FW_O(FWD_DATA_MSB downto FWD_DATA_LSB) <= BP_TEMP; |
-- Destination Register -- |
121,7 → 120,8
LDST_FW_O(FWD_MCR_R_ACC) <= '0'; -- not needed here |
-- Memory Read Access -- |
LDST_FW_O(FWD_MEM_R_ACC) <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_MEM_ACC) and (not CTRL_I(CTRL_MEM_RW)); |
|
-- Memory-Pc Load -- |
LDST_FW_O(FWD_MEM_PC_LD) <= '0'; -- not needed here |
|
|
|
159,8 → 159,7
|
--- Mode for MEM access -- |
XMEM_MODE_O <= MODE_I; -- current processor mode |
|
end process MEM_DATA_INTERFACE; |
|
|
end LOAD_STORE_UNIT_STRUCTURE; |
end Structure; |
/storm_core/trunk/rtl/FLOW_CTRL.vhd
27,7 → 27,7
-- ## Instruction Interface ## |
-- ############################################################################################### |
|
INSTR_I : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); -- instr memory input |
INSTR_I : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); -- instr cache data input |
INST_MREQ_O : out STD_LOGIC; -- automatic instruction fetch memory request |
|
-- ############################################################################################### |
43,12 → 43,13
-- ## Extended Control ## |
-- ############################################################################################### |
|
PC_HALT_O : out STD_LOGIC; |
SREG_I : in STD_LOGIC_VECTOR(31 downto 0); |
EXECUTE_INT_I : in STD_LOGIC; |
STOP_IF_I : in STD_LOGIC; |
HOLD_BUS_I : in STD_LOGIC_VECTOR(02 downto 0); |
EMPTY_PIPE_O : out STD_LOGIC; |
PC_HALT_O : out STD_LOGIC; -- freeze program counter |
SREG_I : in STD_LOGIC_VECTOR(31 downto 0); -- current machine status reg |
EXECUTE_INT_I : in STD_LOGIC; -- interrupt |
STOP_IF_I : in STD_LOGIC; -- freeze instruction fetch |
HOLD_BUS_I : in STD_LOGIC_VECTOR(02 downto 0); -- bubble insert |
EMPTY_PIPE_O : out STD_LOGIC; -- pipeline is empty |
PC_INJECT_O : out STD_LOGIC; -- pc load from memory |
|
-- ############################################################################################### |
-- ## Pipeline Stage Control ## |
90,6 → 91,7
signal IF_CYCLE_MOD : STD_LOGIC; |
signal IF_CYCLE_MOD_NXT : STD_LOGIC; |
signal BRANCH_TAKEN : STD_LOGIC; |
signal PC_INJECT : STD_LOGIC; |
signal WR_IR_EN : STD_LOGIC; |
signal IR_HALT : STD_LOGIC; |
signal CTRL_REG_HALT : STD_LOGIC; |
381,8 → 383,9
|
-- Detector for automatic/manual branches ---------------------------------------------------- |
-- ---------------------------------------------------------------------------------------------- |
BRANCH_DETECTOR: process(EX1_CTRL, VALID_INSTR) |
BRANCH_DETECTOR: process(EX1_CTRL, VALID_INSTR, WB_CTRL) |
variable manual_branch_v : std_logic; |
variable pc_injector_v : std_logic; |
begin |
-- Manual Branch when R_Dest = PC -- |
manual_branch_v := '0'; |
389,8 → 392,18
if (EX1_CTRL(CTRL_RD_3 downto CTRL_RD_0) = C_PC_ADR) and (EX1_CTRL(CTRL_WB_EN) = '1') then |
manual_branch_v := '1'; |
end if; |
|
-- Loading PC from Memory -- |
pc_injector_v := '0'; |
if (WB_CTRL(CTRL_RD_3 downto CTRL_RD_0) = C_PC_ADR) and (WB_CTRL(CTRL_EN) = '1') and |
(WB_CTRL(CTRL_MEM_ACC) = '1') and (WB_CTRL(CTRL_MEM_RW) = '0') then |
pc_injector_v := '1'; |
end if; |
PC_INJECT_O <= pc_injector_v; |
|
-- Branch Taken Signal -- |
BRANCH_TAKEN <= VALID_INSTR and (EX1_CTRL(CTRL_BRANCH) or manual_branch_v); |
BRANCH_TAKEN <= (VALID_INSTR and (EX1_CTRL(CTRL_BRANCH) or manual_branch_v) and |
(not EX1_CTRL(CTRL_MEM_ACC))) or pc_injector_v; |
end process BRANCH_DETECTOR; |
|
|
/storm_core/trunk/rtl/MC_SYS.vhd
53,6 → 53,9
MCR_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- mcr data input |
MCR_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- mcr data output |
|
PC_INJECT_I : in STD_LOGIC; -- pc load from memory |
PC_INJECT_D_I : in STD_LOGIC_VECTOR(31 downto 0); -- write back data |
|
-- ############################################################################################### |
-- ## External Interrupt Lines ## |
-- ############################################################################################### |
158,45 → 161,30
end if; |
end process EXT_INT_SYNC_REG; |
|
EXT_INT_SYNC: process(CLK_I, CP_REG_FILE(CP_SYS_CTRL_0), CP_IRQ, EX_FIQ_I, EX_IRQ_I) |
variable fiq_int_v, irq_int_v : std_logic; |
EXT_INT_SYNC: process(CLK_I) |
begin |
-- switch for internal cp interrupts -- |
if (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_TIE) = '1') then |
if (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_TIM) = '0') then |
fiq_int_v := EX_FIQ_I; |
irq_int_v := CP_IRQ; |
else |
fiq_int_v := CP_IRQ; |
irq_int_v := EX_IRQ_I; |
end if; |
else |
fiq_int_v := EX_FIQ_I; |
irq_int_v := EX_IRQ_I; |
end if; |
|
-- IRQ REQ Buffer -- |
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
EXT_INT_REQ_SYNC <= (others => '0'); |
else |
-- Fast Interrupt Request -- |
-- Fast Interrupt Request (FIQ) -- |
if (FIQ_TAKEN = '1') then |
EXT_INT_REQ_SYNC(0) <= '0'; |
elsif (fiq_int_v = '1') and (MCR_CMSR(SREG_FIQ_DIS) = '0') then |
elsif (EX_FIQ_I = '1') and (MCR_CMSR(SREG_FIQ_DIS) = '0') then |
EXT_INT_REQ_SYNC(0) <= '1'; |
elsif (MCR_CMSR(SREG_FIQ_DIS) = '0') then |
EXT_INT_REQ_SYNC(0) <= '0'; |
end if; |
-- Interrupt Request -- |
-- Normal Interrupt Request (IRQ) -- |
if (IRQ_TAKEN = '1') then |
EXT_INT_REQ_SYNC(1) <= '0'; |
elsif (irq_int_v = '1') and (MCR_CMSR(SREG_IRQ_DIS) = '0') then |
elsif (EX_IRQ_I = '1') and (MCR_CMSR(SREG_IRQ_DIS) = '0') then |
EXT_INT_REQ_SYNC(1) <= '1'; |
elsif (MCR_CMSR(SREG_IRQ_DIS) = '0') then |
EXT_INT_REQ_SYNC(1) <= '0'; |
end if; |
-- Data Fetch Abort Request -- |
-- Data Fetch Abort Request (DAB) -- |
if (DAB_TAKEN = '1') then |
EXT_INT_REQ_SYNC(2) <= '0'; |
elsif (EX_DAB_I = '1') and (MCR_CMSR(SREG_DAB_DIS) = '0') then |
204,7 → 192,7
elsif (MCR_CMSR(SREG_DAB_DIS) = '0') then |
EXT_INT_REQ_SYNC(2) <= '0'; |
end if; |
-- Instruction Fetch Abort Request -- |
-- Instruction Fetch Abort Request (IAB) -- |
if (IAB_TAKEN = '1') then |
EXT_INT_REQ_SYNC(3) <= '0'; |
elsif (EX_IAB_I = '1') and (MCR_CMSR(SREG_IAB_DIS) = '0') then |
311,7 → 299,7
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Undefined32_MODE; |
NEW_MODE <= Undefined32_MODE; |
|
--- Priority 6: Software I nterrupt --- |
--- Priority 6: Software Interrupt --- |
elsif (SWI_TAKEN = '1') then |
INT_VEC <= SWI_INT_VEC; |
FLAG_BUS(SREG_MODE_4 downto SREG_MODE_0) <= Supervisor32_MODE; |
368,6 → 356,8
---- PROGRAM COUNTER --------------------------------------------------------------- |
if (CONT_EXE = '1') then -- load PC with interrupt vector |
MCR_PC <= x"000000" & "000" & INT_VEC; |
elsif (PC_INJECT_I = '1') then -- load pc from memory |
MCR_PC <= PC_INJECT_D_I; |
elsif (CTRL_I(CTRL_BRANCH) = '1') then -- taken branch |
MCR_PC <= MCR_DATA_I; |
elsif (HALT_I = '0') then -- no hold request -> normal operation |
492,7 → 482,7
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
CP_REG_FILE <= (others => (others => '0')); -- clear all |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0214"; -- core update date |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0301"; -- core update date |
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID |
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;) |
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length |
519,20 → 509,6
CP_REG_FILE(CP_CSTAT)(31 downto 16) <= Std_Logic_Vector(unsigned(CP_REG_FILE(CP_CSTAT)(31 downto 16)) + 1); |
end if; |
|
-- Internal Timer: Threshold Value -------------------------------------------- |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_TIME_THRES) then |
CP_REG_FILE(CP_TIME_THRES) <= MCR_DATA_I; |
end if; |
|
-- Internal Timer: Counter Register ------------------------------------------- |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_TIME_COUNT) then |
CP_REG_FILE(CP_TIME_COUNT) <= MCR_DATA_I; |
elsif (CP_REG_FILE(CP_TIME_COUNT) = CP_REG_FILE(CP_TIME_THRES)) then -- match |
CP_REG_FILE(CP_TIME_COUNT) <= (others => '0'); |
elsif (CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_TEN) = '1') then -- timer enable |
CP_REG_FILE(CP_TIME_COUNT) <= Std_Logic_Vector(unsigned(CP_REG_FILE(CP_TIME_COUNT)) + 1); |
end if; |
|
-- Internal LFSR:: Polynomial Register ---------------------------------------- |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_LFSR_POLY) then |
CP_REG_FILE(CP_LFSR_POLY) <= MCR_DATA_I; |
554,7 → 530,7
|
-- Internal IO Register ------------------------------------------- |
CP_REG_FILE(CP_IO_PORT)(CP_IO_I_MSB downto CP_IO_I_LSB) <= IO_PORT_I; |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_TIME_COUNT) then |
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_IO_PORT) then |
CP_REG_FILE(CP_IO_PORT)(CP_IO_O_MSB downto CP_IO_O_LSB) <= MCR_DATA_I(CP_IO_O_MSB downto CP_IO_O_LSB); |
end if; |
|
573,22 → 549,6
BUS_CYCC_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0); |
IO_PORT_O <= CP_REG_FILE(CP_IO_PORT)(CP_IO_O_MSB downto CP_IO_O_LSB); |
|
--- Internal Timer Interrupt --- |
INT_TIMER_IRQ: process(CLK_I) |
begin |
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
CP_IRQ <= '0'; |
elsif (CP_REG_FILE(CP_TIME_COUNT) = CP_REG_FILE(CP_TIME_THRES)) and |
(CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_TEN) = '1') and |
(CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_TIE) = '1') then |
CP_IRQ <= '1'; |
else |
CP_IRQ <= '0'; |
end if; |
end if; |
end process INT_TIMER_IRQ; |
|
--- Internal LFSR XOR --- |
LFSR_UPDATE: process(CP_REG_FILE) |
variable lfsr_tmp_v : std_logic_vector(31 downto 0); |
/storm_core/trunk/doc/STORM CORE datasheet.pdf
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