OpenCores
URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/storm_core/trunk/rtl/CACHE.vhd
9,7 → 9,7
-- # A cache line contains a complete word (32-bit). #
-- # The cache is fully associative. #
-- # *************************************************** #
-- # Last modified: 24.02.2012 #
-- # Last modified: 08.03.2012 #
-- #######################################################
 
library IEEE;
54,11 → 54,13
-- ################################################################################################################
 
B_CS_I : in STD_LOGIC; -- bus unit request
B_P_SEL_I : in STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0); -- bus unit page select
B_D_SEL_O : out STD_LOGIC; -- selected dirty bit
B_A_SEL_O : out STD_LOGIC_VECTOR(31 downto 0); -- selected base adr
B_ADR_I : in STD_LOGIC_VECTOR(31 downto 0); -- address input
B_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data input
B_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data output
B_WE_I : in STD_LOGIC; -- write enable
B_BSA_O : out STD_LOGIC_VECTOR(31 downto 0); -- base adr of selected page
B_DRT_ACK_I : in STD_LOGIC; -- dirty acknowledged
B_MSS_ACK_I : in STD_LOGIC; -- miss acknowledged
B_IO_ACC_I : in STD_LOGIC; -- IO access
73,7 → 75,8
C_MISS_O : out STD_LOGIC; -- cache miss access
C_HIT_O : out STD_LOGIC; -- cache hit access
C_DIRTY_O : out STD_LOGIC; -- cache modified
C_WTHRU_I : in STD_LOGIC -- write through
C_WTHRU_I : in STD_LOGIC; -- write through
C_SYNC_O : out STD_LOGIC -- cache is sync to mem/io
);
end CACHE;
 
80,7 → 83,7
architecture Behavioral of CACHE is
 
-- Is Simulation? --
constant IS_SIM : boolean := FALSE;
constant IS_SIM : boolean := TRUE;
 
-- Cache Arbiter --
type ARB_STATE_TYPE is (STORM_ACCESS, MISS_STATE, IO_REQUEST, IO_PIPE_RESYNC, IO_PIPE_RESYNC_END, DIRTY_STATE, PIPE_RESYNC);
154,14 → 157,16
for i in 0 to CACHE_PAGES-1 loop
PAGE_BASE_ADR(i) <= (others => '0');
end loop;
elsif (SET_NEW_BAS = '1') then
PAGE_BASE_ADR(to_integer(unsigned(NEW_ENTRY_PAGE))) <= ADR_INT(31 downto LOG2_PAGE_SIZE+2);
else
if (SET_NEW_BAS = '1') then
PAGE_BASE_ADR(to_integer(unsigned(NEW_ENTRY_PAGE))) <= ADR_INT(31 downto LOG2_PAGE_SIZE+2);
end if;
end if;
end if;
 
-- Base ADR output for bus unit --
B_BSA_O <= (others => '0');
B_BSA_O(31 downto LOG2_PAGE_SIZE+2) <= PAGE_BASE_ADR(to_integer(unsigned(B_BASE_O_SEL)));
B_A_SEL_O <= (others => '0');
B_A_SEL_O(31 downto LOG2_PAGE_SIZE+2) <= PAGE_BASE_ADR(to_integer(unsigned(B_P_SEL_I)));
end process PAGE_ADR_SYS;
 
 
201,16 → 206,18
for i in 0 to CACHE_PAGES-1 loop
HIST_MEM(i) <= std_logic_vector(to_unsigned(i, LOG2_CACHE_PAGES));
end loop;
elsif (UPDATE_HIST_FF = '1') then
for i in 0 to CACHE_PAGES-1 loop
if (hist_mem_ce_v(CACHE_PAGES-1-i) = '1') then
if (i = CACHE_PAGES-1) then
HIST_MEM(CACHE_PAGES-1-i) <= PAGE_SELECT_FF;
else
HIST_MEM(CACHE_PAGES-1-i) <= HIST_MEM(CACHE_PAGES-1-i-1);
else
if (UPDATE_HIST_FF = '1') then
for i in 0 to CACHE_PAGES-1 loop
if (hist_mem_ce_v(CACHE_PAGES-1-i) = '1') then
if (i = CACHE_PAGES-1) then
HIST_MEM(CACHE_PAGES-1-i) <= PAGE_SELECT_FF;
else
HIST_MEM(CACHE_PAGES-1-i) <= HIST_MEM(CACHE_PAGES-1-i-1);
end if;
end if;
end if;
end loop;
end loop;
end if;
end if;
end if;
end process CACHE_ACCESS_HISTORY;
227,10 → 234,12
for i in 0 to CACHE_PAGES-1 loop
VALID_FLAG(i) <= '0';
end loop;
elsif (CLR_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
else
if (CLR_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_VAL = '1') then
VALID_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
end if;
end if;
end if;
end process PAGE_VALID_SYS;
240,7 → 249,8
-- Page Modification Flag ------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
DIRTY_REG: process(CORE_CLK_I, DIRTY_FLAG, VALID_FLAG)
variable temp_v : std_logic;
variable temp1_v : std_logic;
variable temp2_v : std_logic;
begin
-- Sync update --
if rising_edge(CORE_CLK_I) then
248,29 → 258,41
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '0';
end loop;
elsif (SET_ALL_DRT = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '1';
end loop;
else
if (CLR_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
if (SET_ALL_DRT = '1') then
for i in 0 to CACHE_PAGES-1 loop
DIRTY_FLAG(i) <= '1';
end loop;
else
if (CLR_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '0';
elsif (SET_CUR_DRT = '1') then
DIRTY_FLAG(to_integer(unsigned(PAGE_SELECT))) <= '1';
end if;
end if;
end if;
end if;
 
-- Any dirty bits? --
temp_v := '0';
temp1_v := '0';
for i in 0 to CACHE_PAGES-1 loop
temp_v := temp_v or (DIRTY_FLAG(i) and VALID_FLAG(i));
temp1_v := temp1_v or (DIRTY_FLAG(i) and VALID_FLAG(i));
end loop;
CACHE_DIRTY <= temp_v;
CACHE_DIRTY <= temp1_v;
 
-- Cache sync? --
temp2_v := '1';
for i in 0 to CACHE_PAGES-1 loop
temp2_v := temp2_v and (DIRTY_FLAG(i) nand VALID_FLAG(i));
end loop;
C_SYNC_O <= temp2_v;
end process DIRTY_REG;
 
--- Bus Unit Single Dirty Flag Output ---
B_D_SEL_O <= DIRTY_FLAG(to_integer(unsigned(B_P_SEL_I))) and VALID_FLAG(to_integer(unsigned(B_P_SEL_I)));
 
 
 
-- HIT / MISS Detector ---------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CONTENT_DETECTOR: process(ADR_INT, PAGE_BASE_ADR, VALID_FLAG, P_CS_I)
314,7 → 336,7
 
 
 
CACHE_ARBITER: process(ARB_STATE, HIST_MEM, PAGE_TRANSLATE, ADR_BUF, DAT_BUF, HST_BUF, BIT_BUF, CACHE_R_DATA, DIRTY_FLAG,
CACHE_ARBITER: process(ARB_STATE, HIST_MEM, PAGE_TRANSLATE, ADR_BUF, DAT_BUF, HST_BUF, BIT_BUF, CACHE_R_DATA, DIRTY_FLAG, VALID_FLAG,
CACHE_MISS, CACHE_DIRTY, C_FRESH_I, C_CLEAR_I, C_FLUSH_I, CACHE_HIT, C_WTHRU_I,
P_ADR_I, P_DATA_I, P_CS_I, P_WE_I, P_DQ_I,
B_ADR_I, B_DATA_I, B_CS_I, B_WE_I, B_IO_ACC_I, B_MSS_ACK_I, B_DRT_ACK_I)
375,7 → 397,8
ADR_BUF_NXT <= P_ADR_I;
HST_BUF_NXT <= HIST_MEM(CACHE_PAGES-1); -- next page for writing
BIT_BUF_NXT <= P_CS_I and P_WE_I;
if (C_WTHRU_I = '0') and (DIRTY_FLAG(to_integer(unsigned(HIST_MEM(CACHE_PAGES-1)))) = '1') then
if (C_WTHRU_I = '0') and (DIRTY_FLAG(to_integer(unsigned(HIST_MEM(CACHE_PAGES-1)))) = '1') and
(VALID_FLAG(to_integer(unsigned(HIST_MEM(CACHE_PAGES-1)))) = '1') then
ARB_STATE_NXT <= DIRTY_STATE;
elsif (B_IO_ACC_I = '1') and (P_CS_I = '1') then
ARB_STATE_NXT <= IO_REQUEST;
539,20 → 562,14
 
-- Read-Access Synchronizer ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
R_ACC_SYNC: process(CORE_CLK_I, HALT_I, ARB_STATE)
variable sel_v : std_logic;
R_ACC_SYNC: process(CORE_CLK_I)
begin
sel_v := '0';
if (HALT_I = '1') and (ARB_STATE = STORM_ACCESS) then
sel_v := '1';
end if;
if rising_edge(CORE_CLK_I) then
if (RST_I = '1') then
P_DATA_O_SEL <= '0';
P_DATA_O_BUF <= (others => '0');
else
P_DATA_O_SEL <= sel_v;
elsif (ARB_STATE = STORM_ACCESS) then
P_DATA_O_SEL <= HALT_I;
if (P_DATA_O_SEL = '0') then
P_DATA_O_BUF <= P_DATA_O_INT;
end if;
/storm_core/trunk/rtl/ALU.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Arithmetical/Logical/MCR_Access Unit #
-- # *************************************************** #
-- # Last modified: 02.03.2012 #
-- # Last modified: 08.03.2012 #
-- #######################################################
 
library IEEE;
62,6 → 62,7
 
-- Local Signals --
signal ALU_OUT : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal RESULT_TMP : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal ADDER_RES : STD_LOGIC_VECTOR(DATA_WIDTH downto 0);
signal ADD_MODE : STD_LOGIC_VECTOR(02 downto 0);
signal CARRY_OUT : STD_LOGIC;
185,7 → 186,7
 
-- Flag Logic ------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
ALU_FLAG_LOGIC: process(ADDER_RES, OP_A(31), OP_B(31), ALU_OUT, FLAG_I,
ALU_FLAG_LOGIC: process(ADDER_RES, OP_A, OP_B, ALU_OUT, FLAG_I,
CARRY_OUT, OVFL_OUT, MS_CARRY_REG, MS_OVFL_REG, CTRL_I)
variable is_add_zero_v : std_logic;
variable is_xor_zero_v : std_logic;
244,7 → 245,7
-- Forwarding Paths ------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
-- Operation Data Result --
ALU_FW_O(FWD_DATA_MSB downto FWD_DATA_LSB) <= ALU_OUT(DATA_WIDTH-1 downto 0);
ALU_FW_O(FWD_DATA_MSB downto FWD_DATA_LSB) <= RESULT_TMP;
-- Destination Register Address --
ALU_FW_O(FWD_RD_MSB downto FWD_RD_LSB) <= CTRL_I(CTRL_RD_3 downto CTRL_RD_0);
-- Data Write Back Enabled --
266,8 → 267,10
-- --------------------------------------------------------------------------------------------------------
 
--- MCR / CP Read Access ---
RESULT_O <= MCR_DTA_I when ((CTRL_I(CTRL_MREG_ACC) = '1') and (CTRL_I(CTRL_MREG_RW) = '0')) or
((CTRL_I(CTRL_CP_ACC) = '1') and (CTRL_I(CTRL_CP_RW) = '0')) else ALU_OUT;
RESULT_TMP <= MCR_DTA_I when ((CTRL_I(CTRL_MREG_ACC) = '1') and (CTRL_I(CTRL_MREG_RW) = '0')) or
((CTRL_I(CTRL_CP_ACC) = '1') and (CTRL_I(CTRL_CP_RW) = '0')) else ALU_OUT;
RESULT_O <= RESULT_TMP;
 
--- MCR Connection ---
MCR_DTA_O <= ALU_OUT;
 
/storm_core/trunk/rtl/STORM_TOP.vhd
21,7 → 21,7
-- # - LOAD_STORE_UNIT.vhd | Download at http://opencores.org/project,storm_core #
-- # - OPCODE_DECODER.vhd | #
-- # ***************************************************************************************************** #
-- # Last modified: 15.02.2012 =/\= #
-- # Last modified: 08.03.2012 =/\= #
-- #########################################################################################################
 
library IEEE;
100,6 → 100,7
signal ST_MODE : STD_LOGIC_VECTOR(04 downto 0);
signal C_WTHRU : STD_LOGIC;
signal C_BUS_CYCC : STD_LOGIC_VECTOR(15 downto 0);
signal ADR_FEEDBACK : STD_LOGIC_VECTOR(31 downto 0);
 
-- STORM D-Cache Interface --
signal ST_DC_REQ : STD_LOGIC;
113,9 → 114,13
signal ST_DC_HIT : STD_LOGIC;
signal ST_DC_FRESH : STD_LOGIC;
signal ST_DC_CIO : STD_LOGIC;
signal ST_DC_SYNC : STD_LOGIC;
 
-- Bus Unit D-Cache Interface --
signal BS_DC_CS : STD_LOGIC;
signal BS_DC_P_SEL : STD_LOGIC_VECTOR(log2(D_CACHE_PAGES)-1 downto 0);
signal BS_DC_D_SEL : STD_LOGIC;
signal BS_DC_A_SEL : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_ADR : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DATA_I : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
122,7 → 127,6
signal BS_DC_WE : STD_LOGIC;
signal BS_DC_DIRTY : STD_LOGIC;
signal BS_DC_MISS : STD_LOGIC;
signal BS_DC_BSA_SEL : STD_LOGIC_VECTOR(31 downto 0);
signal BS_DC_DRT_ACK : STD_LOGIC;
signal BS_DC_MSS_ACK : STD_LOGIC;
signal BS_DC_IO_ACC : STD_LOGIC;
137,6 → 141,7
 
-- Bus Unit I-Cache Interface --
signal BS_IC_CS : STD_LOGIC;
signal BS_IC_P_SEL : STD_LOGIC_VECTOR(log2(I_CACHE_PAGES)-1 downto 0);
signal BS_IC_ADR : STD_LOGIC_VECTOR(31 downto 0);
signal BS_IC_DATA_I : STD_LOGIC_VECTOR(31 downto 0);
signal BS_IC_WE : STD_LOGIC;
178,6 → 183,7
D_CACHE_HIT => ST_DC_HIT, -- d-cache hit
D_CACHE_FRESH => ST_DC_FRESH, -- refresh d-cache
D_CACHE_CIO => ST_DC_CIO, -- en cached IO
D_CACHE_SYNC => ST_DC_SYNC, -- d-cache is sync
 
-- Instruction Cache Interface --
I_CACHE_REQ => ST_IC_REQ, -- memory access in next cycle
194,6 → 200,7
C_WTHRU_O => C_WTHRU, -- cache write through
IO_PORT_OUT => IO_PORT_O, -- direct output
IO_PORT_IN => IO_PORT_I, -- direct input
ADR_FEEDBACK_I => ADR_FEEDBACK, -- address feedback for exceptions
 
-- Interrupt Request Lines --
IRQ => IRQ_I, -- interrupt request
215,10 → 222,13
-- Global Control --
CORE_CLK_I => CORE_CLK_I, -- core clock, all triggering on rising edge
RST_I => RST_I, -- global reset, high active, sync
HALT_I => ST_HALT, -- global storm halt signal
HALT_I => ST_HALT, -- halt cache
 
-- Processor Access --
P_CS_I => ST_IC_REQ, -- processor request
B_P_SEL_I => BS_IC_P_SEL, -- bus unit page select
B_D_SEL_O => open, -- selected dirty bit
B_A_SEL_O => open, -- selected base adr
P_ADR_I => ST_IC_ADR, -- address input
P_DATA_I => x"00000000", -- data input
P_DATA_O => ST_IC_RD_DTA, -- data output
231,7 → 241,6
B_DATA_I => BS_IC_DATA_I, -- data input
B_DATA_O => open, -- data output
B_WE_I => BS_IC_WE, -- write enable
B_BSA_O => open, -- base adr of selected page
B_DRT_ACK_I => '1', -- dirty acknowledged
B_MSS_ACK_I => BS_IC_MSS_ACK, -- miss acknowledged
B_IO_ACC_I => '0', -- IO access
243,11 → 252,15
C_MISS_O => BS_IC_MISS, -- cache miss access
C_HIT_O => ST_IC_HIT, -- cache hit access
C_DIRTY_O => open, -- cache modified
C_WTHRU_I => '0' -- write through
C_WTHRU_I => '0', -- write through
C_SYNC_O => open -- cache is sync
);
 
-- selector dummy --
BS_IC_P_SEL <= (others => '0');
 
 
 
-- STORM Data Cache -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
D_CACHE_INST: CACHE
261,7 → 274,7
-- Global Control --
CORE_CLK_I => CORE_CLK_I, -- core clock, all triggering on rising edge
RST_I => RST_I, -- global reset, high active, sync
HALT_I => ST_HALT, -- global storm halt signal
HALT_I => ST_HALT, -- halt cache
 
-- Processor Access --
P_CS_I => ST_DC_REQ, -- processor request
273,11 → 286,13
 
-- Bus Unit Access --
B_CS_I => BS_DC_CS, -- bus unit request
B_P_SEL_I => BS_DC_P_SEL, -- bus unit page select
B_D_SEL_O => BS_DC_D_SEL, -- selected dirty bit
B_A_SEL_O => BS_DC_A_SEL, -- selected base adr
B_ADR_I => BS_DC_ADR, -- address input
B_DATA_I => BS_DC_DATA_I, -- data input
B_DATA_O => BS_DC_DATA_O, -- data output
B_WE_I => BS_DC_WE, -- write enable
B_BSA_O => BS_DC_BSA_SEL, -- base adr of selected page
B_DRT_ACK_I => BS_DC_DRT_ACK, -- dirty acknowledged
B_MSS_ACK_I => BS_DC_MSS_ACK, -- miss acknowledged
B_IO_ACC_I => BS_DC_IO_ACC, -- IO access
289,7 → 304,8
C_MISS_O => BS_DC_MISS, -- cache miss access
C_HIT_O => ST_DC_HIT, -- cache hit access
C_DIRTY_O => BS_DC_DIRTY, -- cache modified
C_WTHRU_I => C_WTHRU -- write through
C_WTHRU_I => C_WTHRU, -- write through
C_SYNC_O => ST_DC_SYNC -- cache is sync
);
 
320,10 → 336,14
I_ABORT_O => I_ABORT, -- bus error during instruction transfer
C_BUS_CYCC_I => C_BUS_CYCC, -- max bus cycle length
CACHED_IO_I => ST_DC_CIO, -- enable cached IO
ADR_FEEDBACK_O => ADR_FEEDBACK, -- address feedback for exception handling
 
-- Data Cache Interface --
DC_CS_O => BS_DC_CS, -- chip select
DC_P_ADR_I => ST_DC_ADR, -- processor address
DC_P_SEL_O => BS_DC_P_SEL, -- page select
DC_D_SEL_I => BS_DC_D_SEL, -- dirty bit of selected page
DC_A_SEL_I => BS_DC_A_SEL, -- base adr of sel page
DC_P_CS_I => ST_DC_REQ, -- processor cache request
DC_P_WE_I => ST_DC_RW, -- processor write enable
DC_ADR_O => BS_DC_ADR, -- cache address
332,7 → 352,6
DC_WE_O => BS_DC_WE, -- write enable
DC_MISS_I => BS_DC_MISS, -- cache miss access
DC_DIRTY_I => BS_DC_DIRTY, -- cache modified
DC_BSA_I => BS_DC_BSA_SEL, -- base address of selected page
DC_DRT_ACK_O => BS_DC_DRT_ACK, -- dirty acknowledged
DC_MSS_ACK_O => BS_DC_MSS_ACK, -- miss acknowledged
DC_IO_ACC_O => BS_DC_IO_ACC, -- IO access
/storm_core/trunk/rtl/BUS_UNIT.vhd
9,7 → 9,7
-- # Note: I-Cache is read-only for the processor and #
-- # write-only for the bus unit. #
-- # ************************************************** #
-- # Last modified: 01.03.2012 #
-- # Last modified: 08.03.2012 #
-- ######################################################
 
library IEEE;
49,6 → 49,7
I_ABORT_O : out STD_LOGIC; -- bus error during instruction transfer
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0); -- max bus cycle length
CACHED_IO_I : in STD_LOGIC; -- enable cached IO
ADR_FEEDBACK_O : out STD_LOGIC_VECTOR(31 downto 0); -- address feedback for exception handling
 
-- ################################################################################################################
-- ## STORM Data Cache Interface ##
56,6 → 57,9
 
DC_CS_O : out STD_LOGIC; -- chip select
DC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0); -- processor address
DC_P_SEL_O : out STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0); -- page select
DC_D_SEL_I : in STD_LOGIC; -- dirty bit of selected page
DC_A_SEL_I : in STD_LOGIC_VECTOR(31 downto 0); -- base adr of sel page
DC_P_CS_I : in STD_LOGIC; -- processor cache request
DC_P_WE_I : in STD_LOGIC; -- processor write enable
DC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- cache address
64,7 → 68,6
DC_WE_O : out STD_LOGIC; -- write enable
DC_MISS_I : in STD_LOGIC; -- cache miss access
DC_DIRTY_I : in STD_LOGIC; -- cache modified
DC_BSA_I : in STD_LOGIC_VECTOR(31 downto 0); -- base address of selected page
DC_DRT_ACK_O : out STD_LOGIC; -- dirty acknowledged
DC_MSS_ACK_O : out STD_LOGIC; -- miss acknowledged
DC_IO_ACC_O : out STD_LOGIC; -- IO access
113,7 → 116,7
constant WB_BST_END_CYC : STD_LOGIC_VECTOR(2 downto 0) := "111"; -- burst end
 
-- Arbiter FSM --
type ARB_STATE_TYPE is (IDLE, UPLOAD_D_PAGE, IO_REQUEST, DOWNLOAD_I_PAGE, DOWNLOAD_D_PAGE, END_TRANSFER);
type ARB_STATE_TYPE is (IDLE, ASSIGN_D_PAGE, UPLOAD_D_PAGE, IO_REQUEST, DOWNLOAD_I_PAGE, DOWNLOAD_D_PAGE, END_TRANSFER);
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE;
 
-- Address Buffer --
122,6 → 125,7
signal WB_ADR_BUF, WB_ADR_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal DC_P_ADR_BUF, IC_P_ADR_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal BASE_BUF, BASE_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal PAGE_BUF, PAGE_BUF_NXT : STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0);
 
-- Wishbone Syncs --
signal WB_DATA_BUF : STD_LOGIC_VECTOR(31 downto 0);
139,6 → 143,7
 
-- Timeout System --
signal TIMEOUT_CNT, TIMEOUT_CNT_NXT : STD_LOGIC_VECTOR(15 downto 0);
signal WB_ACK_CNT, WB_ACK_CNT_NXT : STD_LOGIC_VECTOR(15 downto 0);
 
begin
 
167,6 → 172,7
--- D-Cache ---
DC_DATA_O <= WB_DATA_BUF;
DC_ADR_O <= DC_ADR_BUF;
DC_P_SEL_O <= PAGE_BUF;
 
--- I-Cache ---
IC_DATA_O <= WB_DATA_BUF;
183,8 → 189,11
IO_ACCESS <= '1' when (DC_P_ADR_I >= IO_UC_BEGIN) and (DC_P_ADR_I <= IO_UC_END) and (CACHED_IO_I = '0') else '0';
DC_IO_ACC_O <= IO_ACCESS;
 
--- Core Feedback ---
ADR_FEEDBACK_O <= WB_ADR_BUF;
 
 
 
-- Arbiter State Machine (Sync) ---------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
ARBITER_SYNC: process(CORE_CLK_I)
195,11 → 204,13
TIMEOUT_CNT <= (others => '0');
WB_DATA_BUF <= (others => '0');
WB_ACK_BUF <= '0';
WB_ACK_CNT <= (others => '0');
WB_ERR_BUF <= '0';
WE_FLAG <= '0';
VA_CYC_BUF <= '0';
IC_ADR_BUF <= (others => '0');
DC_ADR_BUF <= (others => '0');
PAGE_BUF <= (others => '0');
WB_ADR_BUF <= (others => '0');
BASE_BUF <= (others => '0');
DC_P_ADR_BUF <= (others => '0');
215,11 → 226,13
-- Wishbone Sync --
WB_DATA_BUF <= WB_DATA_I;
WB_ACK_BUF <= WB_ACK_I;
WB_ACK_CNT <= WB_ACK_CNT_NXT;
WB_ERR_BUF <= WB_ERR_I;
VA_CYC_BUF <= VA_CYC_BUF_NXT;
-- Address Buffer --
IC_ADR_BUF <= IC_ADR_BUF_NXT;
DC_ADR_BUF <= DC_ADR_BUF_NXT;
PAGE_BUF <= PAGE_BUF_NXT;
WB_ADR_BUF <= WB_ADR_BUF_NXT;
BASE_BUF <= BASE_BUF_NXT;
end if;
231,10 → 244,10
 
-- Arbiter State Machine (Async) --------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, WE_FLAG,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, DC_DIRTY_I, DC_MISS_I, DC_BSA_I, DC_P_WE_I, DC_P_CS_I,
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, WE_FLAG,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, PAGE_BUF, DC_D_SEL_I, DC_A_SEL_I, DC_DIRTY_I, DC_MISS_I, DC_P_WE_I, DC_P_CS_I,
IC_ADR_BUF, IC_P_ADR_BUF, IC_MISS_I,
WB_ADR_BUF, WB_ACK_BUF, WB_ERR_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
WB_ADR_BUF, WB_ACK_BUF, WB_ACK_I, WB_ACK_CNT, WB_ERR_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
variable IF_BASE_ADR_V, DF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
begin
--- Base Address Word Alignment ---
248,6 → 261,8
TIMEOUT_CNT_NXT <= TIMEOUT_CNT;
DC_ADR_BUF_NXT <= DC_ADR_BUF;
IC_ADR_BUF_NXT <= IC_ADR_BUF;
PAGE_BUF_NXT <= PAGE_BUF;
WB_ACK_CNT_NXT <= WB_ACK_CNT;
WB_ADR_BUF_NXT <= WB_ADR_BUF;
FREEZE_FLAG_NXT <= FREEZE_FLAG;
FREEZE_DIS_NXT <= '0';
262,6 → 277,11
WB_CYC_O <= '0';
WB_STB_O <= '0';
 
--- Wishbone ACK Counter ---
if (WB_ACK_I = '1') then
WB_ACK_CNT_NXT <= Std_Logic_Vector(unsigned(WB_ACK_CNT) + 1);
end if;
 
--- D-Cache Interface Defaults ---
DC_CS_O <= '0';
DC_WE_O <= '0';
279,8 → 299,9
 
when IDLE => -- waiting for requests
-------------------------------------------------------------------------------
IC_ADR_BUF_NXT <= IF_BASE_ADR_V;
DC_ADR_BUF_NXT <= DF_BASE_ADR_V;
IC_ADR_BUF_NXT <= IF_BASE_ADR_V;
DC_ADR_BUF_NXT <= DF_BASE_ADR_V;
WB_ACK_CNT_NXT <= (others => '0');
if (IC_MISS_I = '1') then -- i-cache miss -> reload cache page
ARB_STATE_NXT <= DOWNLOAD_I_PAGE;
FREEZE_FLAG_NXT <= '1';
297,12 → 318,10
ARB_STATE_NXT <= IO_REQUEST;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DC_P_ADR_I;
WE_FLAG_NXT <= DC_P_WE_I;
WE_FLAG_NXT <= DC_P_WE_I; -- bus read/write
elsif (DC_DIRTY_I = '1') then -- d-cache modification -> copy page to main memory
DC_ADR_BUF_NXT <= DC_BSA_I;
WB_ADR_BUF_NXT <= DC_BSA_I;
BASE_BUF_NXT <= DC_BSA_I;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
ARB_STATE_NXT <= ASSIGN_D_PAGE;
PAGE_BUF_NXT <= (others => '1'); -- last entry
WE_FLAG_NXT <= '1'; -- bus write
FREEZE_FLAG_NXT <= '1';
end if;
316,7 → 335,7
WB_STB_O <= '1'; -- valid transfer
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (IC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + I_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then -- cycle complete?
(to_integer(unsigned(WB_ACK_CNT)) >= I_CACHE_PAGE_SIZE) then --((WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
347,7 → 366,7
DC_WE_O <= '1'; -- cache write access
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (DC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then -- cycle complete?
(to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then --(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
371,13 → 390,13
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '1'; -- io access
WB_CTI_O <= WB_CON_BST_CYC;
WB_CTI_O <= WB_CLASSIC_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
DC_WE_O <= '1'; -- dummy cache write access
DC_ADR_BUF_NXT <= WB_ADR_BUF;
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (WB_ACK_BUF = '1') then -- cycle complete?
if (to_integer(unsigned(WB_ACK_CNT)) >= 1) then --(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
393,6 → 412,19
FREEZE_DIS_NXT <= '1';
end if;
 
when ASSIGN_D_PAGE => -- find dirty pages in cache
-------------------------------------------------------------------------------
if (DC_D_SEL_I = '1') then -- entry is dirty
DC_ADR_BUF_NXT <= DC_A_SEL_I;
WB_ADR_BUF_NXT <= DC_A_SEL_I;
BASE_BUF_NXT <= DC_A_SEL_I;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
elsif (to_integer(unsigned(PAGE_BUF)) = 0) then -- all pages analyzed
ARB_STATE_NXT <= END_TRANSFER;
else
PAGE_BUF_NXT <= Std_Logic_Vector(unsigned(PAGE_BUF)-1);
end if;
 
when UPLOAD_D_PAGE => -- copy d-cache page to main memory
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
406,10 → 438,11
WB_ADR_BUF_NXT <= DC_ADR_BUF;
VA_CYC_BUF_NXT <= '1';
if (WB_ADR_BUF = Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
if (WB_ACK_BUF = '1') then -- cycle complete?
if (to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then --(WB_ACK_BUF = '1') then -- cycle complete?
DC_DRT_ACK_O <= '1'; -- ack of dirty signal
------- if still dirty
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of dirty signal
VA_CYC_BUF_NXT <= '0';
end if;
end if;
419,7 → 452,7
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
ARB_STATE_NXT <= ASSIGN_D_PAGE;
DC_DRT_ACK_O <= '1'; -- ack dirty signal
D_ABORT_O <= '1';
FREEZE_DIS_NXT <= '1';
/storm_core/trunk/rtl/CORE.vhd
21,7 → 21,7
-- # | -> stnolting@googlemail.com #
-- # | -> stnolting@web.de #
-- # *************************************************************************************************** #
-- # Last modified: 02.03.2012 #
-- # Last modified: 08.03.2012 #
-- #######################################################################################################
 
library IEEE;
70,6 → 70,7
D_CACHE_HIT : in STD_LOGIC; -- d-cache hit
D_CACHE_FRESH : out STD_LOGIC; -- refresh d-cache
D_CACHE_CIO : out STD_LOGIC; -- enable cached IO
D_CACHE_SYNC : in STD_LOGIC; -- cache is sync
 
-- ###############################################################################################
-- ## Instruction Cache Interface ##
92,6 → 93,7
C_WTHRU_O : out STD_LOGIC; -- write through
IO_PORT_OUT : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_IN : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
ADR_FEEDBACK_I : in STD_LOGIC_VECTOR(31 downto 0); -- address feedback for exceptions
 
-- ###############################################################################################
-- ## Interrupt Interface ##
253,8 → 255,10
IC_MISS_I => I_CACHE_MISS, -- i-cache miss accessear i-cache
C_WTHRU_O => C_WTHRU_O, -- write through
CACHED_IO_O => D_CACHE_CIO, -- en cached IO
DC_SYNC_I => D_CACHE_SYNC, -- d-cache is sync
IO_PORT_O => IO_PORT_OUT, -- direct output
IO_PORT_I => IO_PORT_IN -- direct input
IO_PORT_I => IO_PORT_IN, -- direct input
ADR_FEEDBACK_I => ADR_FEEDBACK_I -- adr feedback for exception handling
);
 
 
/storm_core/trunk/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and #
-- # system parameters for the STORM Core processor. #
-- # +-------------------------------------------------+ #
-- # Last modified: 02.03.2012 #
-- # Last modified: 08.03.2012 #
-- #######################################################
 
library IEEE;
160,12 → 160,11
constant CP_ID_REG_0 : natural := 0; -- ID register 0
constant CP_ID_REG_1 : natural := 1; -- ID register 1
constant CP_ID_REG_2 : natural := 2; -- ID register 2
constant CP_ID_REG_3 : natural := 3; -- ID register 3
constant CP_ID_REG_4 : natural := 4; -- ID register 4
constant CP_ID_REG_5 : natural := 5; -- ID register 5
 
constant CP_SYS_CTRL_0 : natural := 6; -- system control register 0
constant CP_SYS_CTRL_1 : natural := 7; -- system control register 1
 
constant CP_CSTAT : natural := 8; -- cache statistics register
constant CP_BUS_AFB : natural := 9; -- bus unit adr feedback
 
constant CP_LFSR_POLY : natural := 11; -- Internal lfsr, polynomial
constant CP_LFSR_DATA : natural := 12; -- Internal lfsr, shift register
178,15 → 177,16
constant CP_IO_I_LSB : natural := 16; -- input LSB
constant CP_IO_I_MSB : natural := 31; -- input MSB
 
-- INTERNAL COPROCESSOR, SYSTEM CONTROL REGISTER 0 ----------------------------------------
-- SYSTEM CONTROL REGISTER 0 --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant CSCR0_FDC : natural := 0; -- flush d-cache
constant CSCR0_CDC : natural := 1; -- clear d-cache
constant CSCR0_CIC : natural := 2; -- flush i-cache
constant CSCR0_CWT : natural := 3; -- d-cache write-thru enable
constant CSCR0_DAR : natural := 4; -- auto pre-refresh d-cache for new access
constant CSCR0_IAR : natural := 5; -- auto pre-refresh i-cache for new access
constant CSCR0_DAR : natural := 4; -- d-cache "read through"
constant CSCR0_IAR : natural := 5; -- i-cache "read through"
constant CSCR0_CIO : natural := 6; -- enable cached IO
constant CSCR0_DCS : natural := 7; -- d-cache is sync
 
constant CSCR0_LFSRE : natural := 13; -- internal LFSR enable
constant CSCR0_LFSRM : natural := 14; -- internal LFSR update mode (0:auto/1:access)
332,8 → 332,10
IC_MISS_I : in STD_LOGIC;
C_WTHRU_O : out STD_LOGIC;
CACHED_IO_O : out STD_LOGIC;
DC_SYNC_I : in STD_LOGIC;
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0);
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0)
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0);
ADR_FEEDBACK_I : in STD_LOGIC_VECTOR(31 downto 0)
);
end component;
 
553,11 → 555,13
P_DQ_I : in STD_LOGIC_VECTOR(01 downto 0);
P_WE_I : in STD_LOGIC;
B_CS_I : in STD_LOGIC;
B_P_SEL_I : in STD_LOGIC_VECTOR(LOG2_CACHE_PAGES-1 downto 0);
B_D_SEL_O : out STD_LOGIC;
B_A_SEL_O : out STD_LOGIC_VECTOR(31 downto 0);
B_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
B_DATA_I : in STD_LOGIC_VECTOR(31 downto 0);
B_DATA_O : out STD_LOGIC_VECTOR(31 downto 0);
B_WE_I : in STD_LOGIC;
B_BSA_O : out STD_LOGIC_VECTOR(31 downto 0);
B_DRT_ACK_I : in STD_LOGIC;
B_MSS_ACK_I : in STD_LOGIC;
B_IO_ACC_I : in STD_LOGIC;
567,7 → 571,8
C_MISS_O : out STD_LOGIC;
C_HIT_O : out STD_LOGIC;
C_DIRTY_O : out STD_LOGIC;
C_WTHRU_I : in STD_LOGIC
C_WTHRU_I : in STD_LOGIC;
C_SYNC_O : out STD_LOGIC
);
end component;
 
595,8 → 600,12
I_ABORT_O : out STD_LOGIC;
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0);
CACHED_IO_I : in STD_LOGIC;
ADR_FEEDBACK_O : out STD_LOGIC_VECTOR(31 downto 0);
DC_CS_O : out STD_LOGIC;
DC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_P_SEL_O : out STD_LOGIC_VECTOR(LOG2_D_CACHE_PAGES-1 downto 0);
DC_D_SEL_I : in STD_LOGIC;
DC_A_SEL_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_P_CS_I : in STD_LOGIC;
DC_P_WE_I : in STD_LOGIC;
DC_ADR_O : out STD_LOGIC_VECTOR(31 downto 0);
605,7 → 614,6
DC_WE_O : out STD_LOGIC;
DC_MISS_I : in STD_LOGIC;
DC_DIRTY_I : in STD_LOGIC;
DC_BSA_I : in STD_LOGIC_VECTOR(31 downto 0);
DC_DRT_ACK_O : out STD_LOGIC;
DC_MSS_ACK_O : out STD_LOGIC;
DC_IO_ACC_O : out STD_LOGIC;
656,6 → 664,7
D_CACHE_HIT : in STD_LOGIC;
D_CACHE_FRESH : out STD_LOGIC;
D_CACHE_CIO : out STD_LOGIC;
D_CACHE_SYNC : in STD_LOGIC;
I_CACHE_REQ : out STD_LOGIC;
I_CACHE_ADR : out STD_LOGIC_VECTOR(31 downto 0);
I_CACHE_RD_DTA : in STD_LOGIC_VECTOR(31 downto 0);
668,6 → 677,7
C_WTHRU_O : out STD_LOGIC;
IO_PORT_OUT : out STD_LOGIC_VECTOR(15 downto 0);
IO_PORT_IN : in STD_LOGIC_VECTOR(15 downto 0);
ADR_FEEDBACK_I : in STD_LOGIC_VECTOR(31 downto 0);
IRQ : in STD_LOGIC;
FIQ : in STD_LOGIC
);
/storm_core/trunk/rtl/MC_SYS.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Machine Control System #
-- # *************************************************** #
-- # Last modified: 15.02.2012 #
-- # Last modified: 08.03.2012 #
-- #######################################################
 
library IEEE;
81,6 → 81,7
IC_MISS_I : in STD_LOGIC; -- i-cache miss access
C_WTHRU_O : out STD_LOGIC; -- write through
CACHED_IO_O : out STD_LOGIC; -- en cached IO
DC_SYNC_I : in STD_LOGIC; -- d-cache is sync
 
-- ###############################################################################################
-- ## System Control ##
87,7 → 88,8
-- ###############################################################################################
 
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0) -- direct input
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
ADR_FEEDBACK_I : in STD_LOGIC_VECTOR(31 downto 0) -- adr feedback for exception handling
 
);
end MC_SYS;
210,7 → 212,7
-- ---------------------------------------------------------------------------------------------------
 
-- Pending external interrupt request to stop instruction fetch until pipeline is empty --
PEND_XI_REQ_O <= (EXT_INT_REQ_SYNC(0) or EXT_INT_REQ_SYNC(1) or EXT_INT_REQ_SYNC(2) or EXT_INT_REQ_SYNC(3));
PEND_XI_REQ_O <= EXT_INT_REQ_SYNC(0) or EXT_INT_REQ_SYNC(1) or EXT_INT_REQ_SYNC(2) or EXT_INT_REQ_SYNC(3);
 
-- FIQ Trap taken --
FIQ_TAKEN_NXT <= EXT_INT_REQ_SYNC(0) and EMPTY_PIPE_I and NO_BR_PIPE;
482,7 → 484,7
if rising_edge(CLK_I) then
if (RST_I = '1') then
CP_REG_FILE <= (others => (others => '0')); -- clear all
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0301"; -- core update date
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0308"; -- core update date
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;)
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length
495,6 → 497,7
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_FDC) <= '0'; -- auto-reset flush d-cache
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CDC) <= '0'; -- auto-reset clear d-cache
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIC) <= '0'; -- auto-reset clear i-cache
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_DCS) <= DC_SYNC_I; -- d-cache sync
end if;
 
-- Cache Statistic Register ---------------------------------------------------
509,6 → 512,9
CP_REG_FILE(CP_CSTAT)(31 downto 16) <= Std_Logic_Vector(unsigned(CP_REG_FILE(CP_CSTAT)(31 downto 16)) + 1);
end if;
 
-- Bus Unit Address Feedback --------------------------------------------------
CP_REG_FILE(CP_BUS_AFB) <= ADR_FEEDBACK_I;
 
-- Internal LFSR:: Polynomial Register ----------------------------------------
if (G_HALT_I = '0') and (cr_w_acc_v = '1') and (cp_adr_v = CP_LFSR_POLY) then
CP_REG_FILE(CP_LFSR_POLY) <= MCR_DATA_I;
/storm_core/trunk/doc/STORM CORE datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/software/C/storm_core.h
6,7 → 6,7
//
// Created by Stephan Nolting (stnolting@googlemail.com)
// http://www.opencores.com/project,storm_core
// Last modified 15. Feb. 2012
// Last modified 08. Mar. 2012
////////////////////////////////////////////////////////////////////////////////
 
/* Internal System Coprocessor Register Set */
14,14 → 14,9
#define ID_REG_0 0 // ID register 0
#define ID_REG_1 1 // ID register 1
#define ID_REG_2 2 // ID register 2
#define ID_REG_3 3 // ID register 3
#define ID_REG_4 4 // ID register 4
#define ID_REG_5 5 // ID register 5
#define SYS_CTRL_0 6 // system control register 0
#define SYS_CTRL_1 7 // system control register 1
#define CSTAT 8 // cache statistics register
#define TIME_THRES 9 // Internal timer, threshold value
#define TIME_COUNT 10 // Internal timer, counter
#define ADR_FB 9 // adr feedback from bus unit -> for exception handling
#define LFSR_POLY 11 // Internal LFSR, polynomial
#define LFSR_DATA 12 // Internal LFSR, shift register
#define SYS_IO 13 // System IO ports
33,9 → 28,6
#define DC_WTHRU 3 // cache write-thru enable
#define DC_AUTOPR 4 // auto pre-reload d-cache page
#define IC_AUTOPR 5 // auto pre-reload i-cache page
#define TIME_EN 10 // enable internal timer
#define TIME_INT 11 // int timer interrupt enable
#define TIME_M 12 // int timer interrupt mode
#define LFSR_EN 13 // enable lfsr
#define LFSR_M 14 // lfsr update mode
#define LFSR_D 15 // lfsr shift direction

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.