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URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

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    from Rev 28 to Rev 29
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Rev 28 → Rev 29

/storm_core/trunk/rtl/CACHE.vhd
149,7 → 149,7
 
-- Page Base Address System ----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
PAGE_ADR_SYS: process(CORE_CLK_I, PAGE_BASE_ADR, B_BASE_O_SEL)
PAGE_ADR_SYS: process(CORE_CLK_I, PAGE_BASE_ADR, B_BASE_O_SEL, B_P_SEL_I)
begin
-- Update Base Adr Register --
if rising_edge(CORE_CLK_I) then
/storm_core/trunk/rtl/STORM_TOP.vhd
21,7 → 21,7
-- # - LOAD_STORE_UNIT.vhd | Download at http://opencores.org/project,storm_core #
-- # - OPCODE_DECODER.vhd | #
-- # ***************************************************************************************************** #
-- # Last modified: 08.03.2012 =/\= #
-- # Last modified: 17.03.2012 =/\= #
-- #########################################################################################################
 
library IEEE;
115,6 → 115,7
signal ST_DC_FRESH : STD_LOGIC;
signal ST_DC_CIO : STD_LOGIC;
signal ST_DC_SYNC : STD_LOGIC;
signal ST_PRTCT_IO : STD_LOGIC;
 
-- Bus Unit D-Cache Interface --
signal BS_DC_CS : STD_LOGIC;
183,6 → 184,7
D_CACHE_HIT => ST_DC_HIT, -- d-cache hit
D_CACHE_FRESH => ST_DC_FRESH, -- refresh d-cache
D_CACHE_CIO => ST_DC_CIO, -- en cached IO
IO_PROTECT_O => ST_PRTCT_IO, -- protected IO
D_CACHE_SYNC => ST_DC_SYNC, -- d-cache is sync
 
-- Instruction Cache Interface --
286,9 → 288,9
 
-- Bus Unit Access --
B_CS_I => BS_DC_CS, -- bus unit request
B_P_SEL_I => BS_DC_P_SEL, -- bus unit page select
B_D_SEL_O => BS_DC_D_SEL, -- selected dirty bit
B_A_SEL_O => BS_DC_A_SEL, -- selected base adr
B_P_SEL_I => BS_DC_P_SEL, -- bus unit page select
B_D_SEL_O => BS_DC_D_SEL, -- selected dirty bit
B_A_SEL_O => BS_DC_A_SEL, -- selected base adr
B_ADR_I => BS_DC_ADR, -- address input
B_DATA_I => BS_DC_DATA_I, -- data input
B_DATA_O => BS_DC_DATA_O, -- data output
336,6 → 338,7
I_ABORT_O => I_ABORT, -- bus error during instruction transfer
C_BUS_CYCC_I => C_BUS_CYCC, -- max bus cycle length
CACHED_IO_I => ST_DC_CIO, -- enable cached IO
PROTECTED_IO_I => ST_PRTCT_IO, -- protected IO
ADR_FEEDBACK_O => ADR_FEEDBACK, -- address feedback for exception handling
 
-- Data Cache Interface --
/storm_core/trunk/rtl/BUS_UNIT.vhd
4,12 → 4,10
-- # STORM PROCESSOR BUS UNIT #
-- # -------------------------------------------------- #
-- # This bus unit connects the data and instruction #
-- # of the STORM CORE processor to a Wishbone #
-- # compatible 32-bit bus system. #
-- # Note: I-Cache is read-only for the processor and #
-- # write-only for the bus unit. #
-- # cache of the STORM Core processor to a pipelined #
-- # Wishbone compatible 32-bit bus system. #
-- # ************************************************** #
-- # Last modified: 08.03.2012 #
-- # Last modified: 17.03.2012 #
-- ######################################################
 
library IEEE;
49,6 → 47,7
I_ABORT_O : out STD_LOGIC; -- bus error during instruction transfer
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0); -- max bus cycle length
CACHED_IO_I : in STD_LOGIC; -- enable cached IO
PROTECTED_IO_I : in STD_LOGIC; -- protected IO
ADR_FEEDBACK_O : out STD_LOGIC_VECTOR(31 downto 0); -- address feedback for exception handling
 
-- ################################################################################################################
131,8 → 130,12
signal WB_DATA_BUF : STD_LOGIC_VECTOR(31 downto 0);
signal WB_ACK_BUF : STD_LOGIC;
signal WB_ERR_BUF : STD_LOGIC;
signal VA_CYC_BUF, VA_CYC_BUF_NXT : STD_LOGIC;
signal WE_FLAG, WE_FLAG_NXT : STD_LOGIC;
signal WB_DATA_FF, WB_DATA_FF_NXT : STD_LOGIC_VECTOR(31 downto 0);
signal WB_CTI_O_NXT : STD_LOGIC_VECTOR(02 downto 0);
signal WB_TGC_O_NXT : STD_LOGIC_VECTOR(06 downto 0);
signal WB_STB_O_NXT : STD_LOGIC;
signal WB_CYC_O_NXT : STD_LOGIC;
signal WB_WE_O_NXT : STD_LOGIC;
 
-- Access System --
signal IO_ACCESS : STD_LOGIC;
140,6 → 143,8
-- Local Signals --
signal FREEZE_FLAG, FREEZE_FLAG_NXT : STD_LOGIC; -- freeze flag
signal FREEZE_DIS, FREEZE_DIS_NXT : STD_LOGIC; -- freeze disable
signal BIT_BUF, BIT_BUF_NXT : STD_LOGIC; -- GP bit buffer
signal WORD_BUF, WORD_BUF_NXT : STD_LOGIC_VECTOR(31 downto 0); -- GP word buffer
 
-- Timeout System --
signal TIMEOUT_CNT, TIMEOUT_CNT_NXT : STD_LOGIC_VECTOR(15 downto 0);
177,13 → 182,12
--- I-Cache ---
IC_DATA_O <= WB_DATA_BUF;
IC_ADR_O <= IC_ADR_BUF;
IC_WE_O <= '1'; -- processor cannot change i-cache, no readback necessary
IC_WE_O <= '1'; -- storm cannot change i-cache, no readback necessary
 
--- Wishbone Bus ---
WB_SEL_O <= "1111"; -- cache entry = word
WB_ADR_O <= WB_ADR_BUF;
WB_DATA_O <= x"00000000" when (ARB_STATE = IDLE) else DC_DATA_I;
WB_WE_O <= WE_FLAG;
WB_SEL_O <= "1111"; -- cache entry = 32-bit word
WB_DATA_FF_NXT <= x"00000000" when (ARB_STATE = IDLE) else DC_DATA_I; -- reduce switching losses...
WB_DATA_O <= WB_DATA_FF_NXT when (ARB_STATE = UPLOAD_D_PAGE) else WB_DATA_FF;
 
--- IO Access ---
IO_ACCESS <= '1' when (DC_P_ADR_I >= IO_UC_BEGIN) and (DC_P_ADR_I <= IO_UC_END) and (CACHED_IO_I = '0') else '0';
206,8 → 210,6
WB_ACK_BUF <= '0';
WB_ACK_CNT <= (others => '0');
WB_ERR_BUF <= '0';
WE_FLAG <= '0';
VA_CYC_BUF <= '0';
IC_ADR_BUF <= (others => '0');
DC_ADR_BUF <= (others => '0');
PAGE_BUF <= (others => '0');
215,13 → 217,31
BASE_BUF <= (others => '0');
DC_P_ADR_BUF <= (others => '0');
IC_P_ADR_BUF <= (others => '0');
WB_DATA_FF <= (others => '0');
WB_ADR_O <= (others => '0');
WB_CTI_O <= (others => '0');
WB_TGC_O <= (others => '0');
WB_STB_O <= '0';
WB_CYC_O <= '0';
WB_WE_O <= '0';
BIT_BUF <= '0';
WORD_BUF <= (others => '0');
else
-- Arbiter CTRL --
ARB_STATE <= ARB_STATE_NXT;
BIT_BUF <= BIT_BUF_NXT;
WORD_BUF <= WORD_BUF_NXT;
TIMEOUT_CNT <= TIMEOUT_CNT_NXT;
DC_P_ADR_BUF <= DC_P_ADR_I;
IC_P_ADR_BUF <= IC_P_ADR_I;
WE_FLAG <= WE_FLAG_NXT;
WB_DATA_FF <= WB_DATA_FF_NXT;
WB_ADR_O <= WB_ADR_BUF;
WB_CTI_O <= WB_CTI_O_NXT;
WB_TGC_O <= WB_TGC_O_NXT;
WB_STB_O <= WB_STB_O_NXT;
WB_CYC_O <= WB_CYC_O_NXT;
WB_WE_O <= WB_WE_O_NXT;
-- Bus interface --
if (WB_HALT_I = '0') then
-- Wishbone Sync --
WB_DATA_BUF <= WB_DATA_I;
228,7 → 248,6
WB_ACK_BUF <= WB_ACK_I;
WB_ACK_CNT <= WB_ACK_CNT_NXT;
WB_ERR_BUF <= WB_ERR_I;
VA_CYC_BUF <= VA_CYC_BUF_NXT;
-- Address Buffer --
IC_ADR_BUF <= IC_ADR_BUF_NXT;
DC_ADR_BUF <= DC_ADR_BUF_NXT;
244,13 → 263,13
 
-- Arbiter State Machine (Async) --------------------------------------------------------------------------
-- -----------------------------------------------------------------------------------------------------------
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, WE_FLAG,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, PAGE_BUF, DC_D_SEL_I, DC_A_SEL_I, DC_DIRTY_I, DC_MISS_I, DC_P_WE_I, DC_P_CS_I,
ARBITER_ASYNC: process(ARB_STATE, STORM_MODE_I, FREEZE_FLAG, BASE_BUF, TIMEOUT_CNT, IO_ACCESS, BIT_BUF, WORD_BUF, PROTECTED_IO_I,
DC_ADR_BUF, DC_P_ADR_BUF, DC_P_ADR_I, PAGE_BUF, DC_D_SEL_I, DC_A_SEL_I, DC_DIRTY_I, DC_MISS_I, DC_P_WE_I, DC_P_CS_I,
IC_ADR_BUF, IC_P_ADR_BUF, IC_MISS_I,
WB_ADR_BUF, WB_ACK_BUF, WB_ACK_I, WB_ACK_CNT, WB_ERR_BUF, VA_CYC_BUF, C_BUS_CYCC_I)
WB_ADR_BUF, WB_ACK_BUF, WB_ACK_I, WB_ACK_CNT, WB_ERR_BUF, C_BUS_CYCC_I)
variable IF_BASE_ADR_V, DF_BASE_ADR_V : STD_LOGIC_VECTOR(31 downto 0);
begin
--- Base Address Word Alignment ---
--- Base Address Alignment ---
IF_BASE_ADR_V := (others => '0');
IF_BASE_ADR_V(31 downto LOG2_I_CACHE_PAGE_SIZE+2) := IC_P_ADR_BUF(31 downto LOG2_I_CACHE_PAGE_SIZE+2);
DF_BASE_ADR_V := (others => '0');
267,15 → 286,16
FREEZE_FLAG_NXT <= FREEZE_FLAG;
FREEZE_DIS_NXT <= '0';
BASE_BUF_NXT <= BASE_BUF;
VA_CYC_BUF_NXT <= '0';
BIT_BUF_NXT <= BIT_BUF;
WORD_BUF_NXT <= WORD_BUF;
TIMEOUT_CNT_NXT <= (others => '0');
WE_FLAG_NXT <= WE_FLAG;
 
--- Wishbone Bus Defaults ---
WB_CTI_O <= WB_CLASSIC_CYC;
WB_TGC_O <= "00" & STORM_MODE_I;
WB_CYC_O <= '0';
WB_STB_O <= '0';
WB_CTI_O_NXT <= WB_CLASSIC_CYC;
WB_TGC_O_NXT <= "00" & STORM_MODE_I;
WB_CYC_O_NXT <= '0';
WB_STB_O_NXT <= '0';
WB_WE_O_NXT <= '0';
 
--- Wishbone ACK Counter ---
if (WB_ACK_I = '1') then
302,114 → 322,130
IC_ADR_BUF_NXT <= IF_BASE_ADR_V;
DC_ADR_BUF_NXT <= DF_BASE_ADR_V;
WB_ACK_CNT_NXT <= (others => '0');
PAGE_BUF_NXT <= (others => '1'); -- last entry
if (IC_MISS_I = '1') then -- i-cache miss -> reload cache page
ARB_STATE_NXT <= DOWNLOAD_I_PAGE;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= IF_BASE_ADR_V;
BASE_BUF_NXT <= IF_BASE_ADR_V;
WE_FLAG_NXT <= '0'; -- bus read
elsif (DC_MISS_I = '1') then -- d-cache miss -> reload cache page
ARB_STATE_NXT <= DOWNLOAD_D_PAGE;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DF_BASE_ADR_V;
BASE_BUF_NXT <= DF_BASE_ADR_V;
WE_FLAG_NXT <= '0'; -- bus read
elsif (IO_ACCESS = '1') and (DC_P_CS_I = '1') then -- IO access
ARB_STATE_NXT <= IO_REQUEST;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DC_P_ADR_I;
WE_FLAG_NXT <= DC_P_WE_I; -- bus read/write
if (STORM_MODE_I = User32_MODE) and (PROTECTED_IO_I = '1') then -- unauthorized?
D_ABORT_O <= '1'; -- abort interrupt
else
ARB_STATE_NXT <= IO_REQUEST;
FREEZE_FLAG_NXT <= '1';
WB_ADR_BUF_NXT <= DC_P_ADR_I;
BIT_BUF_NXT <= DC_P_WE_I; -- bus read/write
end if;
elsif (DC_DIRTY_I = '1') then -- d-cache modification -> copy page to main memory
ARB_STATE_NXT <= ASSIGN_D_PAGE;
PAGE_BUF_NXT <= (others => '1'); -- last entry
WE_FLAG_NXT <= '1'; -- bus write
FREEZE_FLAG_NXT <= '1';
end if;
 
when DOWNLOAD_I_PAGE => -- get new i-cache page
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '1'; -- indicate instruction transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
WB_TGC_O_NXT(5) <= '1'; -- indicate instruction transfer
WB_TGC_O_NXT(6) <= '0'; -- mem access
WB_CTI_O_NXT <= WB_INC_BST_CYC;
WB_CYC_O_NXT <= '1'; -- valid cycle
WB_STB_O_NXT <= '1'; -- valid transfer
WB_WE_O_NXT <= '0'; -- bus read
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (IC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + I_CACHE_PAGE_SIZE*4)) and
(to_integer(unsigned(WB_ACK_CNT)) >= I_CACHE_PAGE_SIZE) then --((WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
if (IC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + (I_CACHE_PAGE_SIZE-1)*4)) and
(to_integer(unsigned(WB_ACK_CNT)) >= I_CACHE_PAGE_SIZE) then
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
elsif (WB_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) - 4 + I_CACHE_PAGE_SIZE*4)) then
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
elsif (WB_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + (I_CACHE_PAGE_SIZE-1)*4)) then
WB_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(WB_ADR_BUF) + 4); -- inc counter
end if;
if (IC_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) + I_CACHE_PAGE_SIZE*4)) and
if (IC_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + I_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then
IC_CS_O <= '1';
IC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(IC_ADR_BUF) + 4); -- inc counter
end if;
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
if (TIMEOUT_CNT > C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
IC_MSS_ACK_O <= '1'; -- ack miss!
I_ABORT_O <= '1';
I_ABORT_O <= '1'; -- abort interrupt
FREEZE_DIS_NXT <= '1';
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
end if;
 
when DOWNLOAD_D_PAGE => -- get new d-cache page
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
DC_WE_O <= '1'; -- cache write access
WB_TGC_O_NXT(5) <= '0'; -- indicate data transfer
WB_TGC_O_NXT(6) <= '0'; -- mem access
WB_CTI_O_NXT <= WB_INC_BST_CYC;
WB_CYC_O_NXT <= '1'; -- valid cycle
WB_STB_O_NXT <= '1'; -- valid transfer
DC_WE_O <= '1'; -- cache write access
WB_WE_O_NXT <= '0'; -- bus read
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (DC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
(to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then --(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
if (DC_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) and
(to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
elsif (WB_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) - 4 + D_CACHE_PAGE_SIZE*4)) then
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
elsif (WB_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
WB_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(WB_ADR_BUF) + 4); -- inc counter
end if;
if (DC_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
if (DC_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + D_CACHE_PAGE_SIZE*4)) and
(WB_ACK_BUF = '1') then
DC_CS_O <= '1';
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc counter
end if;
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
if (TIMEOUT_CNT > C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_MSS_ACK_O <= '1'; -- ack miss!
D_ABORT_O <= '1';
D_ABORT_O <= '1'; -- abort interrupt
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
end if;
 
when IO_REQUEST => -- read/write IO location (single 32-bit word)
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '1'; -- io access
WB_CTI_O <= WB_CLASSIC_CYC;
WB_CYC_O <= '1'; -- valid cycle
WB_STB_O <= '1'; -- valid transfer
WB_TGC_O_NXT(5) <= '0'; -- indicate data transfer
WB_TGC_O_NXT(6) <= '1'; -- io access
WB_CTI_O_NXT <= WB_CLASSIC_CYC;
WB_CYC_O_NXT <= '1'; -- valid cycle
WB_STB_O_NXT <= '1'; -- valid transfer
WB_WE_O_NXT <= BIT_BUF; -- bus read/write
DC_WE_O <= '1'; -- dummy cache write access
DC_ADR_BUF_NXT <= WB_ADR_BUF;
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
if (to_integer(unsigned(WB_ACK_CNT)) >= 1) then --(WB_ACK_BUF = '1') then -- cycle complete?
WB_CTI_O <= WB_BST_END_CYC;
if (to_integer(unsigned(WB_ACK_CNT)) >= 1) then
WB_CTI_O_NXT <= WB_CLASSIC_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
DC_MSS_ACK_O <= '1'; -- ack of pseudo miss signal
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
end if;
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
if (TIMEOUT_CNT > C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O_NXT <= WB_CLASSIC_CYC;
ARB_STATE_NXT <= END_TRANSFER;
DC_DRT_ACK_O <= '1'; -- ack of pseudo dirty signal
DC_MSS_ACK_O <= '1'; -- ack of pseudo miss signal
D_ABORT_O <= '1';
D_ABORT_O <= '1'; -- abort interrupt
FREEZE_DIS_NXT <= '1';
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
end if;
 
when ASSIGN_D_PAGE => -- find dirty pages in cache
417,56 → 453,57
if (DC_D_SEL_I = '1') then -- entry is dirty
DC_ADR_BUF_NXT <= DC_A_SEL_I;
WB_ADR_BUF_NXT <= DC_A_SEL_I;
WORD_BUF_NXT <= DC_A_SEL_I;
BASE_BUF_NXT <= DC_A_SEL_I;
ARB_STATE_NXT <= UPLOAD_D_PAGE;
elsif (to_integer(unsigned(PAGE_BUF)) = 0) then -- all pages analyzed
ARB_STATE_NXT <= END_TRANSFER;
else
PAGE_BUF_NXT <= Std_Logic_Vector(unsigned(PAGE_BUF)-1);
PAGE_BUF_NXT <= Std_Logic_Vector(unsigned(PAGE_BUF)-1);
end if;
 
when UPLOAD_D_PAGE => -- copy d-cache page to main memory
-------------------------------------------------------------------------------
WB_TGC_O(5) <= '0'; -- indicate data transfer
WB_TGC_O(6) <= '0'; -- mem access
WB_CTI_O <= WB_INC_BST_CYC;
WB_CYC_O <= VA_CYC_BUF; -- valid cycle, delayed one cycle
WB_STB_O <= VA_CYC_BUF; -- valid transfer, delayed one cycle
DC_CS_O <= '1'; -- enable data read back
DC_WE_O <= '0'; -- cache read access
WB_TGC_O_NXT(5) <= '0'; -- indicate data transfer
WB_TGC_O_NXT(6) <= '0'; -- mem access
WB_CTI_O_NXT <= WB_INC_BST_CYC;
WB_CYC_O_NXT <= '1'; -- valid cycle, delayed one cycle
WB_STB_O_NXT <= '1'; -- valid transfer, delayed one cycle
WB_WE_O_NXT <= '1'; -- bus write
DC_CS_O <= '1'; -- enable data read back
DC_WE_O <= '0'; -- cache read access
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1);
WB_ADR_BUF_NXT <= DC_ADR_BUF;
VA_CYC_BUF_NXT <= '1';
if (WB_ADR_BUF = Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
if (to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then --(WB_ACK_BUF = '1') then -- cycle complete?
if (WB_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
if (to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then
DC_DRT_ACK_O <= '1'; -- ack of dirty signal
------- if still dirty
WB_CTI_O <= WB_BST_END_CYC;
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= END_TRANSFER;
VA_CYC_BUF_NXT <= '0';
WB_CYC_O_NXT <= '0';
WB_STB_O_NXT <= '0';
end if;
end if;
if (DC_ADR_BUF /= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc pointer
if (DC_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then
DC_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(DC_ADR_BUF) + 4); -- inc mem pointer
WB_ADR_BUF_NXT <= Std_Logic_Vector(unsigned(WB_ADR_BUF) + 4); -- inc wb pointer
end if;
-- Timeout or abnormal cycle termination --
if (TIMEOUT_CNT >= C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O <= WB_BST_END_CYC;
if (TIMEOUT_CNT > C_BUS_CYCC_I) or (WB_ERR_BUF = '1') then
WB_CTI_O_NXT <= WB_BST_END_CYC;
ARB_STATE_NXT <= ASSIGN_D_PAGE;
DC_DRT_ACK_O <= '1'; -- ack dirty signal
D_ABORT_O <= '1';
D_ABORT_O <= '1'; -- abort interrupt
FREEZE_DIS_NXT <= '1';
WB_CYC_O_NXT <= '0'; -- terminate cycle
WB_STB_O_NXT <= '0'; -- terminate cycle
end if;
 
when END_TRANSFER => -- terminate cycle
when END_TRANSFER => -- break between cycles
-------------------------------------------------------------------------------
if (DC_DIRTY_I = '1') then -- another dirty page in cache
ARB_STATE_NXT <= UPLOAD_D_PAGE;
else -- finish transfer
FREEZE_FLAG_NXT <= '0';
FREEZE_DIS_NXT <= '0';
ARB_STATE_NXT <= IDLE;
end if;
WB_ACK_CNT_NXT <= (others => '0');
PAGE_BUF_NXT <= (others => '1'); -- last entry
FREEZE_FLAG_NXT <= '0';
FREEZE_DIS_NXT <= '0';
ARB_STATE_NXT <= IDLE;
 
end case;
end process ARBITER_ASYNC;
/storm_core/trunk/rtl/CORE.vhd
21,7 → 21,7
-- # | -> stnolting@googlemail.com #
-- # | -> stnolting@web.de #
-- # *************************************************************************************************** #
-- # Last modified: 08.03.2012 #
-- # Last modified: 17.03.2012 #
-- #######################################################################################################
 
library IEEE;
70,6 → 70,7
D_CACHE_HIT : in STD_LOGIC; -- d-cache hit
D_CACHE_FRESH : out STD_LOGIC; -- refresh d-cache
D_CACHE_CIO : out STD_LOGIC; -- enable cached IO
IO_PROTECT_O : out STD_LOGIC; -- protected IO
D_CACHE_SYNC : in STD_LOGIC; -- cache is sync
 
-- ###############################################################################################
255,6 → 256,7
IC_MISS_I => I_CACHE_MISS, -- i-cache miss accessear i-cache
C_WTHRU_O => C_WTHRU_O, -- write through
CACHED_IO_O => D_CACHE_CIO, -- en cached IO
PRTCT_IO_O => IO_PROTECT_O, -- protected IO
DC_SYNC_I => D_CACHE_SYNC, -- d-cache is sync
IO_PORT_O => IO_PORT_OUT, -- direct output
IO_PORT_I => IO_PORT_IN, -- direct input
/storm_core/trunk/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and #
-- # system parameters for the STORM Core processor. #
-- # +-------------------------------------------------+ #
-- # Last modified: 08.03.2012 #
-- # Last modified: 17.03.2012 #
-- #######################################################
 
library IEEE;
186,7 → 186,8
constant CSCR0_DAR : natural := 4; -- d-cache "read through"
constant CSCR0_IAR : natural := 5; -- i-cache "read through"
constant CSCR0_CIO : natural := 6; -- enable cached IO
constant CSCR0_DCS : natural := 7; -- d-cache is sync
constant CSCR0_PIO : natural := 7; -- protected IO
constant CSCR0_DCS : natural := 8; -- d-cache is sync
 
constant CSCR0_LFSRE : natural := 13; -- internal LFSR enable
constant CSCR0_LFSRM : natural := 14; -- internal LFSR update mode (0:auto/1:access)
264,11 → 265,12
-- Keith Urban - You Gonna Fly
-- Miranda Lambert - Baggage Claim
-- Diamond Rio - Meet In The Middle
-- Lost Trailers - How 'Bout You Don't
 
-- INTERNAL MNEMONICS ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant L_AND : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- logical and
constant L_XOR : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- logical exclusive or
constant L_XOR : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- logical xor
constant A_SUB : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- sub
constant A_RSB : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- reverse sub
constant A_ADD : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- add
280,12 → 282,12
constant A_CMP : STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- compare by subtraction
constant A_CMN : STD_LOGIC_VECTOR(3 downto 0) := "1011"; -- compare by addition
constant L_OR : STD_LOGIC_VECTOR(3 downto 0) := "1100"; -- logical or
constant L_MOV : STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- pass operant B
constant L_MOV : STD_LOGIC_VECTOR(3 downto 0) := "1101"; -- pass operand B
constant L_BIC : STD_LOGIC_VECTOR(3 downto 0) := "1110"; -- bit clear
constant L_NOT : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- logical not
constant L_NAN : STD_LOGIC_VECTOR(3 downto 0) := "1111"; -- logical nand
constant PassA : STD_LOGIC_VECTOR(3 downto 0) := L_TEQ; -- pass operant A
constant PassB : STD_LOGIC_VECTOR(3 downto 0) := L_MOV; -- pass operant B
constant PassA : STD_LOGIC_VECTOR(3 downto 0) := L_TEQ; -- pass operand A
constant PassB : STD_LOGIC_VECTOR(3 downto 0) := L_MOV; -- pass operand B
constant S_LSL : STD_LOGIC_VECTOR(1 downto 0) := "00"; -- logical shift left
constant S_LSR : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- logical shift right
constant S_ASR : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- arithmetical shift right
332,6 → 334,7
IC_MISS_I : in STD_LOGIC;
C_WTHRU_O : out STD_LOGIC;
CACHED_IO_O : out STD_LOGIC;
PRTCT_IO_O : out STD_LOGIC;
DC_SYNC_I : in STD_LOGIC;
IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0);
IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0);
600,6 → 603,7
I_ABORT_O : out STD_LOGIC;
C_BUS_CYCC_I : in STD_LOGIC_VECTOR(15 downto 0);
CACHED_IO_I : in STD_LOGIC;
PROTECTED_IO_I : in STD_LOGIC;
ADR_FEEDBACK_O : out STD_LOGIC_VECTOR(31 downto 0);
DC_CS_O : out STD_LOGIC;
DC_P_ADR_I : in STD_LOGIC_VECTOR(31 downto 0);
664,6 → 668,7
D_CACHE_HIT : in STD_LOGIC;
D_CACHE_FRESH : out STD_LOGIC;
D_CACHE_CIO : out STD_LOGIC;
IO_PROTECT_O : out STD_LOGIC;
D_CACHE_SYNC : in STD_LOGIC;
I_CACHE_REQ : out STD_LOGIC;
I_CACHE_ADR : out STD_LOGIC_VECTOR(31 downto 0);
/storm_core/trunk/rtl/MC_SYS.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Machine Control System #
-- # *************************************************** #
-- # Last modified: 08.03.2012 #
-- # Last modified: 17.03.2012 #
-- #######################################################
 
library IEEE;
81,6 → 81,7
IC_MISS_I : in STD_LOGIC; -- i-cache miss access
C_WTHRU_O : out STD_LOGIC; -- write through
CACHED_IO_O : out STD_LOGIC; -- en cached IO
PRTCT_IO_O : out STD_LOGIC; -- protected IO
DC_SYNC_I : in STD_LOGIC; -- d-cache is sync
 
-- ###############################################################################################
484,10 → 485,11
if rising_edge(CLK_I) then
if (RST_I = '1') then
CP_REG_FILE <= (others => (others => '0')); -- clear all
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0308"; -- core update date
CP_REG_FILE(CP_ID_REG_0) <= x"07DC0311"; -- core update date
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;)
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_PIO) <= '1'; -- IO area is protected
else
 
-- System Control Register 0 --------------------------------------------------
549,6 → 551,7
DC_CLEAR_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CDC);
DC_FRESH_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_DAR);
CACHED_IO_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIO);
PRTCT_IO_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_PIO);
IC_FRESH_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_IAR);
IC_CLEAR_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CIC);
C_WTHRU_O <= CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_CWT);
594,10 → 597,11
when System32_MODE => MCR_DATA_O <= SMSR_SYS;
when others => MCR_DATA_O <= (others => '0');
end case;
elsif (mrd_cp_v = '1') then
-- elsif (mrd_cp_v = '1') then
else
MCR_DATA_O <= CP_REG_FILE(to_integer(unsigned(CTRL_I(CTRL_CP_REG_3 downto CTRL_CP_REG_0))));
else
MCR_DATA_O <= (others => '0');
-- else
-- MCR_DATA_O <= (others => '0');
end if;
end process MREG_READ_ACCESS;
 
/storm_core/trunk/rtl/OPCODE_DECODER.vhd
3,7 → 3,7
-- # *************************************************** #
-- # ARM-Native OPCODE Decoding Unit #
-- # *************************************************** #
-- # Last modified: 25.01.2012 #
-- # Last modified: 18.03.2012 #
-- #######################################################
 
library IEEE;
114,7 → 114,7
(INSTR_REG(25 downto 4) = "0100101111111111110001") then
-- MULL/MLAL/BX
----------------------------------------------------------------------------------
DEC_CTRL(CTRL_UND) <= '1'; -- not implemented
DEC_CTRL(CTRL_UND) <= '1'; -- not supported/implemented
 
elsif (INSTR_REG(25) = '0') and (INSTR_REG(7) = '1') and (INSTR_REG(4) = '1') then
-- Halfword / Signed Data Transfer
664,7 → 664,7
 
 
 
when others => -- COPROCESSOR INTERFACE / SOFTWARE INTERRUPT
when others => -- COPROCESSOR REGISTER TRANSFER / SOFTWARE INTERRUPT
-- ============================================================================================
DEC_CTRL(CTRL_SWI) <= INSTR_REG(25) and INSTR_REG(24); -- SOFTWARE INTERRUPT
 
685,7 → 685,7
end if;
 
 
else -- COPROCESSOR OPERATION / MEMORY TRANSFER
else -- COPROCESSOR OPERATION / COPROCESSOR MEMORY TRANSFER
----------------------------------------------------------------------------------
DEC_CTRL(CTRL_UND) <= '1'; -- undefined instruction, since not implemented
 
/storm_core/trunk/doc/STORM CORE datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/sim/STORM_core_TB.vhd
18,9 → 18,9
-- Address Map --------------------------------------------------------------------
-- -----------------------------------------------------------------------------------
constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
constant INT_MEM_SIZE_C : natural := 1024; -- bytes
constant INT_MEM_SIZE_C : natural := 1*1024; -- bytes
constant GP_IO_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020";
constant GP_IO_SIZE_C : natural := 8; -- bytes
constant GP_IO_SIZE_C : natural := 2*4; -- two 4-byte registers = 8 bytes
 
 
-- Architecture Constants ---------------------------------------------------------
29,9 → 29,9
constant IO_BEGIN_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020"; -- first addr of IO area
constant IO_END_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE024"; -- last addr of IO area
constant I_CACHE_PAGES_C : natural := 4; -- number of pages in I cache
constant I_CACHE_PAGE_SIZE_C : natural := 32; -- page size in I cache
constant I_CACHE_PAGE_SIZE_C : natural := 16; -- page size in I cache
constant D_CACHE_PAGES_C : natural := 4; -- number of pages in D cache
constant D_CACHE_PAGE_SIZE_C : natural := 2; -- page size in D cache
constant D_CACHE_PAGE_SIZE_C : natural := 4; -- page size in D cache
 
 
-- Global Signals -----------------------------------------------------------------
253,60 → 253,62
-- ### WISHBONE FABRIC ###
-- #################################################################################################################################
 
-- Valid Transfer Signal -------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INT_MEM_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= INT_MEM_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(INT_MEM_BASE_C) + INT_MEM_SIZE_C))) else '0';
GP_IO_CTRL_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= GP_IO_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(GP_IO_BASE_C) + GP_IO_SIZE_C))) else '0';
-- DUMMY0_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= DUMMY0_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(DUMMY0_BASE_C) + DUMMY0_SIZE_C))) else '0';
-- DUMMY1_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= DUMMY1_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(DUMMY1_BASE_C) + DUMMY1_SIZE_C))) else '0';
 
 
-- Read-Back Data Selector -----------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_DATA_I <=
INT_MEM_DATA_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else
GP_IO_CTRL_DATA_O when (CORE_WB_ADR_O(31 downto log2(GP_IO_SIZE_C)) = GP_IO_BASE_C( 31 downto log2(GP_IO_SIZE_C))) else
-- DUMMY0_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else
-- DUMMY1_DATA_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else
INT_MEM_DATA_O when (INT_MEM_STB_I = '1') else
GP_IO_CTRL_DATA_O when (GP_IO_CTRL_STB_I = '1') else
-- DUMMY0_DATA_O when (DUMMY0_STB_I = '1') else
-- DUMMY1_DATA_O when (DUMMY1_STB_I = '1') else
x"00000000";
 
 
-- Use this style of data read-back terminal for pipelined Wishbone systems.
-- You have to ensure, that all not selected IO devices set their data output to 0.
-- CORE_WB_DATA_I <= INT_MEM_DATA_O or
-- GP_IO_CTRL_DATA_O or
-- DUMMY0_DATA_O or
-- DUMMY1_DATA_O or
-- x"00000000";
-- You have to ensure, that all not-selected IO devices set their data output to 0.
-- => Output and-gates controlled by the device's STB_I signal.
-- CORE_WB_DATA_I <= INT_MEM_DATA_O or
-- GP_IO_CTRL_DATA_O or
-- DUMMY0_DATA_O or
-- DUMMY1_DATA_O or
-- '0';
 
 
-- Acknowledge Terminal --------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_ACK_I <= INT_MEM_ACK_O or
GP_IO_CTRL_ACK_O or
-- DUMMY0_ACK_O or
-- DUMMY1_ACK_O or
'0';
CORE_WB_ACK_I <= INT_MEM_ACK_O or
GP_IO_CTRL_ACK_O or
-- DUMMY0_ACK_O or
-- DUMMY1_ACK_O or
'0';
 
 
-- Halt Terminal ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_HALT_I <= INT_MEM_HALT_O or
GP_IO_CTRL_HALT_O or
-- DUMMY0_HALT_O or
-- DUMMY1_HALT_O or
'0';
CORE_WB_HALT_I <= INT_MEM_HALT_O or
GP_IO_CTRL_HALT_O or
-- DUMMY0_HALT_O or
-- DUMMY1_HALT_O or
'0';
 
 
-- Halt Terminal ---------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
CORE_WB_ERR_I <= INT_MEM_ERR_O or
GP_IO_CTRL_ERR_O or
-- DUMMY0_ERR_O or
-- DUMMY1_ERR_O or
'0';
CORE_WB_ERR_I <= INT_MEM_ERR_O or
GP_IO_CTRL_ERR_O or
-- DUMMY0_ERR_O or
-- DUMMY1_ERR_O or
'0';
 
 
-- Valid Transfer Signal Terminal ----------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
INT_MEM_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(INT_MEM_SIZE_C)) = INT_MEM_BASE_C(31 downto log2(INT_MEM_SIZE_C))) else '0';
GP_IO_CTRL_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(GP_IO_SIZE_C)) = GP_IO_BASE_C( 31 downto log2(GP_IO_SIZE_C))) else '0';
-- DUMMY0_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY0_SIZE_C)) = DUMMY0_BASE_C( 31 downto log2(DUMMY0_SIZE_C))) else '0';
-- DUMMY1_STB_I <= CORE_WB_STB_O when (CORE_WB_ADR_O(31 downto log2(DUMMY1_SIZE_C)) = DUMMY1_BASE_C( 31 downto log2(DUMMY1_SIZE_C))) else '0';
 
 
 
-- #################################################################################################################################
-- ### SYSTEM COMPONENTS ###
-- #################################################################################################################################
/storm_core/trunk/software/C/extractor.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/software/C/extractor.exe
storm_core/trunk/software/C/extractor.exe Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: storm_core/trunk/software/C/build/STORMcore-RAM.ld =================================================================== --- storm_core/trunk/software/C/build/STORMcore-RAM.ld (revision 28) +++ storm_core/trunk/software/C/build/STORMcore-RAM.ld (revision 29) @@ -4,13 +4,13 @@ /* */ /***********************************************************************/ ENTRY(_start) -STACK_SIZE = 0x400; +STACK_SIZE = 0x800; /* Memory Definitions */ MEMORY { ROM (rx) : ORIGIN = 0xFFFFF000, LENGTH = 0x00000200 - RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00000800 + RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00001000 } /* Section Definitions */
/storm_core/trunk/software/C/storm_extractor.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/software/C/storm_extractor.exe
storm_core/trunk/software/C/storm_extractor.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/software/C/storm_core.h =================================================================== --- storm_core/trunk/software/C/storm_core.h (revision 28) +++ storm_core/trunk/software/C/storm_core.h (revision 29) @@ -6,7 +6,7 @@ // // Created by Stephan Nolting (stnolting@googlemail.com) // http://www.opencores.com/project,storm_core -// Last modified 08. Mar. 2012 +// Last modified 13. Mar. 2012 //////////////////////////////////////////////////////////////////////////////// /* Internal System Coprocessor Register Set */ @@ -16,7 +16,7 @@ #define ID_REG_2 2 // ID register 2 #define SYS_CTRL_0 6 // system control register 0 #define CSTAT 8 // cache statistics register -#define ADR_FB 9 // adr feedback from bus unit -> for exception handling +#define ADR_FB 9 // adr feedback from bus unit -> for exception analysis #define LFSR_POLY 11 // Internal LFSR, polynomial #define LFSR_DATA 12 // Internal LFSR, shift register #define SYS_IO 13 // System IO ports @@ -28,6 +28,9 @@ #define DC_WTHRU 3 // cache write-thru enable #define DC_AUTOPR 4 // auto pre-reload d-cache page #define IC_AUTOPR 5 // auto pre-reload i-cache page +#define CACHED_IO 6 // cached IO +#define PRTC_IO 7 // protected IO +#define DC_SYNC 8 // d-cache is sync #define LFSR_EN 13 // enable lfsr #define LFSR_M 14 // lfsr update mode #define LFSR_D 15 // lfsr shift direction
/storm_core/trunk/software/C/storm_program.dat Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/storm_core/trunk/software/C/storm_program.dat
storm_core/trunk/software/C/storm_program.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: storm_core/trunk/software/C/main.c =================================================================== --- storm_core/trunk/software/C/main.c (revision 28) +++ storm_core/trunk/software/C/main.c (revision 29) @@ -6,11 +6,15 @@ This program outputs the first 30 Fibonacci numbers on the IO.O port. + Afterwards it restarts. + + The program is allready loaded + into the MEMORY.vhd test component. ----------------------------------------*/ -#define REG32 (volatile unsigned int*) /* ---- IO Device Locations ---- */ +#define REG32 (volatile unsigned int*) #define GPIO_OUT (*(REG32 (0xFFFFFE020))) #define GPIO_IN (*(REG32 (0xFFFFFE024))) @@ -17,7 +21,7 @@ int main(void) { - int i, num_a, num_b, tmp; + int i, num_a, num_b, tmp = 0; GPIO_OUT = 0; // clear output
/storm_core/trunk/software/C/storm_program.txt
0,0 → 1,98
000000 => x"EA000012",
000001 => x"E59FF014",
000002 => x"E59FF014",
000003 => x"E59FF014",
000004 => x"E59FF014",
000005 => x"E1A00000",
000006 => x"E51FFFF0",
000007 => x"E59FF010",
000008 => x"00000038",
000009 => x"0000003C",
000010 => x"00000040",
000011 => x"00000044",
000012 => x"00000048",
000013 => x"0000004C",
000014 => x"EAFFFFFE",
000015 => x"EAFFFFFE",
000016 => x"EAFFFFFE",
000017 => x"EAFFFFFE",
000018 => x"EAFFFFFE",
000019 => x"EAFFFFFE",
000020 => x"E59F00C8",
000021 => x"E10F1000",
000022 => x"E3C1107F",
000023 => x"E38110DB",
000024 => x"E129F001",
000025 => x"E1A0D000",
000026 => x"E2400080",
000027 => x"E10F1000",
000028 => x"E3C1107F",
000029 => x"E38110D7",
000030 => x"E129F001",
000031 => x"E1A0D000",
000032 => x"E2400080",
000033 => x"E10F1000",
000034 => x"E3C1107F",
000035 => x"E38110D1",
000036 => x"E129F001",
000037 => x"E1A0D000",
000038 => x"E2400080",
000039 => x"E10F1000",
000040 => x"E3C1107F",
000041 => x"E38110D2",
000042 => x"E129F001",
000043 => x"E1A0D000",
000044 => x"E2400080",
000045 => x"E10F1000",
000046 => x"E3C1107F",
000047 => x"E38110D3",
000048 => x"E129F001",
000049 => x"E1A0D000",
000050 => x"E2400080",
000051 => x"E10F1000",
000052 => x"E3C1107F",
000053 => x"E38110DF",
000054 => x"E129F001",
000055 => x"E1A0D000",
000056 => x"E3A00000",
000057 => x"E59F1038",
000058 => x"E59F2038",
000059 => x"E1510002",
000060 => x"0A000001",
000061 => x"34810004",
000062 => x"3AFFFFFB",
000063 => x"E3A00000",
000064 => x"E1A01000",
000065 => x"E1A02000",
000066 => x"E1A0B000",
000067 => x"E1A07000",
000068 => x"E59FA014",
000069 => x"E1A0E00F",
000070 => x"E1A0F00A",
000071 => x"EAFFFFFE",
000072 => x"00000A00",
000073 => x"00000184",
000074 => x"00000184",
000075 => x"00000130",
000076 => x"E3E03A01",
000077 => x"E3A02000",
000078 => x"E52DE004",
000079 => x"E5032FDF",
000080 => x"E3A0E001",
000081 => x"E5032FDF",
000082 => x"E1A0100E",
000083 => x"E1A0000E",
000084 => x"E1A02000",
000085 => x"EA000000",
000086 => x"E3A0E001",
000087 => x"E2820001",
000088 => x"E08EC001",
000089 => x"E5031FDF",
000090 => x"E350001E",
000091 => x"E3A01000",
000092 => x"E1A02001",
000093 => x"CAFFFFF7",
000094 => x"E1A0100E",
000095 => x"E1A0E00C",
000096 => x"EAFFFFF2",
others => x"F0013007"
/storm_core/trunk/software/C/Makefile
257,7 → 257,7
# Default target.
all: begin gccversion sizebefore build sizeafter finished cmp end
 
build: elf hex lss sym
build: elf hex lss
 
elf: $(TARGET).elf
hex: $(TARGET).hex
268,7 → 268,7
cmp:
@echo
@echo $(MSG_EXTRACT)
extractor.exe $(TARGET).elf
storm_extractor.exe $(TARGET).elf
@echo
 
 
401,8 → 401,8
$(REMOVE) $(TARGET).lnk
$(REMOVE) $(TARGET).lss
$(REMOVE) a.out
$(REMOVE) mnemonic.txt
$(REMOVE) mnemonic.dat
$(REMOVE) storm_program.txt
$(REMOVE) storm_program.dat
$(REMOVE) $(COBJ)
$(REMOVE) $(CPPOBJ)
$(REMOVE) $(AOBJ)

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