URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/storm_core/trunk/rtl/CACHE.vhd
82,9 → 82,6
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architecture Behavioral of CACHE is |
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-- Is Simulation? -- |
constant IS_SIM : boolean := TRUE; |
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-- Cache Arbiter -- |
type ARB_STATE_TYPE is (STORM_ACCESS, MISS_STATE, IO_REQUEST, IO_PIPE_RESYNC, IO_PIPE_RESYNC_END, DIRTY_STATE, PIPE_RESYNC); |
signal ARB_STATE, ARB_STATE_NXT : ARB_STATE_TYPE; |
552,11 → 549,11
end if; |
end process CACHE_ACCESS; |
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-- Dummy for simulation -- |
GEN_DEBUG_MEM: |
for i in 0 to (CACHE_PAGES*PAGE_SIZE)-1 generate |
SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i) when (IS_SIM = TRUE) else x"00000000"; |
end generate; |
-- Dummy cache-memory, for simulation only!!! -- |
-- GEN_DEBUG_MEM: |
-- for i in 0 to (CACHE_PAGES*PAGE_SIZE)-1 generate |
-- SIM_MEM(i) <= CACHE_MEM_HH(i) & CACHE_MEM_HL(i) & CACHE_MEM_LH(i) & CACHE_MEM_LL(i); |
-- end generate; |
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/storm_core/trunk/rtl/BUS_UNIT.vhd
218,7 → 218,7
DC_P_ADR_BUF <= (others => '0'); |
IC_P_ADR_BUF <= (others => '0'); |
WB_DATA_FF <= (others => '0'); |
WB_ADR_O <= (others => '0'); |
WB_ADR_O <= (others => '0'); |
WB_CTI_O <= (others => '0'); |
WB_TGC_O <= (others => '0'); |
WB_STB_O <= '0'; |
234,15 → 234,16
TIMEOUT_CNT <= TIMEOUT_CNT_NXT; |
DC_P_ADR_BUF <= DC_P_ADR_I; |
IC_P_ADR_BUF <= IC_P_ADR_I; |
WB_DATA_FF <= WB_DATA_FF_NXT; |
WB_ADR_O <= WB_ADR_BUF; |
WB_CTI_O <= WB_CTI_O_NXT; |
WB_TGC_O <= WB_TGC_O_NXT; |
WB_STB_O <= WB_STB_O_NXT; |
WB_CYC_O <= WB_CYC_O_NXT; |
WB_WE_O <= WB_WE_O_NXT; |
if (WB_HALT_I = '0') then |
WB_DATA_FF <= WB_DATA_FF_NXT; |
WB_ADR_O <= WB_ADR_BUF; |
WB_CTI_O <= WB_CTI_O_NXT; |
WB_TGC_O <= WB_TGC_O_NXT; |
WB_STB_O <= WB_STB_O_NXT; |
WB_CYC_O <= WB_CYC_O_NXT; |
WB_WE_O <= WB_WE_O_NXT; |
-- Bus interface -- |
if (WB_HALT_I = '0') then |
--if (WB_HALT_I = '0') then |
-- Wishbone Sync -- |
WB_DATA_BUF <= WB_DATA_I; |
WB_ACK_BUF <= WB_ACK_I; |
475,11 → 476,11
TIMEOUT_CNT_NXT <= Std_Logic_Vector(unsigned(TIMEOUT_CNT) + 1); |
if (WB_ADR_BUF >= Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then |
if (to_integer(unsigned(WB_ACK_CNT)) >= D_CACHE_PAGE_SIZE) then |
DC_DRT_ACK_O <= '1'; -- ack of dirty signal |
WB_CTI_O_NXT <= WB_BST_END_CYC; |
ARB_STATE_NXT <= END_TRANSFER; |
WB_CYC_O_NXT <= '0'; |
WB_STB_O_NXT <= '0'; |
WB_STB_O_NXT <= '0'; |
WB_CTI_O_NXT <= WB_BST_END_CYC; |
DC_DRT_ACK_O <= '1'; -- ack of dirty signal |
end if; |
end if; |
if (DC_ADR_BUF < Std_Logic_Vector(unsigned(BASE_BUF) + (D_CACHE_PAGE_SIZE-1)*4)) then |
/storm_core/trunk/doc/STORM CORE datasheet.pdf
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