URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/storm_core/trunk/rtl/CORE_PKG.vhd
5,7 → 5,7
-- # This file contains all needed components and # |
-- # system parameters for the STORM Core processor. # |
-- # +-------------------------------------------------+ # |
-- # Last modified: 17.03.2012 # |
-- # Last modified: 29.03.2012 # |
-- ####################################################### |
|
library IEEE; |
128,8 → 128,10
constant CTRL_SHIFT_V_3 : natural := 44; -- shift value bit 3 |
constant CTRL_SHIFT_V_4 : natural := 45; -- shift value bit 4 |
|
constant CTRL_MSB : natural := 45; -- size of control bus |
constant CTRL_BX : natural := 46; -- is branch and exchange operation |
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constant CTRL_MSB : natural := 46; -- size of control bus |
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-- Progress Redefinitions -- |
constant CTRL_MODE_0 : natural := CTRL_AF; -- mode bit 0 |
constant CTRL_MODE_1 : natural := CTRL_ALU_FS_0; -- mode bit 1 |
/storm_core/trunk/rtl/MC_SYS.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # Machine Control System # |
-- # *************************************************** # |
-- # Last modified: 27.03.2012 # |
-- # Last modified: 29.03.2012 # |
-- ####################################################### |
|
library IEEE; |
130,6 → 130,7
signal IAB_TAKEN_NXT : STD_LOGIC; |
signal DAB_TAKEN_NXT : STD_LOGIC; |
signal DIS_CYCLE_OK : STD_LOGIC; |
signal INVALID_BX_REQ : STD_LOGIC; |
|
-- Coprocessor Signals -- |
signal INVALID_CP_ACC : STD_LOGIC; |
226,7 → 227,7
-- Software Interrupt Trap taken -- |
SWI_TAKEN <= CTRL_I(CTRL_EN) and CTRL_I(CTRL_SWI); |
-- Undefined Instruction Trap taken -- |
UND_TAKEN <= CTRL_I(CTRL_EN) and (CTRL_I(CTRL_UND) or INVALID_CP_ACC); |
UND_TAKEN <= CTRL_I(CTRL_EN) and (CTRL_I(CTRL_UND) or INVALID_CP_ACC or INVALID_BX_REQ); |
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|
|
254,7 → 255,8
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-- Interrupt Handler System ----------------------------------------------------------------------- |
-- --------------------------------------------------------------------------------------------------- |
INT_HANDLER: process(MCR_CMSR, FLAG_I, FIQ_TAKEN, IRQ_TAKEN, DAB_TAKEN, IAB_TAKEN, SWI_TAKEN, UND_TAKEN) |
INT_HANDLER: process(MCR_CMSR, FLAG_I, FIQ_TAKEN, IRQ_TAKEN, DAB_TAKEN, |
IAB_TAKEN, SWI_TAKEN, UND_TAKEN, CTRL_I, MCR_DATA_I) |
begin |
-- default values -- |
CONT_EXE <= '1'; |
268,6 → 270,15
FLAG_BUS(SREG_DAB_DIS) <= MCR_CMSR(SREG_DAB_DIS); -- keep current interrupt settings |
FLAG_BUS(SREG_IAB_DIS) <= MCR_CMSR(SREG_IAB_DIS); -- keep current interrupt settings |
|
--- Short Instruction Mode --- |
if (CTRL_I(CTRL_EN) = '1') and (CTRL_I(CTRL_BX) = '1') and (SHIN_EN = TRUE) then |
FLAG_BUS(SREG_SHIN_M) <= MCR_DATA_I(0); |
INVALID_BX_REQ <= MCR_DATA_I(0); |
else |
FLAG_BUS(SREG_SHIN_M) <= MCR_CMSR(0); |
INVALID_BX_REQ <= '0'; |
end if; |
|
--- Priority 1: Data Fetch Abort --- |
if (DAB_TAKEN = '1') then |
INT_VEC <= DAT_INT_VEC; |
346,13 → 357,13
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
MCR_PC <= BOOT_VEC; -- start-up address |
MCR_CMSR <= x"000003DF"; -- INTs disabled and we're in SYSTEM32 mode |
SMSR_FIQ <= x"000003D0"; -- INTs disabled and return to USER32 mode |
SMSR_SVC <= x"000003D0"; -- INTs disabled and return to USER32 mode |
SMSR_ABT <= x"000003D0"; -- INTs disabled and return to USER32 mode |
SMSR_IRQ <= x"000003D0"; -- INTs disabled and return to USER32 mode |
SMSR_UND <= x"000003D0"; -- INTs disabled and return to USER32 mode |
SMSR_SYS <= x"000003D0"; -- INTs disabled and return to USER32 mode |
MCR_CMSR <= x"000003DF"; -- all INTs disabled and we're in SYSTEM32 mode |
SMSR_FIQ <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_SVC <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_ABT <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_IRQ <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_UND <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
SMSR_SYS <= x"000003D0"; -- all INTs disabled and return to USER32 mode |
elsif (G_HALT_I = '0') then |
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|
378,8 → 389,7
cmsr_acc_case_v := CONT_EXE & CTRL_I(CTRL_EN) & cont_ret_v & mwr_cmsr_v; |
case cmsr_acc_case_v is |
when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" => |
MCR_CMSR(4 downto 0) <= FLAG_BUS(4 downto 0); -- mode bits |
MCR_CMSR(9 downto 6) <= FLAG_BUS(9 downto 6); -- interrupt disable bits |
MCR_CMSR(9 downto 0) <= FLAG_BUS(9 downto 0); -- interrupt de, ctrl, mode bits |
when "0110" | "0111" => -- context down change |
case (current_mode_v) is -- current mode |
when FIQ32_MODE => MCR_CMSR <= SMSR_FIQ; |
485,7 → 495,7
if rising_edge(CLK_I) then |
if (RST_I = '1') then |
CP_REG_FILE <= (others => (others => '0')); -- clear all |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC031B"; -- core update date |
CP_REG_FILE(CP_ID_REG_0) <= x"07DC031D"; -- core update date |
CP_REG_FILE(CP_ID_REG_1) <= x"53744E6F"; -- My ID |
CP_REG_FILE(CP_ID_REG_2) <= x"34373838"; -- My ID ;) |
CP_REG_FILE(CP_SYS_CTRL_0)(CSCR0_MBC_15 downto CSCR0_MBC_0) <= x"0100"; -- max cycle length |
/storm_core/trunk/rtl/OPCODE_DECODER.vhd
3,7 → 3,7
-- # *************************************************** # |
-- # ARM-Native OPCODE Decoding Unit # |
-- # *************************************************** # |
-- # Last modified: 28.03.2012 # |
-- # Last modified: 29.03.2012 # |
-- ####################################################### |
|
library IEEE; |
94,7 → 94,7
--- INSTRUCTION CLASS DECODER --- |
case INSTR_REG(27 downto 26) is |
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when "00" => -- ALU DATA PROCESSING / SREG ACCESS / MUL(MAC) / BX / SWP / (S/U/HW/B) MEM ACCESS |
when "00" => -- ALU DATA PROCESSING / SREG ACCESS / MUL(MAC) / MULL/MLAL / BX / SWP / (S/U/HW/B) MEM ACCESS |
-- =================================================================================== |
if (INSTR_REG(25 downto 22) = "0000") and (INSTR_REG(7 downto 4) = "1001") then |
-- MUL/MAC |
115,12 → 115,20
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassB; |
end if; |
|
elsif ((INSTR_REG(25 downto 23) = "001") and (INSTR_REG(7 downto 4) = "1001")) or |
(INSTR_REG(25 downto 4) = "0100101111111111110001") then |
-- MULL/MLAL/BX |
elsif (INSTR_REG(25 downto 23) = "001") and (INSTR_REG(7 downto 4) = "1001") then |
-- MULL/MLAL |
---------------------------------------------------------------------------------- |
DEC_CTRL(CTRL_UND) <= '1'; -- not supported/implemented |
|
elsif (INSTR_REG(25 downto 4) = "0100101111111111110001") then |
-- Branch and Exchange (BX) |
---------------------------------------------------------------------------------- |
DEC_CTRL(CTRL_BX) <= '1'; -- is bx instruction |
DEC_CTRL(CTRL_BRANCH) <= '1'; -- BRANCH_INSTR |
OP_ADR_OUT(OP_B_ADR_3 downto OP_B_ADR_0) <= INSTR_REG(03 downto 00); |
DEC_CTRL(CTRL_ALU_FS_3 downto CTRL_ALU_FS_0) <= PassB; |
REG_SEL(OP_B_IS_REG) <= '1'; |
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elsif (INSTR_REG(25) = '0') and (INSTR_REG(7) = '1') and (INSTR_REG(4) = '1') then |
-- Halfword / Signed Data Transfer |
---------------------------------------------------------------------------------- |
670,7 → 678,7
end if; |
end if; |
|
-- zhe lonely address inc -- |
-- the lonely address inc -- |
IMM_OUT(31 downto 0) <= x"000000" & '0' & adr_offs_v & "00"; -- auto offset |
|
end if; |
/storm_core/trunk/doc/STORM CORE datasheet.pdf
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