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  • This comparison shows the changes necessary to convert path
    /
    from Rev 33 to Rev 34
    Reverse comparison

Rev 33 → Rev 34

/storm_core/trunk/rtl/ALU.vhd
3,7 → 3,7
-- # *************************************************** #
-- # Arithmetical/Logical/MCR_Access Unit #
-- # *************************************************** #
-- # Last modified: 26.03.2012 #
-- # Last modified: 04.04.2012 #
-- #######################################################
 
library IEEE;
130,7 → 130,7
ALU_OUT <= OP_A xor OP_B;
when L_NOT => -- NOT: result = not(OP_A AND OP_B)
if (STORM_MODE = TRUE) then
ALU_OUT <= not(OP_A and OP_B);
ALU_OUT <= not(OP_A and OP_B); -- STORM_OP: NOT
else
ALU_OUT <= not OP_B; -- ARM_OP: MVN
end if;
231,12 → 231,18
FLAG_O(1) <= is_xor_zero_v;
FLAG_O(2) <= OP_A(31) xor OP_B(31);
FLAG_O(3) <= MS_OVFL_REG;
-- Arithmetical Operations & Compares --
when others =>
FLAG_O(0) <= CARRY_OUT;
-- Arithmetical Sub Operations & Compare --
when A_SUB | A_RSB | A_SBC | A_RSC | A_CMP =>
FLAG_O(0) <= not CARRY_OUT; -- borrow flag
FLAG_O(1) <= is_add_zero_v;
FLAG_O(2) <= ADDER_RES(31);
FLAG_O(3) <= MS_OVFL_REG or OVFL_OUT; --(ADDER_RES(31) and (OP_A(31) xnor OP_B(31))) or MS_OVFL_REG
-- Arithmetical Add Operations & Compare --
when others => -- A_ADD | A_ADC | A_CMN
FLAG_O(0) <= CARRY_OUT; -- carry flag
FLAG_O(1) <= is_add_zero_v;
FLAG_O(2) <= ADDER_RES(31);
FLAG_O(3) <= MS_OVFL_REG or OVFL_OUT; --(ADDER_RES(31) and (OP_A(31) xnor OP_B(31))) or MS_OVFL_REG
end case;
end process ALU_FLAG_LOGIC;
 
/storm_core/trunk/rtl/STORM_TOP.vhd
37,10 → 37,10
-- ## System Architecture Configuration ##
-- ###############################################################################################
 
I_CACHE_PAGES : natural := 4; -- number of pages in I cache
I_CACHE_PAGES : natural := 8; -- number of pages in I cache
I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
D_CACHE_PAGES : natural := 8; -- number of pages in D cache
D_CACHE_PAGE_SIZE : natural := 1; -- page size in D cache
D_CACHE_PAGE_SIZE : natural := 32; -- page size in D cache
BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; -- boot address
IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; -- io begin address
IO_UC_END : STD_LOGIC_VECTOR(31 downto 0) := x"00000000" -- io end address

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