URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/storm_core/trunk/rtl/ALU.vhd
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/storm_core/trunk/rtl/STORM_TOP.vhd
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/storm_core/trunk/rtl/OPERAND_UNIT.vhd
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/storm_core/trunk/rtl/CORE.vhd
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/storm_core/trunk/rtl/BUS_UNIT.vhd
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/storm_core/trunk/rtl/CORE_PKG.vhd
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/storm_core/trunk/rtl/LOAD_STORE_UNIT.vhd
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/storm_core/trunk/rtl/BARREL_SHIFTER.vhd
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/storm_core/trunk/rtl/FLOW_CTRL.vhd
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/storm_core/trunk/rtl/MC_SYS.vhd
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/storm_core/trunk/rtl/OPCODE_DECODER.vhd
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/storm_core/trunk/rtl/CACHE.vhd
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/storm_core/trunk/rtl/WB_UNIT.vhd
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/storm_core/trunk/rtl/REG_FILE.vhd
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/storm_core/trunk/rtl/MULTIPLY_UNIT.vhd
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/storm_core/trunk/rtl/MS_UNIT.vhd
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/storm_core/trunk/doc/wbspec_b4.pdf
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/storm_core/trunk/doc/STORM CORE datasheet.pdf
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storm_core/trunk/doc/STORM CORE datasheet.pdf
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Index: storm_core/trunk/software/ASM/make.bat
===================================================================
--- storm_core/trunk/software/ASM/make.bat (revision 36)
+++ storm_core/trunk/software/ASM/make.bat (nonexistent)
@@ -1,3 +0,0 @@
-@echo off
-arm-elf-as.exe -EB -mapcs-32 main.asm
-extract.exe
\ No newline at end of file
Index: storm_core/trunk/software/ASM/main.asm
===================================================================
--- storm_core/trunk/software/ASM/main.asm (revision 36)
+++ storm_core/trunk/software/ASM/main.asm (nonexistent)
@@ -1,41 +0,0 @@
-/* ### DEMO PROGRAM: FIBONACCI NUMBERS ###
----------------------------------------------
- Calculates and stores the first 30 Fibonacci
- numbers and stores them in the internal memory,
- starting at word location 25 (byte loaction 100). */
-
-.include "macro.inc"
-
-/*-----------------------------------------------------
- Exception Vectors
------------------------------------------------------*/
-
-Vectors: BAL Reset /* Hardware Reset */
- NOP /* Undef Instruction */
- NOP /* Software INT */
- NOP /* Prefetch Abort */
- NOP /* Data Abort */
- NOP /* Reserved */
- NOP /* HW INT req */
- NOP /* Fast HW INT req */
-
-/*-----------------------------------------------------
- Reset Handler
------------------------------------------------------*/
-
-Reset: MOV R0, #0 /* A */
- MOV R1, #1 /* B */
- MOV R2, #0 /* C */
- MOV R3, #100 /* mem area to place results */
-
-LOOP: CMP R3, #220
- BEQ NIRVANA
-
- STR R0, [R3], #4
- ADD R2, R0, R1
- MOV R0, R1
- MOV R1, R2
-
- BAL LOOP
-
-NIRVANA: BAL NIRVANA
Index: storm_core/trunk/software/ASM/arm-elf-as.exe
===================================================================
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Index: storm_core/trunk/software/ASM/arm-elf-as.exe
===================================================================
--- storm_core/trunk/software/ASM/arm-elf-as.exe (revision 36)
+++ storm_core/trunk/software/ASM/arm-elf-as.exe (nonexistent)
storm_core/trunk/software/ASM/arm-elf-as.exe
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-application/octet-stream
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Index: storm_core/trunk/software/ASM/macro.inc
===================================================================
--- storm_core/trunk/software/ASM/macro.inc (revision 36)
+++ storm_core/trunk/software/ASM/macro.inc (nonexistent)
@@ -1,40 +0,0 @@
-@ ###########################################
-@ # STORM CORE Processor assembler macros #
-@ # +-------------------------------------+ #
-@ # Version 1.0, 06.09.2011 #
-@ ###########################################
-
-@ Return from subroutine
-.macro RET
- MOV PC, LR
-.endm
-
-@ Return from exception
-.macro RETI
- MOVS PC, LR
-.endm
-
-@ Push register on stack
-.macro PUSH REG
- STR ®, [SP], #-4
-.endm
-
-@ Pop register from stack
-.macro POP REG
- LDR ®, [SP, #+4]!
-.endm
-
-@ Simple increment
-.macro INC REG
- ADD ®, ®, #1
-.endm
-
-@ Simple decrement
-.macro DEC REG
- SUB ®, ®, #1
-.endm
-
-@ Clear register
-.macro CLR REG
- XOR ®, ®,& REG
-.endm
Index: storm_core/trunk/software/ASM/extract.exe
===================================================================
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Index: storm_core/trunk/software/ASM/extract.exe
===================================================================
--- storm_core/trunk/software/ASM/extract.exe (revision 36)
+++ storm_core/trunk/software/ASM/extract.exe (nonexistent)
storm_core/trunk/software/ASM/extract.exe
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Index: storm_core/trunk/software/C/storm_program.txt
===================================================================
--- storm_core/trunk/software/C/storm_program.txt (revision 36)
+++ storm_core/trunk/software/C/storm_program.txt (nonexistent)
@@ -1,98 +0,0 @@
-000000 => x"EA000012",
-000001 => x"E59FF014",
-000002 => x"E59FF014",
-000003 => x"E59FF014",
-000004 => x"E59FF014",
-000005 => x"E1A00000",
-000006 => x"E51FFFF0",
-000007 => x"E59FF010",
-000008 => x"00000038",
-000009 => x"0000003C",
-000010 => x"00000040",
-000011 => x"00000044",
-000012 => x"00000048",
-000013 => x"0000004C",
-000014 => x"EAFFFFFE",
-000015 => x"EAFFFFFE",
-000016 => x"EAFFFFFE",
-000017 => x"EAFFFFFE",
-000018 => x"EAFFFFFE",
-000019 => x"EAFFFFFE",
-000020 => x"E59F00C8",
-000021 => x"E10F1000",
-000022 => x"E3C1107F",
-000023 => x"E38110DB",
-000024 => x"E129F001",
-000025 => x"E1A0D000",
-000026 => x"E2400080",
-000027 => x"E10F1000",
-000028 => x"E3C1107F",
-000029 => x"E38110D7",
-000030 => x"E129F001",
-000031 => x"E1A0D000",
-000032 => x"E2400080",
-000033 => x"E10F1000",
-000034 => x"E3C1107F",
-000035 => x"E38110D1",
-000036 => x"E129F001",
-000037 => x"E1A0D000",
-000038 => x"E2400080",
-000039 => x"E10F1000",
-000040 => x"E3C1107F",
-000041 => x"E38110D2",
-000042 => x"E129F001",
-000043 => x"E1A0D000",
-000044 => x"E2400080",
-000045 => x"E10F1000",
-000046 => x"E3C1107F",
-000047 => x"E38110D3",
-000048 => x"E129F001",
-000049 => x"E1A0D000",
-000050 => x"E2400080",
-000051 => x"E10F1000",
-000052 => x"E3C1107F",
-000053 => x"E38110DF",
-000054 => x"E129F001",
-000055 => x"E1A0D000",
-000056 => x"E3A00000",
-000057 => x"E59F1038",
-000058 => x"E59F2038",
-000059 => x"E1510002",
-000060 => x"0A000001",
-000061 => x"34810004",
-000062 => x"3AFFFFFB",
-000063 => x"E3A00000",
-000064 => x"E1A01000",
-000065 => x"E1A02000",
-000066 => x"E1A0B000",
-000067 => x"E1A07000",
-000068 => x"E59FA014",
-000069 => x"E1A0E00F",
-000070 => x"E1A0F00A",
-000071 => x"EAFFFFFE",
-000072 => x"00000A00",
-000073 => x"00000184",
-000074 => x"00000184",
-000075 => x"00000130",
-000076 => x"E3E03A01",
-000077 => x"E3A02000",
-000078 => x"E52DE004",
-000079 => x"E5032FDF",
-000080 => x"E3A0E001",
-000081 => x"E5032FDF",
-000082 => x"E1A0100E",
-000083 => x"E1A0000E",
-000084 => x"E1A02000",
-000085 => x"EA000000",
-000086 => x"E3A0E001",
-000087 => x"E2820001",
-000088 => x"E08EC001",
-000089 => x"E5031FDF",
-000090 => x"E350001E",
-000091 => x"E3A01000",
-000092 => x"E1A02001",
-000093 => x"CAFFFFF7",
-000094 => x"E1A0100E",
-000095 => x"E1A0E00C",
-000096 => x"EAFFFFF2",
-others => x"F0013007"
Index: storm_core/trunk/software/C/Makefile
===================================================================
--- storm_core/trunk/software/C/Makefile (revision 36)
+++ storm_core/trunk/software/C/Makefile (nonexistent)
@@ -1,431 +0,0 @@
-# Hey Emacs, this is a -*- makefile -*-
-#
-# WinARM template makefile
-# by Martin Thomas, Kaiserslautern, Germany
-#
-#
-# based on the WinAVR makefile written by Eric B. Weddington, Jörg Wunsch, et al.
-# Released to the Public Domain
-# Please read the make user manual!
-#
-#
-# On command line:
-#
-# make all = Make software.
-#
-# make clean = Clean out built project files.
-#
-# make program = Download the hex file to the device, using lpc21isp
-#
-# (TODO: make filename.s = Just compile filename.c into the assembler code only)
-#
-# To rebuild project do "make clean" then "make all".
-#
-# Changelog:
-# - 17. Feb. 2005 - added thumb-interwork support (mth)
-# - 28. Apr. 2005 - added C++ support (mth)
-# - 29. Arp. 2005 - changed handling for lst-Filename (mth)
-# - 22. Jan. 2012 - modified to handle storm core project
-#
-
-# MCU name and submodel
-MCU = arm7m
-SUBMDL = STORMcore
-
-
-THUMB =
-THUMB_IW =
-
-
-## Create RAM-Image
-RUN_MODE = RAM_RUN
-
-
-# Output format. (can be srec, ihex, binary)
-FORMAT = ihex
-
-
-# Target file name (without extension).
-TARGET = main
-
-
-# List C source files here. (C dependencies are automatically generated.)
-# use file-extension c for "c-only"-files
-#SRC =
-
-# List C source files here which must be compiled in ARM-Mode.
-# use file-extension c for "c-only"-files
-SRCARM = $(TARGET).c
-
-# List C++ source files here.
-# use file-extension cpp for C++-files
-CPPSRC =
-
-# List C++ source files here which must be compiled in ARM-Mode.
-# use file-extension cpp for C++-files
-# CPPSRCARM = $(TARGET).cpp
-CPPSRCARM =
-
-# List Assembler source files here.
-# Make them always end in a capital .S. Files ending in a lowercase .s
-# will not be considered source files but generated files (assembler
-# output from the compiler), and will be deleted upon "make clean"!
-# Even though the DOS/Win* filesystem matches both .s and .S the same,
-# it will preserve the spelling of the filenames, and gcc itself does
-# care about how the name is spelled on its command-line.
-ASRC =
-
-# List Assembler source files here which must be assembled in ARM-Mode..
-ASRCARM = build/storm_startup_code.S
-
-# Optimization level, can be [0, 1, 2, 3, s].
-# 0 = turn off optimization. s = optimize for size.
-# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
-OPT = 2
-
-# Debugging format.
-# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2.
-# AVR (extended) COFF requires stabs, plus an avr-objcopy run.
-#DEBUG = stabs
-DEBUG = dwarf-2
-
-# List any extra directories to look for include files here.
-# Each directory must be seperated by a space.
-#EXTRAINCDIRS = ./include
-EXTRAINCDIRS =
-
-# Compiler flag to set the C Standard level.
-# c89 - "ANSI" C
-# gnu89 - c89 plus GCC extensions
-# c99 - ISO C99 standard (not yet fully implemented)
-# gnu99 - c99 plus GCC extensions
-CSTANDARD = -std=gnu99
-
-# Place -D or -U options for C here
-CDEFS = -D$(RUN_MODE)
-
-# Place -I options here
-CINCS =
-
-# Place -D or -U options for ASM here
-ADEFS = -D$(RUN_MODE)
-
-
-# Compiler flags.
-# -g*: generate debugging information
-# -O*: optimization level
-# -f...: tuning, see GCC manual and avr-libc documentation
-# -Wall...: warning level
-# -Wa,...: tell GCC to pass this to the assembler.
-# -adhlns...: create assembler listing
-#
-# Flags for C and C++ (arm-elf-gcc/arm-elf-g++)
-CFLAGS = -g$(DEBUG)
-CFLAGS += $(CDEFS) $(CINCS)
-CFLAGS += -O$(OPT)
-CFLAGS += -Wall -Wcast-align -Wcast-qual -Wimplicit
-CFLAGS += -Wpointer-arith -Wswitch
-CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused
-#CFLAGS += -Wa,-adhlns=$(<:.c=.lst)
-CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<)
-CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
-
-# flags only for C
-CONLYFLAGS = -Wstrict-prototypes -Wmissing-declarations
-CONLYFLAGS += -Wmissing-prototypes -Wnested-externs
-CONLYFLAGS += $(CSTANDARD)
-
-# flags only for C++ (arm-elf-g++)
-CPPFLAGS =
-
-# Assembler flags.
-# -Wa,...: tell GCC to pass this to the assembler.
-# -ahlms: create listing
-# -gstabs: have the assembler create line number information; note that
-# for use in COFF files, additional information about filenames
-# and function names needs to be present in the assembler source
-# files -- see avr-libc docs [FIXME: not yet described there]
-##ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs
-ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG)
-
-#Additional libraries.
-
-#Support for newlibc-lpc (file: libnewlibc-lpc.a)
-#NEWLIBLPC = -lnewlib-lpc
-NEWLIBCLPC =
-
-MATH_LIB = -lm
-
-# Linker flags.
-# -Wl,...: tell GCC to pass this to linker.
-# -Map: create map file
-# --cref: add cross reference to map file
-LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref
-LDFLAGS += -lc
-LDFLAGS += $(NEWLIBLPC) $(MATH_LIB)
-LDFLAGS += -lc -lgcc
-
-# Set Linker-Script Depending On Selected Memory
-ifeq ($(RUN_MODE),RAM_RUN)
-LDFLAGS +=-Tbuild/$(SUBMDL)-RAM.ld
-else
-LDFLAGS +=-Tbuild/$(SUBMDL)-ROM.ld
-endif
-
-
-
-# ---------------------------------------------------------------------------
-# Flash-Programming support using lpc21isp by Martin Maurer
-
-# Settings and variables:
-LPC21ISP = lpc21isp
-#LPC21ISP = lpc21isp_beta
-LPC21ISP_PORT = com1
-LPC21ISP_BAUD = 115200
-LPC21ISP_XTAL = 14746
-LPC21ISP_FLASHFILE = $(TARGET).hex
-# verbose output:
-## LPC21ISP_DEBUG = -debug
-# enter bootloader via RS232 DTR/RTS (only if hardware supports this
-# feature - see Philips AppNote):
-LPC21ISP_CONTROL = -control
-
-
-# ---------------------------------------------------------------------------
-
-# Define directories, if needed.
-## DIRARM = c:/WinARM/
-## DIRARMBIN = $(DIRAVR)/bin/
-## DIRAVRUTILS = $(DIRAVR)/utils/bin/
-
-# Define programs and commands.
-SHELL = sh
-CC = arm-elf-gcc -mbig-endian
-CPP = arm-elf-g++
-OBJCOPY = arm-elf-objcopy
-OBJDUMP = arm-elf-objdump
-SIZE = arm-elf-size
-NM = arm-elf-nm
-REMOVE = rm -f
-COPY = cp
-
-
-# Define Messages
-# English
-MSG_ERRORS_NONE = Errors: none
-MSG_BEGIN = -------- begin --------
-MSG_END = -------- end --------
-MSG_EXTRACT = Extracting bootloader program file:
-MSG_SIZE_BEFORE = Size before:
-MSG_SIZE_AFTER = Size after:
-MSG_FLASH = Creating load file for Flash:
-MSG_EXTENDED_LISTING = Creating Extended Listing:
-MSG_SYMBOL_TABLE = Creating Symbol Table:
-MSG_LINKING = Linking:
-MSG_COMPILING = Compiling C:
-MSG_COMPILING_ARM = "Compiling C (ARM-only):"
-MSG_COMPILINGCPP = Compiling C++:
-MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):"
-MSG_ASSEMBLING = Assembling:
-MSG_ASSEMBLING_ARM = "Assembling (ARM-only):"
-MSG_CLEANING = Cleaning project:
-MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now.
-
-
-# Define all object files.
-COBJ = $(SRC:.c=.o)
-AOBJ = $(ASRC:.S=.o)
-COBJARM = $(SRCARM:.c=.o)
-AOBJARM = $(ASRCARM:.S=.o)
-CPPOBJ = $(CPPSRC:.cpp=.o)
-CPPOBJARM = $(CPPSRCARM:.cpp=.o)
-
-# Define all listing files.
-LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst)
-LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst)
-
-# Compiler flags to generate dependency files.
-### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d
-GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d
-
-# Combine all necessary flags and optional flags.
-# Add target processor to flags.
-ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS)
-ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS)
-
-
-# Default target.
-all: begin gccversion sizebefore build sizeafter finished cmp end
-
-build: elf hex lss
-
-elf: $(TARGET).elf
-hex: $(TARGET).hex
-lss: $(TARGET).lss
-sym: $(TARGET).sym
-
-# Extract memory file.
-cmp:
- @echo
- @echo $(MSG_EXTRACT)
- storm_extractor.exe $(TARGET).elf
- @echo
-
-
-# Eye candy.
-begin:
- @echo
- @echo $(MSG_BEGIN)
-
-finished:
- @echo $(MSG_ERRORS_NONE)
-
-end:
- @echo $(MSG_END)
- @echo
-
-
-# Display size of file.
-HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
-ELFSIZE = $(SIZE) -A $(TARGET).elf
-sizebefore:
- @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi
-
-sizeafter:
- @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi
-
-
-# Display compiler version information.
-gccversion :
- @$(CC) --version
-
-
-# Program the device.
-program: $(TARGET).hex
- @echo
- @echo $(MSG_LPC21_RESETREMINDER)
- $(LPC21ISP) $(LPC21ISP_CONTROL) $(LPC21ISP_DEBUG) $(LPC21ISP_FLASHFILE) $(LPC21ISP_PORT) $(LPC21ISP_BAUD) $(LPC21ISP_XTAL)
-
-
-# Create final output files (.hex, .eep) from ELF output file.
-# TODO: handling the .eeprom-section should be redundant
-%.hex: %.elf
- @echo
- @echo $(MSG_FLASH) $@
- $(OBJCOPY) -O $(FORMAT) $< $@
-
-
-# Create extended listing file from ELF output file.
-# testing: option -C
-%.lss: %.elf
- @echo
- @echo $(MSG_EXTENDED_LISTING) $@
- $(OBJDUMP) -h -S -C $< > $@
-
-
-# Create a symbol table from ELF output file.
-%.sym: %.elf
- @echo
- @echo $(MSG_SYMBOL_TABLE) $@
- $(NM) -n $< > $@
-
-
-# Link: create ELF output file from object files.
-.SECONDARY : $(TARGET).elf
-.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
-%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM)
- @echo
- @echo $(MSG_LINKING) $@
- $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
-# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS)
-
-# Compile: create object files from C source files. ARM/Thumb
-$(COBJ) : %.o : %.c
- @echo
- @echo $(MSG_COMPILING) $<
- $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
-
-# Compile: create object files from C source files. ARM-only
-$(COBJARM) : %.o : %.c
- @echo
- @echo $(MSG_COMPILING_ARM) $<
- $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@
-
-# Compile: create object files from C++ source files. ARM/Thumb
-$(CPPOBJ) : %.o : %.cpp
- @echo
- @echo $(MSG_COMPILINGCPP) $<
- $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
-
-# Compile: create object files from C++ source files. ARM-only
-$(CPPOBJARM) : %.o : %.cpp
- @echo
- @echo $(MSG_COMPILINGCPP_ARM) $<
- $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@
-
-
-# Compile: create assembler files from C source files. ARM/Thumb
-## does not work - TODO - hints welcome
-##$(COBJ) : %.s : %.c
-## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@
-
-
-# Assemble: create object files from assembler source files. ARM/Thumb
-$(AOBJ) : %.o : %.S
- @echo
- @echo $(MSG_ASSEMBLING) $<
- $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@
-
-
-# Assemble: create object files from assembler source files. ARM-only
-$(AOBJARM) : %.o : %.S
- @echo
- @echo $(MSG_ASSEMBLING_ARM) $<
- $(CC) -c $(ALL_ASFLAGS) $< -o $@
-
-
-# Target: clean project.
-clean: begin clean_list finished end
-
-
-clean_list :
- @echo
- @echo $(MSG_CLEANING)
- $(REMOVE) $(TARGET).hex
- $(REMOVE) $(TARGET).obj
- $(REMOVE) $(TARGET).elf
- $(REMOVE) $(TARGET).map
- $(REMOVE) $(TARGET).obj
- $(REMOVE) $(TARGET).a90
- $(REMOVE) $(TARGET).sym
- $(REMOVE) $(TARGET).lnk
- $(REMOVE) $(TARGET).lss
- $(REMOVE) a.out
- $(REMOVE) storm_program.txt
- $(REMOVE) storm_program.dat
- $(REMOVE) $(COBJ)
- $(REMOVE) $(CPPOBJ)
- $(REMOVE) $(AOBJ)
- $(REMOVE) $(COBJARM)
- $(REMOVE) $(CPPOBJARM)
- $(REMOVE) $(AOBJARM)
- $(REMOVE) $(LST)
- $(REMOVE) $(SRC:.c=.s)
- $(REMOVE) $(SRC:.c=.d)
- $(REMOVE) $(SRCARM:.c=.s)
- $(REMOVE) $(SRCARM:.c=.d)
- $(REMOVE) $(CPPSRC:.cpp=.s)
- $(REMOVE) $(CPPSRC:.cpp=.d)
- $(REMOVE) $(CPPSRCARM:.cpp=.s)
- $(REMOVE) $(CPPSRCARM:.cpp=.d)
- $(REMOVE) .dep/*
-
-
-# Include the dependency files.
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
-
-
-# Listing of phony targets.
-.PHONY : all begin finish end sizebefore sizeafter gccversion \
-build elf hex lss sym clean clean_list program
-
Index: storm_core/trunk/software/C/build/storm_startup_code.S
===================================================================
--- storm_core/trunk/software/C/build/storm_startup_code.S (revision 36)
+++ storm_core/trunk/software/C/build/storm_startup_code.S (nonexistent)
@@ -1,175 +0,0 @@
- .global main // int main(void)
-
- .global _etext // -> .data initial values in ROM
- .global _data // -> .data area in RAM
- .global _edata // end of .data area
- .global __bss_start // -> .bss area in RAM
- .global __bss_end__ // end of .bss area
- .global _stack // top of stack
-
-// Stack Sizes
- .set UND_STACK_SIZE, 0x00000080
- .set ABT_STACK_SIZE, 0x00000080
- .set FIQ_STACK_SIZE, 0x00000080
- .set IRQ_STACK_SIZE, 0X00000080
- .set SVC_STACK_SIZE, 0x00000080
-
-// Standard definitions of Mode bits and Interrupt flags in MSRs
- .set MODE_USR, 0x10 // User Mode
- .set MODE_FIQ, 0x11 // FIQ Mode
- .set MODE_IRQ, 0x12 // IRQ Mode
- .set MODE_SVC, 0x13 // Supervisor Mode
- .set MODE_ABT, 0x17 // Abort Mode
- .set MODE_UND, 0x1B // Undefined Mode
- .set MODE_SYS, 0x1F // System Mode
-
- .equ FIQ_BIT, 0x40 // when FIQ bit is set, FIQ is disabled
- .equ IRQ_BIT, 0x80 // when IRQ bit is set, IRQ is disabled
-
- .text
- .code 32
- .align 2
-
- .global _boot
- .func _boot
-_boot:
-
-// Runtime Interrupt Vectors
-// -------------------------------------------------------------------
-Vectors:
- b _start // reset - _start
- ldr pc,_undf // undefined - _undf
- ldr pc,_swi // SWI - _swi
- ldr pc,_pabt // program abort - _pabt
- ldr pc,_dabt // data abort - _dabt
- nop // reserved
- ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
- ldr pc,_fiq // FIQ - _fiq
-
-
-// Use this group for development
-_undf: .word __undf // undefined
-_swi: .word __swi // SWI
-_pabt: .word __pabt // program abort
-_dabt: .word __dabt // data abort
-_irq: .word __irq // IRQ
-_fiq: .word __fiq // FIQ
-
-__undf: b . // undefined
-__swi: b . // SWI
-__pabt: b . // program abort
-__dabt: b . // data abort
-__irq: b . // IRQ
-__fiq: b . // FIQ
-
- .size _boot, . - _boot
- .endfunc
-
-
-// Setup the operating mode & stack.
-// -------------------------------------------------------------------
- .global _start, start, _mainCRTStartup
- .func _start
-
-_start:
-start:
-_mainCRTStartup:
-
-// Who am I? Where am I going?
-
-// Initialize Interrupt System
-// - Set stack location for each mode
-// - Leave in System Mode with Interrupts Disabled
-// ----------------------------------------------------
- ldr r0,=_stack // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
- sub r0,r0,#UND_STACK_SIZE // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
- sub r0,r0,#ABT_STACK_SIZE // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
- sub r0,r0,#FIQ_STACK_SIZE // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
- sub r0,r0,#IRQ_STACK_SIZE // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
- sub r0,r0,#SVC_STACK_SIZE // Calc stack base
- mrs r1,CPSR
- bic r1,r1,#0x7F
- orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode
- msr CPSR,r1
- mov sp,r0 // Store stack base
-
-// Copy initialized data to its execution address in RAM
-// -------------------------------------------------------------------
-#ifdef ROM_RUN
- ldr r1,=_etext // -> ROM data start
- ldr r2,=_data // -> data start
- ldr r3,=_edata // -> end of data
-x01: cmp r2,r3 // check if data to move
- beq y01
- ldrlo r0,[r1],#4 // copy it
- strlo r0,[r2],#4
- blo x01 // loop until done
-y01:
-#endif
-// Clear .bss
-// ----------
- mov r0,#0 // get a zero
- ldr r1,=__bss_start // -> bss start
- ldr r2,=__bss_end__ // -> bss end
-x02: cmp r1,r2 // check if data to clear
- beq y02
- strlo r0,[r1],#4 // clear 4 bytes
- blo x02 // loop until done
-y02:
-// Call main program: main(0)
-// --------------------------
- mov r0,#0 // no arguments (argc = 0)
- mov r1,r0
- mov r2,r0
- mov fp,r0 // null frame pointer
- mov r7,r0 // null frame pointer for thumb
- ldr r10,=main
- mov lr,pc
- mov pc, r10 // enter main()
-
- .size _start, . - _start
- .endfunc
-
- .global _reset, reset, exit, abort
- .func _reset
-_reset:
-reset:
-exit:
-abort:
-
- b . // loop until reset
-
- .size _reset, . - _reset
- .endfunc
-
- .end
Index: storm_core/trunk/software/C/build/STORMcore-RAM.ld
===================================================================
--- storm_core/trunk/software/C/build/STORMcore-RAM.ld (revision 36)
+++ storm_core/trunk/software/C/build/STORMcore-RAM.ld (nonexistent)
@@ -1,101 +0,0 @@
-/***********************************************************************/
-/* */
-/* RAM.ld: Linker Script File */
-/* */
-/***********************************************************************/
-ENTRY(_start)
-STACK_SIZE = 0x800;
-
-/* Memory Definitions */
-MEMORY
-{
- ROM (rx) : ORIGIN = 0xFFFFF000, LENGTH = 0x00000200
- RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00001000
-}
-
-/* Section Definitions */
-SECTIONS
-{
- /* first section is .text which is used for code */
- .text :
- {
- *storm_startup_code.o (.text) /* Startup code */
- *(.text) /* remaining code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*)
- *(.glue_7)
- *(.glue_7t)
- } > RAM
-
- . = ALIGN(4);
- _etext = . ;
- PROVIDE (etext = .);
-
- /* .data section which is used for initialized data */
- .data :
- {
- _data = .;
- *(.data)
- } > RAM
-
- . = ALIGN(4);
- _edata = . ;
- PROVIDE (edata = .);
-
- /* .bss section which is used for uninitialized data */
- .bss (NOLOAD) :
- {
- __bss_start = . ;
- __bss_start__ = . ;
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- } > RAM
-
- . = ALIGN(4);
- __bss_end__ = . ;
- PROVIDE (__bss_end = .);
-
- .stack ALIGN(256) :
- {
- . += STACK_SIZE;
- PROVIDE (_stack = .);
- } > RAM
-
- _end = . ;
- PROVIDE (end = .);
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
Index: storm_core/trunk/software/C/storm_extractor.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: storm_core/trunk/software/C/storm_extractor.exe
===================================================================
--- storm_core/trunk/software/C/storm_extractor.exe (revision 36)
+++ storm_core/trunk/software/C/storm_extractor.exe (nonexistent)
storm_core/trunk/software/C/storm_extractor.exe
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: storm_core/trunk/software/C/storm_core.h
===================================================================
--- storm_core/trunk/software/C/storm_core.h (revision 36)
+++ storm_core/trunk/software/C/storm_core.h (nonexistent)
@@ -1,42 +0,0 @@
-#ifndef storm_core_h
-#define storm_core_h
-
-////////////////////////////////////////////////////////////////////////////////
-// storm_core.h - STORM Core internal definitions
-//
-// Created by Stephan Nolting (stnolting@googlemail.com)
-// http://www.opencores.com/project,storm_core
-// Last modified 13. Mar. 2012
-////////////////////////////////////////////////////////////////////////////////
-
-/* Internal System Coprocessor Register Set */
-#define SYS_CP 15 // system coprocessor #
-#define ID_REG_0 0 // ID register 0
-#define ID_REG_1 1 // ID register 1
-#define ID_REG_2 2 // ID register 2
-#define SYS_CTRL_0 6 // system control register 0
-#define CSTAT 8 // cache statistics register
-#define ADR_FB 9 // adr feedback from bus unit -> for exception analysis
-#define LFSR_POLY 11 // Internal LFSR, polynomial
-#define LFSR_DATA 12 // Internal LFSR, shift register
-#define SYS_IO 13 // System IO ports
-
-/* CP_SYS_CTRL_0 */
-#define DC_FLUSH 0 // flush d-cache
-#define DC_CLEAR 1 // clear d-cache
-#define IC_CLEAR 2 // flush i-cache
-#define DC_WTHRU 3 // cache write-thru enable
-#define DC_AUTOPR 4 // auto pre-reload d-cache page
-#define IC_AUTOPR 5 // auto pre-reload i-cache page
-#define CACHED_IO 6 // cached IO
-#define PRTC_IO 7 // protected IO
-#define DC_SYNC 8 // d-cache is sync
-#define LFSR_EN 13 // enable lfsr
-#define LFSR_M 14 // lfsr update mode
-#define LFSR_D 15 // lfsr shift direction
-#define MBC_0 16 // max bus cycle length bit 0
-#define MBC_LSB 16
-#define MBC_15 31 // max bus cycle length bit 15
-#define MBC_MSB 31
-
-#endif // storm_core_h
Index: storm_core/trunk/software/C/storm_program.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: storm_core/trunk/software/C/storm_program.dat
===================================================================
--- storm_core/trunk/software/C/storm_program.dat (revision 36)
+++ storm_core/trunk/software/C/storm_program.dat (nonexistent)
storm_core/trunk/software/C/storm_program.dat
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: storm_core/trunk/software/C/main.c
===================================================================
--- storm_core/trunk/software/C/main.c (revision 36)
+++ storm_core/trunk/software/C/main.c (nonexistent)
@@ -1,42 +0,0 @@
-#include "storm_core.h"
-
-/*----------------------------------------
- STORM Core Demo SoC Program
- by Stephan Nolting
-
- This program outputs the first 30
- Fibonacci numbers on the IO.O port.
- Afterwards it restarts.
-
- The program is allready loaded
- into the MEMORY.vhd test component.
-----------------------------------------*/
-
-
-/* ---- IO Device Locations ---- */
-#define REG32 (volatile unsigned int*)
-#define GPIO_OUT (*(REG32 (0xFFFFFE020)))
-#define GPIO_IN (*(REG32 (0xFFFFFE024)))
-
-
-int main(void)
-{
- int i, num_a, num_b, tmp = 0;
-
- GPIO_OUT = 0; // clear output
-
- while(1)
- {
- num_a = 0;
- num_b = 1;
-
- for(i=0; i<31; i++)
- {
- GPIO_OUT = num_a;
- tmp = num_a + num_b;
- num_a = num_b;
- num_b = tmp;
- }
- }
-
-}
Index: storm_core/trunk/software/storm_extractor src/main.c
===================================================================
--- storm_core/trunk/software/storm_extractor src/main.c (revision 36)
+++ storm_core/trunk/software/storm_extractor src/main.c (nonexistent)
@@ -1,166 +0,0 @@
-#include
-#include
-#include
-
-void TextSpeichern (FILE *dateizeiger)
-{
- char buffer[80] = "";
-
- printf ("\nDone!\n\n");
-
- fgets (buffer, 80, stdin); /* von der Tastatur lesen (stdin) */
- return;
-
-}
-
-//**********************************************************************
-// Hauptfunktion
-//**********************************************************************
-int main(int argc, char *argv[])
-{
- FILE * pFile;
- char filename[80] = "a.out";
- long lSize;
- int m = 0;
- int adr_start;
- unsigned char * buffer;
- size_t result;
-
- FILE *f; // txt output file
- FILE *d; // binary output file
-
-
- if (argc > 1)
- {
- while(argv[1][m] != '\0')
- {
- filename[m] = argv[1][m];
- m++;
- }
- }
-
- //system("color 0a");
-
- pFile = fopen (filename , "rb" );
- if (pFile==NULL)
- {
- printf("Cannot open file 'a.out'\n");
- exit (1);
- }
-
- // obtain file size:
- fseek (pFile , 0 , SEEK_END);
- lSize = ftell (pFile);
- rewind (pFile);
-
- // allocate memory to contain the whole file:
- buffer = (unsigned char*) malloc (sizeof(unsigned char)*lSize);
- if (buffer == NULL)
- {
- printf("Memory error\n");
- exit (2);
- }
-
- // copy the file into the buffer:
- result = fread (buffer,1,lSize,pFile);
- if (result != lSize)
- {
- printf("Reading error\n");
- exit (3);
- }
-
-
- // Open txt output file
- f = fopen("storm_program.txt","w+");
- if(f == NULL)
- {
- printf("Error creating txt output file\n");
- exit(10);
- }
-
- // Open dat output file
- d = fopen("storm_program.bin","wb+");
- if(d == NULL)
- {
- printf("Error creating binary output file\n");
- exit(11);
- }
-
- if (buffer[45] == 1)
- {
- adr_start = 56;
- }
- else
- {
- adr_start = 88;
- }
-
- // Beginning of mnemomic part
- unsigned long mnemonic_beginning = 0;
- mnemonic_beginning = ((buffer[adr_start] << 24) | (buffer[adr_start+1] << 16) | (buffer[adr_start+2] << 8) | (buffer[adr_start+3]));
- //printf("Mnemonic start: %u\n", mnemonic_beginning);
-
- // Length of mnemonic part
- unsigned long mnemonic_length = 0;
- mnemonic_length = ((buffer[adr_start+12] << 24) | (buffer[adr_start+13] << 16) | (buffer[adr_start+14] << 8) | (buffer[adr_start+15]));
- if(mnemonic_length == 0)
- {
- printf("Invalid assembler file\n"); //x38 x58
- exit(4);
- }
-
- if (mnemonic_length == 0)
- {
- printf("Assembler file is empty\n");
- exit(5);
- }
-
- printf("Program start: 0x%.8X\n", mnemonic_beginning);
- printf("Program size: 0x%.8X\n", mnemonic_length-4);
-
- int j = mnemonic_beginning;
- int i = 0;
- int k = 0;
- char txt_string[32];
- char dat_string;
- i = 0;
-
- sprintf(txt_string, "SMBR");
- txt_string[4] = (unsigned char)((mnemonic_length-4)>>24);
- txt_string[5] = (unsigned char)((mnemonic_length-4)>>16);
- txt_string[6] = (unsigned char)((mnemonic_length-4)>> 8);
- txt_string[7] = (unsigned char)((mnemonic_length-4)>> 0);
- fputc(txt_string[0], d);
- fputc(txt_string[1], d);
- fputc(txt_string[2], d);
- fputc(txt_string[3], d);
- fputc(txt_string[4], d);
- fputc(txt_string[5], d);
- fputc(txt_string[6], d);
- fputc(txt_string[7], d);
-
- while (j != (mnemonic_length + mnemonic_beginning))
- {
- unsigned long temp = 0;
- temp = ((buffer[j] << 24) | (buffer[j+1] << 16) | (buffer[j+2] << 8) | (buffer[j+3]));
- sprintf(txt_string, "%.6u\ => x\"%.8X\",\n", i ,temp);
- fputs(txt_string, f);
- for(k=0; k<=3; k++)
- {
- dat_string = (signed char) buffer[j+k];
- fputc(dat_string, d);
- }
- j=j+4;
- i++;
- }
- sprintf(txt_string, "others => x\"F0013007\"\n");
- fputs(txt_string, f);
- //printf("others => x\"F0013007\"\n"); // optimized NOP command
-
- // terminate
- fclose(pFile);
- fclose(f);
- fclose(d);
- free (buffer);
- return 0;
-}
Index: storm_core/trunk/sim/STORM_core_TB.vhd
===================================================================
--- storm_core/trunk/sim/STORM_core_TB.vhd (revision 36)
+++ storm_core/trunk/sim/STORM_core_TB.vhd (nonexistent)
@@ -1,372 +0,0 @@
--- #######################################################
--- # < STORM Core Processor by Stephan Nolting > #
--- # *************************************************** #
--- # STORM Core / STORM Demo SoC Testbench #
--- # *************************************************** #
--- # Last modified: 04.03.2012 #
--- #######################################################
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity STORM_core_TB is
-end STORM_core_TB;
-
-architecture Structure of STORM_core_TB is
-
- -- Address Map --------------------------------------------------------------------
- -- -----------------------------------------------------------------------------------
- constant INT_MEM_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"00000000";
- constant INT_MEM_SIZE_C : natural := 1*1024; -- bytes
- constant GP_IO_BASE_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020";
- constant GP_IO_SIZE_C : natural := 2*4; -- two 4-byte registers = 8 bytes
-
-
- -- Architecture Constants ---------------------------------------------------------
- -- -----------------------------------------------------------------------------------
- constant BOOT_VECTOR_C : STD_LOGIC_VECTOR(31 downto 0) := INT_MEM_BASE_C;
- constant IO_BEGIN_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE020"; -- first addr of IO area
- constant IO_END_C : STD_LOGIC_VECTOR(31 downto 0) := x"FFFFE024"; -- last addr of IO area
- constant I_CACHE_PAGES_C : natural := 4; -- number of pages in I cache
- constant I_CACHE_PAGE_SIZE_C : natural := 16; -- page size in I cache
- constant D_CACHE_PAGES_C : natural := 4; -- number of pages in D cache
- constant D_CACHE_PAGE_SIZE_C : natural := 4; -- page size in D cache
-
-
- -- Global Signals -----------------------------------------------------------------
- -- -----------------------------------------------------------------------------------
-
- -- Global Clock & Reset --
- signal EXT_RST : STD_LOGIC;
- signal MAIN_RST : STD_LOGIC;
- signal MAIN_CLK : STD_LOGIC := '0';
- signal STORM_IRQ : STD_LOGIC;
- signal STORM_FIQ : STD_LOGIC;
-
- -- Wishbone Core Bus --
- signal CORE_WB_ADR_O : STD_LOGIC_VECTOR(31 downto 0); -- address
- signal CORE_WB_CTI_O : STD_LOGIC_VECTOR(02 downto 0); -- cycle type
- signal CORE_WB_TGC_O : STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- signal CORE_WB_SEL_O : STD_LOGIC_VECTOR(03 downto 0); -- byte select
- signal CORE_WB_WE_O : STD_LOGIC; -- write enable
- signal CORE_WB_DATA_O : STD_LOGIC_VECTOR(31 downto 0); -- data out
- signal CORE_WB_DATA_I : STD_LOGIC_VECTOR(31 downto 0); -- data in
- signal CORE_WB_STB_O : STD_LOGIC; -- valid transfer
- signal CORE_WB_CYC_O : STD_LOGIC; -- valid cycle
- signal CORE_WB_ACK_I : STD_LOGIC; -- acknowledge
- signal CORE_WB_ERR_I : STD_LOGIC; -- abnormal termination
- signal CORE_WB_HALT_I : STD_LOGIC; -- halt request
-
-
- -- Component interface ------------------------------------------------------------
- -- -----------------------------------------------------------------------------------
-
- -- Internal Working Memory --
- signal INT_MEM_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
- signal INT_MEM_STB_I : STD_LOGIC;
- signal INT_MEM_ACK_O : STD_LOGIC;
- signal INT_MEM_ERR_O : STD_LOGIC;
- signal INT_MEM_HALT_O : STD_LOGIC;
-
- -- General Purpose IO Controller --
- signal GP_IO_CTRL_DATA_O : STD_LOGIC_VECTOR(31 downto 0);
- signal GP_IO_CTRL_STB_I : STD_LOGIC;
- signal GP_IO_CTRL_ACK_O : STD_LOGIC;
- signal GP_IO_CTRL_ERR_O : STD_LOGIC;
- signal GP_IO_CTRL_HALT_O : STD_LOGIC;
- signal GP_IO_OUT_PORT : STD_LOGIC_VECTOR(31 downto 0);
- signal GP_IO_IN_PORT : STD_LOGIC_VECTOR(31 downto 0);
-
-
- -- Logarithm duales ---------------------------------------------------------------
- -- -----------------------------------------------------------------------------------
- function log2(temp : natural) return natural is
- begin
- for i in 0 to integer'high loop
- if (2**i >= temp) then
- return i;
- end if;
- end loop;
- return 0;
- end function log2;
-
-
- -- STORM Core Top Entity ----------------------------------------------------------
- -- -----------------------------------------------------------------------------------
- component STORM_TOP
- generic (
- I_CACHE_PAGES : natural := 4; -- number of pages in I cache
- I_CACHE_PAGE_SIZE : natural := 32; -- page size in I cache
- D_CACHE_PAGES : natural := 8; -- number of pages in D cache
- D_CACHE_PAGE_SIZE : natural := 4; -- page size in D cache
- BOOT_VECTOR : STD_LOGIC_VECTOR(31 downto 0); -- boot address
- IO_UC_BEGIN : STD_LOGIC_VECTOR(31 downto 0); -- begin of uncachable IO area
- IO_UC_END : STD_LOGIC_VECTOR(31 downto 0) -- end of uncachable IO area
- );
- port (
- -- Global Control --
- CORE_CLK_I : in STD_LOGIC; -- core clock input
- RST_I : in STD_LOGIC; -- global reset input
- IO_PORT_O : out STD_LOGIC_VECTOR(15 downto 0); -- direct output
- IO_PORT_I : in STD_LOGIC_VECTOR(15 downto 0); -- direct input
-
- -- Wishbone Bus --
- WB_ADR_O : out STD_LOGIC_VECTOR(31 downto 0); -- address
- WB_CTI_O : out STD_LOGIC_VECTOR(02 downto 0); -- cycle type
- WB_TGC_O : out STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- WB_SEL_O : out STD_LOGIC_VECTOR(03 downto 0); -- byte select
- WB_WE_O : out STD_LOGIC; -- write enable
- WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- data out
- WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- data in
- WB_STB_O : out STD_LOGIC; -- valid transfer
- WB_CYC_O : out STD_LOGIC; -- valid cycle
- WB_ACK_I : in STD_LOGIC; -- acknowledge
- WB_ERR_I : in STD_LOGIC; -- abnormal cycle termination
- WB_HALT_I : in STD_LOGIC; -- halt request
-
- -- Interrupt Request Lines --
- IRQ_I : in STD_LOGIC; -- interrupt request
- FIQ_I : in STD_LOGIC -- fast interrupt request
- );
- end component;
-
-
- -- Internal Working Memory --------------------------------------------------------
- -- -----------------------------------------------------------------------------------
- component MEMORY
- generic (
- MEM_SIZE : natural := 256; -- memory cells
- LOG2_MEM_SIZE : natural := 8; -- log2(memory cells)
- OUTPUT_GATE : boolean := FALSE -- output and-gate, might be necessary for some bus systems
- );
- port (
- -- Wishbone Bus --
- WB_CLK_I : in STD_LOGIC; -- memory master clock
- WB_RST_I : in STD_LOGIC; -- high active sync reset
- WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
- WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
- WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
- WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
- WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
- WB_WE_I : in STD_LOGIC; -- write enable
- WB_STB_I : in STD_LOGIC; -- valid cycle
- WB_ACK_O : out STD_LOGIC; -- acknowledge
- WB_HALT_O : out STD_LOGIC; -- throttle master
- WB_ERR_O : out STD_LOGIC -- abnormal cycle termination
- );
- end component;
-
-
- -- General Purpose IO Controller --------------------------------------------------
- -- -----------------------------------------------------------------------------------
- component GP_IO_CTRL
- port (
- -- Wishbone Bus --
- WB_CLK_I : in STD_LOGIC; -- memory master clock
- WB_RST_I : in STD_LOGIC; -- high active sync reset
- WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
- WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- WB_ADR_I : in STD_LOGIC; -- adr in
- WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
- WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
- WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
- WB_WE_I : in STD_LOGIC; -- write enable
- WB_STB_I : in STD_LOGIC; -- valid cycle
- WB_ACK_O : out STD_LOGIC; -- acknowledge
- WB_HALT_O : out STD_LOGIC; -- throttle master
- WB_ERR_O : out STD_LOGIC; -- abnormal termination
-
- -- IO Port --
- GP_IO_O : out STD_LOGIC_VECTOR(31 downto 00);
- GP_IO_I : in STD_LOGIC_VECTOR(31 downto 00);
-
- -- Input Change INT --
- IO_IRQ_O : out STD_LOGIC
- );
- end component;
-
-begin
-
--- #################################################################################################################################
--- ### STORM CORE PROCESSOR ###
--- #################################################################################################################################
-
- -- CLOCK/RESET GENERATOR -------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
-
- -- Clock Generator --
- MAIN_CLK <= not MAIN_CLK after 20 ns; -- 50MHz
-
- -- Reset System --
- EXT_RST <= '1', '0' after 400 ns;
- MAIN_RST <= EXT_RST;
-
- -- Interrupt Generator --
- STORM_IRQ <= '0', '1' after 2000 ns, '0' after 2020 ns;
- STORM_FIQ <= '0';
-
-
-
- -- STORM CORE PROCESSOR --------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- STORM_TOP_INST: STORM_TOP
- generic map (
- I_CACHE_PAGES => I_CACHE_PAGES_C, -- number of pages in I cache
- I_CACHE_PAGE_SIZE => I_CACHE_PAGE_SIZE_C, -- page size in I cache
- D_CACHE_PAGES => D_CACHE_PAGES_C, -- number of pages in D cache
- D_CACHE_PAGE_SIZE => D_CACHE_PAGE_SIZE_C, -- page size in D cache
- BOOT_VECTOR => BOOT_VECTOR_C, -- startup boot address
- IO_UC_BEGIN => IO_BEGIN_C, -- begin of uncachable IO area
- IO_UC_END => IO_END_C -- end of uncachable IO area
- )
- port map (
- -- Global Control --
- CORE_CLK_I => MAIN_CLK, -- core clock input
- RST_I => MAIN_RST, -- global reset input
- IO_PORT_O => open, -- direct output
- IO_PORT_I => x"0000", -- direct input
-
- -- Wishbone Bus --
- WB_ADR_O => CORE_WB_ADR_O, -- address
- WB_CTI_O => CORE_WB_CTI_O, -- cycle type
- WB_TGC_O => CORE_WB_TGC_O, -- cycle tag
- WB_SEL_O => CORE_WB_SEL_O, -- byte select
- WB_WE_O => CORE_WB_WE_O, -- write enable
- WB_DATA_O => CORE_WB_DATA_O, -- data out
- WB_DATA_I => CORE_WB_DATA_I, -- data in
- WB_STB_O => CORE_WB_STB_O, -- valid transfer
- WB_CYC_O => CORE_WB_CYC_O, -- valid cycle
- WB_ACK_I => CORE_WB_ACK_I, -- acknowledge
- WB_ERR_I => CORE_WB_ERR_I, -- abnormal cycle termination
- WB_HALT_I => CORE_WB_HALT_I, -- halt request
-
- -- Interrupt Request Lines --
- IRQ_I => STORM_IRQ, -- interrupt request
- FIQ_I => STORM_FIQ -- fast interrupt request
- );
-
-
-
--- #################################################################################################################################
--- ### WISHBONE FABRIC ###
--- #################################################################################################################################
-
- -- Valid Transfer Signal -------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- INT_MEM_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= INT_MEM_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(INT_MEM_BASE_C) + INT_MEM_SIZE_C))) else '0';
- GP_IO_CTRL_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= GP_IO_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(GP_IO_BASE_C) + GP_IO_SIZE_C))) else '0';
--- DUMMY0_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= DUMMY0_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(DUMMY0_BASE_C) + DUMMY0_SIZE_C))) else '0';
--- DUMMY1_STB_I <= CORE_WB_STB_O when ((CORE_WB_ADR_O >= DUMMY1_BASE_C) and (CORE_WB_ADR_O < Std_logic_Vector(unsigned(DUMMY1_BASE_C) + DUMMY1_SIZE_C))) else '0';
-
-
- -- Read-Back Data Selector -----------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- CORE_WB_DATA_I <=
- INT_MEM_DATA_O when (INT_MEM_STB_I = '1') else
- GP_IO_CTRL_DATA_O when (GP_IO_CTRL_STB_I = '1') else
--- DUMMY0_DATA_O when (DUMMY0_STB_I = '1') else
--- DUMMY1_DATA_O when (DUMMY1_STB_I = '1') else
- x"00000000";
-
-
- -- Use this style of data read-back terminal for pipelined Wishbone systems.
- -- You have to ensure, that all not-selected IO devices set their data output to 0.
- -- => Output and-gates controlled by the device's STB_I signal.
--- CORE_WB_DATA_I <= INT_MEM_DATA_O or
--- GP_IO_CTRL_DATA_O or
--- DUMMY0_DATA_O or
--- DUMMY1_DATA_O or
--- '0';
-
-
- -- Acknowledge Terminal --------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- CORE_WB_ACK_I <= INT_MEM_ACK_O or
- GP_IO_CTRL_ACK_O or
--- DUMMY0_ACK_O or
--- DUMMY1_ACK_O or
- '0';
-
-
- -- Halt Terminal ---------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- CORE_WB_HALT_I <= INT_MEM_HALT_O or
- GP_IO_CTRL_HALT_O or
--- DUMMY0_HALT_O or
--- DUMMY1_HALT_O or
- '0';
-
-
- -- Halt Terminal ---------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- CORE_WB_ERR_I <= INT_MEM_ERR_O or
- GP_IO_CTRL_ERR_O or
--- DUMMY0_ERR_O or
--- DUMMY1_ERR_O or
- '0';
-
-
-
--- #################################################################################################################################
--- ### SYSTEM COMPONENTS ###
--- #################################################################################################################################
-
- -- Internal Working Memory -----------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- INTERNAL_MEMORY: MEMORY
- generic map (
- MEM_SIZE => INT_MEM_SIZE_C/4, -- memory size in 32-bit cells
- LOG2_MEM_SIZE => log2(INT_MEM_SIZE_C/4), -- log2 memory size in 32-bit cells
- OUTPUT_GATE => FALSE -- not necessary here
- )
- port map(
- WB_CLK_I => MAIN_CLK,
- WB_RST_I => MAIN_RST,
- WB_CTI_I => CORE_WB_CTI_O,
- WB_TGC_I => CORE_WB_TGC_O,
- WB_ADR_I => CORE_WB_ADR_O(log2(INT_MEM_SIZE_C/4)+1 downto 2), -- word boundary access
- WB_DATA_I => CORE_WB_DATA_O,
- WB_DATA_O => INT_MEM_DATA_O,
- WB_SEL_I => CORE_WB_SEL_O,
- WB_WE_I => CORE_WB_WE_O,
- WB_STB_I => INT_MEM_STB_I,
- WB_ACK_O => INT_MEM_ACK_O,
- WB_HALT_O => INT_MEM_HALT_O,
- WB_ERR_O => INT_MEM_ERR_O
- );
-
-
-
- -- General Purpose IO ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- IO_CONTROLLER: GP_IO_CTRL
- port map (
- -- Wishbone Bus --
- WB_CLK_I => MAIN_CLK,
- WB_RST_I => MAIN_RST,
- WB_CTI_I => CORE_WB_CTI_O,
- WB_TGC_I => CORE_WB_TGC_O,
- WB_ADR_I => CORE_WB_ADR_O(2),
- WB_DATA_I => CORE_WB_DATA_O,
- WB_DATA_O => GP_IO_CTRL_DATA_O,
- WB_SEL_I => CORE_WB_SEL_O,
- WB_WE_I => CORE_WB_WE_O,
- WB_STB_I => GP_IO_CTRL_STB_I,
- WB_ACK_O => GP_IO_CTRL_ACK_O,
- WB_HALT_O => GP_IO_CTRL_HALT_O,
- WB_ERR_O => GP_IO_CTRL_ERR_O,
-
- -- IO Port --
- GP_IO_O => GP_IO_OUT_PORT,
- GP_IO_I => GP_IO_IN_PORT,
-
- -- Input Change INT --
- IO_IRQ_O => open
- );
-
- -- Dummy input --
- GP_IO_IN_PORT <= "00000000001100111100110000000000";
-
-end Structure;
\ No newline at end of file
Index: storm_core/trunk/sim/GP_IO_CTRL.vhd
===================================================================
--- storm_core/trunk/sim/GP_IO_CTRL.vhd (revision 36)
+++ storm_core/trunk/sim/GP_IO_CTRL.vhd (nonexistent)
@@ -1,152 +0,0 @@
--- ######################################################
--- # < STORM SoC by Stephan Nolting > #
--- # ************************************************** #
--- # General Purpose 32-bit IO Controller #
--- # ************************************************** #
--- # Last modified: 20.02.2012 #
--- ######################################################
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity GP_IO_CTRL is
- port (
- -- Wishbone Bus --
- WB_CLK_I : in STD_LOGIC; -- memory master clock
- WB_RST_I : in STD_LOGIC; -- high active sync reset
- WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
- WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- WB_ADR_I : in STD_LOGIC; -- adr in
- WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
- WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
- WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
- WB_WE_I : in STD_LOGIC; -- write enable
- WB_STB_I : in STD_LOGIC; -- valid cycle
- WB_ACK_O : out STD_LOGIC; -- acknowledge
- WB_HALT_O : out STD_LOGIC; -- throttle master
- WB_ERR_O : out STD_LOGIC; -- abnormal termination
-
- -- IO Port --
- GP_IO_O : out STD_LOGIC_VECTOR(31 downto 00);
- GP_IO_I : in STD_LOGIC_VECTOR(31 downto 00);
-
- -- Input Change INT --
- IO_IRQ_O : out STD_LOGIC
- );
-end GP_IO_CTRL;
-
-architecture Structure of GP_IO_CTRL is
-
- -- Input / Output Sync Register --
- signal IO_I_SYNC, IO_O_SYNC, IRQ_SYNC : STD_LOGIC_VECTOR(31 downto 0);
-
- -- internal Buffer --
- signal WB_ACK_O_INT : STD_LOGIC;
-
- -- Memory Map (word boundary)
- -- ADR_I = 0 : Access to OUTPUT register
- -- ADR_I = 1 : Access to INPUT register
-
-begin
-
- -- Wishbone Input Interface ----------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- WB_W_ACCESS: process(WB_CLK_I)
- begin
- if rising_edge(WB_CLK_I) then
- if (WB_RST_I = '1') then
- IO_O_SYNC <= (others => '0');
- elsif (WB_STB_I = '1') and (WB_WE_I = '1') and (WB_ADR_I = '0') then -- valid write access
- for i in 0 to 3 loop
- if (WB_SEL_I(i) = '1') then
- IO_O_SYNC(8*i+7 downto 8*i) <= WB_DATA_I(8*i+7 downto 8*i);
- end if;
- end loop;
- end if;
- end if;
- end process WB_W_ACCESS;
-
- --- Out-Port ---
- GP_IO_O <= IO_O_SYNC;
-
-
-
- -- Wishbone Output Interface ---------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- WB_R_ACCESS: process(WB_CLK_I)
- begin
- if rising_edge(WB_CLK_I) then
- if (WB_RST_I = '1') then
- WB_DATA_O <= (others => '0');
- WB_ACK_O_INT <= '0';
- else
- --- Data Output ---
- if (WB_STB_I = '1') and (WB_WE_I = '0') then -- valid read request
- if (WB_ADR_I = '0') then
- WB_DATA_O <= IO_O_SYNC;
- else
- WB_DATA_O <= IO_I_SYNC;
- end if;
- else
- WB_DATA_O <= (others => '0');
- end if;
-
- --- ACK Control ---
- if (WB_CTI_I = "000") or (WB_CTI_I = "111") then
- WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT);
- else
- WB_ACK_O_INT <= WB_STB_I; -- data is valid one cycle later
- end if;
- end if;
- end if;
- end process WB_R_ACCESS;
-
- --- ACK Signal ---
- WB_ACK_O <= WB_ACK_O_INT;
-
- --- Throttle ---
- WB_HALT_O <= '0'; -- yeay, we're at full speed!
-
- --- Error ---
- WB_ERR_O <= '0'; -- nothing can go wrong ;)
-
-
-
- -- Synchronize Input -------------------------------------------------
- -- ----------------------------------------------------------------------
- SYNC_INPUT: process(WB_CLK_I)
- begin
- if rising_edge(WB_CLK_I) then
- if (WB_RST_I = '1') then
- IO_I_SYNC <= (others => '0');
- IRQ_SYNC <= (others => '0');
- else
- IO_I_SYNC <= GP_IO_I;
- IRQ_SYNC <= IO_I_SYNC;
- end if;
- end if;
- end process SYNC_INPUT;
-
-
-
- -- Input Change IRQ --------------------------------------------------
- -- ----------------------------------------------------------------------
- INPUT_CHANGE_IRQ: process(WB_CLK_I)
- begin
- if rising_edge(WB_CLK_I) then
- if (WB_RST_I = '1') then
- IO_IRQ_O <= '0';
- else
- if (IRQ_SYNC /= IO_I_SYNC) then
- IO_IRQ_O <= '1';
- else
- IO_IRQ_O <= '0';
- end if;
- end if;
- end if;
- end process INPUT_CHANGE_IRQ;
-
-
-
-end Structure;
\ No newline at end of file
Index: storm_core/trunk/sim/MEMORY.vhd
===================================================================
--- storm_core/trunk/sim/MEMORY.vhd (revision 36)
+++ storm_core/trunk/sim/MEMORY.vhd (nonexistent)
@@ -1,195 +0,0 @@
--- ######################################################
--- # < STORM SoC by Stephan Nolting > #
--- # ************************************************** #
--- # Internal Memory Component #
--- # ************************************************** #
--- # Last modified: 04.03.2012 #
--- ######################################################
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity MEMORY is
- generic (
- MEM_SIZE : natural := 256; -- memory cells
- LOG2_MEM_SIZE : natural := 8; -- log2(memory cells)
- OUTPUT_GATE : boolean := FALSE -- output and-gate, might be necessary for some bus systems
- );
- port (
- -- Wishbone Bus --
- WB_CLK_I : in STD_LOGIC; -- memory master clock
- WB_RST_I : in STD_LOGIC; -- high active sync reset
- WB_CTI_I : in STD_LOGIC_VECTOR(02 downto 0); -- cycle indentifier
- WB_TGC_I : in STD_LOGIC_VECTOR(06 downto 0); -- cycle tag
- WB_ADR_I : in STD_LOGIC_VECTOR(LOG2_MEM_SIZE-1 downto 0); -- adr in
- WB_DATA_I : in STD_LOGIC_VECTOR(31 downto 0); -- write data
- WB_DATA_O : out STD_LOGIC_VECTOR(31 downto 0); -- read data
- WB_SEL_I : in STD_LOGIC_VECTOR(03 downto 0); -- data quantity
- WB_WE_I : in STD_LOGIC; -- write enable
- WB_STB_I : in STD_LOGIC; -- valid cycle
- WB_ACK_O : out STD_LOGIC; -- acknowledge
- WB_HALT_O : out STD_LOGIC; -- throttle master
- WB_ERR_O : out STD_LOGIC -- abnormal cycle termination
- );
-end MEMORY;
-
-architecture Behavioral of MEMORY is
-
- --- Buffer ---
- signal WB_ACK_O_INT : STD_LOGIC;
- signal WB_DATA_INT : STD_LOGIC_VECTOR(31 downto 0);
-
- --- Memory Type ---
- type MEM_FILE_TYPE is array (0 to MEM_SIZE - 1) of STD_LOGIC_VECTOR(31 downto 0);
-
- --- INIT MEMORY IMAGE ---
- ------------------------------------------------------
- signal MEM_FILE : MEM_FILE_TYPE :=
- (
- 000000 => x"EA000012", -- THIS IS A SIMPLE PROGRAM FOR THE STORM DEMO SOC
- 000001 => x"E59FF014",
- 000002 => x"E59FF014",
- 000003 => x"E59FF014",
- 000004 => x"E59FF014",
- 000005 => x"E1A00000",
- 000006 => x"E51FFFF0",
- 000007 => x"E59FF010",
- 000008 => x"00000038",
- 000009 => x"0000003C",
- 000010 => x"00000040",
- 000011 => x"00000044",
- 000012 => x"00000048",
- 000013 => x"0000004C",
- 000014 => x"EAFFFFFE",
- 000015 => x"EAFFFFFE",
- 000016 => x"EAFFFFFE",
- 000017 => x"EAFFFFFE",
- 000018 => x"EAFFFFFE",
- 000019 => x"EAFFFFFE",
- 000020 => x"E59F00C8",
- 000021 => x"E10F1000",
- 000022 => x"E3C1107F",
- 000023 => x"E38110DB",
- 000024 => x"E129F001",
- 000025 => x"E1A0D000",
- 000026 => x"E2400080",
- 000027 => x"E10F1000",
- 000028 => x"E3C1107F",
- 000029 => x"E38110D7",
- 000030 => x"E129F001",
- 000031 => x"E1A0D000",
- 000032 => x"E2400080",
- 000033 => x"E10F1000",
- 000034 => x"E3C1107F",
- 000035 => x"E38110D1",
- 000036 => x"E129F001",
- 000037 => x"E1A0D000",
- 000038 => x"E2400080",
- 000039 => x"E10F1000",
- 000040 => x"E3C1107F",
- 000041 => x"E38110D2",
- 000042 => x"E129F001",
- 000043 => x"E1A0D000",
- 000044 => x"E2400080",
- 000045 => x"E10F1000",
- 000046 => x"E3C1107F",
- 000047 => x"E38110D3",
- 000048 => x"E129F001",
- 000049 => x"E1A0D000",
- 000050 => x"E2400080",
- 000051 => x"E10F1000",
- 000052 => x"E3C1107F",
- 000053 => x"E38110DF",
- 000054 => x"E129F001",
- 000055 => x"E1A0D000",
- 000056 => x"E3A00000",
- 000057 => x"E59F1038",
- 000058 => x"E59F2038",
- 000059 => x"E1510002",
- 000060 => x"0A000001",
- 000061 => x"34810004",
- 000062 => x"3AFFFFFB",
- 000063 => x"E3A00000",
- 000064 => x"E1A01000",
- 000065 => x"E1A02000",
- 000066 => x"E1A0B000",
- 000067 => x"E1A07000",
- 000068 => x"E59FA014",
- 000069 => x"E1A0E00F",
- 000070 => x"E1A0F00A",
- 000071 => x"EAFFFFFE",
- 000072 => x"00000A00",
- 000073 => x"00000184",
- 000074 => x"00000184",
- 000075 => x"00000130",
- 000076 => x"E3E03A01",
- 000077 => x"E3A02000",
- 000078 => x"E52DE004",
- 000079 => x"E5032FDF",
- 000080 => x"E3A0E001",
- 000081 => x"E5032FDF",
- 000082 => x"E1A0100E",
- 000083 => x"E1A0000E",
- 000084 => x"E1A02000",
- 000085 => x"EA000000",
- 000086 => x"E3A0E001",
- 000087 => x"E2820001",
- 000088 => x"E08EC001",
- 000089 => x"E5031FDF",
- 000090 => x"E350001E",
- 000091 => x"E3A01000",
- 000092 => x"E1A02001",
- 000093 => x"CAFFFFF7",
- 000094 => x"E1A0100E",
- 000095 => x"E1A0E00C",
- 000096 => x"EAFFFFF2",
- others => x"F0013007"
- );
- ------------------------------------------------------
-
-begin
-
- -- STORM data/instruction memory -----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- MEM_FILE_ACCESS: process(WB_CLK_I)
- begin
- --- Sync Write ---
- if rising_edge(WB_CLK_I) then
-
- --- Data Read/Write ---
- if (WB_STB_I = '1') then
- if (WB_WE_I = '1') then
- MEM_FILE(to_integer(unsigned(WB_ADR_I))) <= WB_DATA_I;
- end if;
- WB_DATA_INT <= MEM_FILE(to_integer(unsigned(WB_ADR_I)));
- end if;
-
- --- ACK Control ---
- if (WB_RST_I = '1') then
- WB_ACK_O_INT <= '0';
- elsif (WB_CTI_I = "000") or (WB_CTI_I = "111") then
- WB_ACK_O_INT <= WB_STB_I and (not WB_ACK_O_INT);
- else
- WB_ACK_O_INT <= WB_STB_I;
- end if;
-
- end if;
- end process MEM_FILE_ACCESS;
-
- --- Output Gate ---
- WB_DATA_O <= WB_DATA_INT when (OUTPUT_GATE = FALSE) or ((OUTPUT_GATE = TRUE) and (WB_STB_I = '1')) else (others => '0');
-
- --- ACK Signal ---
- WB_ACK_O <= WB_ACK_O_INT;
-
- --- Throttle ---
- WB_HALT_O <= '0'; -- yeay, we're at full speed!
-
- --- Error ---
- WB_ERR_O <= '0'; -- nothing can go wrong ;)
-
-
-
-end Behavioral;
\ No newline at end of file
Index: storm_core/trunk/sim/Xilinx ISIM/storm_core_debug_wave.wcfg
===================================================================
--- storm_core/trunk/sim/Xilinx ISIM/storm_core_debug_wave.wcfg (revision 36)
+++ storm_core/trunk/sim/Xilinx ISIM/storm_core_debug_wave.wcfg (nonexistent)
@@ -1,2477 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
- STORMcore globals
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- core_clk_i
- core_clk_i
-
-
- halt
- halt
-
-
- rst_i
- rst_i
-
-
- STORMcore interrupt
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- ext_int_req_sync[3:0]
- ext_int_req_sync[3:0]
-
-
- cont_exe
- cont_exe
-
-
- new_mode[4:0]
- new_mode[4:0]
-
-
- STORMcore pipeline
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- of_ctrl_o[45:0]
- of_ctrl_o[45:0]
-
-
- ms_ctrl_o[45:0]
- ms_ctrl_o[45:0]
-
-
- ex1_ctrl_o[45:0]
- ex1_ctrl_o[45:0]
-
-
- mem_ctrl_o[45:0]
- mem_ctrl_o[45:0]
-
-
- wb_ctrl_o[45:0]
- wb_ctrl_o[45:0]
-
-
- STORMcore registers
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- reg_file[0:31]
- reg_file[0:31]
- HEXRADIX
-
- [0]
- reg_file[0]
- HEXRADIX
-
-
- [1]
- reg_file[1]
- HEXRADIX
-
-
- [2]
- reg_file[2]
- HEXRADIX
-
-
- [3]
- reg_file[3]
- HEXRADIX
-
-
- [4]
- reg_file[4]
- HEXRADIX
-
-
- [5]
- reg_file[5]
- HEXRADIX
-
-
- [6]
- reg_file[6]
- HEXRADIX
-
-
- [7]
- reg_file[7]
- HEXRADIX
-
-
- [8]
- reg_file[8]
- HEXRADIX
-
-
- [9]
- reg_file[9]
- HEXRADIX
-
-
- [10]
- reg_file[10]
- HEXRADIX
-
-
- [11]
- reg_file[11]
- HEXRADIX
-
-
- [12]
- reg_file[12]
- HEXRADIX
-
-
- [13]
- reg_file[13]
- HEXRADIX
-
-
- [14]
- reg_file[14]
- HEXRADIX
-
-
- [15]
- reg_file[15]
- HEXRADIX
-
-
- [16]
- reg_file[16]
- HEXRADIX
-
-
- [17]
- reg_file[17]
- HEXRADIX
-
-
- [18]
- reg_file[18]
- HEXRADIX
-
-
- [19]
- reg_file[19]
- HEXRADIX
-
-
- [20]
- reg_file[20]
- HEXRADIX
-
-
- [21]
- reg_file[21]
- HEXRADIX
-
-
- [22]
- reg_file[22]
- HEXRADIX
-
-
- [23]
- reg_file[23]
- HEXRADIX
-
-
- [24]
- reg_file[24]
- HEXRADIX
-
-
- [25]
- reg_file[25]
- HEXRADIX
-
-
- [26]
- reg_file[26]
- HEXRADIX
-
-
- [27]
- reg_file[27]
- HEXRADIX
-
-
- [28]
- reg_file[28]
- HEXRADIX
-
-
- [29]
- reg_file[29]
- HEXRADIX
-
-
- [30]
- reg_file[30]
- HEXRADIX
-
-
- [31]
- reg_file[31]
- HEXRADIX
-
-
-
- mcr_pc[31:0]
- mcr_pc[31:0]
- HEXRADIX
- true
- #ff0000
-
-
- instr_reg[31:0]
- instr_reg[31:0]
- HEXRADIX
- true
- #0000ff
-
-
- mcr_cmsr[31:0]
- mcr_cmsr[31:0]
- true
- #ffffff
-
-
- cp_reg_file[15:0]
- cp_reg_file[15:0]
-
- [15]
- cp_reg_file[15]
- HEXRADIX
-
-
- [14]
- cp_reg_file[14]
- HEXRADIX
-
-
- [13]
- cp_reg_file[13]
- HEXRADIX
-
-
- [12]
- cp_reg_file[12]
- HEXRADIX
-
-
- [11]
- cp_reg_file[11]
- HEXRADIX
-
-
- [10]
- cp_reg_file[10]
- HEXRADIX
-
-
- [9]
- cp_reg_file[9]
- HEXRADIX
-
-
- [8]
- cp_reg_file[8]
- HEXRADIX
-
-
- [7]
- cp_reg_file[7]
- HEXRADIX
-
-
- [6]
- cp_reg_file[6]
- HEXRADIX
-
-
- [5]
- cp_reg_file[5]
- HEXRADIX
-
-
- [4]
- cp_reg_file[4]
- HEXRADIX
-
-
- [3]
- cp_reg_file[3]
- HEXRADIX
-
-
- [2]
- cp_reg_file[2]
- HEXRADIX
-
-
- [1]
- cp_reg_file[1]
- HEXRADIX
-
-
- [0]
- cp_reg_file[0]
- HEXRADIX
-
-
-
- DATA CACHE
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- arb_state
- arb_state
-
-
- b_cs_i
- b_cs_i
-
-
- p_adr_i[31:0]
- p_adr_i[31:0]
- HEXRADIX
-
-
- sim_mem[0:7]
- sim_mem[0:7]
- HEXRADIX
-
- [0]
- sim_mem[0]
- HEXRADIX
-
-
- [1]
- sim_mem[1]
- HEXRADIX
-
-
- [2]
- sim_mem[2]
- HEXRADIX
-
-
- [3]
- sim_mem[3]
- HEXRADIX
-
-
- [4]
- sim_mem[4]
- HEXRADIX
-
-
- [5]
- sim_mem[5]
- HEXRADIX
-
-
- [6]
- sim_mem[6]
- HEXRADIX
-
-
- [7]
- sim_mem[7]
- HEXRADIX
-
-
-
- INSTRUCTION CACHE
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- arb_state
- arb_state
-
-
- sim_mem[0:127]
- sim_mem[0:127]
- HEXRADIX
-
- [0]
- sim_mem[0]
- HEXRADIX
-
-
- [1]
- sim_mem[1]
- HEXRADIX
-
-
- [2]
- sim_mem[2]
- HEXRADIX
-
-
- [3]
- sim_mem[3]
- HEXRADIX
-
-
- [4]
- sim_mem[4]
- HEXRADIX
-
-
- [5]
- sim_mem[5]
- HEXRADIX
-
-
- [6]
- sim_mem[6]
- HEXRADIX
-
-
- [7]
- sim_mem[7]
- HEXRADIX
-
-
- [8]
- sim_mem[8]
- HEXRADIX
-
-
- [9]
- sim_mem[9]
- HEXRADIX
-
-
- [10]
- sim_mem[10]
- HEXRADIX
-
-
- [11]
- sim_mem[11]
- HEXRADIX
-
-
- [12]
- sim_mem[12]
- HEXRADIX
-
-
- [13]
- sim_mem[13]
- HEXRADIX
-
-
- [14]
- sim_mem[14]
- HEXRADIX
-
-
- [15]
- sim_mem[15]
- HEXRADIX
-
-
- [16]
- sim_mem[16]
- HEXRADIX
-
-
- [17]
- sim_mem[17]
- HEXRADIX
-
-
- [18]
- sim_mem[18]
- HEXRADIX
-
-
- [19]
- sim_mem[19]
- HEXRADIX
-
-
- [20]
- sim_mem[20]
- HEXRADIX
-
-
- [21]
- sim_mem[21]
- HEXRADIX
-
-
- [22]
- sim_mem[22]
- HEXRADIX
-
-
- [23]
- sim_mem[23]
- HEXRADIX
-
-
- [24]
- sim_mem[24]
- HEXRADIX
-
-
- [25]
- sim_mem[25]
- HEXRADIX
-
-
- [26]
- sim_mem[26]
- HEXRADIX
-
-
- [27]
- sim_mem[27]
- HEXRADIX
-
-
- [28]
- sim_mem[28]
- HEXRADIX
-
-
- [29]
- sim_mem[29]
- HEXRADIX
-
-
- [30]
- sim_mem[30]
- HEXRADIX
-
-
- [31]
- sim_mem[31]
- HEXRADIX
-
-
- [32]
- sim_mem[32]
- HEXRADIX
-
-
- [33]
- sim_mem[33]
- HEXRADIX
-
-
- [34]
- sim_mem[34]
- HEXRADIX
-
-
- [35]
- sim_mem[35]
- HEXRADIX
-
-
- [36]
- sim_mem[36]
- HEXRADIX
-
-
- [37]
- sim_mem[37]
- HEXRADIX
-
-
- [38]
- sim_mem[38]
- HEXRADIX
-
-
- [39]
- sim_mem[39]
- HEXRADIX
-
-
- [40]
- sim_mem[40]
- HEXRADIX
-
-
- [41]
- sim_mem[41]
- HEXRADIX
-
-
- [42]
- sim_mem[42]
- HEXRADIX
-
-
- [43]
- sim_mem[43]
- HEXRADIX
-
-
- [44]
- sim_mem[44]
- HEXRADIX
-
-
- [45]
- sim_mem[45]
- HEXRADIX
-
-
- [46]
- sim_mem[46]
- HEXRADIX
-
-
- [47]
- sim_mem[47]
- HEXRADIX
-
-
- [48]
- sim_mem[48]
- HEXRADIX
-
-
- [49]
- sim_mem[49]
- HEXRADIX
-
-
- [50]
- sim_mem[50]
- HEXRADIX
-
-
- [51]
- sim_mem[51]
- HEXRADIX
-
-
- [52]
- sim_mem[52]
- HEXRADIX
-
-
- [53]
- sim_mem[53]
- HEXRADIX
-
-
- [54]
- sim_mem[54]
- HEXRADIX
-
-
- [55]
- sim_mem[55]
- HEXRADIX
-
-
- [56]
- sim_mem[56]
- HEXRADIX
-
-
- [57]
- sim_mem[57]
- HEXRADIX
-
-
- [58]
- sim_mem[58]
- HEXRADIX
-
-
- [59]
- sim_mem[59]
- HEXRADIX
-
-
- [60]
- sim_mem[60]
- HEXRADIX
-
-
- [61]
- sim_mem[61]
- HEXRADIX
-
-
- [62]
- sim_mem[62]
- HEXRADIX
-
-
- [63]
- sim_mem[63]
- HEXRADIX
-
-
- [64]
- sim_mem[64]
- HEXRADIX
-
-
- [65]
- sim_mem[65]
- HEXRADIX
-
-
- [66]
- sim_mem[66]
- HEXRADIX
-
-
- [67]
- sim_mem[67]
- HEXRADIX
-
-
- [68]
- sim_mem[68]
- HEXRADIX
-
-
- [69]
- sim_mem[69]
- HEXRADIX
-
-
- [70]
- sim_mem[70]
- HEXRADIX
-
-
- [71]
- sim_mem[71]
- HEXRADIX
-
-
- [72]
- sim_mem[72]
- HEXRADIX
-
-
- [73]
- sim_mem[73]
- HEXRADIX
-
-
- [74]
- sim_mem[74]
- HEXRADIX
-
-
- [75]
- sim_mem[75]
- HEXRADIX
-
-
- [76]
- sim_mem[76]
- HEXRADIX
-
-
- [77]
- sim_mem[77]
- HEXRADIX
-
-
- [78]
- sim_mem[78]
- HEXRADIX
-
-
- [79]
- sim_mem[79]
- HEXRADIX
-
-
- [80]
- sim_mem[80]
- HEXRADIX
-
-
- [81]
- sim_mem[81]
- HEXRADIX
-
-
- [82]
- sim_mem[82]
- HEXRADIX
-
-
- [83]
- sim_mem[83]
- HEXRADIX
-
-
- [84]
- sim_mem[84]
- HEXRADIX
-
-
- [85]
- sim_mem[85]
- HEXRADIX
-
-
- [86]
- sim_mem[86]
- HEXRADIX
-
-
- [87]
- sim_mem[87]
- HEXRADIX
-
-
- [88]
- sim_mem[88]
- HEXRADIX
-
-
- [89]
- sim_mem[89]
- HEXRADIX
-
-
- [90]
- sim_mem[90]
- HEXRADIX
-
-
- [91]
- sim_mem[91]
- HEXRADIX
-
-
- [92]
- sim_mem[92]
- HEXRADIX
-
-
- [93]
- sim_mem[93]
- HEXRADIX
-
-
- [94]
- sim_mem[94]
- HEXRADIX
-
-
- [95]
- sim_mem[95]
- HEXRADIX
-
-
- [96]
- sim_mem[96]
- HEXRADIX
-
-
- [97]
- sim_mem[97]
- HEXRADIX
-
-
- [98]
- sim_mem[98]
- HEXRADIX
-
-
- [99]
- sim_mem[99]
- HEXRADIX
-
-
- [100]
- sim_mem[100]
- HEXRADIX
-
-
- [101]
- sim_mem[101]
- HEXRADIX
-
-
- [102]
- sim_mem[102]
- HEXRADIX
-
-
- [103]
- sim_mem[103]
- HEXRADIX
-
-
- [104]
- sim_mem[104]
- HEXRADIX
-
-
- [105]
- sim_mem[105]
- HEXRADIX
-
-
- [106]
- sim_mem[106]
- HEXRADIX
-
-
- [107]
- sim_mem[107]
- HEXRADIX
-
-
- [108]
- sim_mem[108]
- HEXRADIX
-
-
- [109]
- sim_mem[109]
- HEXRADIX
-
-
- [110]
- sim_mem[110]
- HEXRADIX
-
-
- [111]
- sim_mem[111]
- HEXRADIX
-
-
- [112]
- sim_mem[112]
- HEXRADIX
-
-
- [113]
- sim_mem[113]
- HEXRADIX
-
-
- [114]
- sim_mem[114]
- HEXRADIX
-
-
- [115]
- sim_mem[115]
- HEXRADIX
-
-
- [116]
- sim_mem[116]
- HEXRADIX
-
-
- [117]
- sim_mem[117]
- HEXRADIX
-
-
- [118]
- sim_mem[118]
- HEXRADIX
-
-
- [119]
- sim_mem[119]
- HEXRADIX
-
-
- [120]
- sim_mem[120]
- HEXRADIX
-
-
- [121]
- sim_mem[121]
- HEXRADIX
-
-
- [122]
- sim_mem[122]
- HEXRADIX
-
-
- [123]
- sim_mem[123]
- HEXRADIX
-
-
- [124]
- sim_mem[124]
- HEXRADIX
-
-
- [125]
- sim_mem[125]
- HEXRADIX
-
-
- [126]
- sim_mem[126]
- HEXRADIX
-
-
- [127]
- sim_mem[127]
- HEXRADIX
-
-
-
- BUS UNIT
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- timeout_cnt[15:0]
- timeout_cnt[15:0]
- UNSIGNEDDECRADIX
-
-
- arb_state
- arb_state
-
-
- io_access
- io_access
-
-
- dc_miss_i
- dc_miss_i
-
-
- dc_dirty_i
- dc_dirty_i
-
-
- freeze_storm_o
- freeze_storm_o
-
-
- WISHBONE BUS
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- core_wb_stb_o
- core_wb_stb_o
-
-
- core_wb_adr_o[31:0]
- core_wb_adr_o[31:0]
- HEXRADIX
-
-
- core_wb_we_o
- core_wb_we_o
-
-
- core_wb_data_o[31:0]
- core_wb_data_o[31:0]
- HEXRADIX
-
-
- core_wb_data_i[31:0]
- core_wb_data_i[31:0]
- HEXRADIX
-
-
- core_wb_ack_i
- core_wb_ack_i
-
-
- core_wb_halt_i
- core_wb_halt_i
-
-
- core_wb_err_i
- core_wb_err_i
-
-
- INTERNAL MEMORY
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- wb_stb_i
- wb_stb_i
-
-
- wb_ack_o
- wb_ack_o
-
-
- sim_mem[0:255]
- sim_mem[0:255]
- HEXRADIX
-
- [0]
- sim_mem[0]
- HEXRADIX
-
-
- [1]
- sim_mem[1]
- HEXRADIX
-
-
- [2]
- sim_mem[2]
- HEXRADIX
-
-
- [3]
- sim_mem[3]
- HEXRADIX
-
-
- [4]
- sim_mem[4]
- HEXRADIX
-
-
- [5]
- sim_mem[5]
- HEXRADIX
-
-
- [6]
- sim_mem[6]
- HEXRADIX
-
-
- [7]
- sim_mem[7]
- HEXRADIX
-
-
- [8]
- sim_mem[8]
- HEXRADIX
-
-
- [9]
- sim_mem[9]
- HEXRADIX
-
-
- [10]
- sim_mem[10]
- HEXRADIX
-
-
- [11]
- sim_mem[11]
- HEXRADIX
-
-
- [12]
- sim_mem[12]
- HEXRADIX
-
-
- [13]
- sim_mem[13]
- HEXRADIX
-
-
- [14]
- sim_mem[14]
- HEXRADIX
-
-
- [15]
- sim_mem[15]
- HEXRADIX
-
-
- [16]
- sim_mem[16]
- HEXRADIX
-
-
- [17]
- sim_mem[17]
- HEXRADIX
-
-
- [18]
- sim_mem[18]
- HEXRADIX
-
-
- [19]
- sim_mem[19]
- HEXRADIX
-
-
- [20]
- sim_mem[20]
- HEXRADIX
-
-
- [21]
- sim_mem[21]
- HEXRADIX
-
-
- [22]
- sim_mem[22]
- HEXRADIX
-
-
- [23]
- sim_mem[23]
- HEXRADIX
-
-
- [24]
- sim_mem[24]
- HEXRADIX
-
-
- [25]
- sim_mem[25]
- HEXRADIX
-
-
- [26]
- sim_mem[26]
- HEXRADIX
-
-
- [27]
- sim_mem[27]
- HEXRADIX
-
-
- [28]
- sim_mem[28]
- HEXRADIX
-
-
- [29]
- sim_mem[29]
- HEXRADIX
-
-
- [30]
- sim_mem[30]
- HEXRADIX
-
-
- [31]
- sim_mem[31]
- HEXRADIX
-
-
- [32]
- sim_mem[32]
- HEXRADIX
-
-
- [33]
- sim_mem[33]
- HEXRADIX
-
-
- [34]
- sim_mem[34]
- HEXRADIX
-
-
- [35]
- sim_mem[35]
- HEXRADIX
-
-
- [36]
- sim_mem[36]
- HEXRADIX
-
-
- [37]
- sim_mem[37]
- HEXRADIX
-
-
- [38]
- sim_mem[38]
- HEXRADIX
-
-
- [39]
- sim_mem[39]
- HEXRADIX
-
-
- [40]
- sim_mem[40]
- HEXRADIX
-
-
- [41]
- sim_mem[41]
- HEXRADIX
-
-
- [42]
- sim_mem[42]
- HEXRADIX
-
-
- [43]
- sim_mem[43]
- HEXRADIX
-
-
- [44]
- sim_mem[44]
- HEXRADIX
-
-
- [45]
- sim_mem[45]
- HEXRADIX
-
-
- [46]
- sim_mem[46]
- HEXRADIX
-
-
- [47]
- sim_mem[47]
- HEXRADIX
-
-
- [48]
- sim_mem[48]
- HEXRADIX
-
-
- [49]
- sim_mem[49]
- HEXRADIX
-
-
- [50]
- sim_mem[50]
- HEXRADIX
-
-
- [51]
- sim_mem[51]
- HEXRADIX
-
-
- [52]
- sim_mem[52]
- HEXRADIX
-
-
- [53]
- sim_mem[53]
- HEXRADIX
-
-
- [54]
- sim_mem[54]
- HEXRADIX
-
-
- [55]
- sim_mem[55]
- HEXRADIX
-
-
- [56]
- sim_mem[56]
- HEXRADIX
-
-
- [57]
- sim_mem[57]
- HEXRADIX
-
-
- [58]
- sim_mem[58]
- HEXRADIX
-
-
- [59]
- sim_mem[59]
- HEXRADIX
-
-
- [60]
- sim_mem[60]
- HEXRADIX
-
-
- [61]
- sim_mem[61]
- HEXRADIX
-
-
- [62]
- sim_mem[62]
- HEXRADIX
-
-
- [63]
- sim_mem[63]
- HEXRADIX
-
-
- [64]
- sim_mem[64]
- HEXRADIX
-
-
- [65]
- sim_mem[65]
- HEXRADIX
-
-
- [66]
- sim_mem[66]
- HEXRADIX
-
-
- [67]
- sim_mem[67]
- HEXRADIX
-
-
- [68]
- sim_mem[68]
- HEXRADIX
-
-
- [69]
- sim_mem[69]
- HEXRADIX
-
-
- [70]
- sim_mem[70]
- HEXRADIX
-
-
- [71]
- sim_mem[71]
- HEXRADIX
-
-
- [72]
- sim_mem[72]
- HEXRADIX
-
-
- [73]
- sim_mem[73]
- HEXRADIX
-
-
- [74]
- sim_mem[74]
- HEXRADIX
-
-
- [75]
- sim_mem[75]
- HEXRADIX
-
-
- [76]
- sim_mem[76]
- HEXRADIX
-
-
- [77]
- sim_mem[77]
- HEXRADIX
-
-
- [78]
- sim_mem[78]
- HEXRADIX
-
-
- [79]
- sim_mem[79]
- HEXRADIX
-
-
- [80]
- sim_mem[80]
- HEXRADIX
-
-
- [81]
- sim_mem[81]
- HEXRADIX
-
-
- [82]
- sim_mem[82]
- HEXRADIX
-
-
- [83]
- sim_mem[83]
- HEXRADIX
-
-
- [84]
- sim_mem[84]
- HEXRADIX
-
-
- [85]
- sim_mem[85]
- HEXRADIX
-
-
- [86]
- sim_mem[86]
- HEXRADIX
-
-
- [87]
- sim_mem[87]
- HEXRADIX
-
-
- [88]
- sim_mem[88]
- HEXRADIX
-
-
- [89]
- sim_mem[89]
- HEXRADIX
-
-
- [90]
- sim_mem[90]
- HEXRADIX
-
-
- [91]
- sim_mem[91]
- HEXRADIX
-
-
- [92]
- sim_mem[92]
- HEXRADIX
-
-
- [93]
- sim_mem[93]
- HEXRADIX
-
-
- [94]
- sim_mem[94]
- HEXRADIX
-
-
- [95]
- sim_mem[95]
- HEXRADIX
-
-
- [96]
- sim_mem[96]
- HEXRADIX
-
-
- [97]
- sim_mem[97]
- HEXRADIX
-
-
- [98]
- sim_mem[98]
- HEXRADIX
-
-
- [99]
- sim_mem[99]
- HEXRADIX
-
-
- [100]
- sim_mem[100]
- HEXRADIX
-
-
- [101]
- sim_mem[101]
- HEXRADIX
-
-
- [102]
- sim_mem[102]
- HEXRADIX
-
-
- [103]
- sim_mem[103]
- HEXRADIX
-
-
- [104]
- sim_mem[104]
- HEXRADIX
-
-
- [105]
- sim_mem[105]
- HEXRADIX
-
-
- [106]
- sim_mem[106]
- HEXRADIX
-
-
- [107]
- sim_mem[107]
- HEXRADIX
-
-
- [108]
- sim_mem[108]
- HEXRADIX
-
-
- [109]
- sim_mem[109]
- HEXRADIX
-
-
- [110]
- sim_mem[110]
- HEXRADIX
-
-
- [111]
- sim_mem[111]
- HEXRADIX
-
-
- [112]
- sim_mem[112]
- HEXRADIX
-
-
- [113]
- sim_mem[113]
- HEXRADIX
-
-
- [114]
- sim_mem[114]
- HEXRADIX
-
-
- [115]
- sim_mem[115]
- HEXRADIX
-
-
- [116]
- sim_mem[116]
- HEXRADIX
-
-
- [117]
- sim_mem[117]
- HEXRADIX
-
-
- [118]
- sim_mem[118]
- HEXRADIX
-
-
- [119]
- sim_mem[119]
- HEXRADIX
-
-
- [120]
- sim_mem[120]
- HEXRADIX
-
-
- [121]
- sim_mem[121]
- HEXRADIX
-
-
- [122]
- sim_mem[122]
- HEXRADIX
-
-
- [123]
- sim_mem[123]
- HEXRADIX
-
-
- [124]
- sim_mem[124]
- HEXRADIX
-
-
- [125]
- sim_mem[125]
- HEXRADIX
-
-
- [126]
- sim_mem[126]
- HEXRADIX
-
-
- [127]
- sim_mem[127]
- HEXRADIX
-
-
- [128]
- sim_mem[128]
- HEXRADIX
-
-
- [129]
- sim_mem[129]
- HEXRADIX
-
-
- [130]
- sim_mem[130]
- HEXRADIX
-
-
- [131]
- sim_mem[131]
- HEXRADIX
-
-
- [132]
- sim_mem[132]
- HEXRADIX
-
-
- [133]
- sim_mem[133]
- HEXRADIX
-
-
- [134]
- sim_mem[134]
- HEXRADIX
-
-
- [135]
- sim_mem[135]
- HEXRADIX
-
-
- [136]
- sim_mem[136]
- HEXRADIX
-
-
- [137]
- sim_mem[137]
- HEXRADIX
-
-
- [138]
- sim_mem[138]
- HEXRADIX
-
-
- [139]
- sim_mem[139]
- HEXRADIX
-
-
- [140]
- sim_mem[140]
- HEXRADIX
-
-
- [141]
- sim_mem[141]
- HEXRADIX
-
-
- [142]
- sim_mem[142]
- HEXRADIX
-
-
- [143]
- sim_mem[143]
- HEXRADIX
-
-
- [144]
- sim_mem[144]
- HEXRADIX
-
-
- [145]
- sim_mem[145]
- HEXRADIX
-
-
- [146]
- sim_mem[146]
- HEXRADIX
-
-
- [147]
- sim_mem[147]
- HEXRADIX
-
-
- [148]
- sim_mem[148]
- HEXRADIX
-
-
- [149]
- sim_mem[149]
- HEXRADIX
-
-
- [150]
- sim_mem[150]
- HEXRADIX
-
-
- [151]
- sim_mem[151]
- HEXRADIX
-
-
- [152]
- sim_mem[152]
- HEXRADIX
-
-
- [153]
- sim_mem[153]
- HEXRADIX
-
-
- [154]
- sim_mem[154]
- HEXRADIX
-
-
- [155]
- sim_mem[155]
- HEXRADIX
-
-
- [156]
- sim_mem[156]
- HEXRADIX
-
-
- [157]
- sim_mem[157]
- HEXRADIX
-
-
- [158]
- sim_mem[158]
- HEXRADIX
-
-
- [159]
- sim_mem[159]
- HEXRADIX
-
-
- [160]
- sim_mem[160]
- HEXRADIX
-
-
- [161]
- sim_mem[161]
- HEXRADIX
-
-
- [162]
- sim_mem[162]
- HEXRADIX
-
-
- [163]
- sim_mem[163]
- HEXRADIX
-
-
- [164]
- sim_mem[164]
- HEXRADIX
-
-
- [165]
- sim_mem[165]
- HEXRADIX
-
-
- [166]
- sim_mem[166]
- HEXRADIX
-
-
- [167]
- sim_mem[167]
- HEXRADIX
-
-
- [168]
- sim_mem[168]
- HEXRADIX
-
-
- [169]
- sim_mem[169]
- HEXRADIX
-
-
- [170]
- sim_mem[170]
- HEXRADIX
-
-
- [171]
- sim_mem[171]
- HEXRADIX
-
-
- [172]
- sim_mem[172]
- HEXRADIX
-
-
- [173]
- sim_mem[173]
- HEXRADIX
-
-
- [174]
- sim_mem[174]
- HEXRADIX
-
-
- [175]
- sim_mem[175]
- HEXRADIX
-
-
- [176]
- sim_mem[176]
- HEXRADIX
-
-
- [177]
- sim_mem[177]
- HEXRADIX
-
-
- [178]
- sim_mem[178]
- HEXRADIX
-
-
- [179]
- sim_mem[179]
- HEXRADIX
-
-
- [180]
- sim_mem[180]
- HEXRADIX
-
-
- [181]
- sim_mem[181]
- HEXRADIX
-
-
- [182]
- sim_mem[182]
- HEXRADIX
-
-
- [183]
- sim_mem[183]
- HEXRADIX
-
-
- [184]
- sim_mem[184]
- HEXRADIX
-
-
- [185]
- sim_mem[185]
- HEXRADIX
-
-
- [186]
- sim_mem[186]
- HEXRADIX
-
-
- [187]
- sim_mem[187]
- HEXRADIX
-
-
- [188]
- sim_mem[188]
- HEXRADIX
-
-
- [189]
- sim_mem[189]
- HEXRADIX
-
-
- [190]
- sim_mem[190]
- HEXRADIX
-
-
- [191]
- sim_mem[191]
- HEXRADIX
-
-
- [192]
- sim_mem[192]
- HEXRADIX
-
-
- [193]
- sim_mem[193]
- HEXRADIX
-
-
- [194]
- sim_mem[194]
- HEXRADIX
-
-
- [195]
- sim_mem[195]
- HEXRADIX
-
-
- [196]
- sim_mem[196]
- HEXRADIX
-
-
- [197]
- sim_mem[197]
- HEXRADIX
-
-
- [198]
- sim_mem[198]
- HEXRADIX
-
-
- [199]
- sim_mem[199]
- HEXRADIX
-
-
- [200]
- sim_mem[200]
- HEXRADIX
-
-
- [201]
- sim_mem[201]
- HEXRADIX
-
-
- [202]
- sim_mem[202]
- HEXRADIX
-
-
- [203]
- sim_mem[203]
- HEXRADIX
-
-
- [204]
- sim_mem[204]
- HEXRADIX
-
-
- [205]
- sim_mem[205]
- HEXRADIX
-
-
- [206]
- sim_mem[206]
- HEXRADIX
-
-
- [207]
- sim_mem[207]
- HEXRADIX
-
-
- [208]
- sim_mem[208]
- HEXRADIX
-
-
- [209]
- sim_mem[209]
- HEXRADIX
-
-
- [210]
- sim_mem[210]
- HEXRADIX
-
-
- [211]
- sim_mem[211]
- HEXRADIX
-
-
- [212]
- sim_mem[212]
- HEXRADIX
-
-
- [213]
- sim_mem[213]
- HEXRADIX
-
-
- [214]
- sim_mem[214]
- HEXRADIX
-
-
- [215]
- sim_mem[215]
- HEXRADIX
-
-
- [216]
- sim_mem[216]
- HEXRADIX
-
-
- [217]
- sim_mem[217]
- HEXRADIX
-
-
- [218]
- sim_mem[218]
- HEXRADIX
-
-
- [219]
- sim_mem[219]
- HEXRADIX
-
-
- [220]
- sim_mem[220]
- HEXRADIX
-
-
- [221]
- sim_mem[221]
- HEXRADIX
-
-
- [222]
- sim_mem[222]
- HEXRADIX
-
-
- [223]
- sim_mem[223]
- HEXRADIX
-
-
- [224]
- sim_mem[224]
- HEXRADIX
-
-
- [225]
- sim_mem[225]
- HEXRADIX
-
-
- [226]
- sim_mem[226]
- HEXRADIX
-
-
- [227]
- sim_mem[227]
- HEXRADIX
-
-
- [228]
- sim_mem[228]
- HEXRADIX
-
-
- [229]
- sim_mem[229]
- HEXRADIX
-
-
- [230]
- sim_mem[230]
- HEXRADIX
-
-
- [231]
- sim_mem[231]
- HEXRADIX
-
-
- [232]
- sim_mem[232]
- HEXRADIX
-
-
- [233]
- sim_mem[233]
- HEXRADIX
-
-
- [234]
- sim_mem[234]
- HEXRADIX
-
-
- [235]
- sim_mem[235]
- HEXRADIX
-
-
- [236]
- sim_mem[236]
- HEXRADIX
-
-
- [237]
- sim_mem[237]
- HEXRADIX
-
-
- [238]
- sim_mem[238]
- HEXRADIX
-
-
- [239]
- sim_mem[239]
- HEXRADIX
-
-
- [240]
- sim_mem[240]
- HEXRADIX
-
-
- [241]
- sim_mem[241]
- HEXRADIX
-
-
- [242]
- sim_mem[242]
- HEXRADIX
-
-
- [243]
- sim_mem[243]
- HEXRADIX
-
-
- [244]
- sim_mem[244]
- HEXRADIX
-
-
- [245]
- sim_mem[245]
- HEXRADIX
-
-
- [246]
- sim_mem[246]
- HEXRADIX
-
-
- [247]
- sim_mem[247]
- HEXRADIX
-
-
- [248]
- sim_mem[248]
- HEXRADIX
-
-
- [249]
- sim_mem[249]
- HEXRADIX
-
-
- [250]
- sim_mem[250]
- HEXRADIX
-
-
- [251]
- sim_mem[251]
- HEXRADIX
-
-
- [252]
- sim_mem[252]
- HEXRADIX
-
-
- [253]
- sim_mem[253]
- HEXRADIX
-
-
- [254]
- sim_mem[254]
- HEXRADIX
-
-
- [255]
- sim_mem[255]
- HEXRADIX
-
-
-
- IO Controller
- label
- #3e3e3e
- 230 230 230
- HEXRADIX
-
-
- wb_stb_i
- wb_stb_i
-
-
- wb_ack_o
- wb_ack_o
-
-
- io_o_sync[31:0]
- io_o_sync[31:0]
- HEXRADIX
-
-
- io_o_sync[31:0]
- io_o_sync[31:0]
- UNSIGNEDDECRADIX
-
-