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/tlb/rtl/datacache.v
1,12 → 1,27
`include "config.v" |
|
module datacache(input clk,input stall,input [4:0] stginhibit,input [4:0] codemiss,input [31:0] addrA,output `muxnet [511:0] dataA,input [511:0] cacheLine,input [31:0] writeData,output `muxnet cacheHit,input readen,input writeen,input insert,input initEntry,input [1:0] readsz,output `muxnet [31:0] oldAddr); |
module datacache( |
input clk, |
input stall, |
input [4:0] stginhibit, |
input [4:0] codemiss, |
input [31:0] addrA, |
output wire [511:0] dataA, |
input [511:0] cacheLine, |
input [31:0] writeData, |
output wire cacheHit, |
input readen, |
input writeen, |
input insert, |
input initEntry, |
input [1:0] readsz, |
output wire [31:0] oldAddr); |
|
wire tagwe; |
wire [31:0] tagAddrA; |
wire [31:0] tagAddrW; |
wire [119:0] tagDataA; |
`muxnet [119:0] tagDataW; |
wire [119:0] tagDataW; |
reg [31:0] tagAddrA_reg; |
|
reg readen_reg=0; |
39,7 → 54,7
wire [1:0] newPos2; |
wire [1:0] newPos3; |
|
`muxnet hit3,hit2,hit1,hit0; |
wire hit3,hit2,hit1,hit0; |
wire hit; |
|
wire ram0We,ram1We,ram2We,ram3We; |
96,90 → 111,90
assign pad1[5:0]=6'b0; |
assign pad0[5:0]=6'b0; |
|
assign hit3=(readen_reg || writeen_reg) ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit2=(readen_reg || writeen_reg) ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit1=(readen_reg || writeen_reg) ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit0=(readen_reg || writeen_reg) ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit3=(readen_reg || writeen_reg) ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'bz; |
assign hit2=(readen_reg || writeen_reg) ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'bz; |
assign hit1=(readen_reg || writeen_reg) ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'bz; |
assign hit0=(readen_reg || writeen_reg) ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'bz; |
|
assign hit3=insert_reg ? (pos3==2'b11) : 1'b`muxval; |
assign hit2=insert_reg ? (pos2==2'b11) : 1'b`muxval; |
assign hit1=insert_reg ? (pos1==2'b11) : 1'b`muxval; |
assign hit0=insert_reg ? (pos0==2'b11) : 1'b`muxval; |
assign hit3=insert_reg ? (pos3==2'b11) : 1'bz; |
assign hit2=insert_reg ? (pos2==2'b11) : 1'bz; |
assign hit1=insert_reg ? (pos1==2'b11) : 1'bz; |
assign hit0=insert_reg ? (pos0==2'b11) : 1'bz; |
|
assign hit3=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval; |
assign hit2=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval; |
assign hit1=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval; |
assign hit0=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'b`muxval; |
assign hit3=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz; |
assign hit2=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz; |
assign hit1=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz; |
assign hit0=(!insert_reg && !readen_reg && !writeen_reg) ? 1'b0 : 1'bz; |
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assign hit=hit3 || hit2 || hit1 || hit0; |
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assign cacheHit= (insert_reg && hit0) ? val0 && dir0 : 1'b`muxval; |
assign cacheHit= (insert_reg && hit1) ? val1 && dir1 : 1'b`muxval; |
assign cacheHit= (insert_reg && hit2) ? val2 && dir2 : 1'b`muxval; |
assign cacheHit= (insert_reg && hit3) ? val3 && dir3 : 1'b`muxval; |
assign cacheHit= insert_reg ? 1'b`muxval : hit; |
assign cacheHit= (insert_reg && hit0) ? val0 && dir0 : 1'bz; |
assign cacheHit= (insert_reg && hit1) ? val1 && dir1 : 1'bz; |
assign cacheHit= (insert_reg && hit2) ? val2 && dir2 : 1'bz; |
assign cacheHit= (insert_reg && hit3) ? val3 && dir3 : 1'bz; |
assign cacheHit= insert_reg ? 1'bz : hit; |
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assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
dir3,dir2,dir1,dir0 } : 120'b`muxval; |
dir3,dir2,dir1,dir0 } : 120'bz; |
assign tagDataW=(writeen_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
dir3,dir2,dir1,1'b1 } : 120'b`muxval; |
dir3,dir2,dir1,1'b1 } : 120'bz; |
assign tagDataW=(writeen_reg && hit1) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
dir3,dir2,1'b1,dir0 } : 120'b`muxval; |
dir3,dir2,1'b1,dir0 } : 120'bz; |
assign tagDataW=(writeen_reg && hit2) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
dir3,1'b1,dir1,dir0 } : 120'b`muxval; |
dir3,1'b1,dir1,dir0 } : 120'bz; |
assign tagDataW=(writeen_reg && hit3) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
1'b1,dir2,dir1,dir0 } : 120'b`muxval; |
1'b1,dir2,dir1,dir0 } : 120'bz; |
assign tagDataW=(writeen_reg && !hit) ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,val0, |
dir3,dir2,dir1,dir0 } : 120'b`muxval; |
dir3,dir2,dir1,dir0 } : 120'bz; |
|
assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,val1,1'b1, |
dir3,dir2,dir1,1'b0 } : 120'b`muxval; |
dir3,dir2,dir1,1'b0 } : 120'bz; |
assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,val2,1'b1,val0, |
dir3,dir2,1'b0,dir0 } : 120'b`muxval; |
dir3,dir2,1'b0,dir0 } : 120'bz; |
assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
val3,1'b1,val1,val0, |
dir3,1'b0,dir1,dir0 } : 120'b`muxval; |
dir3,1'b0,dir1,dir0 } : 120'bz; |
assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6], |
newPos3,newPos2,newPos1,newPos0, |
1'b1,val2,val1,val0, |
1'b0,dir2,dir1,dir0 } : 120'b`muxval; |
1'b0,dir2,dir1,dir0 } : 120'bz; |
// assign tagDataW=(insert_reg && !hit) ? 120'b0 : 120'bz; |
assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0, |
2'b11,2'b10,2'b01,2'b00, |
1'b0,1'b0,1'b0,1'b0, |
1'b0,1'b0,1'b0,1'b0} : 120'b`muxval; |
assign tagDataW=(!insert_reg && !readen_reg && !writeen_reg && !initEntry_reg) ? 120'b0 : 120'b`muxval; |
1'b0,1'b0,1'b0,1'b0} : 120'bz; |
assign tagDataW=(!insert_reg && !readen_reg && !writeen_reg && !initEntry_reg) ? 120'b0 : 120'bz; |
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assign dataA=(!insert_reg && hit0) ? {480'b0,dataA0} : 512'b`muxval; |
assign dataA=(!insert_reg && hit1) ? {480'b0,dataA1} : 512'b`muxval; |
assign dataA=(!insert_reg && hit2) ? {480'b0,dataA2} : 512'b`muxval; |
assign dataA=(!insert_reg && hit0) ? {480'b0,dataA0} : 512'bz; |
assign dataA=(!insert_reg && hit1) ? {480'b0,dataA1} : 512'bz; |
assign dataA=(!insert_reg && hit2) ? {480'b0,dataA2} : 512'bz; |
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assign dataA=(!insert_reg && hit3) ? {480'b0,dataA3} : 512'b`muxval; |
assign dataA=(!insert_reg && hit3) ? {480'b0,dataA3} : 512'bz; |
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assign dataA=(insert_reg && hit0) ? ramDataR0 : 512'b`muxval; |
assign dataA=(insert_reg && hit0) ? ramDataR0 : 512'bz; |
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assign dataA=(insert_reg && hit1) ? ramDataR1 : 512'b`muxval; |
assign dataA=(insert_reg && hit2) ? ramDataR2 : 512'b`muxval; |
assign dataA=(insert_reg && hit3) ? ramDataR3 : 512'b`muxval; |
assign dataA=(insert_reg && hit1) ? ramDataR1 : 512'bz; |
assign dataA=(insert_reg && hit2) ? ramDataR2 : 512'bz; |
assign dataA=(insert_reg && hit3) ? ramDataR3 : 512'bz; |
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assign dataA= hit ? 512'b`muxval : 512'b0; //change to accomodate non-read ops |
assign dataA= hit ? 512'bz : 512'b0; //change to accomodate non-read ops |
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assign ramDataW0=insert_reg ? cacheLine_reg : ramDataWA0; |
assign ramDataW1=insert_reg ? cacheLine_reg : ramDataWA1; |
191,11 → 206,11
assign ram2We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit2; |
assign ram3We=(insert_reg || (writeen_reg && !stall && !codemiss[4] && !stginhibit[4])) && hit3; |
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assign oldAddr=(insert_reg && hit0) ? pad0 : 32'b`muxval; |
assign oldAddr=(insert_reg && hit1) ? pad1 : 32'b`muxval; |
assign oldAddr=(insert_reg && hit2) ? pad2 : 32'b`muxval; |
assign oldAddr=(insert_reg && hit3) ? pad3 : 32'b`muxval; |
assign oldAddr=(!insert_reg) ? 32'b0 : 32'b`muxval; |
assign oldAddr=(insert_reg && hit0) ? pad0 : 32'bz; |
assign oldAddr=(insert_reg && hit1) ? pad1 : 32'bz; |
assign oldAddr=(insert_reg && hit2) ? pad2 : 32'bz; |
assign oldAddr=(insert_reg && hit3) ? pad3 : 32'bz; |
assign oldAddr=(!insert_reg) ? 32'b0 : 32'bz; |
|
assign ramAddrA={tagAddrA[31:6],6'b0}; |
assign ramAddrW={tagAddrA_reg[31:6],6'b0}; |
272,40 → 287,40
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module datacache_get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3, |
input hit0,input hit1,input hit2,input hit3, |
output `muxnet [1:0] newPos0,output `muxnet [1:0] newPos1,output `muxnet [1:0] newPos2,output `muxnet [1:0] newPos3); |
output wire [1:0] newPos0,output wire [1:0] newPos1,output wire [1:0] newPos2,output wire [1:0] newPos3); |
wire hit; |
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assign hit=hit0 || hit1 || hit2 || hit3; |
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assign newPos0=hit0 ? 0 : 2'b`muxval; |
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos0=hit0 ? 0 : 2'bz; |
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'bz; |
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'bz; |
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos1=hit1 ? 0 : 2'b`muxval; |
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos1=hit1 ? 0 : 2'bz; |
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'bz; |
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'bz; |
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos2=hit2 ? 0 : 2'b`muxval; |
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos2=hit2 ? 0 : 2'bz; |
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'bz; |
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'bz; |
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos3=hit3 ? 0 : 2'b`muxval; |
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos3=hit3 ? 0 : 2'bz; |
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'bz; |
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'bz; |
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'bz; |
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assign newPos0=hit ? 2'b`muxval : pos0; |
assign newPos1=hit ? 2'b`muxval : pos1; |
assign newPos2=hit ? 2'b`muxval : pos2; |
assign newPos3=hit ? 2'b`muxval : pos3; |
assign newPos0=hit ? 2'bz : pos0; |
assign newPos1=hit ? 2'bz : pos1; |
assign newPos2=hit ? 2'bz : pos2; |
assign newPos3=hit ? 2'bz : pos3; |
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endmodule |
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module datacache_data_sel(input [511:0] dataIn,input [5:0] sel, input [1:0] readsz, output `muxnet [31:0] dataOut); |
module datacache_data_sel(input [511:0] dataIn,input [5:0] sel, input [1:0] readsz, output wire [31:0] dataOut); |
wire [255:0] bit5Data; |
wire [127:0] bit4Data; |
wire [63:0] bit3Data; |
321,16 → 336,16
assign data16 =sel[1] ? data32[31:16] : data32[15:0]; |
assign data8 =sel[0] ? data16[15:8] : data16[7:0]; |
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assign dataOut=(readsz==0) ? {24'b0,data8} : 32'b`muxval; |
assign dataOut=(readsz==1) ? {16'b0,data16} : 32'b`muxval; |
assign dataOut=(readsz==2) ? data32 : 32'b`muxval; |
assign dataOut=(readsz==4) ? 32'b0 : 32'b`muxval; |
assign dataOut=(readsz==0) ? {24'b0,data8} : 32'bz; |
assign dataOut=(readsz==1) ? {16'b0,data16} : 32'bz; |
assign dataOut=(readsz==2) ? data32 : 32'bz; |
assign dataOut=(readsz==4) ? 32'b0 : 32'bz; |
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endmodule |
|
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module datacache_write_shift(input [31:0] dataIn,input [1:0] writesz,input [31:0] addr, output wire [511:0] dataOut, output wire [63:0] byteEnable); |
`muxnet [511:0] data6; |
wire [511:0] data6; |
wire [511:0] data5; |
wire [511:0] data4; |
wire [511:0] data3; |
338,7 → 353,7
wire [511:0] data1; |
wire [511:0] data0; |
|
`muxnet [63:0] byteEnable6; |
wire [63:0] byteEnable6; |
wire [63:0] byteEnable5; |
wire [63:0] byteEnable4; |
wire [63:0] byteEnable3; |
347,10 → 362,10
wire [63:0] byteEnable0; |
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// change data6 to explicit mux! |
assign data6=(writesz==0) ? {504'b0,dataIn[7:0]} : 512'b`muxval; |
assign data6=(writesz==1) ? {496'b0,dataIn[15:0]} : 512'b`muxval; |
assign data6=(writesz==2) ? {480'b0,dataIn} : 512'b`muxval; |
assign data6=(writesz==3) ? 512'b0 : 512'b`muxval; |
assign data6=(writesz==0) ? {504'b0,dataIn[7:0]} : 512'bz; |
assign data6=(writesz==1) ? {496'b0,dataIn[15:0]} : 512'bz; |
assign data6=(writesz==2) ? {480'b0,dataIn} : 512'bz; |
assign data6=(writesz==3) ? 512'b0 : 512'bz; |
|
assign data5=addr[5] ? { data6[255:0], 256'b0 }: data6; |
assign data4=addr[4] ? { data5[383:0], 128'b0 }: data5; |
361,10 → 376,10
|
assign dataOut=data0; |
//change byteEnable6 to explicit mux! |
assign byteEnable6=(writesz==0) ? 64'b0001 : 64'b`muxval; |
assign byteEnable6=(writesz==1) ? 64'b0011 : 64'b`muxval; |
assign byteEnable6=(writesz==2) ? 64'b1111 : 64'b`muxval; |
assign byteEnable6=(writesz==3) ? 64'b0000 : 64'b`muxval; |
assign byteEnable6=(writesz==0) ? 64'b0001 : 64'bz; |
assign byteEnable6=(writesz==1) ? 64'b0011 : 64'bz; |
assign byteEnable6=(writesz==2) ? 64'b1111 : 64'bz; |
assign byteEnable6=(writesz==3) ? 64'b0000 : 64'bz; |
|
assign byteEnable5=addr[5] ? { byteEnable6[31:0],32'b0 } : byteEnable6; |
assign byteEnable4=addr[4] ? { byteEnable5[47:0],16'b0 } : byteEnable5; |
/tlb/rtl/codecache.v
1,21 → 1,32
`include "config.v" |
|
module codecache(input clk,input [31:0] addrA,output `muxnet [31:0] dataA,input [511:0] cacheLine,output wire hit,input readen,input insert,input initEntry); |
module codecache( |
input clk, |
input [31:0] addrA, |
input [31:0] addrB, |
input tlbA; |
input tlbB; |
output [31:0] dataA, |
input [127:0] cacheLine, |
output hit, |
input readen, |
input insert, |
input initEntry); |
wire tagwe; |
wire [31:0] tagAddrA; |
wire [31:0] tagAddrW; |
wire [115:0] tagDataA; |
`muxnet [115:0] tagDataW; |
wire [123:0] tagDataA; |
wire [123:0] tagDataW; |
reg [31:0] tagAddrA_reg; |
|
wire ram0We,ram1We,ram2We,ram3We; |
wire [31:0] ramAddrW; |
wire [511:0] ramDataR0; |
wire [511:0] ramDataR1; |
wire [511:0] ramDataR2; |
wire [511:0] ramDataR3; |
wire [511:0] ramDataW; |
reg [511:0] cacheLine_reg; |
wire [127:0] ramDataR0; |
wire [127:0] ramDataR1; |
wire [127:0] ramDataR2; |
wire [127:0] ramDataR3; |
wire [127:0] ramDataW; |
reg [127:0] cacheLine_reg; |
|
wire [31:0] pad0; |
wire [31:0] pad1; |
36,13 → 47,18
wire [1:0] newPos3; |
|
|
`muxnet hit3,hit2,hit1,hit0; |
wire hit3,hit2,hit1,hit0; |
wire hit3A,hit2A,hit1A,hit0A; |
wire hit3B,hit2B,hit1B,hit0B; |
wire hitA,hitB; |
|
reg readen_reg=0; |
reg insert_reg=0; |
reg initEntry_reg=0; |
reg [31:0] addrA_reg; |
reg [115:0] tagDataA_fwd; |
wire [115:0] ramTagDataA; |
reg [31:0] addrB_reg; |
reg [123:0] tagDataA_fwd; |
wire [123:0] ramTagDataA; |
reg tag_fwd=0; |
|
wire [31:0] dataA0; |
49,18 → 65,20
wire [31:0] dataA1; |
wire [31:0] dataA2; |
wire [31:0] dataA3; |
|
codecacheramtag tag0(clk,tagwe,tagAddrA[11:4],tagAddrW[11:4],ramTagDataA,tagDataW); |
codecacheram ram0(clk,ram0We,tagAddrA[11:4],ramAddrW[11:4],ramDataR0,ramDataW); |
codecacheram ram1(clk,ram1We,tagAddrA[11:4],ramAddrW[11:4],ramDataR1,ramDataW); |
codecacheram ram2(clk,ram2We,tagAddrA[11:4],ramAddrW[11:4],ramDataR2,ramDataW); |
codecacheram ram3(clk,ram3We,tagAddrA[11:4],ramAddrW[11:4],ramDataR3,ramDataW); |
instr_sel instr_sel0(ramDataR0,tagAddrA_reg[3:2],dataA0); |
instr_sel instr_sel1(ramDataR1,tagAddrA_reg[3:2],dataA1); |
instr_sel instr_sel2(ramDataR2,tagAddrA_reg[3:2],dataA2); |
instr_sel instr_sel3(ramDataR3,tagAddrA_reg[3:2],dataA3); |
get_new_pos newpos0(pos0,pos1,pos2,pos3,hit0A&tlbA||hit0B&tlbB, |
hit1A&tlbA||hit1B&tlbB,hit2A&tlbA||hit2B&tlbB,hit3A&tlbA||hit3B&tlbB, |
newPos0,newPos1,newPos2,newPos3); |
|
codecacheramtag tag0(clk,tagwe,tagAddrA[11:6],tagAddrW[11:6],ramTagDataA,tagDataW); |
codecacheram ram0(clk,ram0We,tagAddrA[11:6],ramAddrW[11:6],ramDataR0,ramDataW); |
codecacheram ram1(clk,ram1We,tagAddrA[11:6],ramAddrW[11:6],ramDataR1,ramDataW); |
codecacheram ram2(clk,ram2We,tagAddrA[11:6],ramAddrW[11:6],ramDataR2,ramDataW); |
codecacheram ram3(clk,ram3We,tagAddrA[11:6],ramAddrW[11:6],ramDataR3,ramDataW); |
instr_sel instr_sel0(ramDataR0,tagAddrA_reg[5:2],dataA0); |
instr_sel instr_sel1(ramDataR1,tagAddrA_reg[5:2],dataA1); |
instr_sel instr_sel2(ramDataR2,tagAddrA_reg[5:2],dataA2); |
instr_sel instr_sel3(ramDataR3,tagAddrA_reg[5:2],dataA3); |
get_new_pos newpos0(pos0,pos1,pos2,pos3,hit0,hit1,hit2,hit3,newPos0,newPos1,newPos2,newPos3); |
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assign tagAddrA=addrA; |
assign tagwe=readen_reg || insert_reg || initEntry_reg; |
assign tagAddrW=tagAddrA_reg; |
67,37 → 85,39
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assign tagDataA=tag_fwd ? tagDataA_fwd : ramTagDataA; |
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assign { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],pos3,pos2,pos1,pos0,val3,val2,val1,val0 } = tagDataA; |
assign pad3[5:0]=6'b0; |
assign pad2[5:0]=6'b0; |
assign pad1[5:0]=6'b0; |
assign pad0[5:0]=6'b0; |
assign { pad3[31:4],pad2[31:4],pad1[31:4],pad0[31:4],pos3,pos2,pos1,pos0,val3,val2,val1,val0 } = tagDataA; |
assign pad3[3:0]=4'b0; |
assign pad2[3:0]=4'b0; |
assign pad1[3:0]=4'b0; |
assign pad0[3:0]=4'b0; |
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assign tagDataW=readen_reg ? { pad3[31:6],pad2[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,val0 } : 116'b`muxval; |
assign tagDataW=(insert_reg && hit0) ? { pad3[31:6],pad2[31:6],pad1[31:6],tagAddrA_reg[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,1'b1 } : 116'b`muxval; |
assign tagDataW=(insert_reg && hit1) ? { pad3[31:6],pad2[31:6],tagAddrA_reg[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,val2,1'b1,val0 } : 116'b`muxval; |
assign tagDataW=(insert_reg && hit2) ? { pad3[31:6],tagAddrA_reg[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,val3,1'b1,val1,val0 } : 116'b`muxval; |
assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:6],pad1[31:6],pad0[31:6],newPos3,newPos2,newPos1,newPos0,1'b1,val2,val1,val0 } : 116'b`muxval; |
assign tagDataW=readen_reg ? { pad3[31:4],pad2[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,val0 } : 124'bz; |
assign tagDataW=(insert_reg && hit0) ? { pad3[31:4],pad2[31:4],pad1[31:4],tagAddrA_reg[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,val1,1'b1 } : 124'bz; |
assign tagDataW=(insert_reg && hit1) ? { pad3[31:4],pad2[31:4],tagAddrA_reg[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,val2,1'b1,val0 } : 124'bz; |
assign tagDataW=(insert_reg && hit2) ? { pad3[31:4],tagAddrA_reg[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,val3,1'b1,val1,val0 } : 124'bz; |
assign tagDataW=(insert_reg && hit3) ? { tagAddrA_reg[31:6],pad2[31:4],pad1[31:4],pad0[31:4],newPos3,newPos2,newPos1,newPos0,1'b1,val2,val1,val0 } : 124'bz; |
// assign tagDataW=(insert_reg && !hit) ? 116'b0 : 116'bz; |
assign tagDataW=initEntry_reg ? { 26'b0,26'b0,26'b0,26'b0,2'b11,2'b10,2'b01,2'b00,1'b0,1'b0,1'b0,1'b0} : 116'b`muxval; |
assign tagDataW=(!insert_reg && !readen_reg && !initEntry_reg) ? 116'b0 : 116'b`muxval; |
assign tagDataW=initEntry_reg ? { 28'b0,28'b0,28'b0,28'b0,2'b11,2'b10,2'b01,2'b00,1'b0,1'b0,1'b0,1'b0} : 124'bz; |
assign tagDataW=(!insert_reg && !readen_reg && !initEntry_reg) ? 124'b0 : 124'bz; |
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assign hit3=readen_reg ? val3 && (pad3[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit2=readen_reg ? val2 && (pad2[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit1=readen_reg ? val1 && (pad1[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit0=readen_reg ? val0 && (pad0[31:6]==tagAddrA_reg[31:6]) : 1'b`muxval; |
assign hit3A=readen_reg & val3 && (pad3[31:4]==tagAddrA_reg[31:4]) : 1'bz; |
assign hit2A=readen_reg & val2 && (pad2[31:4]==tagAddrA_reg[31:4]) : 1'bz; |
assign hit1A=readen_reg & val1 && (pad1[31:4]==tagAddrA_reg[31:4]) : 1'bz; |
assign hit0A=readen_reg & val0 && (pad0[31:4]==tagAddrA_reg[31:4]) : 1'bz; |
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assign hit3=insert_reg ? (pos3==2'b11) : 1'b`muxval; |
assign hit2=insert_reg ? (pos2==2'b11) : 1'b`muxval; |
assign hit1=insert_reg ? (pos1==2'b11) : 1'b`muxval; |
assign hit0=insert_reg ? (pos0==2'b11) : 1'b`muxval; |
assign hit3B=readen_reg & val3 && (pad3[31:4]==tagAddrB_reg[31:4]) : 1'bz; |
assign hit2B=readen_reg & val2 && (pad2[31:4]==tagAddrB_reg[31:4]) : 1'bz; |
assign hit1B=readen_reg & val1 && (pad1[31:4]==tagAddrB_reg[31:4]) : 1'bz; |
assign hit0B=readen_reg & val0 && (pad0[31:4]==tagAddrB_reg[31:4]) : 1'bz; |
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assign hit3=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval; |
assign hit2=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval; |
assign hit1=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval; |
assign hit0=(!insert_reg && !readen_reg) ? 1'b0 : 1'b`muxval; |
assign hit3=insert_reg & (pos3==2'b11); |
assign hit2=insert_reg & (pos2==2'b11); |
assign hit1=insert_reg & (pos1==2'b11); |
assign hit0=insert_reg & (pos0==2'b11); |
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assign hit=hit3 || hit2 || hit1 || hit0; |
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assign hitA=hit3A || hit2A || hit1A || hit0A; |
assign hitB=hit3B || hit2B || hit1B || hit0B; |
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assign ram0We=insert_reg && hit0; |
assign ram1We=insert_reg && hit1; |
104,15 → 124,21
assign ram2We=insert_reg && hit2; |
assign ram3We=insert_reg && hit3; |
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assign dataA=hit0 ? dataA0 : 32'b`muxval; |
assign dataA=hit1 ? dataA1 : 32'b`muxval; |
assign dataA=hit2 ? dataA2 : 32'b`muxval; |
assign dataA=hit3 ? dataA3 : 32'b`muxval; |
assign dataA= hit ? 32'b`muxval : 32'b0; |
assign dataA=hit0A & tlbA ? dataA0 : 32'bz; |
assign dataA=hit1A & tlbA ? dataA1 : 32'bz; |
assign dataA=hit2A & tlbA ? dataA2 : 32'bz; |
assign dataA=hit3A & tlbA ? dataA3 : 32'bz; |
assign dataA=hit0B & tlbB ? dataA0 : 32'bz; |
assign dataA=hit1B & tlbB ? dataA1 : 32'bz; |
assign dataA=hit2B & tlbB ? dataA2 : 32'bz; |
assign dataA=hit3B & tlbB ? dataA3 : 32'bz; |
assign dataA= hitA & tlbA || hitB & tlbB ? 32'bz : 32'b0; |
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assign ramDataW=cacheLine_reg; |
assign ramAddrW=tagAddrA_reg; |
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assign hit=hitA & tlbA || hitB & tlbB; |
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always @(posedge clk) |
begin |
readen_reg<=readen; |
119,21 → 145,26
tagAddrA_reg<=tagAddrA; |
insert_reg<=insert; |
addrA_reg<=addrA; |
addrB_reg<=addrB; |
cacheLine_reg<=cacheLine; |
initEntry_reg<=initEntry; |
tagDataA_fwd<=ramTagDataA; |
tag_fwd<=(readen_reg || insert_reg || initEntry_reg) && (addrA[11:6]==addrA_reg[11:6]); |
tag_fwd<=(readen_reg || insert_reg || initEntry_reg) && (addrA[11:4]==addrA_reg[11:4]); |
end |
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endmodule |
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module codecacheram(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [511:0] dataA,input [511:0] dataW); |
reg [511:0] ram [63:0]; |
module codecacheram(input clk,input we,input [7:0] addrA,input [7:0] addrW,output [127:0] dataA,input [127:0] dataW); |
reg [127:0] ram [127:0]; |
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reg [7:0] addrA_reg; |
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assign dataA=ram[addrA_reg]; |
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always @(posedge clk) |
begin |
dataA<=ram[addrA]; |
if (we) ram[addrW]<=dataW; |
addrA_reg<=addrA; |
end |
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endmodule |
148,12 → 179,15
length =29*4=116 bit tag |
*/ |
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module codecacheramtag(input clk,input we,input [5:0] addrA,input [5:0] addrW,output reg [115:0] dataA,input [115:0] dataW); |
reg [115:0] ram [63:0]; |
module codecacheramtag(input clk,input we,input [7:0] addrA,input [7:0] addrW,output reg [123:0] dataA,input [123:0] dataW); |
reg [123:0] ram [63:0]; |
|
reg [7:0] addrA_reg; |
assign dataA=ram[addrA_reg]; |
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always @(posedge clk) |
begin |
dataA<=ram[addrA]; |
addrA_reg<=addrA; |
if (we) ram[addrW]<=dataW; |
end |
|
161,14 → 195,10
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|
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module instr_sel(input [511:0] dataIn,input [3:0] sel, output [31:0] instr); |
wire [255:0] bit3Data; |
wire [127:0] bit2Data; |
module instr_sel(input [127:0] dataIn,input [1:0] sel, output [31:0] instr); |
wire [63:0] bit1Data; |
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assign bit3Data=sel[3] ? dataIn[511:256] : dataIn[255:0]; |
assign bit2Data=sel[2] ? bit3Data[255:128] : bit3Data[127:0]; |
assign bit1Data=sel[1] ? bit2Data[127:64] : bit2Data[63:0]; |
assign bit1Data=sel[1] ? dataIn[127:64] : dataIn[63:0]; |
assign instr =sel[0] ? bit1Data[63:32] : bit1Data[31:0]; |
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endmodule |
176,34 → 206,34
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module get_new_pos(input [1:0] pos0,input [1:0] pos1,input [1:0] pos2,input [1:0] pos3, |
input hit0,input hit1,input hit2,input hit3, |
output `muxnet [1:0] newPos0,output `muxnet [1:0] newPos1,output `muxnet [1:0] newPos2,output `muxnet [1:0] newPos3); |
output wire [1:0] newPos0,output wire [1:0] newPos1,output wire [1:0] newPos2,output wire [1:0] newPos3); |
wire hit; |
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assign hit=hit0 || hit1 || hit2 || hit3; |
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assign newPos0=hit0 ? 0 : 2'b`muxval; |
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos0=hit0 ? 0 : 2'bz; |
assign newPos1=hit0 ? ((pos1<pos0) ? pos1+1:pos1 ) : 2'bz; |
assign newPos2=hit0 ? ((pos2<pos0) ? pos2+1:pos2 ) : 2'bz; |
assign newPos3=hit0 ? ((pos3<pos0) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos1=hit1 ? 0 : 2'b`muxval; |
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos1=hit1 ? 0 : 2'bz; |
assign newPos0=hit1 ? ((pos0<pos1) ? pos0+1:pos0 ) : 2'bz; |
assign newPos2=hit1 ? ((pos2<pos1) ? pos2+1:pos2 ) : 2'bz; |
assign newPos3=hit1 ? ((pos3<pos1) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos2=hit2 ? 0 : 2'b`muxval; |
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'b`muxval; |
assign newPos2=hit2 ? 0 : 2'bz; |
assign newPos1=hit2 ? ((pos1<pos2) ? pos1+1:pos1 ) : 2'bz; |
assign newPos0=hit2 ? ((pos0<pos2) ? pos0+1:pos0 ) : 2'bz; |
assign newPos3=hit2 ? ((pos3<pos2) ? pos3+1:pos3 ) : 2'bz; |
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assign newPos3=hit3 ? 0 : 2'b`muxval; |
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'b`muxval; |
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'b`muxval; |
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'b`muxval; |
assign newPos3=hit3 ? 0 : 2'bz; |
assign newPos1=hit3 ? ((pos1<pos3) ? pos1+1:pos1 ) : 2'bz; |
assign newPos2=hit3 ? ((pos2<pos3) ? pos2+1:pos2 ) : 2'bz; |
assign newPos0=hit3 ? ((pos0<pos3) ? pos0+1:pos0 ) : 2'bz; |
|
assign newPos0=hit ? 2'b`muxval : pos0; |
assign newPos1=hit ? 2'b`muxval : pos1; |
assign newPos2=hit ? 2'b`muxval : pos2; |
assign newPos3=hit ? 2'b`muxval : pos3; |
assign newPos0=hit ? 2'bz : pos0; |
assign newPos1=hit ? 2'bz : pos1; |
assign newPos2=hit ? 2'bz : pos2; |
assign newPos3=hit ? 2'bz : pos3; |
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endmodule |