URL
https://opencores.org/ocsvn/suslik/suslik/trunk
Subversion Repositories suslik
Compare Revisions
- This comparison shows the changes necessary to convert path
/suslik/trunk/rtl
- from Rev 8 to Rev 4
- ↔ Reverse comparison
Rev 8 → Rev 4
/cpu.v
1,5 → 1,5
|
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec); |
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr); |
|
input [31:0] instr, val1, val2; |
output [31:0] valres; |
7,12 → 7,10
output cjmp; |
input [31:0] const1; |
input [31:0] retaddr; |
output wrspec; |
|
wire [5:0] code; |
wire [31:0] valcmp; |
wire CF,NF,VF,ZF; |
|
|
/* |
wrtval=1 if valres needs to be stored in register. |
cjmpinstr=1 if compare and jump instruction |
34,7 → 32,7
assign valres=(code==9) ? val1 + const1 : 32'bz; |
assign valres=(code==10)? val1 - val2 : 32'bz; |
assign valres=(code==11)? val1 - const1 : 32'bz; |
assign valres=wrspec ? val1 : 32'bz; |
//12=no-op |
assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz; |
assign valres=(code==46) ? retaddr : 32'bz; |
assign valres=(code==14)? val1 << val2[5:0] : 32'bz; |
44,10 → 42,9
assign valres=(code==18)? {32{val1[31]},val1} >> val2[5:0] : 32'bz; |
assign valres=(code==19)? {32{val1[31]},val1} >> const1[5:0] : 32'bz; |
|
assign valres=wrtval | wrspec ? 32'bz : 32'b0; |
assign valres=wrtval ? 32'bz : 32'b0; |
|
assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46)); |
assign wrspec=(code==12) && (instr[15:6]=10'd1); |
|
//flags for compare &jump |
assign {CF,valcmp}=val1 - val2; |
288,7 → 285,7
module cpu(input clk,input busEnRead,input busEnWrite, input busDataReady, output wire busRead, output wire busWrite,output wire [31:0] busAddr, |
input [511:0] busInput,output wire [511:0] busOutput, |
output wire [31:0] ioBusAddr,output wire [1:0] ioBusSize, output wire [31:0] ioBusOut, input [31:0] ioBusIn, input ioBusRdy, |
output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy, input [15:0] irq); |
output wire ioBusWr,output wire ioBusRd,output wire [3:0] dummy); |
wire [31:0] fetchaddr,fetchdata,readaddr,readdata; |
reg [31:0] readaddr_reg; |
reg [4:0] stginhibit=5'b11110; |
381,16 → 378,12
wire ioInstrWrtVal; |
wire ioInstrDoStall; |
wire ioInstrKeepStalling; |
|
reg [15:0] irq_bits=16'b0; |
reg [31:0] irq_handler=32'hffff_fff0; |
|
wire wrspec; |
|
//dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB); |
datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr); |
regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF); |
aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec); |
aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr); |
ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling, |
ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd); |
subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits); |
539,19 → 532,12
//cycle 1 |
if (!stall) |
begin |
stginhibit[1]<=0; |
cycle1prev<=1; |
IP<=fetchaddr+4; |
IP2<=fetchaddr; |
multiCycleStall[1]<=multiCycleStall[0]; |
multiCycleStall[0]<=0; |
if (irq) |
begin |
stginhibit<=5'b11110; |
codeMiss<=0; |
IP<=irq_handler; |
irq_bits<=irq; |
end |
stginhibit[1]<=0; |
cycle1prev<=1; |
IP<=fetchaddr+4; |
IP2<=fetchaddr; |
multiCycleStall[1]<=multiCycleStall[0]; |
multiCycleStall[0]<=0; |
end |
else cycle1prev<=0; |
|
666,12 → 652,6
IP<=IP5; |
multiCycleStall[0]<=1; |
end |
else if (wrspec) |
begin |
case (instr4[31:16]) |
16'd0: irq_handler<=opF; |
endcase |
end |
end |
else |
begin |