URL
https://opencores.org/ocsvn/sv_dir_tb/sv_dir_tb/trunk
Subversion Repositories sv_dir_tb
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/trunk/doc/directedtbusers1.docx
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trunk/doc/directedtbusers1.docx
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Index: trunk/doc/Figures.pptx
===================================================================
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Index: trunk/doc/Figures.pptx
===================================================================
--- trunk/doc/Figures.pptx (nonexistent)
+++ trunk/doc/Figures.pptx (revision 2)
trunk/doc/Figures.pptx
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Index: trunk/sv/tb_cmd.sv
===================================================================
--- trunk/sv/tb_cmd.sv (nonexistent)
+++ trunk/sv/tb_cmd.sv (revision 2)
@@ -0,0 +1,218 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+/////////////////////////////////////
+
+ ////////////////////////////////////
+ // command class
+ typedef class tb_cmd;
+class tb_cmd;
+ integer idx; // the index in the list
+ integer valid_fld; // number of valid fields
+ string cmd; // instruction text
+ string var1; // variable field one
+ string var2;
+ string var3;
+ string var4;
+ string var5;
+ string var6;
+ string cmd_str; // any Dynamic text
+
+ integer line_num; // file line number
+ integer file_idx; // index of file name
+
+ tb_cmd next; // ref to next command
+ tb_cmd prev; // ref to prev command
+
+ // prototypes
+ // function to parse string into fields.
+ extern function tb_cmd parse_cmd(string str);
+ // function print this data.
+ extern function void print();
+ extern function new();
+
+endclass // tb_cmd
+
+/// tb_cmd methods
+ // new function init members.
+ function tb_cmd::new();
+ idx = 0;
+ valid_fld = 0;
+ cmd = "";
+ var1 = "";
+ var2 = "";
+ var3 = "";
+ var4 = "";
+ var5 = "";
+ var6 = "";
+ cmd_str = "";
+ line_num = 0;
+ file_idx = 0;
+ next = null;
+ prev = null;
+ endfunction
+
+ // print function intended for debug and developent.
+ function void tb_cmd::print();
+ $display("***************");
+ $display("idx is: %d", this.idx);
+ $display("valid_fld is: %d", this.valid_fld);
+ $display("cmd is: %s", this.cmd);
+ $display("var1 is: %s", this.var1);
+ $display("var2 is: %s", this.var2);
+ $display("var3 is: %s", this.var3);
+ $display("var4 is: %s", this.var4);
+ $display("var5 is: %s", this.var5);
+ $display("var6 is: %s", this.var6);
+ $display("cmd_str is: %s", this.cmd_str);
+ $display("line_num is: %d", this.line_num);
+ $display("file_idx is: %d", this.file_idx);
+ endfunction
+
+ ///////////
+ // function parse_cmd
+ function tb_cmd tb_cmd::parse_cmd(string str);
+ byte c = 0;
+ byte c1 = 0;
+ integer err = 0;
+ integer length;
+ integer len;
+ integer idx = 0;
+ integer i;
+ integer tidx;
+ integer nonw;
+ integer gotd;
+ string tmp_str;
+ string sub_str;
+ string com_chars;
+ string dummy;
+ integer done = 0;
+ integer ds_start = 1000;
+ integer cs_start = 0;
+ integer ds_found = 0;
+ integer cs_found = 0;
+
+ // get length of string could include new line
+ length = str.len();
+ tmp_str = str.substr(0,length-2);
+ // if there is a comment get the start location.
+ // then strip off the comment.
+ idx = 0;
+ while((tmp_str.substr(idx,idx+1) != "--") && (idx < length-1)) begin
+ idx++;
+ end
+ if(idx != length) begin
+ cs_start = idx;
+ cs_found = 1;
+ tmp_str = tmp_str.substr(0, cs_start-1);
+ length = tmp_str.len();
+ end
+ // Look for dynamic text.
+ // if there is a dynamic text string, locate its start
+ idx = 0;
+ while((tmp_str.getc(idx) != "\"") && (idx < length)) begin
+ idx++;
+ end
+ if(idx < length) begin
+ ds_start = idx+1;
+ ds_found = 1;
+ dummy = tmp_str.substr(ds_start, length-2);
+ end
+ this.valid_fld = 0;
+ // if this is a full line comment, zero valid fields
+ if(cs_start == 0 && cs_found) begin
+ this.valid_fld = 0;
+ end else begin
+ // if there was a dynamic string ...
+ if(ds_found) begin
+ sub_str = tmp_str.substr(0, ds_start-2);
+ this.cmd_str = tmp_str.substr(ds_start, length-1);
+ end else begin
+ sub_str = tmp_str;
+ this.cmd_str = "";
+ end
+ // now parse the string into fields.
+ // get the sub string length
+ len = sub_str.len();
+ dummy = "";
+ tidx = 0;
+ idx = 0;
+ nonw = 0;
+ gotd = 0;
+
+ // extract fields
+ for (i = 0; i <= len; i++) begin
+ if (is_ws(sub_str[i])) begin
+ if (nonw) begin
+ nonw = 0;
+ gotd = 1;
+ end else begin
+ continue;
+ end
+ end else begin
+ dummy = {dummy, sub_str[i]};
+ nonw = 1;
+ end
+ // if we transitioned to white from char
+ if (gotd == 1) begin
+ case(tidx)
+ 0: this.cmd = dummy;
+ 1: this.var1 = dummy;
+ 2: this.var2 = dummy;
+ 3: this.var3 = dummy;
+ 4: this.var4 = dummy;
+ 5: this.var5 = dummy;
+ 6: this.var6 = dummy;
+ default: err = 1;
+ endcase
+ if(err == 0) begin
+ tidx++;
+ this.valid_fld++;
+ gotd = 0;
+ dummy = "";
+ end else begin
+ if(this.line_num != 0) begin
+ $fatal(0,"ERROR: Found more than six parameters in line: %s\nAt line: %d", tmp_str, this.line_num);
+ end
+ end
+ end
+ end // end for
+ // get any left overs
+ if(dummy != "") begin
+ case(tidx)
+ 0: this.cmd = dummy;
+ 1: this.var1 = dummy;
+ 2: this.var2 = dummy;
+ 3: this.var3 = dummy;
+ 4: this.var4 = dummy;
+ 5: this.var5 = dummy;
+ 6: this.var6 = dummy;
+ default: err = 1;
+ endcase
+ if(err == 0) begin
+ this.valid_fld++;
+ end else begin
+ if(this.line_num != 0) begin
+ $fatal(0,"ERROR: Found more than six parameters on line: %s\nAt line: %d", tmp_str, this.line_num);
+ end
+ end
+ end
+ end
+
+ //this.print();
+ return this;
+ endfunction // parse_cmd
+
Index: trunk/sv/gfuncts.sv
===================================================================
--- trunk/sv/gfuncts.sv (nonexistent)
+++ trunk/sv/gfuncts.sv (revision 2)
@@ -0,0 +1,96 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//////////////////////////////////////////////////////////////////////////
+// general functions
+//
+// stm2_int: convert a simulus entry to integer.
+// is_var: check for and return varable type.
+// is_ws: check if character is white space.
+// is_digi: Check if is decimal character
+// is_alpha: Check if is alphabetic character, Limited.
+//
+/////////////////////////////////////////////////////////////////////////
+// stimulus value convert functions
+// to_int function to convert string to integer
+function integer stm2_int(string str);
+ integer t, i, len, rtn;
+ string tmp_str;
+
+ i = 0;
+ t = str.getc(i);
+ if ((t == "x") || (t == "h")) begin
+ tmp_str = str.substr(1, str.len()-1);
+ rtn = tmp_str.atohex();
+ end else if (t == "b") begin
+ tmp_str = str.substr(1, str.len()-1);
+ rtn = tmp_str.atobin();
+ end else begin
+ rtn = str.atoi();
+ end
+ return rtn;
+endfunction // stm2_int
+
+//////////////////////////////////////////////////////////////////////
+// is_var function
+// check if the string passed is a variable definition "syntax" wise
+// return 0 if not a variable def
+// return 1 if defined as value
+// return 2 if defined as index
+// retrun 3 if condition operator
+function int is_var(string v);
+ byte c;
+ c = v[0];
+ if(is_digi(c)) begin
+ return 0;
+ end else if(c == "$") begin
+ return 1;
+ end else if (c == "<" || c == ">" || c == "=" || c == "!") begin
+ return 3;
+ end else if (c != "x" && c != "h" && c != "b") begin
+ return 2;
+ end else
+ return 0;
+endfunction
+
+//////////////////////////////////////////////////////////////////////
+// string functions
+// check character for white space
+// return 1 if is white, 0 other wise.
+function int is_ws(byte c);
+ if (c == " " || c == "\t" || c == "\n")
+ return 1;
+ else
+ return 0;
+endfunction // is_ws
+//////////////////////////////////////////////////////////////////////
+// check for decimal digit return 1 if is, else 0
+function int is_digi(byte c);
+ if (c >= "0" && c <= "9")
+ return 1;
+ else
+ return 0;
+endfunction
+//////////////////////////////////////////////////////////////////////
+// check for alpha character.
+// includes [ \ ] ^ _ ` { \ } ~
+// return 1 if is, else 0
+function int is_alpha(byte c);
+ if(c >= "A" && c <= "~")
+ return 1;
+ else
+ return 0;
+endfunction
Index: trunk/sv/tb_types.sv
===================================================================
--- trunk/sv/tb_types.sv (nonexistent)
+++ trunk/sv/tb_types.sv (revision 2)
@@ -0,0 +1,71 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+/////////////////////////////////////
+
+//////////////////////////////////////////
+// type definitions for the sv tb_pkg
+/////////////////////////////////////////
+ typedef class lst_item;
+ typedef class cmd_lst;
+ typedef class tb_cmd;
+ typedef class tb_trans;
+
+ ////////////////////////////////////
+ typedef struct {
+ string cmd;
+ integer par1;
+ integer par2;
+ integer par3;
+ integer par4;
+ integer par5;
+ integer par6;
+ string dym_str;
+ integer valid;
+ } cmd_val_t;
+
+
+ typedef struct {
+ string txt;
+ integer val;
+ } lst_item_t;
+
+//////////////////////////////////////////////////////////////
+// this class is a container class that is used to
+// pass in information and get information from the
+// command list.
+class tb_trans;
+ cmd_lst cmd;
+ cmd_val_t rtn_val;
+ integer next;
+
+ extern function new();
+endclass // class tb_trans
+
+
+function tb_trans::new();
+ cmd = new();
+ rtn_val.cmd = "";
+ rtn_val.dym_str = "";
+ rtn_val.par1 = 0;
+ rtn_val.par2 = 0;
+ rtn_val.par3 = 0;
+ rtn_val.par4 = 0;
+ rtn_val.par5 = 0;
+ rtn_val.par6 = 0;
+ rtn_val.valid = 0;
+ next = 0;
+endfunction
Index: trunk/sv/lst_item.sv
===================================================================
--- trunk/sv/lst_item.sv (nonexistent)
+++ trunk/sv/lst_item.sv (revision 2)
@@ -0,0 +1,157 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+/////////////////////////////////////
+
+ ////////////////////////////////
+ // list class. enables a list of items to be
+ // created and accessed by an index or text.
+typedef class lst_item;
+class lst_item;
+ string name;
+ string txt;
+ integer val;
+ integer index;
+ lst_item next;
+ lst_item prev;
+
+ extern function new(string ID);
+ extern function void print();
+ extern function void add_itm(lst_item item);
+ extern function lst_item get(integer idx);
+ extern function lst_item find(string txt);
+ extern function void set(integer idx, integer val);
+
+endclass // lst_item
+
+ /////////////////////////////////////////////////
+ // lst_item methods
+ // function lst_item::new
+ function lst_item::new(string ID);
+ name = ID;
+ txt = "";
+ val = 0;
+ index = 0;
+ next = null;
+ prev = null;
+ endfunction // new
+
+//////////////////////////////////////////////////
+ // function lst_item::print
+ function void lst_item::print();
+ lst_item lst;
+ lst = this;
+ while(lst != null) begin
+ $display("%s %s %d %d", lst.name, lst.txt, lst.val, lst.index);
+ lst = lst.next;
+ end
+ //$display("%s %s %d %d", lst.name, lst.txt, lst.val, lst.index);
+ endfunction // print
+
+////////////////////////////////////////////////////////
+ // function lst_item::set
+ function void lst_item::set(integer idx, integer val);
+ lst_item tmp_itm;
+
+ tmp_itm = this;
+ while (tmp_itm != null) begin
+ if (tmp_itm.index == idx) begin
+ tmp_itm.val = val;
+ break;
+ end
+ tmp_itm = tmp_itm.next;
+ end
+
+ endfunction // lst_item::set
+
+/////////////////////////////////////////////////
+ // function lst_item::add_itm
+ function void lst_item::add_itm(lst_item item);
+ lst_item tmp_itm;
+ lst_item new_itm;
+ tmp_itm = this;
+ // first item
+ if((tmp_itm.next == null) && (tmp_itm.txt == ""))begin
+ tmp_itm.txt = item.txt;
+ tmp_itm.val = item.val;
+ tmp_itm.prev = null;
+ // second item
+ end else if((tmp_itm.next == null) && (tmp_itm.txt != ""))begin
+ new_itm = new("");
+ new_itm.index = tmp_itm.index + 1;
+ new_itm.txt = item.txt;
+ new_itm.val = item.val;
+ tmp_itm.next = new_itm;
+ new_itm.prev = tmp_itm;
+ // other items
+ end else begin
+ while (tmp_itm.next != null) begin
+ tmp_itm = tmp_itm.next;
+ end
+ new_itm = new("");
+ new_itm.index = tmp_itm.index + 1;
+ new_itm.txt = item.txt;
+ new_itm.val = item.val;
+ tmp_itm.next = new_itm;
+ new_itm.prev = tmp_itm;
+ end
+ //this = tmp_itm;
+ endfunction // lst_item::add_itm
+
+////////////////////////////////////////////////////////////
+ // function lst_item::get index
+ function lst_item lst_item::get(integer idx);
+ lst_item tmp_itm;
+ tmp_itm = new("");
+ tmp_itm = this;
+ while (tmp_itm != null) begin
+ if (tmp_itm.index == idx) begin
+ return tmp_itm;
+ end
+ tmp_itm = tmp_itm.next;
+ end
+
+ check_lst_item_get : assert (tmp_itm) else begin
+ $warning("Item index >>> %4d <<< was not found on the %s list.", idx, this.name);
+ end
+ //if (tmp_itm.index != idx) begin
+ // $display("ERROR: lst_item.get Index not found !! Returning NULL object");
+ // tmp_itm = new("");
+ // return tmp_itm;
+ //end
+
+ return tmp_itm;
+ endfunction // get
+
+///////////////////////////////////////////////////////////
+ // function lst_item::find txt
+ function lst_item lst_item::find(string txt);
+ lst_item tmp_itm;
+ tmp_itm = new("");
+ tmp_itm = this;
+ // go through the list
+ while (tmp_itm != null) begin
+ if (tmp_itm.txt == txt) begin
+ break;
+ end
+ tmp_itm = tmp_itm.next;
+ end
+ // check for found
+ check_lst_item_find : assert (tmp_itm) else begin
+ $warning("Item >>> %s <<< was not found on the %s list.", txt, this.name);
+ end
+ return tmp_itm;
+ endfunction // find
Index: trunk/sv/cmd_lst.sv
===================================================================
--- trunk/sv/cmd_lst.sv (nonexistent)
+++ trunk/sv/cmd_lst.sv (revision 2)
@@ -0,0 +1,804 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+/////////////////////////////////////
+// command list class
+class cmd_lst;
+ tb_cmd lst_cmds;
+ lst_item file_lst;
+ lst_item var_lst;
+ lst_item inst_lst;
+
+ integer lst_sz;
+ integer lst_idx;
+ integer last_idx;
+ integer curr_line_num;
+ string file_name;
+ string include_name;
+
+ integer call_stack [8:1];
+ integer call_index = 0;
+ integer loop_cnt [7:0];
+ integer loop_term [7:0];
+ integer loop_line [7:0];
+ integer loop_num = 0;
+ integer if_state = 0;
+ integer wh_state = 0;
+ integer wh_top = 0;
+
+ //prototypes
+ extern function void define_instruction(string inst_txt, int args);
+ extern function void define_defaults();
+ extern function void load_stm(string stm_file);
+ extern function void load_include();
+ extern function void add_cmd(tb_cmd cmd);
+ extern function void check_cmds();
+ extern function tb_trans get(tb_trans inst);
+ extern function integer exec_defaults(tb_trans r);
+ extern function new();
+ extern function void print_cmds();
+ extern function void print_str();
+ extern function void print_str_wvar();
+endclass // cmd_lst
+
+////////////////////////////////////////////////////////////////////////////////////////
+// method definitions.
+///////////////////////////////////////////////////////////
+// function cmd_lst::new
+function cmd_lst::new();
+ lst_cmds = new();
+ file_lst = new("Files");
+ var_lst = new("Variables");
+ inst_lst = new("Instructions");
+ lst_sz = 0;
+ lst_idx = 0;
+ last_idx = 0;
+ curr_line_num = 0;
+ file_name = "";
+ include_name = "";
+endfunction // new
+
+///////////////////////////////////////////////////////////
+// function cmd_lst::get
+function tb_trans cmd_lst::get(tb_trans inst);
+ tb_trans rtn;
+ cmd_lst tmp_cmd;
+ lst_item tmp_item;
+ integer int_val;
+ integer tmp_int;
+ integer len;
+ string tmp_str;
+
+ rtn = inst;
+ rtn.rtn_val.par1 = 0;
+ rtn.rtn_val.par2 = 0;
+ rtn.rtn_val.par3 = 0;
+ rtn.rtn_val.par4 = 0;
+ rtn.rtn_val.par5 = 0;
+ rtn.rtn_val.par6 = 0;
+
+ if(rtn.next > rtn.cmd.lst_cmds.idx) begin
+ while (rtn.next > rtn.cmd.lst_cmds.idx && rtn.cmd.lst_cmds != null) begin
+ rtn.cmd.lst_cmds = rtn.cmd.lst_cmds.next;
+ check_get_next : assert (rtn.cmd.lst_cmds != null) else begin
+ $fatal(0, "cmd_lst::get failed due to attemped access to commands behond the end of the script.");
+ end
+ end
+ end else if (rtn.next < rtn.cmd.lst_cmds.idx) begin
+ while (rtn.next < rtn.cmd.lst_cmds.idx && rtn.cmd.lst_cmds != null) begin
+ rtn.cmd.lst_cmds = rtn.cmd.lst_cmds.prev;
+ check_get_prev : assert (rtn.cmd.lst_cmds != null) else begin
+ $fatal(0, "cmd_lst::get failed due to attemped access to commands before the beginning of the script.");
+ end
+ end
+ end
+
+ rtn.rtn_val.cmd = rtn.cmd.lst_cmds.cmd;
+ for (int i = 1; i <= rtn.cmd.lst_cmds.valid_fld - 1; i++) begin
+ case (i)
+ 1: tmp_str = rtn.cmd.lst_cmds.var1;
+ 2: tmp_str = rtn.cmd.lst_cmds.var2;
+ 3: tmp_str = rtn.cmd.lst_cmds.var3;
+ 4: tmp_str = rtn.cmd.lst_cmds.var4;
+ 5: tmp_str = rtn.cmd.lst_cmds.var5;
+ 6: tmp_str = rtn.cmd.lst_cmds.var6;
+ default: $display("ERROR: more than six parameters ????");
+ endcase
+ tmp_int = is_var(tmp_str);
+ if (tmp_int == 0) begin
+ tmp_int = stm2_int(tmp_str);
+ end else if (tmp_int == 1) begin
+ len = tmp_str.len();
+ tmp_str = tmp_str.substr(1, len - 1);
+ tmp_item = rtn.cmd.var_lst.find(tmp_str);
+ tmp_int = tmp_item.val;
+ end else if (tmp_int == 2) begin
+ tmp_item = rtn.cmd.var_lst.find(tmp_str);
+ tmp_int = tmp_item.index;
+ end else if (tmp_int == 3) begin
+ case (tmp_str)
+ "==" : tmp_int = 0;
+ "!=" : tmp_int = 1;
+ ">" : tmp_int = 2;
+ "<" : tmp_int = 3;
+ ">=" : tmp_int = 4;
+ "<=" : tmp_int = 5;
+ default : $display("Condition text not found ???");
+ endcase
+ end else begin
+ $display("is_var() returned an unknown value???");
+ end
+
+ case (i)
+ 1: rtn.rtn_val.par1 = tmp_int;
+ 2: rtn.rtn_val.par2 = tmp_int;
+ 3: rtn.rtn_val.par3 = tmp_int;
+ 4: rtn.rtn_val.par4 = tmp_int;
+ 5: rtn.rtn_val.par5 = tmp_int;
+ 6: rtn.rtn_val.par6 = tmp_int;
+ default: $display("ERROR: more than six parameters ????");
+ endcase
+ end
+
+ return rtn;
+endfunction
+
+///////////////////////////////////////////////////////////
+// function cmd_lst::define_instruction
+function void cmd_lst::define_instruction(string inst_txt, int args);
+ lst_item tmp_lst;
+ lst_item new_itm;
+ integer stat = 0;
+ // search the list for this instruction
+ tmp_lst = new("");
+ tmp_lst = this.inst_lst;
+ while(tmp_lst != null) begin
+ if(tmp_lst.txt != inst_txt) begin
+ tmp_lst = tmp_lst.next;
+ end else begin
+ check_duplicate_inst : assert (0) else begin
+ $fatal(0, "Duplicate instruction definition attempted : %s", inst_txt);
+ end
+ //$display("ERROR: Duplicate instruction definition attempted : %s", inst_txt);
+ //stat = 1;
+ //return stat;
+ end
+ end
+ // all good lets add this instruction to the list
+ new_itm = new("");
+ new_itm.txt = inst_txt;
+ new_itm.val = args;
+ inst_lst.add_itm(new_itm);
+
+ //return stat;
+endfunction // define_instruction
+
+/////////////////////////////////////////////////////////
+// function cmd_lst::add_cmd
+// INPUT: tb_cmd cmd
+function void cmd_lst::add_cmd(tb_cmd cmd);
+ tb_cmd tmp_cmd;
+ tb_cmd new_cmd;
+ integer stat = 0;
+
+ tmp_cmd = new();
+ tmp_cmd = this.lst_cmds;
+
+ // first
+ if((this.lst_cmds.next == null) && (this.lst_cmds.cmd == "")) begin
+ new_cmd = new();
+ new_cmd = cmd;
+ new_cmd.idx = 0;
+ this.lst_cmds = new_cmd;
+ // second
+ end else if(this.lst_cmds.next == null) begin
+ new_cmd = new();
+ new_cmd = cmd;
+ new_cmd.idx = 1;
+ tmp_cmd.next = new_cmd;
+ new_cmd.prev = tmp_cmd;
+ // rest
+ end else begin
+ while (tmp_cmd.next != null) begin
+ tmp_cmd = tmp_cmd.next;
+ end
+ new_cmd = new();
+ new_cmd = cmd;
+ new_cmd.idx = tmp_cmd.idx + 1;
+ tmp_cmd.next = new_cmd;
+ new_cmd.prev = tmp_cmd;
+ end
+ this.lst_sz++;
+ this.last_idx = new_cmd.idx;
+endfunction
+
+/////////////////////////////////////////////////////////
+// function cmd_lst::load stimulus
+function void cmd_lst::load_stm(string stm_file);
+ tb_cmd new_cmd;
+ tb_cmd tst_cmd;
+ integer in_fh;
+ integer stat = 0;
+ integer fstat = 0;
+ integer idx = 0;
+ integer len;
+ integer i, ilen;
+ string input_str;
+ string tstr;
+ lst_item tmp_item;
+ // open the file passed and test for existance.
+ in_fh = $fopen(stm_file, "r");
+ check_file_open : assert (in_fh != 0) else begin
+ $fatal(0, "ERROR: File not found in cmd_lst::load_stm : %s", stm_file);
+ end
+
+ this.file_name = stm_file;
+ // this is the main file, add to file list.
+ tmp_item = new("");
+ tmp_item.txt = stm_file;
+ file_lst.add_itm(tmp_item);
+
+ this.curr_line_num = 0;
+ // new the test results storage ...
+ tmp_item = new("");
+
+ while (! $feof(in_fh)) begin
+ fstat = $fgets(input_str, in_fh);
+ // increment the line number
+ this.curr_line_num++;
+ tst_cmd = new();
+ if (input_str == "\n" || input_str == "")
+ continue;
+ // check for special commands DEFINE_VAR and INCLUDE
+ tst_cmd = tst_cmd.parse_cmd(input_str);
+ len = tst_cmd.cmd.len();
+ if (tst_cmd.cmd == "DEFINE_VAR") begin
+ tmp_item.txt = tst_cmd.var1;
+ tmp_item.val = stm2_int(tst_cmd.var2);
+ var_lst.add_itm(tmp_item);
+ // check for INCLUDE file def
+ end else if (tst_cmd.cmd == "INCLUDE") begin
+ if(tst_cmd.var1 != "") begin
+ this.include_name = tst_cmd.var1;
+ end else if (tst_cmd.cmd_str != "") begin
+ tstr = tst_cmd.cmd_str;
+ ilen = tstr.len();
+ i = ilen-1;
+ // strip any trailing spaces
+ while(tstr[i] == " ") begin
+ tstr = tstr.substr(0,i-1);
+ i--;
+ end
+ this.include_name = tstr;
+ end else begin
+ check_include : assert (0) else begin
+ $fatal(0, "No INCLUDE file found in command on\n line: %4d in file: %s", curr_line_num, stm_file);
+ end
+ end
+ this.load_include();
+ // check for inline variable.
+ end else if(tst_cmd.cmd[len-1] == ":") begin
+ tmp_item.txt = tst_cmd.cmd.substr(0, len-2);
+ tmp_item.val = this.last_idx + 1;
+ var_lst.add_itm(tmp_item);
+ // else is a standard command
+ end else begin
+ // parse out the command
+ new_cmd = new();
+ new_cmd = new_cmd.parse_cmd(input_str);
+ if (new_cmd.valid_fld > 0) begin
+ new_cmd.line_num = curr_line_num;
+ new_cmd.file_idx = 0;
+ this.add_cmd(new_cmd);
+ end
+ end
+ end // while (! $feof(in_fh))
+
+ check_cmds();
+endfunction // load_stm
+//////////////////////////////////////////////////////
+// function cmd_lst::load_include
+function void cmd_lst::load_include();
+ tb_cmd tmp_cmd;
+ tb_cmd new_cmd;
+ tb_cmd tst_cmd;
+ integer inc_fh;
+ integer stat = 0;
+ integer idx = 0;
+ string input_str;
+ lst_item tmp_item;
+ lst_item var_item;
+ integer file_idx;
+ integer len;
+ integer file_line = 0;
+
+ // open the file passed and test for existance.
+ inc_fh = $fopen(this.include_name, "r");
+ check_include_open : assert(inc_fh != 0) else begin
+ $fatal(0, "INCLUDE File not found: %s\nFound in file: %s\nOn line: %4d", this.include_name, this.file_name, this.curr_line_num);
+ end
+
+ // this is an include file, add to list.
+ tmp_item = new("");
+ tmp_item.txt = this.include_name;
+ file_lst.add_itm(tmp_item);
+ tmp_item = file_lst.find(this.include_name);
+ file_idx = tmp_item.index;
+
+ // new the test results storage ...
+ var_item = new("");
+
+ while (! $feof(inc_fh)) begin
+ file_line++;
+ stat = $fgets(input_str, inc_fh);
+ tst_cmd = new();
+ // skip blank lines
+ if (input_str == "\n" || input_str == "")
+ continue;
+ // check for special commands DEFINE_VAR, INCLUDE and inline variables
+ tst_cmd = tst_cmd.parse_cmd(input_str);
+ len = tst_cmd.cmd.len();
+ // DEFINE_VAR
+ if (tst_cmd.cmd == "DEFINE_VAR") begin
+ var_item.txt = tst_cmd.var1;
+ var_item.val = stm2_int(tst_cmd.var2);
+ var_lst.add_itm(var_item);
+ continue;
+ // INCLUDE Not nested.
+ end else if (tst_cmd.cmd == "INCLUDE") begin
+ check_nest_include : assert (0) else begin
+ $fatal(0, "INCLUDE can not be nested!!\nFound in file: %s\nOn line: %4d", this.include_name, file_line);
+ end
+ // In line VAR
+ end else if (tst_cmd.cmd[len - 1] == ":") begin
+ var_item.txt = tst_cmd.cmd.substr(0, len-2);
+ var_item.val = this.last_idx + 1;
+ var_lst.add_itm(var_item);
+ continue;
+ end
+ // parse out the command
+ new_cmd = new();
+ new_cmd = new_cmd.parse_cmd(input_str);
+ if (new_cmd.valid_fld > 0) begin
+ new_cmd.file_idx = file_idx;
+ new_cmd.line_num = file_line;
+ this.add_cmd(new_cmd);
+ end
+ end // while (! $feof(inc_fh))
+endfunction // load_include
+
+////////////////////////////////////////////////////////////
+// function check_cmds
+// checks that the commands loaded exist, have correct # params and
+// variable names exist
+function void cmd_lst::check_cmds();
+ tb_cmd tmp_cmd;
+ tb_cmd dum;
+ int found;
+ string cname;
+ string fname;
+ string t_var;
+ byte c;
+ int num_params;
+ lst_item tmp_lst;
+ lst_item flst;
+ lst_item tmp_item;
+ integer stat = 0;
+ integer file_idx;
+ integer len;
+ integer vtype;
+
+ tmp_cmd = this.lst_cmds;
+ // go through all the commands from the stimulus file.
+ while(tmp_cmd != null) begin
+ cname = tmp_cmd.cmd;
+ num_params = tmp_cmd.valid_fld;
+ tmp_lst = this.inst_lst;
+ found = 0;
+ // get the file name from this command
+ file_idx = tmp_cmd.file_idx;
+ flst = this.file_lst;
+ while (flst != null) begin
+ if(flst.index == file_idx) begin
+ fname = flst.txt;
+ end
+ flst = flst.next;
+ end
+ // go through the list of valid commands
+ while (tmp_lst != null && found == 0) begin
+ if (tmp_lst.txt == cname) begin
+ found = 1;
+ check_num_params : assert ((tmp_lst.val == num_params - 1) || (tmp_lst.val >= 7)) else begin
+ $fatal(0, "Incorrect number of parameters found in command on\n line: %4d in file: %s", tmp_cmd.line_num, fname);
+ end
+ end
+ tmp_lst = tmp_lst.next;
+ end
+ // if we did not find a command
+ check_valid_instruction : assert (found != 0) else begin
+ $fatal(0, "Command %s was not found in the list of valid commands on\n line: %4d in file: %s", cname, tmp_cmd.line_num, fname);
+ end
+
+ // Check the line for invalid variable names
+ if(num_params != 0) begin
+ tmp_lst = this.var_lst;
+ for (int i = 1; i <= num_params - 1; i++) begin
+ case (i)
+ 1: t_var = tmp_cmd.var1;
+ 2: t_var = tmp_cmd.var2;
+ 3: t_var = tmp_cmd.var3;
+ 4: t_var = tmp_cmd.var4;
+ 5: t_var = tmp_cmd.var5;
+ 6: t_var = tmp_cmd.var6;
+ default: $display("ERROR: num_params greater than six???");
+ endcase
+ c = t_var[0];
+ vtype = is_var(t_var);
+ if(vtype) begin
+ if(c == "$") begin
+ len = t_var.len();
+ t_var = t_var.substr(1, len - 1);
+ end
+ // if condition operator skip
+ if(vtype == 3) begin
+ continue;
+ end
+ end else begin
+ continue;
+ end
+ tmp_item = var_lst.find(t_var);
+ check_valid_variable : assert (tmp_item != null) else begin
+ $fatal(0, "Variable number: %2d >>> %s <<< on line %4d in file: %s Is NOT defined!!", i, t_var, tmp_cmd.line_num, fname);
+ end
+ end
+ end
+
+ tmp_cmd = tmp_cmd.next;
+ end
+endfunction // cmd_lst::check_cmds
+
+/////////////////////////////////////////////////////////////
+//
+ function void cmd_lst::define_defaults();
+ this.define_instruction("ABORT", 0);
+ this.define_instruction("FINISH", 0);
+ this.define_instruction("EQU_VAR", 2);
+ this.define_instruction("ADD_VAR", 2);
+ this.define_instruction("SUB_VAR", 2);
+ this.define_instruction("CALL", 1);
+ this.define_instruction("RETURN_CALL", 0);
+ this.define_instruction("JUMP", 1);
+ this.define_instruction("LOOP", 1);
+ this.define_instruction("END_LOOP", 0);
+ this.define_instruction("IF", 3);
+ this.define_instruction("ELSEIF", 3);
+ this.define_instruction("ELSE", 0);
+ this.define_instruction("END_IF", 0);
+ this.define_instruction("WHILE", 3);
+ this.define_instruction("END_WHILE", 0);
+endfunction // define_defaults
+
+///////////////////////////////////////////////////////////////////
+//
+function integer cmd_lst::exec_defaults(tb_trans r);
+ integer rtn = 0;
+ lst_item tmp_item;
+ integer idx = 0;
+ string cmd_string;
+
+ // get the command string
+ cmd_string = r.cmd.lst_cmds.cmd;
+ // output the dynamic text if there is some. (Note: before command runs.)
+ r.cmd.print_str_wvar();
+
+ /// The Main else if chain /////////////////////////////////////////////////
+ // ABORT
+ if(cmd_string == "ABORT") begin
+ $display("The test has aborted due to an error!!");
+ $finish(2);
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // FINISH
+ end else if (cmd_string == "FINISH") begin
+ $display("Test Finished with NO error!!");
+ $finish();
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // ADD_VAR
+ end else if (cmd_string == "ADD_VAR") begin
+ tmp_item = this.var_lst.get(r.rtn_val.par1);
+ idx = tmp_item.index;
+ tmp_item.val = tmp_item.val + r.rtn_val.par2;
+ r.cmd.var_lst.set(idx, tmp_item.val);
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // SUB_VAR
+ end else if (cmd_string == "SUB_VAR") begin
+ tmp_item = this.var_lst.get(r.rtn_val.par1);
+ idx = tmp_item.index;
+ tmp_item.val = tmp_item.val - r.rtn_val.par2;
+ r.cmd.var_lst.set(idx, tmp_item.val);
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // EQU_VAR
+ end else if (cmd_string == "EQU_VAR") begin
+ tmp_item = this.var_lst.get(r.rtn_val.par1);
+ idx = tmp_item.index;
+ tmp_item.val = r.rtn_val.par2;
+ r.cmd.var_lst.set(idx, tmp_item.val);
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // CALL
+ end else if (cmd_string == "CALL") begin
+ call_index++;
+ check_call_depth : assert(call_index <= 8) else begin
+ $fatal(0,"CALL nesting depth maximum is 7. On Line: %4d", r.cmd.lst_cmds.line_num);
+ end
+ call_stack[call_index] = r.cmd.lst_cmds.idx + 1;
+ r.next = r.rtn_val.par1;
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // RETURN_CALL
+ end else if (cmd_string == "RETURN_CALL") begin
+ check_call_under_run : assert(call_index > 0) else begin
+ $fatal(0,"RETURN_CALL causing nesting underflow?. On Line: %4d", r.cmd.lst_cmds.line_num);
+ end
+ r.next = call_stack[call_index];
+ call_index--;
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // JUMP
+ end else if (cmd_string == "JUMP") begin
+ r.next = r.rtn_val.par1;
+ call_index = 0;
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // LOOP
+ end else if (cmd_string == "LOOP") begin
+ loop_num++;
+ loop_line[loop_num] = r.cmd.lst_cmds.idx + 1;
+ loop_cnt[loop_num] = 0;
+ loop_term[loop_num] = r.rtn_val.par1;
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // END_LOOP
+ end else if (cmd_string == "END_LOOP") begin
+ loop_cnt[loop_num]++;
+ if(loop_cnt[loop_num] == loop_term[loop_num]) begin
+ loop_num--;
+ r.next = r.cmd.lst_cmds.idx + 1;
+ end else begin
+ r.next = loop_line[loop_num];
+ end
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // IF
+ end else if (cmd_string == "IF") begin
+ if_state = 0;
+ case (r.rtn_val.par2)
+ 0: if(r.rtn_val.par1 == r.rtn_val.par3) if_state = 1;
+ 1: if(r.rtn_val.par1 != r.rtn_val.par3) if_state = 1;
+ 2: if(r.rtn_val.par1 > r.rtn_val.par3) if_state = 1;
+ 3: if(r.rtn_val.par1 < r.rtn_val.par3) if_state = 1;
+ 4: if(r.rtn_val.par1 >= r.rtn_val.par3) if_state = 1;
+ 5: if(r.rtn_val.par1 <= r.rtn_val.par3) if_state = 1;
+ default: if_op_error : assert (0) else begin
+ $fatal(0, "IF statement had unknown operator in par2. On Line: %4d", r.cmd.lst_cmds.line_num);
+ end
+ endcase
+
+ if (!if_state) begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ while(cmd_string != "ELSE" && cmd_string != "ELSEIF" && cmd_string != "END_IF") begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ check_if_end : assert (r.cmd.lst_cmds.next != null) else begin
+ $fatal(0,"Unable to find terminating element for IF statement!!");
+ end
+ end
+ r.next--;
+ end
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // ELSEIF
+ end else if (cmd_string == "ELSEIF") begin
+ if(if_state) begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ while(cmd_string != "END_IF") begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ check_elseif_statement : assert (r.cmd.lst_cmds.next != null) else begin
+ $fatal(0,"Unable to find terminating element for ESLEIF statement!!");
+ end
+ end
+ r.next--;
+ end else begin
+ case (r.rtn_val.par2)
+ 0: if(r.rtn_val.par1 == r.rtn_val.par3) if_state = 1;
+ 1: if(r.rtn_val.par1 != r.rtn_val.par3) if_state = 1;
+ 2: if(r.rtn_val.par1 > r.rtn_val.par3) if_state = 1;
+ 3: if(r.rtn_val.par1 < r.rtn_val.par3) if_state = 1;
+ 4: if(r.rtn_val.par1 >= r.rtn_val.par3) if_state = 1;
+ 5: if(r.rtn_val.par1 <= r.rtn_val.par3) if_state = 1;
+ default: elseif_op_error : assert (0) else begin
+ $fatal(0, "ELSEIF statement had unknown operator in par2. On Line: %4d", r.cmd.lst_cmds.line_num);
+ end
+ endcase
+
+ if (!if_state) begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ while(cmd_string != "ELSE" && cmd_string != "ELSEIF" && cmd_string != "END_IF") begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ check_elseif_end : assert (r.cmd.lst_cmds.next != null) else begin
+ $fatal(0,"Unable to find terminating element for IF statement!!");
+ end
+ end
+ r.next--;
+ end
+ end
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // ELSEIF
+ end else if (cmd_string == "ELSE") begin
+ if(if_state) begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ while(cmd_string != "END_IF") begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ check_else_statement : assert (r.cmd.lst_cmds.next != null) else begin
+ $fatal(0,"Unable to find terminating element for ELSE statement!!");
+ end
+ end
+ r.next--;
+ end
+ rtn = 1;
+ ///////////////////////////////////////////////////////////////////////////
+ // END_IF
+ end else if (cmd_string == "END_IF") begin
+ rtn = 1;
+ // This command is just a place holder, skip to next instruction.
+
+ ///////////////////////////////////////////////////////////////////////////
+ // WHILE non-nested implementation
+ end else if (cmd_string == "WHILE") begin
+ wh_state = 0;
+ wh_top = r.cmd.lst_cmds.idx;
+ case (r.rtn_val.par2)
+ 0: if(r.rtn_val.par1 == r.rtn_val.par3) wh_state = 1;
+ 1: if(r.rtn_val.par1 != r.rtn_val.par3) wh_state = 1;
+ 2: if(r.rtn_val.par1 > r.rtn_val.par3) wh_state = 1;
+ 3: if(r.rtn_val.par1 < r.rtn_val.par3) wh_state = 1;
+ 4: if(r.rtn_val.par1 >= r.rtn_val.par3) wh_state = 1;
+ 5: if(r.rtn_val.par1 <= r.rtn_val.par3) wh_state = 1;
+ default: while_op_error : assert (0) else begin
+ $fatal(0, "WHILE statement had unknown operator in par2. On Line: %4d", r.cmd.lst_cmds.line_num);
+ end
+ endcase
+
+ if(!wh_state) begin
+ while(cmd_string != "END_WHILE") begin
+ r = r.cmd.get(r);
+ cmd_string = r.cmd.lst_cmds.cmd;
+ r.next++;
+ check_while_statement : assert (r.cmd.lst_cmds.next != null) else begin
+ $fatal(0,"Unable to find terminating element for WHILE statement!!");
+ end
+ end
+ end
+ rtn = 1;
+
+ ///////////////////////////////////////////////////////////////////////////
+ // END_WHILE
+ end else if (cmd_string == "END_WHILE") begin
+ r.next = wh_top;
+ rtn = 1;
+ end
+
+ return rtn;
+endfunction // exec_defaults
+
+// dynamic print function.
+function void cmd_lst::print_str();
+ if (this.lst_cmds.cmd_str != "") begin
+ $display("%s", this.lst_cmds.cmd_str);
+ end
+endfunction
+
+// dynamic print function with variable sub
+// output var in HEX.
+function void cmd_lst::print_str_wvar();
+
+ integer len;
+ integer vlen;
+ integer v;
+ integer i = 0;
+ integer j = 0;
+ integer val;
+ string sval;
+ string tmp;
+ string tmpv;
+ string vari;
+ string varv;
+ lst_item lvar;
+
+ if (this.lst_cmds.cmd_str == "") begin
+ return;
+ end
+
+ len = this.lst_cmds.cmd_str.len();
+ tmp = this.lst_cmds.cmd_str;
+
+ while (i < len) begin
+ if (tmp[i] == "$") begin
+ i++;
+ j = 0;
+ vari = "";
+ while (tmp[i] != " " && i < len) begin
+ vari = {vari,tmp[i]};
+ i++;
+ j++;
+ end
+ lvar = this.var_lst.find(vari);
+ val = lvar.val;
+ // convert var to str
+ $sformat(varv,"%x",val);
+ j = 0;
+ vlen = varv.len();
+ tmpv = varv;
+ // strip pre-padding
+ while(varv[j] == "0" && j < vlen) begin
+ j++;
+ v = tmpv.len();
+ tmpv = tmpv.substr(1, v-1);
+ end
+
+ sval = {sval, "0x", tmpv};
+ end else begin
+ sval = {sval,tmp[i]};
+ i++;
+ end
+ end
+ $display(sval);
+
+endfunction
+
+////////////////////////////////////////////////////////////
+// print commands function: intened for debug and dev
+function void cmd_lst::print_cmds();
+ tb_cmd tmp_cmd;
+ tmp_cmd = this.lst_cmds;
+ while(tmp_cmd != null) begin
+ tmp_cmd.print();
+ tmp_cmd = tmp_cmd.next;
+ end
+ //tmp_cmd.print();
+ $display("List Size: %s", this.lst_sz);
+ $display();
+ $display();
+endfunction // print_cmds
Index: trunk/sv/tb_pkg.sv
===================================================================
--- trunk/sv/tb_pkg.sv (nonexistent)
+++ trunk/sv/tb_pkg.sv (revision 2)
@@ -0,0 +1,31 @@
+////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+/////////////////////////////////////
+
+/////////////////////////////////////////////////////////
+// the test bench package.
+//
+package tb_pkg;
+
+ `include "tb_types.sv"
+ `include "gfuncts.sv"
+ `include "lst_item.sv"
+ `include "tb_cmd.sv"
+ `include "cmd_lst.sv"
+
+endpackage: tb_pkg // tb
+
Index: trunk/examples/standard/stm/test_include.stm
===================================================================
--- trunk/examples/standard/stm/test_include.stm (nonexistent)
+++ trunk/examples/standard/stm/test_include.stm (revision 2)
@@ -0,0 +1,95 @@
+DEFINE_VAR VAR1 0
+DEFINE_VAR VAR2 0
+DEFINE_VAR VAR3 0
+DEFINE_VAR VAR4 0
+DEFINE_VAR VAR5 0
+DEFINE_VAR VAR6 0
+DEFINE_VAR VAR7 0
+DEFINE_VAR VAR8 0
+DEFINE_VAR VAR9 0
+
+-- CALL depth testing
+TEST1_CALL:
+ ADD_VAR VAR1 2 "The Call TEST1_CALL ...
+ CALL $TEST2_CALL
+RETURN_CALL
+
+TEST2_CALL:
+ ADD_VAR VAR1 2 "The Call TEST2_CALL ...
+ CALL $TEST3_CALL
+RETURN_CALL
+
+TEST3_CALL:
+ ADD_VAR VAR1 2 "The Call TEST3_CALL ...
+ CALL $TEST4_CALL
+RETURN_CALL
+
+TEST4_CALL:
+ ADD_VAR VAR1 2 "The Call TEST4_CALL ...
+ CALL $TEST5_CALL
+RETURN_CALL
+
+TEST7_CALL:
+ ADD_VAR VAR1 2 "The Call TEST7_CALL ...
+RETURN_CALL
+
+TEST_CALL:
+ ADD_VAR VAR1 1 "The Call TEST_CALL ...
+ ADD_VAR VAR2 2
+ CALL $TEST1_CALL
+RETURN_CALL
+
+TEST5_CALL:
+ ADD_VAR VAR1 2 "The Call TEST5_CALL ...
+ CALL $TEST6_CALL
+RETURN_CALL
+
+TEST6_CALL:
+ ADD_VAR VAR1 2 "The Call TEST6_CALL ...
+ CALL $TEST7_CALL
+RETURN_CALL
+
+-- test JUMP location
+JUMP1_LOC:
+
+-- LOOP testing
+LOOP 10 "Loop top variable comment??
+ ADD_VAR VAR1 1 "Jump Loops ...
+ ADD_VAR VAR2 2
+ ADD_VAR VAR3 3
+ ADD_VAR VAR4 4
+ ADD_VAR VAR5 5
+ ADD_VAR VAR6 6
+ ADD_VAR VAR7 7
+ ADD_VAR VAR8 8
+ ADD_VAR VAR9 9
+END_LOOP
+
+LOOP 5
+ SUB_VAR VAR1 1
+ SUB_VAR VAR2 2
+ SUB_VAR VAR3 3
+ SUB_VAR VAR4 4
+ SUB_VAR VAR5 5
+ SUB_VAR VAR6 6
+ SUB_VAR VAR7 7
+ SUB_VAR VAR8 8
+ SUB_VAR VAR9 9
+END_LOOP
+
+-- Loops in Loops ....
+LOOP 2
+ LOOP 2
+ LOOP 2
+ LOOP 2
+ ADD_VAR VAR1 1 "Loop level 4
+ END_LOOP
+ ADD_VAR VAR1 1 "Loop level 3
+ END_LOOP
+ ADD_VAR VAR1 1 "Loop level 2
+ END_LOOP
+ ADD_VAR VAR1 1 "Loop level 1
+END_LOOP
+
+
+JUMP $TEST_END "Jumping to the end ...
Index: trunk/examples/standard/stm/stimulus_file.stm
===================================================================
--- trunk/examples/standard/stm/stimulus_file.stm (nonexistent)
+++ trunk/examples/standard/stm/stimulus_file.stm (revision 2)
@@ -0,0 +1,61 @@
+
+-- define variables use all notations.
+DEFINE_VAR TEMP_VAR1 xE
+DEFINE_VAR TEMP_VAR2 h10
+DEFINE_VAR TEMP_VAR3 b001110100
+DEFINE_VAR TEMP_VAR4 16
+DEFINE_VAR TEMP_VAR5 b100000
+DEFINE_VAR TEMP_VAR6 xff
+DEFINE_VAR TEMP_VAR7 4
+
+-- DUT access instructions
+RESET
+
+WRITE 0 x55555555
+WRITE 1 xaaaaaaaa
+
+READ 0
+VERIFY x55555555
+READ 1
+VERIFY xaaaaaaaa
+
+
+-- Rest of this test case demonstrates default instructions.
+IF $TEMP_VAR1 == 15
+ VERIFY xaaaaaaaa "Fell into the IF statement.
+ELSEIF $TEMP_VAR1 < 14
+ VERIFY xaaaaaaaa "Fell into the ELSEIF statement.
+ELSE
+ VERIFY xaaaaaaaa "Fell into the ELSE statement.
+END_IF
+
+WHILE $TEMP_VAR2 <= 20
+ ADD_VAR TEMP_VAR2 1 "$TEMP_VAR2
+END_WHILE
+
+ADD_VAR TEMP_VAR1 1 "Test $TEMP_VAR1 string 1
+ADD_VAR TEMP_VAR2 2 "Test $TEMP_VAR1 string $TEMP_VAR1 2
+ADD_VAR TEMP_VAR3 3 "Test string 3
+ADD_VAR TEMP_VAR4 4 "Test string 4
+ADD_VAR TEMP_VAR5 5 "Test string 5
+ADD_VAR TEMP_VAR6 6 "Test string 6
+ADD_VAR TEMP_VAR7 7 "Test string 7
+
+LOOP 10
+ ADD_VAR TEMP_VAR2 2
+ ADD_VAR TEMP_VAR3 2
+ ADD_VAR TEMP_VAR4 2
+ ADD_VAR TEMP_VAR5 2
+END_LOOP
+
+CALL $TEST_CALL
+
+JUMP $JUMP1_LOC
+
+
+TEST_END:
+FINISH
+
+-- more instructions in the include file.
+INCLUDE "../stm/test_include.stm
+
Index: trunk/examples/standard/sim/build
===================================================================
--- trunk/examples/standard/sim/build (nonexistent)
+++ trunk/examples/standard/sim/build (revision 2)
@@ -0,0 +1,4 @@
+vlib work
+vlog +acc +incdir+../../../sv/ ../sv/dut_if.sv
+vlog +acc +incdir+../../../sv/ ../sv/dut.sv
+vlog +acc +incdir+../../../sv/ ../sv/tb_top.sv
Index: trunk/examples/standard/sv/dut_if.sv
===================================================================
--- trunk/examples/standard/sv/dut_if.sv (nonexistent)
+++ trunk/examples/standard/sv/dut_if.sv (revision 2)
@@ -0,0 +1,34 @@
+interface dut_if();
+ logic rst_n;
+ logic clk;
+ logic [31:0] out1;
+ logic [31:0] out2;
+ logic [31:0] addr;
+ logic [31:0] data_in;
+ logic [31:0] data_out;
+ logic sel;
+ logic ack;
+
+ modport dut_conn(
+ input rst_n,
+ input clk,
+ output out1,
+ output out2,
+ input addr,
+ input data_in,
+ output data_out,
+ input sel,
+ output ack
+ );
+ modport tb_conn(
+ output rst_n,
+ output clk,
+ input out1,
+ input out2,
+ output addr,
+ output data_in,
+ input data_out,
+ output sel,
+ input ack
+ );
+endinterface
Index: trunk/examples/standard/sv/dut.sv
===================================================================
--- trunk/examples/standard/sv/dut.sv (nonexistent)
+++ trunk/examples/standard/sv/dut.sv (revision 2)
@@ -0,0 +1,65 @@
+
+module dut_module (
+ rst_n, // reset not
+ clk, // input clock
+ out1, // output buss one
+ out2, // output buss two
+ addr, // address
+ data_in, // write data
+ data_out, // read data
+ sel, // select
+ ack // acknowlage out.
+);
+
+
+input rst_n;
+input clk;
+output [31:0] out1;
+output [31:0] out2;
+input [31:0] addr;
+input [31:0] data_in;
+input sel;
+output [31:0] data_out;
+output ack;
+
+logic rst_n;
+logic clk;
+logic sel;
+logic ack;
+logic [31:0] out1;
+logic [31:0] out2;
+logic [31:0] addr;
+logic [31:0] data_in;
+logic [31:0] data_out;
+
+
+ initial begin
+ out1 = 32'h00000000;
+ out2 = 32'h00000000;
+ ack = 1'b0;
+ data_out = 32'hzzzzzzzz;
+ end
+
+
+ always @(posedge clk) begin
+ if(rst_n == 0) begin
+ out1 = 0;
+ out2 = 0;
+ data_out = 32'hzzzzzzzz;
+ ack = 0;
+ end else if (sel == 1) begin
+ if(addr == 0) begin
+ out1 = data_in;
+ end else begin
+ out2 = data_in;
+ end
+ #1;
+ ack = 1;
+ #1;
+ ack = 0;
+ end else begin
+ ack = 0;
+ end
+ end
+
+endmodule // dut_module
Index: trunk/examples/standard/sv/tb_mod.sv
===================================================================
--- trunk/examples/standard/sv/tb_mod.sv (nonexistent)
+++ trunk/examples/standard/sv/tb_mod.sv (revision 2)
@@ -0,0 +1,145 @@
+
+ `include "../sv/tb_pkg.sv"
+
+module tb_mod (dut_if.tb_conn tif);
+
+ import tb_pkg::*;
+
+ integer in_fh;
+ integer stat;
+ integer idx = 0;
+ logic clock;
+
+ //////////////////////////////////////////////
+ // DUT signals
+ logic rst_n;
+ logic clk;
+ logic sel;
+ logic ack;
+ logic [31:0] out1;
+ logic [31:0] out2;
+ logic [31:0] addr;
+ logic [31:0] data_in;
+ logic [31:0] data_out;
+
+ ////////////////////////////////////////////////////
+ // instruction variables
+ integer was_def = 0;
+ string cmd_string;
+ logic [31:0] tmp_vec;
+
+ // package and container
+ cmd_lst cmds;
+ tb_trans r;
+
+ ////////////////////////////////////////////////////////////////////
+ // clock driver
+ initial begin
+ while(1) begin
+ #10 clock = 0;
+ #10 clock = 1;
+ end
+ end
+
+ ////////////////////////////////////////////////////////
+ // drive DUT signals through interface
+ assign tif.clk = clock;
+ assign tif.sel = sel;
+ assign tif.rst_n = rst_n;
+ assign tif.addr = addr;
+ assign tif.data_in = data_in;
+ assign data_out = tif.data_out;
+ assign ack = tif.ack;
+ assign out1 = tif.out1;
+ assign out2 = tif.out2;
+
+ //////////////////////////////////////////////////////////
+ // stimulus_file processing
+ initial begin : Process_STM
+ cmds = new();
+ r = new();
+ // define the default instructions
+ cmds.define_defaults();
+ // User instructions
+ cmds.define_instruction("RESET", 0);
+ cmds.define_instruction("READ", 1);
+ cmds.define_instruction("WRITE", 2);
+ cmds.define_instruction("VERIFY", 1);
+ cmds.define_instruction("TEST_CMD", 7);
+
+ // load the stimulus file
+ cmds.load_stm(tb_top.stm_file);
+
+ r.cmd = cmds;
+ /////////////////////////////////////////////////////
+ // the main loop.
+ while (r.cmd != null) begin
+ r = r.cmd.get(r);
+ r.next++;
+
+ // process default instructions
+ was_def = r.cmd.exec_defaults(r);
+ if(was_def) begin
+ continue;
+ end
+
+ ///////////////////////////////////////////////////////
+ // Process User instructions.
+ // output any dynamic string
+ r.cmd.print_str_wvar();
+ // get the command string
+ cmd_string = r.cmd.lst_cmds.cmd;
+
+ ///////////////////////////////////////////////////////////////////////////
+ // RESET
+ if (cmd_string == "RESET") begin
+ @(posedge clock)
+ #1;
+ rst_n = 0;
+ sel = 0;
+ addr = 0;
+ data_in = 0;
+ @(posedge clock)
+ @(posedge clock)
+ rst_n = 1;
+ //@(posedge clock)
+ ///////////////////////////////////////////////////////////////////////////
+ // READ
+ end else if (cmd_string == "READ") begin
+ @(posedge clock)
+ #1;
+ if(r.rtn_val.par1 == 0) begin
+ tmp_vec = out1;
+ end else begin
+ tmp_vec = out2;
+ end
+ #1;
+ ///////////////////////////////////////////////////////////////////////////
+ // WRITE
+ end else if (cmd_string == "WRITE") begin
+ @(posedge clock)
+ addr = r.rtn_val.par1;
+ data_in = r.rtn_val.par2;
+ sel = 1;
+ @(posedge ack)
+ #1;
+ sel = 0;
+ //////////////////////////////////////////////////////////////////////////
+ // VERIFY
+ end else if (cmd_string == "VERIFY") begin
+ verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
+ $warning("VERIFY failed expected: %x Got: %x", r.rtn_val.par1, tmp_vec);
+ end
+ //////////////////////////////////////////////////////////////////////////
+ // TEST_CMD
+ end else if (cmd_string == "TEST_CMD") begin
+ //#1;
+ end else begin
+ $display("ERROR: Command %s not found in the else if chain. Is it spelled correctly in the else if?", cmd_string);
+ end // end of else if chain
+ end // end main while loop
+ // should never end up outside the while loop.
+ $display("ERROR: Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
+ end // end Process_STM
+
+endmodule // tb_mod
Index: trunk/examples/standard/sv/tb_top.sv
===================================================================
--- trunk/examples/standard/sv/tb_top.sv (nonexistent)
+++ trunk/examples/standard/sv/tb_top.sv (revision 2)
@@ -0,0 +1,33 @@
+
+`include "../sv/tb_mod.sv"
+
+module tb_top ();
+
+ // default stimulus file name
+ string stm_file = "../stm/stimulus_file.stm";
+ string tmp_fn;
+ // handle the plus args Change stimulus file name.
+ initial begin : file_select
+ if($value$plusargs("STM_FILE=%s", tmp_fn)) begin
+ stm_file = tmp_fn;
+ end
+ end
+
+ dut_if theif();
+
+ dut_module u1 (
+ .rst_n (theif.rst_n),
+ .clk (theif.clk),
+ .out1 (theif.out1),
+ .out2 (theif.out2),
+ .addr (theif.addr),
+ .data_in (theif.data_in),
+ .data_out (theif.data_out),
+ .sel (theif.sel),
+ .ack (theif.ack)
+ );
+
+
+ tb_mod tb_inst(theif);
+
+endmodule // tb_top
Index: trunk/examples/internal/stm/stimulus_file.stm
===================================================================
--- trunk/examples/internal/stm/stimulus_file.stm (nonexistent)
+++ trunk/examples/internal/stm/stimulus_file.stm (revision 2)
@@ -0,0 +1,64 @@
+
+DEFINE_VAR TEMP_VAR1 xE
+DEFINE_VAR TEMP_VAR2 h10
+DEFINE_VAR TEMP_VAR3 b001110100
+DEFINE_VAR TEMP_VAR4 16
+DEFINE_VAR TEMP_VAR5 b100000
+DEFINE_VAR TEMP_VAR6 xff
+DEFINE_VAR TEMP_VAR7 4
+
+DEFINE_VAR ADDR x10000000
+DEFINE_VAR EXPECT 0
+
+
+RESET
+
+READ 0
+READ x10000000
+WRITE 0 1
+-- fill with incrementing data
+EQU_VAR EXPECT $TEMP_VAR4
+LOOP 64
+ WRITE $ADDR $EXPECT
+ ADD_VAR ADDR 1
+ ADD_VAR EXPECT 2
+END_LOOP
+
+EQU_VAR ADDR x10000000
+EQU_VAR EXPECT $TEMP_VAR4
+
+-- test the data
+LOOP 64
+ READ $ADDR
+ VERIFY $EXPECT
+ ADD_VAR EXPECT 2
+ ADD_VAR ADDR 1
+END_LOOP
+
+
+EQU_VAR ADDR x20000000
+WRITE $ADDR x0ffff
+READ $ADDR
+VERIFY x0ffff
+
+WRITE x20000003 x55555555
+
+READ x20000001
+READ x20000001
+WRITE x20000001 xaaaaaaaa
+
+READ x20000001
+READ x20000001
+
+SET_I x12345678
+READ x20000001
+VERIFY x12340000
+
+SET_I x87654321
+READ x20000001
+VERIFY x87650000
+
+
+TEST_END:
+FINISH
+
Index: trunk/examples/internal/sim/build
===================================================================
--- trunk/examples/internal/sim/build (nonexistent)
+++ trunk/examples/internal/sim/build (revision 2)
@@ -0,0 +1,8 @@
+vlib work
+## package
+vlog +acc +incdir+../../../sv/ ../../../sv/tb_pkg.sv
+## DUT
+vlog +acc +incdir+../sv/ ../sv/dut_if.sv ../sv/mem_mod.v ../sv/gpio_mod.v ../sv/cpu_mod.v ../sv/arb.v
+vlog +acc +incdir+../sv/ ../sv/dut_top.v
+## test bench.
+vlog +acc +incdir+../../../sv/ ../sv/tb_top.sv
Index: trunk/examples/internal/sim/modelsim.ini
===================================================================
--- trunk/examples/internal/sim/modelsim.ini (nonexistent)
+++ trunk/examples/internal/sim/modelsim.ini (revision 2)
@@ -0,0 +1,1726 @@
+; Copyright 1991-2012 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+vital2000 = $MODEL_TECH/../vital2000
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+verilog = $MODEL_TECH/../verilog
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.2
+mtiUvm = $MODEL_TECH/../uvm-1.1b
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
+; a condition coverage or expression coverage expression, by changing FecEffort.
+; Higher FecEffort leads to a longer compile time, but more expressions covered.
+; This is a number from 1 to 3, with the following meanings (the default is 1):
+; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
+; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
+; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
+; FecEffort = 2
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
+; a condition coverage or expression coverage expression, by changing FecEffort.
+; Higher FecEffort leads to a longer compile time, but more expressions covered.
+; This is a number from 1 to 3, with the following meanings (the default is 1):
+; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
+; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
+; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
+; FecEffort = 2
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => _
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = [ ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt" and "spsl".
+; SVExtensions = uslt,spsl
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
+; a condition coverage or expression coverage expression, by changing FecEffort.
+; Higher FecEffort leads to a longer compile time, but more expressions covered.
+; This is a number from 1 to 3, with the following meanings (the default is 1):
+; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
+; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
+; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
+; FecEffort = 2
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt" and "spsl".
+; SVExtensions = uslt,spsl
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is 0 (disabled). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase
+DefaultRadix = hex
+;DefaultRadixFlags = showbase
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = /bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+; The default is UVMControl = struct
+
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file.
+; Value is the number of seconds between updated. After at least the
+; interval number of seconds, the wlf file is flushed, ensuring that the data
+; is correct when viewed from a separate live viewer. Setting to 0 means no
+; updating. Default is 10 seconds, which has a tiny performance impact
+; WLFUpdateInterval = 10
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
+; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Specify the relative size of logged objects that will trigger "large object"
+; messages at log/wave/list time. This size value is an approximation of
+; the number of bytes needed to store the value of the object before compression
+; and optimization.
+; The default LargeObjectSize size is 500k
+; LargeObjectSize = 500000
+
+; Specify whether to output "large object" warning messages.
+; The default is 0 which means the warning messages will come out.
+; LargeObjectSilent = 0
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 2000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 2000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveACTMaxOps = 10000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt" and "spsl".
+; SVExtensions = uslt,spsl
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: = [,...]
+; suppress can be used to achieve +nowarn
functionality
+; The format is: suppress = ,,[,,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
Index: trunk/examples/internal/sv/gpio_mod.v
===================================================================
--- trunk/examples/internal/sv/gpio_mod.v (nonexistent)
+++ trunk/examples/internal/sv/gpio_mod.v (revision 2)
@@ -0,0 +1,55 @@
+
+module gpio_mod (
+ clk, // input clock
+ rst_n,
+ addr, // address
+ datai, // data in
+ datao, // data out
+ w_n, // Write not
+ sel, // select input
+ io_o, // gpio out
+ io_i // gpio in
+);
+
+
+input rst_n;
+input clk;
+input sel;
+input [31:0] addr;
+input [31:0] datai;
+output [31:0] datao;
+input w_n;
+input [31:0] io_i;
+output [31:0] io_o;
+
+reg [31:0] io_mode; // 1 = output
+reg [31:0] tdatao;
+reg [31:0] tio_o;
+
+assign datao = tdatao;
+assign io_o = tio_o & io_mode;
+
+always @(posedge clk) begin
+ if(rst_n == 0) begin
+ tio_o <= 32'h00000000;
+ io_mode <= 32'h00000000;
+
+ end else if (w_n == 1 && sel == 1'b1) begin
+ if (addr[3:0] > 4'h0) begin
+ tdatao <= io_i & ~io_mode;
+ end else begin
+ tdatao <= io_mode;
+ end
+ end else if (w_n == 0 && sel == 1'b1) begin
+ if (addr[3:0] > 4'h0) begin
+ tio_o <= datai;
+ end else begin
+ io_mode <= datai;
+ end
+ end else if (sel == 1'b0) begin
+ tdatao <= 32'hzzzzzzzz;
+ end
+end
+
+
+endmodule
Index: trunk/examples/internal/sv/dut_if.sv
===================================================================
--- trunk/examples/internal/sv/dut_if.sv (nonexistent)
+++ trunk/examples/internal/sv/dut_if.sv (revision 2)
@@ -0,0 +1,47 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright ///////////////////////////////////
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+// $Author: $
+//
+//
+// Description :
+// This file was generated by SV TB Gen Beta 1.0
+// on 14 Jul 2014 10:38:58
+//////////////////////////////////////////////////////////////////////////////
+// This software contains concepts confidential to ////////////////
+// /////////. and is only made available within the terms of a written
+// agreement.
+///////////////////////////////////////////////////////////////////////////////
+
+interface dut_if();
+
+ logic rst_n;
+ logic clk;
+ logic w_n;
+ logic [31:0] addr;
+ logic [31:0] datao;
+ logic [31:0] datai;
+ logic ack;
+
+ modport dut_conn(
+ input rst_n,
+ input clk,
+ output w_n,
+ output addr,
+ output datao,
+ input datai,
+ input ack
+ );
+
+ modport tb_conn(
+ output rst_n,
+ output clk,
+ input w_n,
+ input addr,
+ input datao,
+ output datai,
+ output ack
+ );
+
+endinterface
Index: trunk/examples/internal/sv/mem_mod.v
===================================================================
--- trunk/examples/internal/sv/mem_mod.v (nonexistent)
+++ trunk/examples/internal/sv/mem_mod.v (revision 2)
@@ -0,0 +1,53 @@
+
+
+module mem_mod (
+ clk, // input clock
+ addr, // address
+ datai, // data in
+ datao, // data out
+ sel, // select
+ w_n // Write not
+);
+
+
+ //input rst_n;
+ input clk;
+ input [31:0] addr;
+ input [31:0] datai;
+ output [31:0] datao;
+ input w_n;
+ input sel;
+
+ reg [31:0] mem[0:64];
+ reg [31:0] dout;
+ reg [6:0] aidx;
+
+ assign datao = dout;
+
+ integer i;
+
+ initial begin
+ i = 0;
+ while (i < 64) begin
+ mem[i] = 0;
+ i = i + 1;
+ end
+ end
+
+
+ always @(posedge clk) begin
+ if (addr[15:0] < 16'h0040 && sel == 1'b1) begin
+ aidx = addr[6:0];
+ if (w_n == 1'b1) begin
+ dout <= mem[aidx];
+ end else if (w_n == 1'b0) begin
+ mem[aidx] <= datai;
+ end
+ end else if (sel == 1'b0) begin
+ dout <= 32'hzzzzzzzz;
+ end
+ end
+
+
+
+endmodule
Index: trunk/examples/internal/sv/dut_top.v
===================================================================
--- trunk/examples/internal/sv/dut_top.v (nonexistent)
+++ trunk/examples/internal/sv/dut_top.v (revision 2)
@@ -0,0 +1,69 @@
+
+module top (
+ rst_n, // reset not
+ clk, // input clock
+ out1, // output buss one
+ in1, // output buss two
+ state // acknowlage out.
+);
+
+input rst_n;
+input clk;
+output [31:0] out1;
+input [31:0] in1;
+output [7:0] state;
+
+
+wire rstw;
+wire clkw;
+wire [31:0] addrw;
+wire [15:0] selw;
+wire [31:0] dataow;
+wire [31:0] dataiw;
+wire w_nw;
+
+wire [31:0] tout1;
+
+assign out1 = tout1;
+assign clkw = clk;
+assign rstw = rst_n;
+
+bus_arb arb (
+ .rst_n (rstw),
+ .clk (clkw),
+ .addr (addrw[31:28]),
+ .sel (selw)
+);
+
+mem_mod mem (
+ .clk (clkw),
+ .addr (addrw),
+ .datai (dataow),
+ .datao (dataiw),
+ .sel (selw[1]),
+ .w_n (w_nw)
+);
+
+gpio_mod gpio (
+ .clk (clkw),
+ .rst_n (rstw),
+ .addr (addrw),
+ .datai (dataow),
+ .datao (dataiw),
+ .w_n (w_nw),
+ .sel (selw[2]),
+ .io_o (tout1),
+ .io_i (in1)
+);
+
+cpu_mod cpu (
+ .rst_n (rstw),
+ .clk (clkw),
+ .addr (addrw),
+ .datai (dataiw),
+ .datao (dataow),
+ .w_n (w_nw),
+ .ack ()
+);
+
+endmodule
Index: trunk/examples/internal/sv/arb.v
===================================================================
--- trunk/examples/internal/sv/arb.v (nonexistent)
+++ trunk/examples/internal/sv/arb.v (revision 2)
@@ -0,0 +1,40 @@
+
+module bus_arb (
+ rst_n, // reset not
+ clk, // input clock
+ addr, // address
+ sel // selects
+);
+
+
+input rst_n;
+input clk;
+input [3:0] addr;
+output [15:0] sel;
+
+reg [15:0] tsel;
+assign sel = tsel;
+
+ always @(addr) begin
+ case (addr)
+ 0: tsel = 16'h0001;
+ 1: tsel = 16'h0002;
+ 2: tsel = 16'h0004;
+ 3: tsel = 16'h0008;
+ 4: tsel = 16'h0010;
+ 5: tsel = 16'h0020;
+ 6: tsel = 16'h0040;
+ 7: tsel = 16'h0080;
+ 8: tsel = 16'h0100;
+ 9: tsel = 16'h0200;
+ 10: tsel = 16'h0400;
+ 11: tsel = 16'h0800;
+ 12: tsel = 16'h1000;
+ 13: tsel = 16'h2000;
+ 14: tsel = 16'h4000;
+ 15: tsel = 16'h8000;
+ endcase
+ end
+
+
+endmodule
Index: trunk/examples/internal/sv/cpu_mod.v
===================================================================
--- trunk/examples/internal/sv/cpu_mod.v (nonexistent)
+++ trunk/examples/internal/sv/cpu_mod.v (revision 2)
@@ -0,0 +1,25 @@
+
+module cpu_mod (
+ rst_n, // reset not
+ clk, // input clock
+ addr, // address
+ datai, // data in
+ datao, // data out
+ w_n, // Write not
+ ack // ack
+);
+
+input rst_n;
+input clk;
+output w_n;
+output [31:0] addr;
+output [31:0] datao;
+input [31:0] datai;
+input ack;
+
+
+wire tack;
+wire trst_n;
+
+
+endmodule
Index: trunk/examples/internal/sv/tb_mod.sv
===================================================================
--- trunk/examples/internal/sv/tb_mod.sv (nonexistent)
+++ trunk/examples/internal/sv/tb_mod.sv (revision 2)
@@ -0,0 +1,162 @@
+
+module tb_prg (dut_if.tb_conn tif);
+
+ import tb_pkg::*;
+
+ // package and container
+ cmd_lst cmds;
+ tb_trans r;
+
+ integer in_fh;
+ integer stat;
+ integer fi;
+ logic clock;
+ lst_item ti;
+
+ string STM_FILE = "../stm/stimulus_file.stm";
+ string tmp_fn;
+
+ // Handle plus args
+ initial begin : file_select
+ if($value$plusargs("STM_FILE=%s", tmp_fn)) begin
+ STM_FILE = tmp_fn;
+ end
+ end
+
+ //////////////////////////////////////////////
+ // DUT signals
+ logic ack;
+ logic [31:0] datai;
+ logic [31:0] datao;
+ logic [31:0] addr;
+ logic w_n = 1'b1;
+ logic clk;
+ logic rst_n;
+ logic [31:0] tdut_out;
+ logic [31:0] tdut_in = 0;
+
+ ////////////////////////////////////////////////////////
+ // drive / read DUT signals by hierarchy connection
+ assign tif.rst_n = rst_n;
+ assign tif.clk = clock;
+ assign tb_top.U1.cpu.w_n = w_n;
+ assign tb_top.U1.cpu.addr = addr;
+ assign tb_top.U1.cpu.datao = datao;
+ assign datai = tb_top.U1.cpu.datai;
+ assign tb_top.U1.in1 = tdut_in;
+ assign tdut_out = tb_top.U1.out1;
+ assign ack = tb_top.U1.cpu.ack;
+
+ ////////////////////////////////////////////////////
+ // instruction variables
+ integer was_def = 0;
+ string cmd_string;
+ logic [31:0] tmp_vec;
+
+ ////////////////////////////////////////////////////////////////////
+ // clock driver
+ initial begin
+ clock = 1;
+ while(1) begin
+ #10 clock = 0;
+ #10 clock = 1;
+ end
+ end
+
+ //////////////////////////////////////////////////////////
+ // stimulus_file processing
+ initial begin : Process_STM
+ cmds = new();
+ r = new();
+ // define the default instructions
+ cmds.define_defaults();
+ // User instructions
+ cmds.define_instruction("RESET", 0);
+ cmds.define_instruction("READ", 1);
+ cmds.define_instruction("WRITE", 2);
+ cmds.define_instruction("VERIFY", 1);
+ cmds.define_instruction("SET_I", 1);
+ cmds.define_instruction("READ_O", 1);
+
+ // load the stimulus file
+ cmds.load_stm(STM_FILE);
+
+ r.cmd = cmds;
+ /////////////////////////////////////////////////////
+ // the main loop.
+ while (r.cmd != null) begin
+ r = r.cmd.get(r);
+ r.next++;
+
+ // process default instructions
+ was_def = r.cmd.exec_defaults(r);
+ if(was_def) begin
+ continue;
+ end
+
+ ///////////////////////////////////////////////////////
+ // Process User instructions.
+ // get the command string
+ cmd_string = r.cmd.lst_cmds.cmd;
+ // output the dynamic text if there is some. (Note: before command runs.)
+ r.cmd.print_str_wvar();
+
+ ///////////////////////////////////////////////////////////////////////////
+ // RESET
+ if (cmd_string == "RESET") begin
+ rst_n = 1'b1;
+ @(posedge clock);
+ rst_n = 1'b0;
+ @(posedge clock);
+ @(posedge clock);
+ @(posedge clock);
+ rst_n = 1'b1;
+ @(posedge clock);
+ ///////////////////////////////////////////////////////////////////////////
+ // READ
+ end else if (cmd_string == "READ") begin
+ @(posedge clock);
+ addr = r.rtn_val.par1;
+ @(posedge clock);
+ @(posedge clock);
+ addr = 0;
+ tmp_vec = datai;
+ ///////////////////////////////////////////////////////////////////////////
+ // WRITE
+ end else if (cmd_string == "WRITE") begin
+ @(posedge clock);
+ addr = r.rtn_val.par1;
+ datao = r.rtn_val.par2;
+ @(posedge clock)
+ w_n = 1'b0;
+ @(posedge clock);
+ w_n = 1'b1;
+ addr = 0;
+ #1;
+ ///////////////////////////////////////////////////////////////////////////
+ // VERIFY
+ end else if (cmd_string == "VERIFY") begin
+ verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
+ fi = r.cmd.lst_cmds.file_idx;
+ ti = r.cmd.file_lst.get(fi);
+ $fatal(0,"VERIFY failed expected: %x Got: %x\nOn line number %3d of file %s",
+ r.rtn_val.par1, tmp_vec, r.cmd.lst_cmds.line_num, ti.txt);
+ end
+ ///////////////////////////////////////////////////////////////////////////
+ // SET_I
+ end else if (cmd_string == "SET_I") begin
+ tdut_in = r.rtn_val.par1;
+ #0;
+ end else if (cmd_string == "READ_O") begin
+ tmp_vec = tdut_out;
+ #0;
+ end else begin
+ $display("ERROR: Command not found in the else if chain. Is it spelled correctly in the else if?");
+ end // end of else if chain
+ end // end main while loop
+ // should never end up outside the while loop.
+ $display("ERROR: Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
+ end // end Process_STM
+
+endmodule // tb_prg
+
Index: trunk/examples/internal/sv/tb_top.sv
===================================================================
--- trunk/examples/internal/sv/tb_top.sv (nonexistent)
+++ trunk/examples/internal/sv/tb_top.sv (revision 2)
@@ -0,0 +1,18 @@
+
+`include "../sv/tb_mod.sv"
+
+module tb_top ();
+
+ top U1 (
+ .rst_n (theif.rst_n),
+ .clk (theif.clk),
+ .out1 (),
+ .in1 (),
+ .state ()
+ );
+
+ dut_if theif();
+
+ tb_prg prg_inst(theif);
+
+endmodule
Index: trunk/tb_gen/test_dut.v
===================================================================
--- trunk/tb_gen/test_dut.v (nonexistent)
+++ trunk/tb_gen/test_dut.v (revision 2)
@@ -0,0 +1,21 @@
+
+module test_mod (
+
+);
+// comment 1
+input rst_n, clk, sel, sig1, sig2,
+ sig3,sig4,sig5,
+ sig6, sig7, sig8;
+output o1, o2,o3,data_valid,o4, o5;
+// comment 2
+input [31:0] addr, dat_in, inv1,
+ test_bus, ctl_bus;
+input singlei;
+output singleo;
+output [31:0] response, dat_out,B1,B2,b3;
+
+input [8:0] singlei1;
+output [8:0] singleo1;
+inout io1,io2, io3, io4;
+
+endmodule
\ No newline at end of file
Index: trunk/tb_gen/tb_gen.tcl
===================================================================
--- trunk/tb_gen/tb_gen.tcl (nonexistent)
+++ trunk/tb_gen/tb_gen.tcl (revision 2)
@@ -0,0 +1,752 @@
+#! /usr/bin/env wish
+##-------------------------------------------------------------------------------
+## Copyright 2014 Ken Campbell
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+## http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##-------------------------------------------------------------------------------
+##-- $Author: $ Ken Campbell
+##--
+##-- $Date: $ June 26 2014
+##--
+##-- $Id: $
+##--
+##-- $Source: $
+##--
+##-- Description :
+##-- This application takes a text file containing the definition of a Verilog
+## module, produces a file set for the SV Directed Test Bench.
+##--
+##------------------------------------------------------------------------------
+
+## package requires
+package require Iwidgets 4.0
+
+## set the current version info
+set version "Beta 1.0"
+## put up a title on the main window boarder
+wm title . "SV TB Gen $version"
+
+## the location of the template by default
+set template "./tb_mod_template.sv"
+
+set use_list 0
+
+## Working Directory or vhdl directory
+set workd [frame .wdf]
+set ent_dir [iwidgets::entryfield $workd.cen1 -labeltext "Working Directory"]
+button $workd.br0 -text "Browse" -command {fill_list}
+pack $workd.br0 -side right
+pack $ent_dir -fill x
+pack $workd -fill x -pady 6
+
+## Output directory
+set tlist [frame .lstf]
+set odir [iwidgets::entryfield $tlist.ent1 -labeltext "Output Directory"]
+set lbut [button $tlist.br1 -text "Browse" -command {browsed_from_set $odir $odir}]
+pack $lbut -side right
+pack $odir -fill x
+pack $tlist -fill x
+
+## Template location
+set tdirf [frame .tmpf]
+set tdir [iwidgets::entryfield $tdirf.ent2 -width 60 -labeltext "Template Location"]
+set tbut [button $tdirf.br2 -text "Browse" -command {browse_set_entry $tdir}]
+pack $tbut -side right
+pack $tdir -fill x
+pack $tdirf -fill x -pady 6
+$tdir delete 0 end
+$tdir insert end $template
+$tdir configure -state readonly
+
+## type spec
+set tsf [frame .tsfr]
+set load_but [button $tsf.bt1 -text "Generate" -command ttb_gen]
+set mo_sel [iwidgets::optionmenu $tsf.mode -labeltext "Mode"]
+set gbatv 0
+#set gbat [checkbutton $tsf.chb1 -text "Gen Build Script" -variable gbatv]
+set cpakv 0
+#set cpak [checkbutton $tsf.chb2 -text "Copy Package" -variable cpakv]
+##$mo_sel insert end Work Recurse List
+$mo_sel insert end "No mod" "Gen mod"
+set p_view [iwidgets::feedback $tsf.fb1 -labeltext "Generation Status" -barheight 10]
+set statsVar ""
+##set stat_txt [label $tsf.lb1 -textvariable statsVar]
+set stat_txt [label .lb1 -textvariable statsVar]
+
+## about button
+button $tsf.bout1 -text "About" -command show_about
+
+#pack $cpak -side left
+#pack $gbat -side left
+pack $mo_sel -side left
+pack $load_but -side left -padx 20
+pack $p_view -side left
+pack $tsf.bout1 -side right
+pack $tsf -fill x
+pack $stat_txt -fill x
+
+## create paned window
+set win [iwidgets::panedwindow .pw -width 200 -height 300 ]
+$win add top -margin 4 -minimum 100
+$win add middle -margin 4 -minimum 100
+$win configure -orient vertical
+$win fraction 80 20
+$win paneconfigure 1 -minimum 60
+## create two locations for objects
+set wtop [$win childsite 0]
+set wbot [$win childsite 1]
+pack $win -fill both -expand yes
+## create two object boxes
+set list_win [iwidgets::selectionbox $wtop.sb -margin 2 -itemscommand load_ent_file \
+ -itemslabel "SV Files" -selectionlabel "Selected SV File"]
+set view_win [iwidgets::scrolledtext $wbot.rts -borderwidth 2 -wrap none]
+pack $list_win -fill both -expand yes
+pack $view_win -fill both -expand yes
+
+## some tags for the view window
+##$view_win tag configure highlite -background #a0b7ce
+$view_win tag configure highlite -background grey80
+
+###########################################################################
+## some debug and help procs
+## Message Error, terminate
+proc msg_error { msg } {
+ tk_messageBox -message $msg -type ok
+ exit
+}
+###########################################################################
+## Message, continue
+proc dbg_msg { msg } {
+ tk_messageBox -message $msg -type ok
+}
+#########################################################################
+## browse and get directory
+## Using extfileselectiondialog get a directory and update the
+## field passed to it
+proc browsed_from_set { src dest } {
+ set wdir [$src get]
+ if {$wdir == ""} {
+ iwidgets::extfileselectiondialog .dsb -modality application -fileson false
+ } else {
+ iwidgets::extfileselectiondialog .dsb -modality application -fileson false \
+ -directory $wdir
+ }
+
+ if {[.dsb activate]} {
+ set dchoice [.dsb get]
+ $dest configure -state normal
+ $dest delete 0 end
+ $dest insert 0 "$dchoice"
+ $dest configure -state readonly
+ }
+ destroy .dsb
+}
+#########################################################################
+## browse and get file name
+## Using extfileselectiondialog get a directory and update the
+## field passed to it
+proc browse_set_entry { dest } {
+iwidgets::extfileselectiondialog .dsb -modality application
+
+ if {[.dsb activate]} {
+ set dchoice [.dsb get]
+ $dest configure -state normal
+ $dest delete 0 end
+ $dest insert 0 "$dchoice"
+ $dest configure -state readonly
+ }
+ destroy .dsb
+}
+##########################################################################
+## proc pars_pindef
+proc pars_pindef { pins } {
+ set pdef {}
+ set def_lst {}
+ set lc 0
+
+ set logic_lst {}
+ set dut_modport {}
+ set names_lst {}
+
+ foreach l $pins {
+ set is_mult [string first "," $l]
+ set is_bv [string first "\[" $l]
+ set l [string trim $l "\;"]
+ ## if is a vector def
+ #puts $l
+ #puts "is_bv: $is_bv"
+ if {$is_bv > 0} {
+ set is_cbv [string first "\]" $l]
+ set bv_spec [string range $l $is_bv $is_cbv]
+ set type [string range $l 0 $is_bv-1]
+ set names [string range $l $is_cbv+1 end]
+ set snames [split $names ","]
+ foreach n $snames {
+ ##set n [string trim $n "\;"]
+ lappend names_lst [string trim $n]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ append tmp $bv_spec " [string trim $n]\;"
+ lappend logic_lst $tmp
+ set tmp [string trim $type]
+ append tmp " [string trim $n],"
+ lappend dut_modport $tmp
+ #puts "$type $bv_spec [string trim $n]\;"
+ }
+ } else {
+ set sl [split $l ","]
+ set frst [split [lindex $sl 0]]
+ set type [string trim [lindex $frst 0]]
+ set fname [string trim [lindex $frst end]]
+ set sl [lrange $sl 1 end]
+ lappend names_lst [string trim $fname]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ #set tmp "logic "
+ append tmp "$fname\;"
+ lappend logic_lst $tmp
+ set tmp $type
+ append tmp " $fname,"
+ lappend dut_modport $tmp
+ foreach n $sl {
+ lappend names_lst [string trim $n]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ append tmp "[string trim $n]\;"
+ lappend logic_lst $tmp
+ set tmp $type
+ append tmp " [string trim $n],"
+ lappend dut_modport $tmp
+ }
+ }
+ }
+
+ lappend def_lst $logic_lst
+ lappend def_lst $dut_modport
+ lappend def_lst $names_lst
+
+ return $def_lst
+}
+## end pars_pindef
+
+##--------------------------------------------------------------------------------
+## Write header to file passed
+proc write_header { handle } {
+ global version
+ ##global scan_date
+ set raw_date [clock scan now]
+ set scan_date [clock format $raw_date -format "%d %b %Y %T"]
+
+ ## so CVS will not modify selections, they have to be chopped up
+ set auth "// \$Auth"
+ append auth "or: \$"
+
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle "// Copyright ///////////////////////////////////"
+ puts $handle "// All Rights Reserved"
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle "$auth"
+ puts $handle "//"
+ puts $handle "//"
+ puts $handle "// Description :"
+ puts $handle "// This file was generated by SV TB Gen $version"
+ puts $handle "// on $scan_date"
+ puts $handle "//////////////////////////////////////////////////////////////////////////////"
+ puts $handle "// This software contains concepts confidential to ////////////////"
+ puts $handle "// /////////. and is only made available within the terms of a written"
+ puts $handle "// agreement."
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle ""
+ }
+
+#####################################################################
+## A directory has been selected now fill the list win with *V files
+proc fill_list {} {
+ global ent_dir odir
+ global tlist_ent use_list list_win ts_ent statsVar
+ global view_win mo_sel
+
+ ## get the user selection
+ browsed_from_set $ent_dir $ent_dir
+ ## as a default make output dir = input dir
+ set tmp_dir [$ent_dir get]
+ $odir delete 0 end
+ $odir insert end $tmp_dir
+ $odir configure -state readonly
+
+ ## clear the list window and selection
+ $list_win clear items
+ $list_win clear selection
+ $view_win clear
+ ## get the working directory
+ set dir [$ent_dir get]
+ ## get the list of VHDL files in working directory
+ set ftype ".*v"
+ set file_lst ""
+ set file_lst [glob -directory $dir *$ftype]
+
+ ## for each of the files in the file_lst
+ foreach l $file_lst {
+ ## creat string that is just the file name: no path
+ set testt $l
+ set nstart [string last "/" $l]
+ incr nstart
+ set name_str [string range $l $nstart end]
+ ## insert item on list
+ $list_win insert items 1 $name_str
+ }
+}
+
+######################################################################
+## load the vhdl file that has just been selected from list_win
+proc load_ent_file {} {
+ global ent_dir list_win view_win statsVar
+
+ ## update selection with selected item
+ $list_win selectitem
+ set sel_dx [$list_win curselection]
+ if {$sel_dx == ""} {
+ return
+ }
+ ## recover the selected item
+ set ln [$list_win get]
+ ## Get the working directory
+ #puts $ln
+ set lp [$ent_dir get]
+ ## append the file name
+ append lp "/" $ln
+ ## if the file does not exist return
+ set fexist [file exist $lp]
+ if {$fexist == 0} {
+ return
+ }
+ set ent_file [open $lp r]
+ ## clear the view_win
+ $view_win clear
+ set file_list {}
+ ## load file to memory
+ while {![eof $ent_file]} {
+ ## Get a line
+ set rline [gets $ent_file]
+ lappend file_list $rline
+ }
+ close $ent_file
+ ## put file in text window and highlite the entity part
+ set ent_found 0
+ set in_ent 0
+ set statsVar ""
+ foreach l $file_list {
+ if {$in_ent == 0} {
+ set ent_def [string first module $l]
+ if {$ent_def >= 0} {
+ set ent_name [lindex $l 1]
+ set statsVar "Module: $ent_name found"
+ set ent_found 1
+ set in_ent 1
+ $view_win insert end "$l\n" highlite
+ } else {
+ $view_win insert end "$l\n"
+ }
+ } else {
+ set ent_def [string first "endmodule" $l]
+ if {$ent_def >= 0} {
+ set end_name [lindex $l 1]
+ set end_found 1
+ set in_ent 0
+ $view_win insert end "$l\n" highlite
+ } else {
+ $view_win insert end "$l\n" highlite
+ }
+ }
+ }
+ if {$ent_found == 0} {
+ set statsVar "No Module found!!"
+ }
+ ##$view_win import $lp
+ ##$view_win yview moveto 1
+ ##puts $lp
+}
+
+#########################################################################
+proc ttb_gen {} {
+ global mo_sel template ent_dir list_win odir p_view tdir
+ global cpakv gbatv
+
+ set template [$tdir get]
+
+ $p_view configure -steps 7
+ $p_view reset
+ ## recover the selected item
+ set ln [$list_win get]
+ ## Get the working directory
+ #puts $ln
+ set lp [$ent_dir get]
+ ## append the file name
+ append lp "/" $ln
+
+ set path_text $lp
+ set destin_text [$odir get]
+ set infile [open $path_text r]
+ set file_list {}
+
+
+##################################################################
+## Read in the file and strip comments as we do
+ while {![eof $infile]} {
+ ## Get a line
+ set rline [gets $infile]
+ #puts $rline
+ ## get rid of white space
+ set rline [string trim $rline]
+ ## Find comment if there
+ set cindex [string first "//" $rline]
+ ## if a comment was found at the start of the line
+ if {$cindex == 0 || $rline == ""} {
+ continue
+ ## else was not found so put line in list
+ } elseif {$cindex > 0} {
+ # get rid of trailing comments and trim off spaces
+ set rline [string trim [string range $rline 0 $cindex-1]]
+ lappend file_list $rline
+ } else {
+ lappend file_list $rline
+ }
+ }
+ close $infile
+
+ $p_view step
+ ## check for the module def
+ set mod_name ""
+ foreach l $file_list {
+ set mod_def [string first module $l]
+ if {$mod_def >= 0} {
+ set ml [split $l]
+ set mod_name [lindex $l 1]
+ break
+ }
+ }
+
+ #puts "Module name is: $mod_name"
+ ## if no ent die
+ if {$mod_def < 0} {
+ dbg_msg "A module definition was not found in the file provided."
+ return
+ ## exit
+ }
+ $p_view step
+ set mod_list {}
+ ## check for end module
+ foreach l $file_list {
+ lappend mod_list $l
+ set end_def [string first endmodule $l]
+ if {$end_def >= 0} {
+ break
+ }
+ }
+ ## if no end die
+ if {$end_def < 0} {
+ dbg_msg "no endmodule statement found for this module"
+ return
+ ## exit
+ }
+ ####
+ ## collect the parameters if there are.
+ set parameter_list {}
+ set p_found 0
+ foreach l $mod_list {
+ set p_found [string first "parameter" $l]
+ if {$p_found >= 0} {
+ lappend $parameter_list $l
+ }
+ }
+
+ #foreach l $mod_list {
+ # puts $l
+ #}
+ ####################################################################
+ ## a few checks have been done, and non-relevant stuff stripped off.
+ ## now create an arrry of just the pin names and related info
+ set port_lst {}
+ set lc 0
+ foreach l $mod_list {
+ ## make lines that are continued, one line.
+ set cont [string first "\;" $l]
+ if {$cont < 0 && $lc == 0} {
+ set tmp $l
+ set lc 1
+ continue
+ } elseif {$cont < 0 && $lc == 1} {
+ append tmp $l
+ continue
+ } elseif {$lc == 1} {
+ append tmp $l
+ set lc 0
+ set l $tmp
+ }
+
+ ## look for the port statements
+ set inp [string first "input" $l]
+ if {$inp >= 0} {
+ lappend port_lst $l
+ }
+ set onp [string first "output" $l]
+ if {$onp >= 0} {
+ lappend port_lst $l
+ }
+ set ionp [string first "inout" $l]
+ if {$ionp >= 0} {
+ lappend port_lst $l
+ }
+ }
+
+ #foreach p $port_lst {
+ # puts $p
+ #}
+ ## Change the port list into a pin info list
+ set io_pins [pars_pindef $port_lst]
+
+ set log_lst [lindex $io_pins 0]
+ set mod_lst [lindex $io_pins 1]
+ set name_lst [lindex $io_pins 2]
+
+ #foreach r $log_lst {
+ # puts $r
+ #}
+ #foreach r $mod_lst {
+ # puts $r
+ #}
+ #foreach r $name_lst {
+ # puts $r
+ #}
+
+
+ # dbg_msg $split_pin
+ ## calculate the longest pin name in characters
+ set name_length 0
+ foreach l $name_lst {
+ set temp_length [string length $l]
+ if {$temp_length > $name_length} {
+ set name_length $temp_length
+ }
+ }
+ #dbg_msg $name_length
+ ## Make the name length one bigger
+ incr name_length
+
+ $p_view step
+#########################################################################
+## Generate the tb top.
+ set tfn $destin_text
+ append tfn "/tb_top.sv"
+ set tfh [open $tfn w]
+
+ write_header $tfh
+ puts $tfh "`include \"../sv/tb_prg.sv\""
+ puts $tfh ""
+ puts $tfh "module tb_top \(\)\;"
+ puts $tfh ""
+ puts $tfh " string STM_FILE = \"../stm/stimulus_file.stm\"\;"
+ puts $tfh " string tmp_fn"
+ puts $tfh ""
+ puts $tfh " // Handle plus args"
+ puts $tfh " initial begin : file_select"
+ puts $tfh " if\(\$value\$plusargs\(\"STM_FILE=%s\", tmp_fn\)\) begin"
+ puts $tfh " stm_file = tmp_fn\;"
+ puts $tfh " end"
+ puts $tfh " end"
+ puts $tfh ""
+ puts $tfh " dut_if theif\(\)\;"
+ puts $tfh ""
+ puts $tfh " $mod_name u1 \("
+
+ set llen [llength $name_lst]
+ set idx 1
+ foreach n $name_lst {
+ set ln $n
+ set len [string length $ln]
+ while {$len < $name_length} {
+ append ln " "
+ set len [string length $ln]
+ }
+ if {$idx < $llen} {
+ puts $tfh " .$ln \(theif.$n\),"
+ } else {
+ puts $tfh " .$ln \(theif.$n\)"
+ }
+ incr idx
+ }
+
+ puts $tfh " \)\;"
+ puts $tfh ""
+ puts $tfh " tb_mod prg_inst\(theif\)\;"
+ puts $tfh ""
+ puts $tfh "endmodule"
+
+ close $tfh
+############################################################################
+## generate the interface file.
+ set ifn $destin_text
+ append ifn "/dut_if.sv"
+ set ifh [open $ifn w]
+
+ write_header $ifh
+ puts $ifh "interface dut_if\(\)\;"
+ puts $ifh ""
+ foreach l $log_lst {
+ puts $ifh " $l"
+ }
+
+ puts $ifh ""
+ puts $ifh " modport dut_conn\("
+ set llen [llength $mod_lst]
+ set idx 1
+ foreach p $mod_lst {
+ if {$idx < $llen} {
+ puts $ifh " $p"
+ } else {
+ puts $ifh " [string trim $p ","]"
+ }
+ incr idx
+ }
+ puts $ifh " \)\;"
+ puts $ifh ""
+ puts $ifh " modport tb_conn\("
+ set idx 1
+ foreach p $mod_lst {
+ set in [string first "input" $p]
+ set out [string first "output" $p]
+ if {$in >= 0} {
+ set type "output "
+ } elseif {$out >= 0} {
+ set type "input "
+ } else {
+ set type "inout "
+ }
+
+ set sp [split $p]
+ if {$idx < $llen} {
+ puts $ifh " $type [lindex $sp end]"
+ } else {
+ puts $ifh " $type [string trim [lindex $sp end] ","]"
+ }
+ incr idx
+ }
+ puts $ifh " \)\;"
+ puts $ifh ""
+ puts $ifh "endinterface"
+ close $ifh
+
+##########################################################################
+## generate the tb_prg file from template.
+ set prg_gen [$mo_sel get]
+ if {$prg_gen == "No mod"} {
+ return
+ }
+ set tpl_fh [open $template r]
+ set tpl_lst {}
+ set hfound 0
+ while {![eof $tpl_fh]} {
+ set rline [gets $tpl_fh]
+ if {$hfound == 0} {
+ set head [string first ">>header" $rline]
+ if {$head == 0} {
+ set hfound 1
+ }
+ } else {
+ lappend tpl_lst $rline
+ }
+ }
+
+ #foreach l $tpl_lst {
+ # puts $l
+ #}
+
+ set pfn $destin_text
+ append pfn "/tb_mod.sv"
+ set pfh [open $pfn w]
+
+ set idx 0
+ foreach l $tpl_lst {
+ set ent_pt [string first ">>insert sigs" $l]
+ if {$ent_pt == 0} {
+ set tpl_lst [lreplace $tpl_lst $idx $idx]
+ foreach l $log_lst {
+ set tpl_lst [linsert $tpl_lst $idx " $l"]
+ incr $idx
+ }
+ break
+ }
+ incr idx
+ }
+
+ set idx 0
+ foreach l $tpl_lst {
+ set ent_pt [string first ">>drive sigs" $l]
+ if {$ent_pt == 0} {
+ set tpl_lst [lreplace $tpl_lst $idx $idx]
+ set midx 0
+ foreach l $name_lst {
+ set dir [lindex $mod_lst $midx]
+ #puts $dir
+ set idir [string first "input" $dir]
+ if {$idir >= 0} {
+ set tmp " assign tif."
+ append tmp "$l = $l\;"
+ set tpl_lst [linsert $tpl_lst $idx $tmp]
+ } else {
+ set tmp " assign $l"
+ append tmp " = tif.$l\;"
+ set tpl_lst [linsert $tpl_lst $idx $tmp]
+ }
+ incr idx
+ incr midx
+ }
+ break
+ }
+ incr idx
+ }
+
+ write_header $pfh
+ #foreach l $tpl_lst {
+ # puts $pfh $l
+ #}
+
+ close $pfh
+}
+## end ttb_gen
+#################################################
+## show about message
+proc show_about {} {
+ global version
+
+ set msg "Copyright 2014 Ken Campbell\n
+Version $version\n
+Licensed under the Apache License, Version 2.0 (the \"License\"); You may not use this file except in compliance with the License. You may obtain a copy of the License at\n
+http://www.apache.org/licenses/LICENSE-2.0\n
+Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and limitations under the License."
+
+ dbg_msg $msg
+}
+
+## enable pop up console for debug
+bind . {catch {console show}}
Index: trunk/tb_gen/tb_gen_cmd
===================================================================
--- trunk/tb_gen/tb_gen_cmd (nonexistent)
+++ trunk/tb_gen/tb_gen_cmd (revision 2)
@@ -0,0 +1,545 @@
+#! /usr/bin/env wish
+##-------------------------------------------------------------------------------
+## Copyright 2014 Ken Campbell
+##
+## Licensed under the Apache License, Version 2.0 (the "License");
+## you may not use this file except in compliance with the License.
+## You may obtain a copy of the License at
+##
+## http://www.apache.org/licenses/LICENSE-2.0
+##
+## Unless required by applicable law or agreed to in writing, software
+## distributed under the License is distributed on an "AS IS" BASIS,
+## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+## See the License for the specific language governing permissions and
+## limitations under the License.
+##-------------------------------------------------------------------------------
+##-- $Author: $ Ken Campbell
+##--
+##-- $Date: $ June 26 2014
+##--
+##-- $Id: $
+##--
+##-- $Source: $
+##--
+##-- Description :
+##-- This application takes a text file containing the definition of a Verilog
+## module, produces a file set for the SV Directed Test Bench.
+##--
+##------------------------------------------------------------------------------
+
+## set the current version info
+set version "Beta 1.0"
+
+
+set gen_mod 0
+set des_dir "./"
+
+
+proc print_help {} {
+ puts ""
+ puts "tb_gen_cmd Help"
+ puts "------------------------------"
+ puts "general use: tb_gen_cmd "
+ puts ""
+ puts "The non optional input parameter is the path to and name of the"
+ puts "source file containing the Module."
+ puts ""
+ puts " Options:"
+ puts " -des : Destination directory, default is the current directory"
+ puts " -mod : Enable the output of the tb_mod.sv file"
+ puts " NOTE: will over write existing file."
+ puts ""
+ puts " help : print this help message"
+ puts ""
+ puts "An environment variable needs to be set up. TBGEN must point to the"
+ puts "location of tb_gen directory. The source of the template."
+ puts ""
+}
+
+if {$::argc <= 0} {
+ puts "No Arguments passed to tb_gen_cmd!!"
+ print_help
+ exit
+}
+## get the value of the environment variable.
+set tbgen $::env(TBGEN)
+if {$tbgen == ""} {
+ puts "ERROR: Environment variable TBGEN is not set to a valid value."
+ exit
+}
+## get the first parameter, check for help
+set mod_fn [lindex $::argv 0]
+if {$mod_fn == "help"} {
+ print_help
+ exit
+}
+
+set idx 0
+set des 0
+foreach arg $::argv {
+ ## if des has been found, set destination dir variable.
+ if {$des == 1} {
+ set des_dir $arg
+ set des 0
+ }
+ ## checking that the first param is the source module
+ if {"$arg" == "$mod_fn" && $idx == 0} {
+ incr idx
+ continue
+ } elseif {$idx == 0} {
+ puts "The first parameter must be the path and file name of the module file."
+ exit
+ }
+ ## flag to turn on prg.sv file gen
+ if {$arg == "-mod"} {
+ set gen_mod 1
+ }
+ ## flag for the destination dir
+ if {$arg == "-des"} {
+ set des 1
+ }
+
+ incr idx
+}
+
+puts "********************************************************************"
+puts "** tb_gen_cmd Script Directed TB version: $version"
+puts "** Source file for module definition: $mod_fn"
+puts "** Destination output directory is: $des_dir"
+
+
+##########################################################################
+## proc pars_pindef
+proc pars_pindef { pins } {
+ set pdef {}
+ set def_lst {}
+ set lc 0
+
+ set logic_lst {}
+ set dut_modport {}
+ set names_lst {}
+
+ foreach l $pins {
+ set is_mult [string first "," $l]
+ set is_bv [string first "\[" $l]
+ set l [string trim $l "\;"]
+ ## if is a vector def
+ if {$is_bv > 0} {
+ set is_cbv [string first "\]" $l]
+ set bv_spec [string range $l $is_bv $is_cbv]
+ set type [string range $l 0 $is_bv-1]
+ set names [string range $l $is_cbv+1 end]
+ set snames [split $names ","]
+ foreach n $snames {
+ lappend names_lst [string trim $n]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ append tmp $bv_spec " [string trim $n]\;"
+ lappend logic_lst $tmp
+ set tmp [string trim $type]
+ append tmp " [string trim $n],"
+ lappend dut_modport $tmp
+ }
+ } else {
+ set sl [split $l ","]
+ set frst [split [lindex $sl 0]]
+ set type [string trim [lindex $frst 0]]
+ set fname [string trim [lindex $frst end]]
+ set sl [lrange $sl 1 end]
+ lappend names_lst [string trim $fname]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ append tmp "$fname\;"
+ lappend logic_lst $tmp
+ set tmp $type
+ append tmp " $fname,"
+ lappend dut_modport $tmp
+ foreach n $sl {
+ lappend names_lst [string trim $n]
+ if {$type != "inout"} {
+ set tmp "logic "
+ } else {
+ set tmp "wire "
+ }
+ append tmp "[string trim $n]\;"
+ lappend logic_lst $tmp
+ set tmp $type
+ append tmp " [string trim $n],"
+ lappend dut_modport $tmp
+ }
+ }
+ }
+
+ lappend def_lst $logic_lst
+ lappend def_lst $dut_modport
+ lappend def_lst $names_lst
+
+ return $def_lst
+}
+## end pars_pindef
+
+##--------------------------------------------------------------------------------
+## Write header to file passed
+proc write_header { handle } {
+ global version
+ ##global scan_date
+ set raw_date [clock scan now]
+ set scan_date [clock format $raw_date -format "%d %b %Y %T"]
+
+ ## so CVS will not modify selections, they have to be chopped up
+ set auth "// \$Auth"
+ append auth "or: \$"
+
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle "// Copyright ///////////////////////////////////"
+ puts $handle "// All Rights Reserved"
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle "$auth"
+ puts $handle "//"
+ puts $handle "//"
+ puts $handle "// Description :"
+ puts $handle "// This file was generated by tb_gen_cmd $version"
+ puts $handle "// on $scan_date"
+ puts $handle "//////////////////////////////////////////////////////////////////////////////"
+ puts $handle "// This software contains concepts confidential to ////////////////"
+ puts $handle "// /////////. and is only made available within the terms of a written"
+ puts $handle "// agreement."
+ puts $handle "///////////////////////////////////////////////////////////////////////////////"
+ puts $handle ""
+}
+
+#########################################################################
+# Generate files
+set template $tbgen
+append template "/tb_prg_template.sv"
+
+## the source module file
+set ln $mod_fn
+## Get the working directory
+set lp $des_dir
+
+set path_text $lp
+set destin_text $des_dir
+set infile [open $ln r]
+set file_list {}
+
+
+##################################################################
+## Read in the file and strip comments as we do
+while {![eof $infile]} {
+ ## Get a line
+ set rline [gets $infile]
+ ## get rid of white space
+ set rline [string trim $rline]
+ ## Find comment if there
+ set cindex [string first "//" $rline]
+ ## if a comment was found at the start of the line
+ if {$cindex == 0 || $rline == ""} {
+ continue
+ ## else was not found so put line in list
+ } elseif {$cindex > 0} {
+ # get rid of trailing comments and trim off spaces
+ set rline [string trim [string range $rline 0 $cindex-1]]
+ lappend file_list $rline
+ } else {
+ lappend file_list $rline
+ }
+}
+close $infile
+
+## check for the module def
+set mod_name ""
+foreach l $file_list {
+ set mod_def [string first module $l]
+ if {$mod_def >= 0} {
+ set ml [split $l]
+ set mod_name [lindex $l 1]
+ break
+ }
+}
+
+## if no module die
+if {$mod_def < 0} {
+ puts "A module definition was not found in the file provided."
+ exit
+}
+set mod_list {}
+## check for end module
+foreach l $file_list {
+ lappend mod_list $l
+ set end_def [string first endmodule $l]
+ if {$end_def >= 0} {
+ break
+ }
+}
+## if no end die
+if {$end_def < 0} {
+ puts "no endmodule statement found for this module"
+ exit
+}
+
+####
+## collect the parameters if there are.
+set parameter_list {}
+set p_found 0
+foreach l $mod_list {
+ set p_found [string first "parameter" $l]
+ if {$p_found >= 0} {
+ lappend $parameter_list $l
+ }
+}
+
+####################################################################
+## a few checks have been done, and non-relevant stuff stripped off.
+## now create an arrry of just the pin names and related info
+set port_lst {}
+set lc 0
+foreach l $mod_list {
+ ## make lines that are continued, one line.
+ set cont [string first "\;" $l]
+ if {$cont < 0 && $lc == 0} {
+ set tmp $l
+ set lc 1
+ continue
+ } elseif {$cont < 0 && $lc == 1} {
+ append tmp $l
+ continue
+ } elseif {$lc == 1} {
+ append tmp $l
+ set lc 0
+ set l $tmp
+ }
+
+ ## look for the port statements
+ set inp [string first "input" $l]
+ if {$inp >= 0} {
+ lappend port_lst $l
+ }
+ set onp [string first "output" $l]
+ if {$onp >= 0} {
+ lappend port_lst $l
+ }
+ set ionp [string first "inout" $l]
+ if {$ionp >= 0} {
+ lappend port_lst $l
+ }
+}
+
+## Change the port list into a pin info list
+set io_pins [pars_pindef $port_lst]
+
+set log_lst [lindex $io_pins 0]
+set mod_lst [lindex $io_pins 1]
+set name_lst [lindex $io_pins 2]
+
+#foreach r $log_lst {
+# puts $r
+#}
+#foreach r $mod_lst {
+# puts $r
+#}
+#foreach r $name_lst {
+# puts $r
+#}
+
+## calculate the longest pin name in characters
+set name_length 0
+foreach l $name_lst {
+ set temp_length [string length $l]
+ if {$temp_length > $name_length} {
+ set name_length $temp_length
+ }
+}
+## Make the name length one bigger
+incr name_length
+
+#########################################################################
+## Generate the tb top.
+set tfn $destin_text
+append tfn "/tb_top.sv"
+set tfh [open $tfn w]
+
+write_header $tfh
+puts $tfh "`include \"../sv/tb_prg.sv\""
+puts $tfh ""
+puts $tfh "module tb_top \(\)\;"
+puts $tfh ""
+puts $tfh " string STM_FILE = \"../stm/stimulus_file.stm\"\;"
+puts $tfh " string tmp_fn"
+puts $tfh ""
+puts $tfh " // Handle plus args"
+puts $tfh " initial begin : file_select"
+puts $tfh " if\(\$value\$plusargs\(\"STM_FILE=%s\", tmp_fn\)\) begin"
+puts $tfh " stm_file = tmp_fn\;"
+puts $tfh " end"
+puts $tfh " end"
+puts $tfh ""
+puts $tfh " dut_if theif\(\)\;"
+puts $tfh ""
+puts $tfh " $mod_name u1 \("
+
+set llen [llength $name_lst]
+set idx 1
+foreach n $name_lst {
+ set ln $n
+ set len [string length $ln]
+ while {$len < $name_length} {
+ append ln " "
+ set len [string length $ln]
+ }
+ if {$idx < $llen} {
+ puts $tfh " .$ln \(theif.$n\),"
+ } else {
+ puts $tfh " .$ln \(theif.$n\)"
+ }
+ incr idx
+}
+
+puts $tfh " \)\;"
+puts $tfh ""
+puts $tfh " tb_mod prg_inst\(theif\)\;"
+puts $tfh ""
+puts $tfh "endmodule"
+
+close $tfh
+############################################################################
+## generate the interface file.
+set ifn $destin_text
+append ifn "/dut_if.sv"
+set ifh [open $ifn w]
+
+write_header $ifh
+puts $ifh "interface dut_if\(\)\;"
+puts $ifh ""
+foreach l $log_lst {
+ puts $ifh " $l"
+}
+
+puts $ifh ""
+puts $ifh " modport dut_conn\("
+set llen [llength $mod_lst]
+set idx 1
+foreach p $mod_lst {
+ if {$idx < $llen} {
+ puts $ifh " $p"
+ } else {
+ puts $ifh " [string trim $p ","]"
+ }
+ incr idx
+}
+puts $ifh " \)\;"
+puts $ifh ""
+puts $ifh " modport tb_conn\("
+set idx 1
+foreach p $mod_lst {
+ set in [string first "input" $p]
+ set out [string first "output" $p]
+ if {$in >= 0} {
+ set type "output "
+ } elseif {$out >= 0} {
+ set type "input "
+ } else {
+ set type "inout "
+ }
+
+ set sp [split $p]
+ if {$idx < $llen} {
+ puts $ifh " $type [lindex $sp end]"
+ } else {
+ puts $ifh " $type [string trim [lindex $sp end] ","]"
+ }
+ incr idx
+}
+puts $ifh " \)\;"
+puts $ifh ""
+puts $ifh "endinterface"
+close $ifh
+
+##########################################################################
+## generate the tb_prg file from template.
+if {gen_mod == 0} {
+ exit
+}
+
+set tpl_fh [open $template r]
+set tpl_lst {}
+set hfound 0
+while {![eof $tpl_fh]} {
+ set rline [gets $tpl_fh]
+ if {$hfound == 0} {
+ set head [string first ">>header" $rline]
+ if {$head == 0} {
+ set hfound 1
+ }
+ } else {
+ lappend tpl_lst $rline
+ }
+}
+
+#foreach l $tpl_lst {
+# puts $l
+#}
+
+set pfn $destin_text
+append pfn "/tb_mod.sv"
+set pfh [open $pfn w]
+
+set idx 0
+foreach l $tpl_lst {
+ set ent_pt [string first ">>insert sigs" $l]
+ if {$ent_pt == 0} {
+ set tpl_lst [lreplace $tpl_lst $idx $idx]
+ foreach l $log_lst {
+ set tpl_lst [linsert $tpl_lst $idx " $l"]
+ incr $idx
+ }
+ break
+ }
+ incr idx
+}
+
+set idx 0
+foreach l $tpl_lst {
+ set ent_pt [string first ">>drive sigs" $l]
+ if {$ent_pt == 0} {
+ set tpl_lst [lreplace $tpl_lst $idx $idx]
+ set midx 0
+ foreach l $name_lst {
+ set dir [lindex $mod_lst $midx]
+ #puts $dir
+ set idir [string first "input" $dir]
+ if {$idir >= 0} {
+ set tmp " assign tif."
+ append tmp "$l = $l\;"
+ set tpl_lst [linsert $tpl_lst $idx $tmp]
+ } else {
+ set tmp " assign $l"
+ append tmp " = tif.$l\;"
+ set tpl_lst [linsert $tpl_lst $idx $tmp]
+ }
+ incr idx
+ incr midx
+ }
+ break
+ }
+ incr idx
+}
+
+write_header $pfh
+foreach l $tpl_lst {
+ puts $pfh $l
+}
+
+close $pfh
+
+puts "********************************************************************"
+puts "** tb_gen_cmd Generation Done."
+
+exit
Index: trunk/tb_gen/tb_mod_template.sv
===================================================================
--- trunk/tb_gen/tb_mod_template.sv (nonexistent)
+++ trunk/tb_gen/tb_mod_template.sv (revision 2)
@@ -0,0 +1,118 @@
+/////////////////////////////////////////////////////////////////
+// Copyright 2014 Ken Campbell
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// test bench module file template.
+////////////////////////////////////////////////////////////////
+>>header
+// The package.
+ `include "../sv/tb_pkg.sv"
+
+module tb_mod (dut_if.tb_conn tif);
+
+ import tb_pkg::*;
+
+ // package and container
+ cmd_lst cmds;
+ tb_trans r;
+
+ integer in_fh;
+ integer stat;
+ logic clock;
+
+ //////////////////////////////////////////////
+ // DUT signals
+>>insert sigs
+
+ ////////////////////////////////////////////////////////
+ // drive DUT signals through interface
+>>drive sigs
+
+ ////////////////////////////////////////////////////
+ // instruction variables
+ integer was_def = 0;
+ string cmd_string;
+ logic [31:0] tmp_vec;
+
+ ////////////////////////////////////////////////////////////////////
+ // clock driver
+ initial begin
+ while(1) begin
+ #10 clock = 0;
+ #10 clock = 1;
+ end
+ end
+
+ //////////////////////////////////////////////////////////
+ // stimulus_file processing
+ initial begin : Process_STM
+ cmds = new();
+ r = new();
+ // define the default instructions
+ cmds.define_defaults();
+ // User instructions
+ cmds.define_instruction("RESET", 0);
+ //cmds.define_instruction("READ", 1);
+ //cmds.define_instruction("WRITE", 2);
+ //cmds.define_instruction("VERIFY", 1);
+
+ // load the stimulus file
+ cmds.load_stm(`STM_FILE);
+
+ r.cmd = cmds;
+ /////////////////////////////////////////////////////
+ // the main loop.
+ while (r.cmd != null) begin
+ r = r.cmd.get(r);
+ r.next++;
+
+ // process default instructions
+ was_def = r.cmd.exec_defaults(r);
+ if(was_def) begin
+ continue;
+ end
+
+ ///////////////////////////////////////////////////////
+ // Process User instructions.
+ // get the command string
+ cmd_string = r.cmd.lst_cmds.cmd;
+ // output the dynamic text if there is some. (Note: before command runs.)
+ r.cmd.print_str_wvar();
+
+ ///////////////////////////////////////////////////////////////////////////
+ // RESET
+ if (cmd_string == "RESET") begin
+ @(posedge clock)
+ ///////////////////////////////////////////////////////////////////////////
+ // READ
+ //end else if (cmd_string == "READ") begin
+ // @(posedge clock)
+ ///////////////////////////////////////////////////////////////////////////
+ // WRITE
+ //end else if (cmd_string == "WRITE") begin
+ //////////////////////////////////////////////////////////////////////////
+ // VERIFY
+ //end else if (cmd_string == "VERIFY") begin
+ // verify_command : assert (tmp_vec == r.rtn_val.par1) else begin
+ // $fatal(0,"VERIFY failed expected: %x Got: %x", r.rtn_val.par1, tmp_vec);
+ // end
+ end else begin
+ $display("ERROR: Command not found in the else if chain. Is it spelled correctly in the else if?");
+ end // end of else if chain
+ end // end main while loop
+ // should never end up outside the while loop.
+ $display("ERROR: Some how, a run off the beginning or end of the instruction sequence, has not been caught!!");
+ end // end Process_STM
+
+endmodule // tb_mod