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Rev 16 → Rev 17

/trunk/bench/verilog/test_bench_top.v File deleted
/trunk/bench/verilog/aes192lowarea/test_bench_top.v
1,3 → 1,45
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Test Bench ////
//// ////
//// ////
//// Author: Javier Castillo ////
//// ////
//// ////
//// Adapted to SystemC ////
//// AES project by: jcastillo@opensocdesign.com ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2005 Javier Castillo ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// CVS Log
//
// $Log: not supported by cvs2svn $
 
`timescale 10ns/1ns
 
module top;
31,7 → 73,7
load_i = #17 'b1;
load_i = #22 'b0;
$display("Ejecutando");
$display("Running");
wait(ready_o);
$display("%H",data_o);
$finish;
40,4 → 82,4
always #5 clk = !clk;
 
endmodule
endmodule
/trunk/rtl/systemc/sbox.h File deleted
/trunk/rtl/systemc/aes.h File deleted
/trunk/rtl/systemc/mixcolum.h File deleted
/trunk/rtl/systemc/word_mixcolum.cpp File deleted
/trunk/rtl/systemc/byte_mixcolum.h File deleted
/trunk/rtl/systemc/stimulus.h File deleted
/trunk/rtl/systemc/transactor.h File deleted
/trunk/rtl/systemc/sbox.cpp File deleted
/trunk/rtl/systemc/aesmodel.h File deleted
/trunk/rtl/systemc/byte_mixcolum.cpp File deleted
/trunk/rtl/systemc/mixcolum.cpp File deleted
/trunk/rtl/systemc/adapt.h File deleted
/trunk/rtl/systemc/stimulus.cpp File deleted
/trunk/rtl/systemc/aes.cpp File deleted
/trunk/rtl/systemc/word_mixcolum.h File deleted
/trunk/rtl/verilog/aes192lowarea/top.v File deleted \ No newline at end of file
/trunk/rtl/verilog/aes192lowarea/keysched192.v
1,3 → 1,50
//////////////////////////////////////////////////////////////////////
//// ////
//// Key schedule ////
//// ////
//// This file is part of the SystemC AES ////
//// ////
//// Description: ////
//// Generate the next round key from the previous one ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
`include "timescale.v"
 
202,4 → 249,4
 
end
 
endmodule
endmodule
/trunk/rtl/verilog/aes192lowarea/aes192.v
1,3 → 1,52
//////////////////////////////////////////////////////////////////////
//// ////
//// AES top file ////
//// ////
//// This file is part of the SystemC AES ////
//// ////
//// Description: ////
//// AES top ////
//// ////
//// Generated automatically using SystemC to Verilog translator ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, jcastilo@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
 
`include "timescale.v"
 
module aes192(clk,reset,load_i,decrypt_i,data_i,key_i,ready_o,data_o);

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