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https://opencores.org/ocsvn/systemverilog-uart16550/systemverilog-uart16550/trunk
Subversion Repositories systemverilog-uart16550
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/systemverilog-uart16550/systemverilog-uart16550/trunk/doc/origin_doc/UART_spec.doc
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systemverilog-uart16550/systemverilog-uart16550/trunk/doc/origin_doc/UART_spec.doc
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Index: systemverilog-uart16550/systemverilog-uart16550/trunk/doc/UART_spec_SV.doc
===================================================================
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Index: systemverilog-uart16550/systemverilog-uart16550/trunk/doc/UART_spec_SV.doc
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/doc/UART_spec_SV.doc (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/doc/UART_spec_SV.doc (nonexistent)
systemverilog-uart16550/systemverilog-uart16550/trunk/doc/UART_spec_SV.doc
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## -1 +0,0 ##
-application/octet-stream
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Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_be.list
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_be.list (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_be.list (nonexistent)
@@ -1,5 +0,0 @@
-../rtl/uart_interface.sv
-../bench/uart_top_package.sv
-../bench/uart_interface_be.sv
-../bench/uart_be.sv
-../bench/uart_wrapper.sv
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/makefile
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/makefile (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/makefile (nonexistent)
@@ -1,50 +0,0 @@
-#/* *****************************************************************************
-# * title: uart_16550_rll module *
-# * description: RS232 Protocol 16550D uart (mostly supported) *
-# * languages: systemVerilog *
-# * *
-# * Copyright (C) 2010 miyagi.hiroshi *
-# * *
-# * This library is free software; you can redistribute it and/or *
-# * modify it under the terms of the GNU Lesser General Public *
-# * License as published by the Free Software Foundation; either *
-# * version 2.1 of the License, or (at your option) any later version. *
-# * *
-# * This library is distributed in the hope that it will be useful, *
-# * but WITHOUT ANY WARRANTY; without even the implied warranty of *
-# * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
-# * Lesser General Public License for more details. *
-# * *
-# * You should have received a copy of the GNU Lesser General Public *
-# * License along with this library; if not, write to the Free Software *
-# * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
-# * *
-# * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
-# * from http://www.gnu.org/licenses/lgpl.txt *
-# *****************************************************************************
-# * redleaflogic,ltd *
-# * miyagi.hiroshi@redleaflogic.biz *
-# * $Id: uart_test.sv 108 2010-03-30 02:56:26Z hiroshi $ *
-# ***************************************************************************** */
-
-.SUFFIXES :
-.SUFFIXES : .v .sv .vcd .log
-
-all: uart_test.log
-
-align = ALIGN_4B
-
-.sv.log:
- vlog -f uart_rtl.list -sv +acc=rn +define+${align}+
- vlog -f uart_be.list -sv +acc=rn +define+${align}+
- vsim -i top < modelSim.in
- mv transcript uart_test_${align}.log
- mv uart_16550_rll.dump uart_test_a_${align}.dump
-
-work:
- vlib work
-
-clean:
- - \rm -rf ./work *.vcd *.wlf *.dump *.log
-
-
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/modelSim.in
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/modelSim.in (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/modelSim.in (nonexistent)
@@ -1 +0,0 @@
-run -all ; quit -f
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_wave.do
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_wave.do (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_wave.do (nonexistent)
@@ -1,39 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /top/clk_sys
-add wave -noupdate -format Logic /top/rst_p
-add wave -noupdate -format Logic /top/intr_o
-add wave -noupdate -format Logic /top/bench_intr_o
-add wave -noupdate -format Logic /top/DUT/srx_i
-add wave -noupdate -format Logic /top/DUT/stx_o
-add wave -noupdate -format Literal /top/DUT/ut/um/u_register/u_reg
-add wave -noupdate -format Literal /top/DUT/ut/um/u_register/fifo_trans/u_fifo
-add wave -noupdate -format Literal /top/DUT/ut/um/u_register/fifo_rec/u_fifo
-add wave -noupdate -format Literal /top/DUT/ut/um/u_trans/trans_codec
-add wave -noupdate -format Literal /top/DUT/ut/um/u_trans/next_state
-add wave -noupdate -format Literal /top/DUT/ut/um/u_rec/rec_codec
-add wave -noupdate -format Literal /top/DUT/ut/um/u_rec/next_state
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_register/u_reg
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_register/fifo_trans/u_fifo
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_register/fifo_rec/u_fifo
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_trans/trans_codec
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_trans/next_state
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_rec/rec_codec
-add wave -noupdate -format Literal /top/BENCH/ut/um/u_rec/next_state
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 382
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ps
-update
-WaveRestoreZoom {0 ps} {67582904522 ps}
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_test.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_test.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_test.sv (nonexistent)
@@ -1,168 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_test.sv 112 2010-03-30 04:37:33Z hiroshi $ *
- ***************************************************************************** */
-
-#(STEP*100) ;
-$display("char7 pari non, buad rate setup 19200bps") ;
-$fdisplay(file_a, "char7 pari non, buad rate setup 19200bps") ;
-
-UART_R = 0 ; // all cleaer register
-
-$display("fifo trigger level 14byte") ;
-$fdisplay(file_a, "fifo trigger level 14byte") ;
-UART_R.fifo_control_reg.define_fifo_trigger_level = BYTE_14 ;
-wb_DUT.write( UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
-wb_BENCH.write(UART_R.fifo_control_reg, UART_FIFO_CONTROL) ;
-
-
-UART_R.line_control_reg.divisor_access = 1'b1 ;
-UART_R.baud_reg = 8'd64 ; // 19200bps
-wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
-wb_BENCH.write(UART_R.baud_reg, UART_BAUD) ;
-wb_DUT.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
-wb_DUT.write(UART_R.baud_reg, UART_BAUD) ;
-// --
-UART_R.line_control_reg.divisor_access = 1'b0 ;
-UART_R.line_control_reg.char_length = CHAR_7_BIT ;
-UART_R.line_control_reg.parity_enable = 1'b0 ;
-UART_R.line_control_reg.even_parity = 1'b1 ;
-wb_BENCH.write(UART_R.line_control_reg, UART_LINE_CONTROL) ;
-wb_DUT.write( UART_R.line_control_reg, UART_LINE_CONTROL) ;
-
-UART_R.interrupt_enable_reg.trans_holding_reg_empty = 1'b1 ;
-wb_DUT.write(UART_R.interrupt_enable_reg, UART_INTERRUPT_ENABLE) ;
-wb_DUT.nop() ;
-wdat = 1 ;
-
-for(i=0;i<8;i+=1) begin
- wb_DUT.write(wdat< accept") ;
-$fdisplay(file_a, "timeout intr -> accept") ;
-wb_DUT.read(rdat, UART_LINE_STATUS) ;
-$display("line_status = %b", rdat) ;
-$fdisplay(file_a, "line_status = %b", rdat) ;
-
-wb_DUT.read(rdat, UART_INTERRUPT_IDENT) ;
-$display("interrupt_ident = %b", rdat) ;
-$fdisplay(file_a, "interrupt_ident = %b", rdat) ;
-
-wb_DUT.read(rdat, UART_RXD) ;
-wb_DUT.read(rdat, UART_INTERRUPT_IDENT) ;
-$display("interrupt_ident = %b", rdat) ;
-$fdisplay(file_a, "interrupt_ident = %b", rdat) ;
-
-#(STEP*500) ;
-
-
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/README_sim.txt
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/README_sim.txt (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/README_sim.txt (nonexistent)
@@ -1,17 +0,0 @@
-
- ** run simulation ** by hiroshi
-
-Environment : unix or cygwin
-
-* align 4byte versoin
-
- make clean
- make work
- make align=ALIGN_4B
-
-* align 1byte versoin
-
- make clean
- make work
- make align=ALIGN_1B
-
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_rtl.list
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_rtl.list (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/sim/uart_rtl.list (nonexistent)
@@ -1,15 +0,0 @@
-../rtl/uart_package.sv
-../rtl/fifo_package.sv
-../rtl/uart_interface.sv
-../rtl/fifo_interface.sv
-../rtl/uart_16550_rll.sv
-../rtl/uart_codec_state.sv
-../rtl/uart_receiver.sv
-../rtl/uart_register.sv
-../rtl/uart_transmitter.sv
-../rtl/uart_fifo.sv
-../rtl/uart_baud.sv
-../rtl/uart_noize_shaver.sv
-../bench/uart_top.sv
-
-
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qpf
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qpf (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qpf (nonexistent)
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
-# Date created = 20:55:27 March 09, 2010
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "9.1"
-DATE = "20:55:27 March 09, 2010"
-
-# Revisions
-
-PROJECT_REVISION = "uart_top"
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qsf
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qsf (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qsf (nonexistent)
@@ -1,73 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
-# Date created = 20:55:27 March 09, 2010
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# uart_top_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY uart_top
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:55:27 MARCH 09, 2010"
-set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
-set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clk_sys
-set_instance_assignment -name CLOCK_SETTINGS clk_sys -to clk_i
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
-set_global_assignment -name VERILOG_MACRO "SYN="
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_16550_rll.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/fifo_interface.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_package.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/fifo_package.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_baud.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_noize_shaver.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../bench/uart_top.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_transmitter.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_codec_state.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_fifo.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_interface.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_receiver.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/uart_register.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qws
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qws (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/syn/uart_top.qws (nonexistent)
@@ -1,7 +0,0 @@
-[ProjectWorkspace]
-ptn_Child1=Frames
-[ProjectWorkspace.Frames]
-ptn_Child1=ChildFrames
-[ProjectWorkspace.Frames.ChildFrames]
-ptn_Child1=Document-0
-ptn_Child2=Document-1
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_be.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_be.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_be.sv (nonexistent)
@@ -1,146 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_be.sv 108 2010-03-30 02:56:26Z hiroshi $ *
- ***************************************************************************** */
-
-`ifdef SYN
-/* empty */
-`else
-timeunit 1ps ;
-timeprecision 1ps ;
-`endif
-import uart_top_package:: * ;
-import uart_package:: * ;
-module top ;
-
- u_reg_t UART_R ;
-
- logic clk_sys ;
- logic rst_p ;
- logic intr_o, bench_intr_o ;
- logic [31:0] rdat, rdat1, rdat2, dat, wdat ;
- integer i, j, k ;
- logic ri, dcd ;
-
- logic [31:0] file_a ;
-`ifdef ALIGN_4B
- localparam UART_RXD = 'h0 ;
- localparam UART_TXD = 'h0 ;
- localparam UART_INTERRUPT_ENABLE = 'h4 ;
- localparam UART_INTERRUPT_IDENT = 'h8 ;
- localparam UART_FIFO_CONTROL = 'hA ;
- localparam UART_LINE_CONTROL = 'hC ;
- localparam UART_MODEM_CONTROL = 'h10 ;
- localparam UART_LINE_STATUS = 'h14 ;
- localparam UART_MODEM_STATUS = 'h18 ;
- localparam UART_SCRATCH = 'h1C ;
- localparam UART_BAUD = 'h0 ;
-`else
- localparam UART_RXD = 'h0 ;
- localparam UART_TXD = 'h0 ;
- localparam UART_INTERRUPT_ENABLE = 'h1 ;
- localparam UART_INTERRUPT_IDENT = 'h2 ;
- localparam UART_FIFO_CONTROL = 'h2 ;
- localparam UART_LINE_CONTROL = 'h3 ;
- localparam UART_MODEM_CONTROL = 'h4 ;
- localparam UART_LINE_STATUS = 'h5 ;
- localparam UART_MODEM_STATUS = 'h6 ;
- localparam UART_SCRATCH = 'h7 ;
- localparam UART_BAUD = 'h0 ;
-`endif
- uart_bus uart_bus_DUT() ;
- uart_bus uart_bus_BENCH() ;
- wb_ext_bus wb_DUT() ;
- wb_ext_bus wb_BENCH() ;
-
- assign wb_DUT.clk_i = clk_sys ;
- assign wb_DUT.nrst_i = ~rst_p ;
- assign wb_BENCH.clk_i = clk_sys ;
- assign wb_BENCH.nrst_i = ~rst_p ;
-
- // --------------
- // - initial -
- // --------------
- initial begin
- fork
- clock_sys ;
- test_pat(file_a) ;
- join
- end
-
- // ------------
- // - task -
- // ------------
- task test_pat(logic [31:0] file_a) ;
- integer i ;
- file_a = $fopen("uar_16550_rll.dump") ;
- ri = 1'b0 ;
- dcd = 1'b0 ;
-
- rst_p = 1'b1 ;
- #(STEP*20) ;
- rst_p = 1'b0 ;
-
- `include "uart_test.sv"
-
- $display(" ----------- happy end SIM !!! --------------") ;
-
- $fclose(file_a) ;
-
- $stop ;
- // $finish ;
- endtask
- task clock_sys ;
- clk_sys = 0 ;
- #(STEP) ;
- forever #(STEP/2) clk_sys = ~clk_sys ;
- endtask
-
- assign intr_o = wb_DUT.intr_o ;
- assign bench_intr_o = wb_BENCH.intr_o ;
-
- assign uart_bus_DUT.srx_i = uart_bus_BENCH.stx_o ;
- assign uart_bus_BENCH.srx_i = uart_bus_DUT.stx_o ;
- assign uart_bus_DUT.cts_i = uart_bus_BENCH.rts_o ;
- assign uart_bus_BENCH.cts_i = uart_bus_DUT.rts_o ;
- assign uart_bus_DUT.dsr_i = uart_bus_BENCH.dtr_o ;
- assign uart_bus_BENCH.dsr_i = uart_bus_DUT.dtr_o ;
-
- assign uart_bus_DUT.ri_i = ri ;
- assign uart_bus_DUT.dcd_i = dcd ;
- assign uart_bus_BENCH.ri_i = 1'b0 ;
- assign uart_bus_BENCH.dcd_i = 1'b0 ;
-
- // ----------
- // - DUT -
- // ----------
- uart_wrapper DUT(.wb_ext_bus(wb_DUT),
- .uart_bus(uart_bus_DUT)) ;
-
- uart_wrapper BENCH(.uart_bus(uart_bus_BENCH),
- .wb_ext_bus(wb_BENCH)) ;
-endmodule
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_interface_be.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_interface_be.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_interface_be.sv (nonexistent)
@@ -1,155 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_interface_be.sv 108 2010-03-30 02:56:26Z hiroshi $ *
- ***************************************************************************** */
-
-`ifdef SYN
-/* empty */
-`else
-timeunit 1ps ;
-timeprecision 1ps ;
-`endif
-import uart_top_package:: * ;
-interface wb_ext_bus() ;
- wire clk_i ; // clock
- wire nrst_i ; // reset
- wire [15:0] adr_i ; // address
- wire [31:0] dat_i ; // data input
- wire [31:0] dat_o ; // clk_rst_manager
- wire we_i ; // write enable
- wire [3:0] sel_i ; // select
- wire stb_i ; //
- wire ack_o ; // acknowledge accept
- wire cyc_i ; // cycle assrted
- wire intr_o ; //
-
- modport master_mp(
- output clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, cyc_i, stb_i,
- input dat_o, ack_o, intr_o
- ) ;
-
- modport slave_mp(
- input clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, stb_i, cyc_i,
- output dat_o, ack_o, intr_o) ;
-
-
- logic [31:0] bw_data ;
- logic [4:0] b_addr ;
- logic cs3, we ;
- logic [3:0] be ;
-
- assign adr_i = b_addr ;
- assign dat_i = we == 1'b1 ? bw_data : 'hx ;
- assign stb_i = cs3 ;
- assign cyc_i = cs3 ;
- assign we_i = we ;
- assign sel_i = be ;
- assign clk_b = clk_i ;
-
- initial begin
- bw_data = 0 ;
- b_addr = 0;
- cs3 = 1'b0 ;
- we = 1'b0 ;
- be = 4'b0000 ;
- end
-
- task write(
- input logic [31:0] wdat,
- input logic [4:0] adr
- ) ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- b_addr = adr ;
- cs3 = 1'b1 ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- bw_data = wdat ;
- we = 1'b1 ;
-`ifdef ALIGN_4B
- be = 4'b1111 ;
-`else
- be[0] = adr[1:0] == 2'b00 ;
- be[1] = adr[1:0] == 2'b01 ;
- be[2] = adr[1:0] == 2'b10 ;
- be[3] = adr[1:0] == 2'b11 ;
-`endif
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- cs3 = 1'b0 ;
- we = 1'b0 ;
- be = 4'b0000 ;
- b_addr = 'hx ;
- bw_data = 'hx ;
- endtask
-
- task read(
- output logic [31:0] rdat,
- input logic [4:0] adr
- ) ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- b_addr = adr ;
- cs3 = 1'b1 ;
- we = 1'b0 ;
- be = 4'b0000 ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- cs3 = 1'b1 ;
- we = 1'b0 ;
-`ifdef ALIGN_4B
- be = 4'b1111 ;
-`else
- be[0] = adr[1:0] == 2'b00 ;
- be[1] = adr[1:0] == 2'b01 ;
- be[2] = adr[1:0] == 2'b10 ;
- be[3] = adr[1:0] == 2'b11 ;
-`endif
- @(posedge clk_b) ;
- rdat = dat_o ;
- #(STEP*0.1) ;
- cs3 = 1'b0 ;
- we = 1'b0 ;
- be = 4'b0000 ;
- b_addr = 'hx ;
- bw_data = 'hx ;
- endtask
-
- task nop() ;
- @(posedge clk_b) ;
- #(STEP*0.1) ;
- b_addr = 'hx ;
- bw_data = 'hx ;
- cs3 = 1'b0 ;
- we = 1'b0 ;
- be = 4'b0000 ;
- endtask
-
-endinterface : wb_ext_bus
-
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top_package.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top_package.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top_package.sv (nonexistent)
@@ -1,40 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_top_package.sv 108 2010-03-30 02:56:26Z hiroshi $ *
- ***************************************************************************** */
-
-package uart_top_package ;
-`ifdef SYN
- /* empty */
-`else
- timeunit 1ps ;
- timeprecision 1ps ;
-`endif
-
-parameter STEP = 50000 ;
-
-endpackage : uart_top_package
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_wrapper.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_wrapper.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_wrapper.sv (nonexistent)
@@ -1,70 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_wrapper.sv 108 2010-03-30 02:56:26Z hiroshi $ *
- ***************************************************************************** */
-
-`ifdef SYN
-/* empty */
-`else
-timeunit 1ps ;
-timeprecision 1ps ;
-`endif
-import uart_top_package:: * ;
-module uart_wrapper (interface wb_ext_bus, interface uart_bus) ;
-
- logic [31:0] dat_o ;
- logic ack_o ;
- logic intr_o ;
- logic stx_o ;
- logic rts_o ;
- logic dtr_o ;
-
- wire clk_i = wb_ext_bus.clk_i ;
- wire nrst_i = wb_ext_bus.nrst_i ;
- wire [15:0] adr_i = wb_ext_bus.adr_i ;
- wire [31:0] dat_i = wb_ext_bus.dat_i ;
- wire we_i = wb_ext_bus.we_i ;
- wire [3:0] sel_i = wb_ext_bus.sel_i ;
- wire stb_i = wb_ext_bus.stb_i ;
- wire cyc_i = wb_ext_bus.cyc_i ;
-
- assign wb_ext_bus.dat_o = dat_o ;
- assign wb_ext_bus.ack_o = ack_o ;
- assign wb_ext_bus.intr_o = intr_o ;
- assign uart_bus.stx_o = stx_o ;
- assign uart_bus.rts_o = rts_o ;
- assign uart_bus.dtr_o = dtr_o ;
-
- wire srx_i = uart_bus.srx_i ;
- wire cts_i = uart_bus.cts_i ;
- wire dsr_i = uart_bus.dsr_i ;
- wire ri_i = uart_bus.ri_i ;
- wire dcd_i = uart_bus.dcd_i ;
-
- uart_top ut(.*) ;
-
-endmodule
Index: systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top.sv
===================================================================
--- systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top.sv (revision 2)
+++ systemverilog-uart16550/systemverilog-uart16550/trunk/bench/uart_top.sv (nonexistent)
@@ -1,87 +0,0 @@
-/* *****************************************************************************
- * title: uart_16550_rll module *
- * description: RS232 Protocol 16550D uart (mostly supported) *
- * languages: systemVerilog *
- * *
- * Copyright (C) 2010 miyagi.hiroshi *
- * *
- * This library is free software; you can redistribute it and/or *
- * modify it under the terms of the GNU Lesser General Public *
- * License as published by the Free Software Foundation; either *
- * version 2.1 of the License, or (at your option) any later version. *
- * *
- * This library is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
- * Lesser General Public License for more details. *
- * *
- * You should have received a copy of the GNU Lesser General Public *
- * License along with this library; if not, write to the Free Software *
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
- * *
- * *** GNU LESSER GENERAL PUBLIC LICENSE *** *
- * from http://www.gnu.org/licenses/lgpl.txt *
- *****************************************************************************
- * redleaflogic,ltd *
- * miyagi.hiroshi@redleaflogic.biz *
- * $Id: uart_top.sv 108 2010-03-30 02:56:26Z hiroshi $ *
- ***************************************************************************** */
-
-`ifdef SYN
-/* empty */
-`else
-timeunit 1ps ;
-timeprecision 1ps ;
-`endif
-// import uart_top_package:: * ;
-module uart_top
- (
- input wire clk_i, // clock
- input wire nrst_i, // reset
- input wire [15:0] adr_i, // address
- input wire [31:0] dat_i, // data input
- output wire [31:0] dat_o, // clk_rst_manager
- input wire we_i, // write enable
- input wire [3:0] sel_i, // select
- input wire stb_i, //
- output wire ack_o, // acknowledge accept
- input wire cyc_i, // cycle assrted
- output wire intr_o, //
-
- output wire stx_o,
- output wire rts_o,
- output wire dtr_o,
- input wire srx_i,
- input wire cts_i,
- input wire dsr_i,
- input wire ri_i,
- input wire dcd_i
- ) ;
-
- uart_bus uart_bus() ;
- wb_bus wb_bus() ;
-
- assign wb_bus.clk_i = clk_i ;
- assign wb_bus.nrst_i = nrst_i ;
- assign wb_bus.adr_i = adr_i ;
- assign wb_bus.dat_i = dat_i ;
- assign dat_o = wb_bus.dat_o ;
- assign wb_bus.we_i = we_i ;
- assign wb_bus.sel_i = sel_i ;
- assign wb_bus.stb_i = stb_i ;
- assign ack_o = wb_bus.ack_o ;
- assign wb_bus.cyc_i = cyc_i ;
- assign intr_o = wb_bus.intr_o ;
- assign stx_o = uart_bus.stx_o ;
- assign rts_o = uart_bus.rts_o ;
- assign dtr_o = uart_bus.dtr_o ;
-
- assign uart_bus.srx_i = srx_i ;
- assign uart_bus.cts_i = cts_i ;
- assign uart_bus.dsr_i = dsr_i ;
- assign uart_bus.ri_i = ri_i ;
- assign uart_bus.dcd_i = dcd_i ;
-
- uart_16550_rll um(.wb_bus(wb_bus.slave_mp), .uart_bus(uart_bus)) ;
-
-endmodule