URL
https://opencores.org/ocsvn/t400/t400/trunk
Subversion Repositories t400
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- This comparison shows the changes necessary to convert path
/t400
- from Rev 179 to Rev 180
- ↔ Reverse comparison
Rev 179 → Rev 180
/tags/rel_1_2/bench/vhdl/tb_t421-c.vhd
0,0 → 1,27
------------------------------------------------------------------------------- |
-- |
-- Testbench for the T421 system toplevel. |
-- |
-- $Id$ |
-- |
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration tb_t421_behav_c0 of tb_t421 is |
|
for behav |
|
for t421_b: t421 |
use configuration work.t421_struct_c0; |
end for; |
|
for tb_elems_b: tb_elems |
use configuration work.tb_elems_behav_c0; |
end for; |
|
end for; |
|
end tb_t421_behav_c0; |
tags/rel_1_2/bench/vhdl/tb_t421-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_int-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_int-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_int-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for interrupt evaluation.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_int_behav_c0 of tb_int is
+
+ for behav
+
+ for t420_b: t420
+ use configuration work.t420_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_int_behav_c0;
tags/rel_1_2/bench/vhdl/tb_int-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_pack-p.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_pack-p.vhd (revision 180)
@@ -0,0 +1,39 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_pack.pc_t;
+
+package tb_pack is
+
+ component tb_elems
+ generic (
+ period_g : time := 4.75 us;
+ d_width_g : integer := 4;
+ g_width_g : integer := 4
+ );
+ port (
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_d_i : in std_logic_vector(d_width_g-1 downto 0);
+ io_g_i : in std_logic_vector(g_width_g-1 downto 0);
+ io_in_o : out std_logic_vector(g_width_g-1 downto 0);
+ so_i : in std_logic;
+ si_o : out std_logic;
+ sk_i : in std_logic;
+ ck_o : out std_logic
+ );
+ end component;
+
+ signal tb_pc_s : pc_t;
+ signal tb_sa_s : pc_t;
+
+end tb_pack;
tags/rel_1_2/bench/vhdl/tb_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/lpm_rom.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/lpm_rom.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/lpm_rom.vhd (revision 180)
@@ -0,0 +1,437 @@
+--------------------------------------------------------------------------
+-- This VHDL file was developed by Altera Corporation. It may be
+-- freely copied and/or distributed at no cost. Any persons using this
+-- file for any purpose do so at their own risk, and are responsible for
+-- the results of such use. Altera Corporation does not guarantee that
+-- this file is complete, correct, or fit for any particular purpose.
+-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
+-- accompany any copy of this file.
+--
+--------------------------------------------------------------------------
+-- LPM Synthesizable Models (Support string type generic)
+--------------------------------------------------------------------------
+-- Version 2.0 (lpm 220) Date 01/04/00
+--
+-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
+-- read in values from LPM_FILE (*.hex) when the DATA width is greater
+-- than 16 bits.
+-- 2. Explicit sign conversions are added to standard logic vector
+-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
+-- LPM_COMPARE.
+-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
+-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
+-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
+-- 5. Fixed LPM_DIVIDE to divide correctly.
+--------------------------------------------------------------------------
+-- Version 1.9 (lpm 220) Date 11/30/99
+--
+-- 1. Fixed UNUSED file not found problem and initialization problem
+-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
+-- 2. Fixed LPM_MULT when SUM port is not used.
+-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
+-- at the same time.
+-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
+-- and counter is incrementing.
+-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
+-- simulating LPM_COUNTER.
+--------------------------------------------------------------------------
+-- Version 1.8 (lpm 220) Date 10/25/99
+--
+-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
+-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
+-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
+-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
+-- changes.
+--------------------------------------------------------------------------
+-- Version 1.7 (lpm 220) Date 07/13/99
+--
+-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
+-- Quartus behaviour and LPM220-compliant behaviour.
+--------------------------------------------------------------------------
+-- Version 1.6 (lpm 220) Date 06/15/99
+--
+-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
+-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
+-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
+-- comply with the specfication.
+-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
+-- LPM_FIFO_DC; they are all initialized to 0's.
+--------------------------------------------------------------------------
+-- Version 1.5 (lpm 220) Date 05/10/99
+--
+-- Changed LPM_MODULUS from string type to integer.
+--------------------------------------------------------------------------
+-- Version 1.4 (lpm 220) Date 02/05/99
+--
+-- 1. Added LPM_DIVIDE module.
+-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
+-- and LPM_COMPARE
+-- 3. Replaced the constants holding string with the actual string.
+--------------------------------------------------------------------------
+-- Version 1.3 Date 07/30/96
+--
+-- Modification History
+--
+-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
+-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
+-- and LPM_PVALUE
+--
+-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
+--------------------------------------------------------------------------
+-- Excluded Functions:
+--
+-- LPM_FSM and LPM_TTABLE
+--
+--------------------------------------------------------------------------
+-- Assumptions:
+--
+-- 1. All ports and signal types are std_logic or std_logic_vector
+-- from IEEE 1164 package.
+-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
+-- package are assumed to be accessible from IEEE library.
+-- 3. lpm_component_package must be accessible from library work.
+-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
+-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
+-- string "UNUSED".
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+--use work.LPM_COMPONENTS.all;
+use std.textio.all;
+
+entity LPM_ROM is
+ generic (LPM_WIDTH : positive;
+ LPM_WIDTHAD : positive;
+ LPM_NUMWORDS : natural := 0;
+ LPM_ADDRESS_CONTROL : string := "REGISTERED";
+ LPM_OUTDATA : string := "REGISTERED";
+ LPM_FILE : string;
+ LPM_TYPE : string := "LPM_ROM";
+ LPM_HINT : string := "UNUSED");
+ port (ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
+ INCLOCK : in STD_LOGIC := '0';
+ OUTCLOCK : in STD_LOGIC := '0';
+ MEMENAB : in STD_LOGIC := '1';
+ Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
+
+ function int_to_str( value : integer ) return string is
+ variable ivalue,index : integer;
+ variable digit : integer;
+ variable line_no: string(8 downto 1) := " ";
+ begin
+ ivalue := value;
+ index := 1;
+ while (ivalue > 0 ) loop
+ digit := ivalue MOD 10;
+ ivalue := ivalue/10;
+ case digit is
+ when 0 =>
+ line_no(index) := '0';
+ when 1 =>
+ line_no(index) := '1';
+ when 2 =>
+ line_no(index) := '2';
+ when 3 =>
+ line_no(index) := '3';
+ when 4 =>
+ line_no(index) := '4';
+ when 5 =>
+ line_no(index) := '5';
+ when 6 =>
+ line_no(index) := '6';
+ when 7 =>
+ line_no(index) := '7';
+ when 8 =>
+ line_no(index) := '8';
+ when 9 =>
+ line_no(index) := '9';
+ when others =>
+ ASSERT FALSE
+ REPORT "Illegal number!"
+ SEVERITY ERROR;
+ end case;
+ index := index + 1;
+ end loop;
+ return line_no;
+ end;
+
+ function hex_str_to_int( str : string ) return integer is
+ variable len : integer := str'length;
+ variable ivalue : integer := 0;
+ variable digit : integer;
+ begin
+ for i in len downto 1 loop
+ case str(i) is
+ when '0' =>
+ digit := 0;
+ when '1' =>
+ digit := 1;
+ when '2' =>
+ digit := 2;
+ when '3' =>
+ digit := 3;
+ when '4' =>
+ digit := 4;
+ when '5' =>
+ digit := 5;
+ when '6' =>
+ digit := 6;
+ when '7' =>
+ digit := 7;
+ when '8' =>
+ digit := 8;
+ when '9' =>
+ digit := 9;
+ when 'A' =>
+ digit := 10;
+ when 'a' =>
+ digit := 10;
+ when 'B' =>
+ digit := 11;
+ when 'b' =>
+ digit := 11;
+ when 'C' =>
+ digit := 12;
+ when 'c' =>
+ digit := 12;
+ when 'D' =>
+ digit := 13;
+ when 'd' =>
+ digit := 13;
+ when 'E' =>
+ digit := 14;
+ when 'e' =>
+ digit := 14;
+ when 'F' =>
+ digit := 15;
+ when 'f' =>
+ digit := 15;
+ when others =>
+ ASSERT FALSE
+ REPORT "Illegal character "& str(i) & "in Intel Hex File! "
+ SEVERITY ERROR;
+ end case;
+ ivalue := ivalue * 16 + digit;
+ end loop;
+ return ivalue;
+ end;
+
+ procedure Shrink_line(L : inout LINE; pos : in integer) is
+ subtype nstring is string(1 to pos);
+ variable stmp : nstring;
+ begin
+ if pos >= 1 then
+ read(l, stmp);
+ end if;
+ end;
+
+end LPM_ROM;
+
+architecture LPM_SYN of lpm_rom is
+
+--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
+type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
+
+signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0);
+signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
+
+begin
+
+ enable_mem: process(memenab, q2)
+ begin
+ if (memenab = '1') then
+ q <= q2;
+ else
+ q <= (OTHERS => 'Z');
+ end if;
+ end process;
+
+ sync: process(address, address_reg, q_tmp, q_reg)
+ begin
+ if (lpm_address_control = "REGISTERED") then
+ address_tmp <= address_reg;
+ else
+ address_tmp <= address;
+ end if;
+ if (lpm_outdata = "REGISTERED") then
+ q2 <= q_reg;
+ else
+ q2 <= q_tmp;
+ end if;
+ end process;
+
+ input_reg: process (inclock)
+ begin
+ if inclock'event and inclock = '1' then
+ address_reg <= address;
+ end if;
+ end process;
+
+ output_reg: process (outclock)
+ begin
+ if outclock'event and outclock = '1' then
+ q_reg <= q_tmp;
+ end if;
+ end process;
+
+ memory: process(memenab, address_tmp)
+ variable mem_data : lpm_memory;
+ variable mem_data_tmp : integer := 0;
+ variable mem_init: boolean := false;
+ variable i, j, k, lineno : integer := 0;
+ variable buf: line ;
+ variable booval: boolean ;
+ FILE mem_data_file: TEXT IS IN LPM_FILE;
+ variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
+ variable startadd: string(4 downto 1);
+ variable ibase: integer := 0;
+ variable ibyte: integer := 0;
+ variable istartadd: integer := 0;
+ variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
+ begin
+ -- INITIALIZE --
+ if NOT(mem_init) then
+ -- INITIALIZE TO 0 --
+ for i in mem_data'LOW to mem_data'HIGH loop
+ mem_data(i) := (OTHERS => '0');
+ end loop;
+
+ if (LPM_FILE = "UNUSED") then
+ ASSERT FALSE
+ REPORT "Initialization file not found!"
+ SEVERITY ERROR;
+ else
+ WHILE NOT ENDFILE(mem_data_file) loop
+ booval := true;
+ READLINE(mem_data_file, buf);
+ lineno := lineno + 1;
+ check_sum_vec := (OTHERS => '0');
+ if (buf(buf'LOW) = ':') then
+ i := 1;
+ shrink_line(buf, i);
+ READ(L=>buf, VALUE=>byte, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
+ SEVERITY ERROR;
+ end if;
+ ibyte := hex_str_to_int(byte);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, 8);
+ READ(L=>buf, VALUE=>startadd, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ istartadd := hex_str_to_int(startadd);
+ addr(2) := startadd(4);
+ addr(1) := startadd(3);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
+ addr(2) := startadd(2);
+ addr(1) := startadd(1);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
+ READ(L=>buf, VALUE=>rec_type, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
+ else
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ case rec_type is
+ when "00"=> -- Data record
+ i := 0;
+ k := lpm_width / 8;
+ if ((lpm_width MOD 8) /= 0) then
+ k := k + 1;
+ end if;
+ -- k = no. of bytes per CAM entry.
+ while (i < ibyte) loop
+ mem_data_tmp := 0;
+ for j in 1 to k loop
+ READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
+ mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
+ end loop;
+ i := i + k;
+ mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
+ istartadd := istartadd + 1;
+ end loop;
+ when "01"=>
+ exit;
+ when "02"=>
+ ibase := 0;
+ if (ibyte /= 2) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
+ SEVERITY ERROR;
+ end if;
+ for i in 0 to (ibyte-1) loop
+ READ(L=>buf, VALUE=>base,good=>booval);
+ ibase := ibase * 256 + hex_str_to_int(base);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
+ end loop;
+ ibase := ibase * 16;
+ when OTHERS =>
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
+ SEVERITY ERROR;
+ end case;
+ READ(L=>buf, VALUE=>checksum,good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
+ SEVERITY ERROR;
+ end if;
+
+ check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
+ check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum),8);
+
+ if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
+ SEVERITY ERROR;
+ end if;
+ end loop;
+ end if;
+ mem_init := TRUE;
+ end if;
+
+ -- MEMORY FUNCTION --
+ --if memenab = '1' then
+ q_tmp <= mem_data(to_integer(UNSIGNED(address_tmp)));
+ --else
+ -- q_tmp <= (OTHERS => 'Z');
+ --end if;
+ end process;
+
+end LPM_SYN;
+
+
+---------------------------------------------------------------------------
+
+
+-- pragma translate_off
+configuration lpm_rom_c0 of lpm_rom is
+
+ for lpm_syn
+ end for;
+
+end lpm_rom_c0;
+-- pragma translate_on
tags/rel_1_2/bench/vhdl/lpm_rom.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_microbus.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_microbus.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_microbus.vhd (revision 180)
@@ -0,0 +1,264 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for MICROBUS evaluation.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_microbus is
+
+end tb_microbus;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.t400_system_comp_pack.t420;
+use work.tb_pack.all;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_microbus is
+
+ -- 5 MHz clock
+ constant period_c : time := 200 ns;
+ signal ck_s : std_logic;
+ signal en_ck_s : std_logic := '0';
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(3 downto 0);
+ signal io_g_s : std_logic_vector(3 downto 0);
+ signal io_in_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal cs_n_s,
+ rd_n_s,
+ wr_n_s : std_logic;
+
+ signal tb_io_l_s : std_logic_vector(7 downto 0);
+
+begin
+
+
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t420_b : t420
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_4_c,
+ opt_microbus_g => t400_opt_microbus_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => en_ck_s,
+ reset_n_i => reset_n_s,
+ cko_i => io_in_s(2),
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s,
+ io_in_i => io_in_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+ io_in_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => tb_io_l_s,
+ io_d_i => io_d_s,
+ io_g_i => io_g_s,
+ io_in_o => open,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Process ck_div
+ --
+ -- Purpose:
+ -- Generates the en_ck_s signal from the high frequency clock.
+ --
+ ck_div: process (ck_s)
+ variable cnt_v : natural := 0;
+ begin
+ if ck_s'event and ck_s = '1' then
+ en_ck_s <= '0';
+
+ if cnt_v = 25 then
+ cnt_v := 0;
+ en_ck_s <= '1';
+ else
+ cnt_v := cnt_v + 1;
+ end if;
+ end if;
+ end process ck_div;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process microbus
+ --
+ -- Purpose:
+ -- Implements the microbus testbench element.
+ -- a) sends twelve bytes of data to the DUT
+ -- HELLO WORLD!
+ -- b) reads twelve bytes from the DUT and compares them against
+ -- the original sequence
+ --
+ microbus: process
+ procedure tb_pass_fail(pass : in boolean) is
+ begin
+ tb_io_l_s <= "00000000";
+ wait for 1 us;
+ tb_io_l_s <= "10100000";
+ wait for 1 us;
+ tb_io_l_s <= "01010000";
+ wait for 1 us;
+
+ if pass then
+ tb_io_l_s <= "00000000";
+ else
+ tb_io_l_s <= "11110000";
+ end if;
+ wait for 1 us;
+ end;
+
+ constant msg_c : string := string'("HELLO WORLD!");
+ begin
+ -- default settings
+ cs_n_s <= '1';
+ rd_n_s <= '1';
+ wr_n_s <= '1';
+ io_l_s <= (others => 'H');
+ tb_io_l_s <= (others => '0');
+
+ --
+ -- send the message string
+ --
+ for idx in msg_c'range loop
+ wait until io_g_s(0)'event and io_g_s(0) = '1';
+ if idx mod 2 = 0 then
+ -- short wait for even positions
+ wait for 1 us;
+ else
+ -- long wait for odd positions
+ wait for 1 ms;
+ end if;
+
+ io_l_s <= std_logic_vector(to_unsigned(character'pos(msg_c(idx)), 8));
+ wait for 10 ns;
+ cs_n_s <= '0';
+ wr_n_s <= '0';
+ wait for 400 ns;
+ cs_n_s <= '1';
+ wr_n_s <= '1';
+ wait for 10 ns;
+ io_l_s <= (others => 'H');
+ end loop;
+
+ --
+ -- and receive it again
+ --
+ for idx in msg_c'range loop
+ wait until io_g_s(0)'event and io_g_s(0) = '1';
+ if idx mod 2 = 0 then
+ -- short wait for even positions
+ wait for 1 us;
+ else
+ -- long wait for odd positions
+ wait for 1 ms;
+ end if;
+
+ cs_n_s <= '0';
+ rd_n_s <= '0';
+ wait for 400 ns;
+ if character'pos(msg_c(idx)) /= to_integer(unsigned(io_l_s)) then
+ tb_pass_fail(pass => false);
+ end if;
+ cs_n_s <= '1';
+ rd_n_s <= '1';
+
+ -- ack with dummy write
+ wait for 1 us;
+ cs_n_s <= '0';
+ wr_n_s <= '0';
+ wait for 400 ns;
+ cs_n_s <= '1';
+ wr_n_s <= '1';
+ end loop;
+
+ tb_pass_fail(pass => true);
+ wait;
+ end process microbus;
+ --
+ io_in_s(1) <= rd_n_s;
+ io_in_s(2) <= cs_n_s;
+ io_in_s(3) <= wr_n_s;
+ --
+ -----------------------------------------------------------------------------
+
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_microbus.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/t410_rom-lpm-a.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/t410_rom-lpm-a.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/t410_rom-lpm-a.vhd (revision 180)
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------------
+--
+-- T410 ROM wrapper for lpm_rom.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+architecture lpm of t410_rom is
+
+ component lpm_rom
+ generic (
+ LPM_WIDTH : positive;
+ LPM_WIDTHAD : positive;
+ LPM_NUMWORDS : natural := 0;
+ LPM_ADDRESS_CONTROL : string := "REGISTERED";
+ LPM_OUTDATA : string := "REGISTERED";
+ LPM_FILE : string;
+ LPM_TYPE : string := "LPM_ROM";
+ LPM_HINT : string := "UNUSED"
+ );
+ port (
+ ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
+ INCLOCK : in STD_LOGIC := '0';
+ OUTCLOCK : in STD_LOGIC := '0';
+ MEMENAB : in STD_LOGIC := '1';
+ Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
+ );
+ end component;
+
+ signal vdd_s : std_logic;
+
+begin
+
+ vdd_s <= '1';
+
+ rom_b : lpm_rom
+ generic map (
+ LPM_WIDTH => 8,
+ LPM_WIDTHAD => 9,
+ LPM_OUTDATA => "UNREGISTERED",
+ LPM_FILE => "rom_41x.hex"
+ )
+ port map (
+ ADDRESS => addr_i,
+ INCLOCK => ck_i,
+ OUTCLOCK => ck_i,
+ MEMENAB => vdd_s,
+ Q => data_o
+ );
+
+end lpm;
tags/rel_1_2/bench/vhdl/t410_rom-lpm-a.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_prod-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_prod-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_prod-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the production test.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_prod_behav_c0 of tb_prod is
+
+ for behav
+
+ for t420_b: t420
+ use configuration work.t420_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_prod_behav_c0;
tags/rel_1_2/bench/vhdl/tb_prod-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/t420_rom-lpm-a.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/t420_rom-lpm-a.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/t420_rom-lpm-a.vhd (revision 180)
@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------------
+--
+-- T420 ROM wrapper for lpm_rom.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+architecture lpm of t420_rom is
+
+ component lpm_rom
+ generic (
+ LPM_WIDTH : positive;
+ LPM_WIDTHAD : positive;
+ LPM_NUMWORDS : natural := 0;
+ LPM_ADDRESS_CONTROL : string := "REGISTERED";
+ LPM_OUTDATA : string := "REGISTERED";
+ LPM_FILE : string;
+ LPM_TYPE : string := "LPM_ROM";
+ LPM_HINT : string := "UNUSED"
+ );
+ port (
+ ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
+ INCLOCK : in STD_LOGIC := '0';
+ OUTCLOCK : in STD_LOGIC := '0';
+ MEMENAB : in STD_LOGIC := '1';
+ Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
+ );
+ end component;
+
+ signal vdd_s : std_logic;
+
+begin
+
+ vdd_s <= '1';
+
+ rom_b : lpm_rom
+ generic map (
+ LPM_WIDTH => 8,
+ LPM_WIDTHAD => 10,
+ LPM_OUTDATA => "UNREGISTERED",
+ LPM_FILE => "rom_42x.hex"
+ )
+ port map (
+ ADDRESS => addr_i,
+ INCLOCK => ck_i,
+ OUTCLOCK => ck_i,
+ MEMENAB => vdd_s,
+ Q => data_o
+ );
+
+end lpm;
tags/rel_1_2/bench/vhdl/t420_rom-lpm-a.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_elems-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_elems-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_elems-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- Generic testbench elements
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elems_behav_c0 of tb_elems is
+
+ for behav
+ end for;
+
+end tb_elems_behav_c0;
tags/rel_1_2/bench/vhdl/tb_elems-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/lpm_ram_dq.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/lpm_ram_dq.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/lpm_ram_dq.vhd (revision 180)
@@ -0,0 +1,439 @@
+--------------------------------------------------------------------------
+-- This VHDL file was developed by Altera Corporation. It may be
+-- freely copied and/or distributed at no cost. Any persons using this
+-- file for any purpose do so at their own risk, and are responsible for
+-- the results of such use. Altera Corporation does not guarantee that
+-- this file is complete, correct, or fit for any particular purpose.
+-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
+-- accompany any copy of this file.
+--
+--------------------------------------------------------------------------
+-- LPM Synthesizable Models (Support string type generic)
+--------------------------------------------------------------------------
+-- Version 2.0 (lpm 220) Date 01/04/00
+--
+-- 1. Fixed LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO and LPM_ROM to correctly
+-- read in values from LPM_FILE (*.hex) when the DATA width is greater
+-- than 16 bits.
+-- 2. Explicit sign conversions are added to standard logic vector
+-- comparisons in LPM_RAM_DQ, LPM_RAM_DP, LPM_RAM_IO, LPM_ROM, and
+-- LPM_COMPARE.
+-- 3. LPM_FIFO_DC is rewritten to have correct outputs.
+-- 4. LPM_FIFO outputs zeros when nothing has been read from it, and
+-- outputs LPM_NUMWORDS mod exp(2, LPM_WIDTHU) when it is full.
+-- 5. Fixed LPM_DIVIDE to divide correctly.
+--------------------------------------------------------------------------
+-- Version 1.9 (lpm 220) Date 11/30/99
+--
+-- 1. Fixed UNUSED file not found problem and initialization problem
+-- with LPM_RAM_DP, LPM_RAM_DQ, and LPM_RAM_IO.
+-- 2. Fixed LPM_MULT when SUM port is not used.
+-- 3. Fixed LPM_FIFO_DC to enable read when rdclock and wrclock rise
+-- at the same time.
+-- 4. Fixed LPM_COUNTER comparison problem when signed library is loaded
+-- and counter is incrementing.
+-- 5. Got rid of "Illegal Character" error message at time = 0 ns when
+-- simulating LPM_COUNTER.
+--------------------------------------------------------------------------
+-- Version 1.8 (lpm 220) Date 10/25/99
+--
+-- 1. Some LPM_PVALUE implementations were missing, and now implemented.
+-- 2. Fixed LPM_COUNTER to count correctly without conversion overflow,
+-- that is, when LPM_MODULUS = 2 ** LPM_WIDTH.
+-- 3. Fixed LPM_RAM_DP sync process sensitivity list to detect wraddress
+-- changes.
+--------------------------------------------------------------------------
+-- Version 1.7 (lpm 220) Date 07/13/99
+--
+-- Changed LPM_RAM_IO so that it can be used to simulate both MP2 and
+-- Quartus behaviour and LPM220-compliant behaviour.
+--------------------------------------------------------------------------
+-- Version 1.6 (lpm 220) Date 06/15/99
+--
+-- 1. Fixed LPM_ADD_SUB sign extension problem and subtraction bug.
+-- 2. Fixed LPM_COUNTER to use LPM_MODULUS value.
+-- 3. Added CIN and COUT port, and discarded EQ port in LPM_COUNTER to
+-- comply with the specfication.
+-- 4. Included LPM_RAM_DP, LPM_RAM_DQ, LPM_RAM_IO, LPM_ROM, LPM_FIFO, and
+-- LPM_FIFO_DC; they are all initialized to 0's.
+--------------------------------------------------------------------------
+-- Version 1.5 (lpm 220) Date 05/10/99
+--
+-- Changed LPM_MODULUS from string type to integer.
+--------------------------------------------------------------------------
+-- Version 1.4 (lpm 220) Date 02/05/99
+--
+-- 1. Added LPM_DIVIDE module.
+-- 2. Added CLKEN port to LPM_MUX, LPM_DECODE, LPM_ADD_SUB, LPM_MULT
+-- and LPM_COMPARE
+-- 3. Replaced the constants holding string with the actual string.
+--------------------------------------------------------------------------
+-- Version 1.3 Date 07/30/96
+--
+-- Modification History
+--
+-- 1. Changed the DEFAULT value to "UNUSED" for LPM_SVALUE, LPM_AVALUE,
+-- LPM_MODULUS, and LPM_NUMWORDS, LPM_HINT,LPM_STRENGTH, LPM_DIRECTION,
+-- and LPM_PVALUE
+--
+-- 2. Added the two dimentional port components (AND, OR, XOR, and MUX).
+--------------------------------------------------------------------------
+-- Excluded Functions:
+--
+-- LPM_FSM and LPM_TTABLE
+--
+--------------------------------------------------------------------------
+-- Assumptions:
+--
+-- 1. All ports and signal types are std_logic or std_logic_vector
+-- from IEEE 1164 package.
+-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
+-- package are assumed to be accessible from IEEE library.
+-- 3. lpm_component_package must be accessible from library work.
+-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
+-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
+-- string "UNUSED".
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+--use IEEE.std_logic_unsigned.all;
+use std.textio.all;
+
+entity LPM_RAM_DQ is
+ generic (LPM_WIDTH : positive;
+ LPM_WIDTHAD : positive;
+ LPM_NUMWORDS : natural := 0;
+ LPM_INDATA : string := "REGISTERED";
+ LPM_ADDRESS_CONTROL: string := "REGISTERED";
+ LPM_OUTDATA : string := "REGISTERED";
+ LPM_FILE : string := "UNUSED";
+ LPM_TYPE : string := "LPM_RAM_DQ";
+ LPM_HINT : string := "UNUSED");
+ port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
+ ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
+ INCLOCK : in std_logic := '0';
+ OUTCLOCK : in std_logic := '0';
+ WE : in std_logic;
+ Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
+
+ function int_to_str( value : integer ) return string is
+ variable ivalue,index : integer;
+ variable digit : integer;
+ variable line_no: string(8 downto 1) := " ";
+ begin
+ ivalue := value;
+ index := 1;
+ while (ivalue > 0) loop
+ digit := ivalue MOD 10;
+ ivalue := ivalue/10;
+ case digit is
+ when 0 =>
+ line_no(index) := '0';
+ when 1 =>
+ line_no(index) := '1';
+ when 2 =>
+ line_no(index) := '2';
+ when 3 =>
+ line_no(index) := '3';
+ when 4 =>
+ line_no(index) := '4';
+ when 5 =>
+ line_no(index) := '5';
+ when 6 =>
+ line_no(index) := '6';
+ when 7 =>
+ line_no(index) := '7';
+ when 8 =>
+ line_no(index) := '8';
+ when 9 =>
+ line_no(index) := '9';
+ when others =>
+ ASSERT FALSE
+ REPORT "Illegal number!"
+ SEVERITY ERROR;
+ end case;
+ index := index + 1;
+ end loop;
+ return line_no;
+ end;
+
+ function hex_str_to_int( str : string ) return integer is
+ variable len : integer := str'length;
+ variable ivalue : integer := 0;
+ variable digit : integer;
+ begin
+ for i in len downto 1 loop
+ case str(i) is
+ when '0' =>
+ digit := 0;
+ when '1' =>
+ digit := 1;
+ when '2' =>
+ digit := 2;
+ when '3' =>
+ digit := 3;
+ when '4' =>
+ digit := 4;
+ when '5' =>
+ digit := 5;
+ when '6' =>
+ digit := 6;
+ when '7' =>
+ digit := 7;
+ when '8' =>
+ digit := 8;
+ when '9' =>
+ digit := 9;
+ when 'A' =>
+ digit := 10;
+ when 'a' =>
+ digit := 10;
+ when 'B' =>
+ digit := 11;
+ when 'b' =>
+ digit := 11;
+ when 'C' =>
+ digit := 12;
+ when 'c' =>
+ digit := 12;
+ when 'D' =>
+ digit := 13;
+ when 'd' =>
+ digit := 13;
+ when 'E' =>
+ digit := 14;
+ when 'e' =>
+ digit := 14;
+ when 'F' =>
+ digit := 15;
+ when 'f' =>
+ digit := 15;
+ when others =>
+ ASSERT FALSE
+ REPORT "Illegal character "& str(i) & "in Intel Hex File! "
+ SEVERITY ERROR;
+ end case;
+ ivalue := ivalue * 16 + digit;
+ end loop;
+ return ivalue;
+ end;
+
+ procedure Shrink_line(L : inout LINE; pos : in integer) is
+ subtype nstring is string(1 to pos);
+ variable stmp : nstring;
+ begin
+ if pos >= 1 then
+ read(l, stmp);
+ end if;
+ end;
+
+end LPM_RAM_DQ;
+
+architecture LPM_SYN of lpm_ram_dq is
+
+--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
+type lpm_memory is array(integer range (2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
+
+signal data_tmp, data_reg : std_logic_vector(lpm_width-1 downto 0);
+signal q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
+signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
+signal we_tmp, we_reg : std_logic;
+
+begin
+
+ sync: process(data, data_reg, address, address_reg,
+ we, we_reg, q_tmp, q_reg)
+ begin
+ if (lpm_address_control = "REGISTERED") then
+ address_tmp <= address_reg;
+ we_tmp <= we_reg;
+ else
+ address_tmp <= address;
+ we_tmp <= we;
+ end if;
+ if (lpm_indata = "REGISTERED") then
+ data_tmp <= data_reg;
+ else
+ data_tmp <= data;
+ end if;
+ if (lpm_outdata = "REGISTERED") then
+ q <= q_reg;
+ else
+ q <= q_tmp;
+ end if;
+ end process;
+
+ input_reg: process (inclock)
+ begin
+ if inclock'event and inclock = '1' then
+ data_reg <= data;
+ address_reg <= address;
+ we_reg <= we;
+ end if;
+ end process;
+
+ output_reg: process (outclock)
+ begin
+ if outclock'event and outclock = '1' then
+ q_reg <= q_tmp;
+ end if;
+ end process;
+
+ memory: process(data_tmp, we_tmp, address_tmp)
+ variable mem_data : lpm_memory;
+ variable mem_data_tmp : integer := 0;
+ variable mem_init: boolean := false;
+ variable i,j,k,lineno: integer := 0;
+ variable buf: line ;
+ variable booval: boolean ;
+ FILE unused_file: TEXT IS OUT "UNUSED";
+ FILE mem_data_file: TEXT IS IN LPM_FILE;
+ variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
+ variable startadd: string(4 downto 1);
+ variable ibase: integer := 0;
+ variable ibyte: integer := 0;
+ variable istartadd: integer := 0;
+ variable check_sum_vec, check_sum_vec_tmp: unsigned(7 downto 0);
+ begin
+ -- INITIALIZE --
+ if NOT(mem_init) then
+ -- INITIALIZE TO 0 --
+ for i in mem_data'LOW to mem_data'HIGH loop
+ mem_data(i) := (OTHERS => '0');
+ end loop;
+
+ if (LPM_FILE = "UNUSED") then
+ ASSERT FALSE
+ REPORT "Initialization file not found!"
+ SEVERITY WARNING;
+ else
+ WHILE NOT ENDFILE(mem_data_file) loop
+ booval := true;
+ READLINE(mem_data_file, buf);
+ lineno := lineno + 1;
+ check_sum_vec := (OTHERS => '0');
+ if (buf(buf'LOW) = ':') then
+ i := 1;
+ shrink_line(buf, i);
+ READ(L=>buf, VALUE=>byte, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format!"
+ SEVERITY ERROR;
+ end if;
+ ibyte := hex_str_to_int(byte);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(ibyte, check_sum_vec'length);
+ READ(L=>buf, VALUE=>startadd, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ istartadd := hex_str_to_int(startadd);
+ addr(2) := startadd(4);
+ addr(1) := startadd(3);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
+ addr(2) := startadd(2);
+ addr(1) := startadd(1);
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(addr), check_sum_vec'length);
+ READ(L=>buf, VALUE=>rec_type, good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(rec_type), check_sum_vec'length);
+ else
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ case rec_type is
+ when "00"=> -- Data record
+ i := 0;
+ k := lpm_width / 8;
+ if ((lpm_width MOD 8) /= 0) then
+ k := k + 1;
+ end if;
+ -- k = no. of bytes per CAM entry.
+ while (i < ibyte) loop
+ mem_data_tmp := 0;
+ for j in 1 to k loop
+ READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(datain), check_sum_vec'length);
+ mem_data_tmp := mem_data_tmp * 256 + hex_str_to_int(datain);
+ end loop;
+ i := i + k;
+ mem_data(ibase + istartadd) := STD_LOGIC_VECTOR(to_unsigned(mem_data_tmp, lpm_width));
+ istartadd := istartadd + 1;
+ end loop;
+ when "01"=>
+ exit;
+ when "02"=>
+ ibase := 0;
+ if (ibyte /= 2) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format for record type 02! "
+ SEVERITY ERROR;
+ end if;
+ for i in 0 to (ibyte-1) loop
+ READ(L=>buf, VALUE=>base,good=>booval);
+ ibase := ibase * 256 + hex_str_to_int(base);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal Intel Hex Format! "
+ SEVERITY ERROR;
+ end if;
+ check_sum_vec := unsigned(check_sum_vec) + to_unsigned(hex_str_to_int(base), check_sum_vec'length);
+ end loop;
+ ibase := ibase * 16;
+ when OTHERS =>
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Illegal record type in Intel Hex File! "
+ SEVERITY ERROR;
+ end case;
+ READ(L=>buf, VALUE=>checksum,good=>booval);
+ if not (booval) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Checksum is missing! "
+ SEVERITY ERROR;
+ end if;
+
+ check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
+ check_sum_vec_tmp := to_unsigned(hex_str_to_int(checksum), check_sum_vec_tmp'length);
+
+ if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
+ ASSERT FALSE
+ REPORT "[Line "& int_to_str(lineno) & "]:Incorrect checksum!"
+ SEVERITY ERROR;
+ end if;
+ end loop;
+ end if;
+ mem_init := TRUE;
+ end if;
+
+ -- MEMORY FUNCTION --
+ if we_tmp = '1' then
+ mem_data (to_integer(unsigned(address_tmp))) := data_tmp;
+ end if;
+ q_tmp <= mem_data(to_integer(unsigned(address_tmp)));
+ end process;
+
+end LPM_SYN;
+
+
+-- pragma translate_off
+configuration lpm_ram_dq_c0 of lpm_ram_dq is
+
+ for lpm_syn
+ end for;
+
+end lpm_ram_dq_c0;
+-- pragma translate_on
tags/rel_1_2/bench/vhdl/lpm_ram_dq.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/t410_rom-lpm-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/t410_rom-lpm-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/t410_rom-lpm-c.vhd (revision 180)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- T410 ROM wrapper for lpm_rom.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t410_rom_struct_c0 of t410_rom is
+
+ for lpm
+
+ for rom_b: lpm_rom
+ use configuration work.lpm_rom_c0;
+ end for;
+
+ end for;
+
+end t410_rom_struct_c0;
tags/rel_1_2/bench/vhdl/t410_rom-lpm-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/t420_rom-lpm-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/t420_rom-lpm-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/t420_rom-lpm-c.vhd (revision 180)
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- T420 ROM wrapper for lpm_rom.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t420_rom_struct_c0 of t420_rom is
+
+ for lpm
+
+ for rom_b: lpm_rom
+ use configuration work.lpm_rom_c0;
+ end for;
+
+ end for;
+
+end t420_rom_struct_c0;
tags/rel_1_2/bench/vhdl/t420_rom-lpm-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t410.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t410.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t410.vhd (revision 180)
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T410 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_t410 is
+
+end tb_t410;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_system_comp_pack.t410;
+use work.tb_pack.tb_elems;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_t410 is
+
+ -- 210.4 kHz clock
+ constant period_c : time := 4.75 us;
+ signal ck_s : std_logic;
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(3 downto 0);
+ signal io_g_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal vdd_s : std_logic;
+
+begin
+
+
+ vdd_s <= '1';
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t410_b : t410
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_8_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => vdd_s,
+ reset_n_i => reset_n_s,
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => io_l_s,
+ io_d_i => io_d_s,
+ io_g_i => io_g_s,
+ io_in_o => open,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_t410.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t420.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t420.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t420.vhd (revision 180)
@@ -0,0 +1,131 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T420 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_t420 is
+
+end tb_t420;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_system_comp_pack.t420;
+use work.tb_pack.tb_elems;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_t420 is
+
+ -- 210.4 kHz clock
+ constant period_c : time := 4.75 us;
+ signal ck_s : std_logic;
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(3 downto 0);
+ signal io_g_s : std_logic_vector(3 downto 0);
+ signal io_in_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal vdd_s : std_logic;
+
+begin
+
+
+ vdd_s <= '1';
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t420_b : t420
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_4_c,
+ opt_cko_g => t400_opt_cko_gpi_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => vdd_s,
+ reset_n_i => reset_n_s,
+ cko_i => io_in_s(2),
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s,
+ io_in_i => io_in_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+ io_in_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => io_l_s,
+ io_d_i => io_d_s,
+ io_g_i => io_g_s,
+ io_in_o => io_in_s,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_t420.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t411.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t411.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t411.vhd (revision 180)
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T411 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_t411 is
+
+end tb_t411;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_system_comp_pack.t411;
+use work.tb_pack.tb_elems;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_t411 is
+
+ -- 210.4 kHz clock
+ constant period_c : time := 4.75 us;
+ signal ck_s : std_logic;
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(1 downto 0);
+ signal io_g_s : std_logic_vector(2 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal vdd_s : std_logic;
+
+begin
+
+
+ vdd_s <= '1';
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t411_b : t411
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_8_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => vdd_s,
+ reset_n_i => reset_n_s,
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 2,
+ g_width_g => 3
+ )
+ port map (
+ io_l_i => io_l_s,
+ io_d_i => io_d_s,
+ io_g_i => io_g_s,
+ io_in_o => open,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_t411.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_int.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_int.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_int.vhd (revision 180)
@@ -0,0 +1,191 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for interrupt evaluation.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_int is
+
+end tb_int;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.t400_system_comp_pack.t420;
+use work.tb_pack.all;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_int is
+
+ -- 210.4 kHz clock
+ constant period_c : time := 4.75 us;
+ signal ck_s : std_logic;
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(3 downto 0);
+ signal io_g_s : std_logic_vector(3 downto 0);
+ signal io_in_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal vdd_8_s : std_logic_vector(7 downto 0);
+
+begin
+
+
+ vdd_8_s <= (others => '1');
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t420_b : t420
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_4_c,
+ opt_l_out_type_3_g => t400_opt_out_type_od_c,
+ opt_l_out_type_2_g => t400_opt_out_type_od_c,
+ opt_l_out_type_1_g => t400_opt_out_type_od_c,
+ opt_l_out_type_0_g => t400_opt_out_type_od_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => vdd_8_s(0),
+ reset_n_i => reset_n_s,
+ cko_i => io_in_s(2),
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s,
+ io_in_i => io_in_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+ io_in_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => vdd_8_s,
+ io_d_i => io_d_s,
+ io_g_i => vdd_8_s(3 downto 0),
+ io_in_o => open,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Process int
+ --
+ -- Purpose:
+ -- Generates interrupts based on current PC.
+ --
+ int: process
+ variable int_v : std_logic;
+ begin
+ loop
+ wait until tb_pc_s'event;
+ -- see if we need to generate an interrupt
+ case to_integer(tb_pc_s) is
+ when 16#030# =>
+ int_v := '0';
+ when 16#0b0# =>
+ int_v := '0';
+ when 16#1b0# =>
+ int_v := '0';
+ when 16#230# =>
+ int_v := '0';
+ when 16#2b0# =>
+ int_v := '0';
+ when 16#330# =>
+ int_v := '0';
+ when 16#3b0# =>
+ int_v := '0';
+ when others =>
+ int_v := 'H';
+ end case;
+
+ io_in_s(1) <= int_v;
+
+ if int_v = '0' then
+ -- wait for appropriate interrupt active time
+ wait for period_c * 4 * 3; -- three instruction cycles
+ io_in_s(1) <= 'H';
+ end if;
+ end loop;
+ end process int;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- MUX the nibbles of SA to L
+ -----------------------------------------------------------------------------
+ io_l_s(3 downto 0) <= std_logic_vector(tb_sa_s(3 downto 0))
+ when io_g_s(1 downto 0) = "00" else
+ std_logic_vector(tb_sa_s(7 downto 4))
+ when io_g_s(1 downto 0) = "01" else
+ '0' & '0' & std_logic_vector(tb_sa_s(9 downto 8))
+ when io_g_s(1 downto 0) = "10" else
+ (others => 'H');
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_int.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t421.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t421.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t421.vhd (revision 180)
@@ -0,0 +1,130 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T421 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_t421 is
+
+end tb_t421;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_system_comp_pack.t421;
+use work.tb_pack.tb_elems;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_t421 is
+
+ -- 210.4 kHz clock
+ constant period_c : time := 4.75 us;
+ signal ck_s : std_logic;
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s : std_logic_vector(3 downto 0);
+ signal io_g_s : std_logic_vector(3 downto 0);
+ signal io_in_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal vdd_s : std_logic;
+
+begin
+
+
+ vdd_s <= '1';
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t421_b : t421
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_4_c,
+ opt_cko_g => t400_opt_cko_gpi_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => vdd_s,
+ reset_n_i => reset_n_s,
+ cko_i => io_in_s(2),
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'H');
+ io_g_s <= (others => 'H');
+ io_in_s <= (others => 'H');
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => io_l_s,
+ io_d_i => io_d_s,
+ io_g_i => io_g_s,
+ io_in_o => io_in_s,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_t421.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_microbus-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_microbus-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_microbus-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for MICROBUS evaluation.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_microbus_behav_c0 of tb_microbus is
+
+ for behav
+
+ for t420_b: t420
+ use configuration work.t420_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_microbus_behav_c0;
tags/rel_1_2/bench/vhdl/tb_microbus-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_prod.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_prod.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_prod.vhd (revision 180)
@@ -0,0 +1,444 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the production test as proposed by
+-- "Testing of COP400 Familiy Devices"
+-- National Semiconductor
+-- COP Note 7
+-- April 1991
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+entity tb_prod is
+
+end tb_prod;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.t400_system_comp_pack.t420;
+use work.tb_pack.all;
+use work.t400_opt_pack.all;
+
+architecture behav of tb_prod is
+
+ -- 5 MHz clock
+ constant period_c : time := 200 ns;
+ signal ck_s : std_logic;
+ signal en_ck_s : std_logic := '0';
+
+ signal reset_n_s : std_logic;
+
+ signal io_l_s : std_logic_vector(7 downto 0);
+ signal io_d_s,
+ d_s : std_logic_vector(3 downto 0);
+ signal exp_d_s : std_logic_vector(3 downto 0) := "0000";
+ signal io_g_s,
+ g_s : std_logic_vector(3 downto 0);
+ signal exp_g_s : std_logic_vector(3 downto 0) := "0000";
+ signal io_in_s : std_logic_vector(3 downto 0);
+
+ signal si_s,
+ so_s,
+ sk_s : std_logic;
+
+ signal cs_n_s,
+ rd_n_s,
+ wr_n_s : std_logic;
+
+ signal tb_io_l_s : std_logic_vector(7 downto 0);
+ signal disable_s : boolean := true;
+ signal pass_s : std_logic := 'L';
+ signal fail_s : std_logic := 'L';
+
+ signal vdd4_s : std_logic_vector(3 downto 0);
+
+begin
+
+ vdd4_s <= (others => '1');
+ reset_n_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- DUT
+ -----------------------------------------------------------------------------
+ t420_b : t420
+ generic map (
+ opt_ck_div_g => t400_opt_ck_div_4_c
+ )
+ port map (
+ ck_i => ck_s,
+ ck_en_i => en_ck_s,
+ reset_n_i => reset_n_s,
+ cko_i => io_in_s(2),
+ si_i => si_s,
+ so_o => so_s,
+ sk_o => sk_s,
+ io_l_b => io_l_s,
+ io_d_o => io_d_s,
+ io_g_b => io_g_s,
+ io_in_i => io_in_s
+ );
+
+ io_l_s <= (others => 'H');
+ io_d_s <= (others => 'L');
+ io_g_s <= (others => 'L');
+ io_in_s <= (others => 'H');
+
+ io_in_s <= io_g_s; -- feedthrough for production test
+
+ d_s <= to_X01(io_d_s);
+ g_s <= to_X01(io_g_s);
+
+
+ -----------------------------------------------------------------------------
+ -- Testbench elements
+ -----------------------------------------------------------------------------
+ tb_elems_b : tb_elems
+ generic map (
+ period_g => period_c,
+ d_width_g => 4,
+ g_width_g => 4
+ )
+ port map (
+ io_l_i => tb_io_l_s,
+ io_d_i => vdd4_s,
+ io_g_i => vdd4_s,
+ io_in_o => open,
+ so_i => so_s,
+ si_o => si_s,
+ sk_i => sk_s,
+ ck_o => ck_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Process ck_div
+ --
+ -- Purpose:
+ -- Generates the en_ck_s signal from the high frequency clock.
+ --
+ ck_div: process (ck_s)
+ variable cnt_v : natural := 0;
+ begin
+ if ck_s'event and ck_s = '1' then
+ en_ck_s <= '0';
+
+ if cnt_v = 25 then
+ cnt_v := 0;
+ en_ck_s <= '1';
+ else
+ cnt_v := cnt_v + 1;
+ end if;
+ end if;
+ end process ck_div;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process exp
+ --
+ -- Purpose:
+ -- Sets the expected values for D and G ports.
+ --
+ exp: process
+ procedure w_p(signal sig : in std_logic_vector) is
+ begin
+ wait until sig'event;
+ end;
+
+ procedure exp_d_p(exp : in natural) is
+ begin
+ w_p(d_s);
+ exp_d_s <= std_logic_vector(to_unsigned(exp, 4));
+ end;
+
+ procedure exp_g_p(exp : in natural) is
+ begin
+ w_p(g_s);
+ exp_g_s <= std_logic_vector(to_unsigned(exp, 4));
+ end;
+
+ begin
+ -- default settings
+ pass_s <= 'L';
+ exp_d_s <= (others => '0');
+ exp_g_s <= (others => '0');
+
+ wait for 1 us;
+ disable_s <= false;
+
+ -- G(0 > 9)
+ exp_g_p(9);
+
+ -- G(9 > 6)
+ exp_g_p(6);
+
+ -- D(0 > 13)
+ exp_d_p(13);
+
+ -- D(13 > 3)
+ exp_d_p(3);
+
+ -- D(3 > 2)
+ exp_d_p(2);
+
+ -- D(2 > 3)
+ exp_d_p(3);
+
+ -- G(6 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 8)
+ exp_g_p(8);
+
+ -- G(8 > 9)
+ exp_g_p(9);
+
+ -- G(9 > 11)
+ exp_g_p(11);
+
+ -- G(11 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 1)
+ exp_g_p(1);
+
+ -- D(2 > 0)
+ exp_d_p(0);
+
+ -- G(1 > 5)
+ exp_g_p(5);
+
+ -- D(0 > 15)
+ exp_d_p(15);
+
+ -- G(5 > 9)
+ exp_g_p(9);
+
+ -- D(15 > 0)
+ exp_d_p(0);
+
+ -- G(9 > 10)
+ exp_g_p(10);
+
+ -- G(10 > 9)
+ exp_g_p(9);
+
+ -- G(9 > 1)
+ exp_g_p(1);
+
+ -- G(1 > 4)
+ exp_g_p(4);
+
+ -- G(4 > 14)
+ exp_g_p(14);
+
+ -- G(14 > 3)
+ exp_g_p(3);
+
+ -- G(3 > 14)
+ exp_g_p(14);
+
+ -- G(14 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 9)
+ exp_g_p(9);
+
+ -- G(9 > 10)
+ exp_g_p(10);
+
+ -- G (10 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 10)
+ exp_g_p(10);
+
+ -- G(10 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 10)
+ exp_g_p(10);
+
+ -- G(10 > 0)
+ exp_g_p(0);
+
+ -- G(0 > 10)
+ exp_g_p(10);
+
+ -- G(10 > 7)
+ exp_g_p(7);
+
+ -- G(7 > 10)
+ exp_g_p(10);
+
+ -- D was at 15 before
+-- -- D(15 > 0)
+-- exp_d_p(0);
+
+ -- G(10 > 1)
+ exp_g_p(1);
+
+ -- G(1 > 0)
+ exp_g_p(0);
+
+ -- D(0 > 11)
+ exp_d_p(11);
+
+ -- G(10 > 9)
+ exp_g_p(9);
+
+ ---------------------------------------------------------------------------
+ -- RAM tests
+ --
+ for reg in 0 to 3 loop
+ exp_g_p(7);
+ exp_g_p(14);
+ exp_g_p(5);
+ exp_g_p(12);
+ exp_g_p(3);
+ exp_g_p(10);
+ exp_g_p(1);
+ exp_g_p(8);
+ exp_g_p(15);
+ exp_g_p(6);
+ exp_g_p(13);
+ exp_g_p(4);
+ exp_g_p(11);
+ exp_g_p(2);
+ exp_g_p(9);
+ exp_g_p(0);
+ end loop;
+
+ wait for 1 us;
+ if fail_s /= '1' then
+ pass_s <= '1';
+ end if;
+ wait;
+ end process exp;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process exp_d
+ --
+ -- Purpose:
+ -- Checks the expected value for the D port.
+ --
+ exp_d: process (ck_s)
+ begin
+ if disable_s then
+ fail_s <= 'L';
+ elsif ck_s'event and ck_s = '0' then
+ if d_s /= exp_d_s then
+ fail_s <= '1';
+ end if;
+ end if;
+ end process exp_d;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process exp_g
+ --
+ -- Purpose:
+ -- Checks the expected value for the G port.
+ --
+ exp_g: process (ck_s)
+ begin
+ if disable_s then
+ fail_s <= 'L';
+ elsif ck_s'event and ck_s = '0' then
+ if g_s /= exp_g_s then
+ fail_s <= '1';
+ end if;
+ end if;
+ end process exp_g;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process pass_fail
+ --
+ -- Purpose:
+ -- Collects the pass/fail signal and generates the respective sequence
+ -- on tb_io_l_s.
+ --
+ pass_fail: process
+ procedure tb_pass_fail(pass : in boolean) is
+ begin
+ tb_io_l_s <= "00000000";
+ wait for 1 us;
+ tb_io_l_s <= "10100000";
+ wait for 1 us;
+ tb_io_l_s <= "01010000";
+ wait for 1 us;
+
+ if pass then
+ tb_io_l_s <= "00000000";
+ else
+ tb_io_l_s <= "11110000";
+ end if;
+ wait for 1 us;
+ end;
+
+ begin
+ tb_io_l_s <= (others => '0');
+
+ loop
+ wait until pass_s'event or fail_s'event;
+ if fail_s = '1' then
+ tb_pass_fail(pass => false);
+ elsif pass_s = '1' then
+ tb_pass_fail(pass => true);
+ end if;
+ end loop;
+ end process pass_fail;
+ --
+ -----------------------------------------------------------------------------
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_prod.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_elems.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_elems.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_elems.vhd (revision 180)
@@ -0,0 +1,306 @@
+-------------------------------------------------------------------------------
+--
+-- Generic testbench elements
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_elems is
+
+ generic (
+ period_g : time := 4.75 us;
+ d_width_g : integer := 4;
+ g_width_g : integer := 4
+ );
+ port (
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_d_i : in std_logic_vector(d_width_g-1 downto 0);
+ io_g_i : in std_logic_vector(g_width_g-1 downto 0);
+ io_in_o : out std_logic_vector(g_width_g-1 downto 0);
+ so_i : in std_logic;
+ si_o : out std_logic;
+ sk_i : in std_logic;
+ ck_o : out std_logic
+ );
+
+end tb_elems;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture behav of tb_elems is
+
+ signal en_ck_s : std_logic;
+
+begin
+
+ en_ck_s <= 'H';
+
+ -----------------------------------------------------------------------------
+ -- Pass/fail catcher
+ -----------------------------------------------------------------------------
+ pass_fail: process (io_l_i)
+ type pass_fail_t is (IDLE,
+ GOT_0, GOT_A, GOT_5);
+ variable state_v : pass_fail_t := IDLE;
+ variable sig_v : std_logic_vector(3 downto 0);
+ begin
+ sig_v := to_X01(io_l_i(7 downto 4));
+
+ case state_v is
+ when IDLE =>
+ en_ck_s <= 'Z';
+ if sig_v = "0000" then
+ state_v := GOT_0;
+ end if;
+ when GOT_0 =>
+ if sig_v = "1010" then
+ state_v := GOT_A;
+ elsif sig_v /= "0000" then
+ state_v := IDLE;
+ end if;
+ when GOT_A =>
+ if sig_v = "0101" then
+ state_v := GOT_5;
+ elsif sig_v /= "1010" then
+ state_v := IDLE;
+ end if;
+ when GOT_5 =>
+ if sig_v = "0000" then
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS."
+ severity note;
+ elsif sig_v = "1111" then
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with FAIL."
+ severity note;
+ elsif sig_v /= "0101" then
+ state_v := IDLE;
+ end if;
+ end case;
+ end process pass_fail;
+
+
+ -----------------------------------------------------------------------------
+ -- D monitor
+ -----------------------------------------------------------------------------
+ d_moni: process (io_d_i)
+ type d_moni_t is (IDLE,
+ STEP_1, STEP_2,
+ STEP_3, STEP_4);
+ variable state_v : d_moni_t := IDLE;
+ variable sig_v : unsigned(3 downto 0);
+ begin
+ sig_v := (others => '0');
+ sig_v(io_d_i'range) := unsigned(to_X01(io_d_i));
+
+ case state_v is
+ when IDLE =>
+ en_ck_s <= 'Z';
+ if sig_v = 1 then
+ state_v := STEP_1;
+ end if;
+ when STEP_1 =>
+ if sig_v = 2 then
+ state_v := STEP_2;
+ else
+ state_v := IDLE;
+ end if;
+ when STEP_2 =>
+ if sig_v = 4 then
+ state_v := STEP_3;
+ elsif sig_v /= 0 then
+ state_v := IDLE;
+ else
+ -- sim finished for 2-bit D ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS (D-Port 2 bit)."
+ severity note;
+ end if;
+ when STEP_3 =>
+ if sig_v = 8 then
+ state_v := STEP_4;
+ elsif sig_v /= 0 then
+ state_v := IDLE;
+ else
+ -- sim finished for 3-bit D ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS (D-Port 3 bit)."
+ severity note;
+ end if;
+ when STEP_4 =>
+ if sig_v = 15 then
+ -- sim finished pass for 4-bit D ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS (D-Port 4 bit)."
+ severity note;
+ elsif sig_v = 0 then
+ -- sim finished fail for 4-bit D ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with FAIL (D-Port 4 bit)."
+ severity note;
+ else
+ state_v := IDLE;
+ end if;
+
+ when others =>
+ null;
+ end case;
+
+ end process d_moni;
+
+
+ -----------------------------------------------------------------------------
+ -- G monitor
+ -----------------------------------------------------------------------------
+ g_moni: process (io_g_i)
+ type d_moni_t is (IDLE,
+ STEP_1, STEP_2, STEP_3,
+ STEP_4);
+ variable state_v : d_moni_t := IDLE;
+ variable sig_v : unsigned(3 downto 0);
+ begin
+ sig_v := (others => '0');
+ sig_v(io_g_i'range) := unsigned(to_X01(io_g_i));
+
+ case state_v is
+ when IDLE =>
+ en_ck_s <= 'Z';
+ if sig_v = 1 then
+ state_v := STEP_1;
+ end if;
+ when STEP_1 =>
+ if sig_v = 2 then
+ state_v := STEP_2;
+ else
+ state_v := IDLE;
+ end if;
+ when STEP_2 =>
+ if sig_v = 4 then
+ state_v := STEP_3;
+ else
+ state_v := IDLE;
+ end if;
+ when STEP_3 =>
+ if sig_v = 8 then
+ state_v := STEP_4;
+ elsif sig_v /= 0 then
+ state_v := IDLE;
+ else
+ -- sim finished for 3-bit G ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS (G-Port 3 bit)."
+ severity note;
+ end if;
+ when STEP_4 =>
+ if sig_v /= 15 then
+ state_v := IDLE;
+ else
+ -- sim finished for 4-bit G ports
+ en_ck_s <= '0';
+ assert false
+ report "Simulation finished with PASS (G-Port 4 bit)."
+ severity note;
+ end if;
+
+ when others =>
+ null;
+ end case;
+
+ end process g_moni;
+
+
+ -- feed back G on IN
+ io_in_o <= io_g_i;
+
+
+ -----------------------------------------------------------------------------
+ -- SIO peer
+ -----------------------------------------------------------------------------
+ sio_peer: process
+ begin
+ si_o <= '0';
+
+ wait until io_l_i(4) = '0';
+
+ while io_l_i(4) = '0' loop
+ si_o <= so_i xor sk_i after 10 us;
+
+ wait until io_l_i'event or so_i'event or sk_i'event;
+ end loop;
+
+ -- now feed SO back to SI upon SK edge
+ loop
+ wait until sk_i'event and sk_i = '1';
+ si_o <= so_i after 10 us;
+ end loop;
+
+ wait;
+ end process sio_peer;
+
+
+ -----------------------------------------------------------------------------
+ -- Clock generator
+ -----------------------------------------------------------------------------
+ clk: process
+ begin
+ ck_o <= '0';
+ wait for period_g / 2;
+ ck_o <= '1';
+ wait for period_g / 2;
+
+ if to_X01(en_ck_s) /= '1' then
+ wait;
+ end if;
+ end process clk;
+
+end behav;
tags/rel_1_2/bench/vhdl/tb_elems.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t410-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t410-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t410-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T410 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_t410_behav_c0 of tb_t410 is
+
+ for behav
+
+ for t410_b: t410
+ use configuration work.t410_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_t410_behav_c0;
tags/rel_1_2/bench/vhdl/tb_t410-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t411-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t411-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t411-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T411 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_t411_behav_c0 of tb_t411 is
+
+ for behav
+
+ for t411_b: t411
+ use configuration work.t411_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_t411_behav_c0;
tags/rel_1_2/bench/vhdl/tb_t411-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/bench/vhdl/tb_t420-c.vhd
===================================================================
--- tags/rel_1_2/bench/vhdl/tb_t420-c.vhd (nonexistent)
+++ tags/rel_1_2/bench/vhdl/tb_t420-c.vhd (revision 180)
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- Testbench for the T420 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration tb_t420_behav_c0 of tb_t420 is
+
+ for behav
+
+ for t420_b: t420
+ use configuration work.t420_struct_c0;
+ end for;
+
+ for tb_elems_b: tb_elems
+ use configuration work.tb_elems_behav_c0;
+ end for;
+
+ end for;
+
+end tb_t420_behav_c0;
tags/rel_1_2/bench/vhdl/tb_t420-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/t400_tech_comp_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/t400_tech_comp_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/t400_tech_comp_pack-p.vhd (revision 180)
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package t400_tech_comp_pack is
+
+ component t400_por
+ generic (
+ delay_g : integer := 4;
+ cnt_width_g : integer := 2
+ );
+ port (
+ clk_i : in std_logic;
+ por_n_o : out std_logic
+ );
+ end component;
+
+ component generic_ram
+ generic (
+ addr_width_g : integer := 10;
+ data_width_g : integer := 8
+ );
+ port (
+ clk_i : in std_logic;
+ a_i : in std_logic_vector(addr_width_g-1 downto 0);
+ we_i : in std_logic;
+ d_i : in std_logic_vector(data_width_g-1 downto 0);
+ d_o : out std_logic_vector(data_width_g-1 downto 0)
+ );
+ end component;
+
+ component generic_ram_ena
+ generic (
+ addr_width_g : integer := 10;
+ data_width_g : integer := 8
+ );
+ port (
+ clk_i : in std_logic;
+ a_i : in std_logic_vector(addr_width_g-1 downto 0);
+ we_i : in std_logic;
+ ena_i : in std_logic;
+ d_i : in std_logic_vector(data_width_g-1 downto 0);
+ d_o : out std_logic_vector(data_width_g-1 downto 0)
+ );
+ end component;
+
+
+end t400_tech_comp_pack;
tags/rel_1_2/rtl/tech/t400_tech_comp_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/spartan/t400_por-c.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/spartan/t400_por-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/spartan/t400_por-c.vhd (revision 180)
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+-- $Id$
+-------------------------------------------------------------------------------
+
+configuration t400_por_rtl_c0 of t400_por is
+
+ for spartan
+ end for;
+
+end t400_por_rtl_c0;
tags/rel_1_2/rtl/tech/spartan/t400_por-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/spartan/t400_por.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/spartan/t400_por.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/spartan/t400_por.vhd (revision 180)
@@ -0,0 +1,107 @@
+-------------------------------------------------------------------------------
+--
+-- T400 Core
+--
+-- $Id$
+--
+-- Wrapper for technology dependent power-on reset circuitry.
+--
+-- Xilinx Spartan3 flavor.
+--
+-- Generate a reset upon power-on for specified number of clocks.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t400_por is
+
+ generic (
+ delay_g : integer := 4;
+ cnt_width_g : integer := 2
+ );
+ port (
+ clk_i : in std_logic;
+ por_n_o : out std_logic
+ );
+
+end t400_por;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture spartan of t400_por is
+
+ -----------------------------------------------------------------------------
+ -- According to
+ -- "XST User Guide", Chapter 6 "VHDL Language Support", "Initial Values"
+ -- XST honors the initial value assigned to a flip-flop. Simple :-)
+ --
+ signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
+ := to_unsigned(delay_g, cnt_width_g);
+ signal por_n_q : std_logic := '0';
+ --
+ -----------------------------------------------------------------------------
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process por_cnt
+ --
+ -- Purpose:
+ -- Generate a power-on reset for the specified number of clocks.
+ --
+ por_cnt: process (clk_i)
+ begin
+ if clk_i'event and clk_i = '1' then
+ if por_cnt_q = 0 then
+ por_n_q <= '1';
+ else
+ por_cnt_q <= por_cnt_q - 1;
+ end if;
+ end if;
+ end process por_cnt;
+ --
+ -----------------------------------------------------------------------------
+
+ por_n_o <= por_n_q;
+
+end spartan;
tags/rel_1_2/rtl/tech/spartan/t400_por.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/cyclone/t400_por-c.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/cyclone/t400_por-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/cyclone/t400_por-c.vhd (revision 180)
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+-- $Id$
+-------------------------------------------------------------------------------
+
+configuration t400_por_rtl_c0 of t400_por is
+
+ for cyclone
+ end for;
+
+end t400_por_rtl_c0;
tags/rel_1_2/rtl/tech/cyclone/t400_por-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/cyclone/t400_por.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/cyclone/t400_por.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/cyclone/t400_por.vhd (revision 180)
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+--
+-- T400 Core
+--
+-- $Id$
+--
+-- Wrapper for technology dependent power-on reset circuitry.
+--
+-- Altera Cyclone flavor.
+--
+-- Generate a reset upon power-on for specified number of clocks.
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t400_por is
+
+ generic (
+ delay_g : integer := 4;
+ cnt_width_g : integer := 2
+ );
+ port (
+ clk_i : in std_logic;
+ por_n_o : out std_logic
+ );
+
+end t400_por;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture cyclone of t400_por is
+
+ signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
+ -- pragma translate_off
+ -- initialize for simulation only
+ := (others => '0')
+ -- pragma translate_on
+ ;
+ signal por_n_q : std_logic
+ -- pragma translate_off
+ -- initialize for simulation only
+ := '0'
+ -- pragma translate_on
+ ;
+
+ -- Specify power-up level of por counter and por source.
+ -- Refer to "Quartus II Integrated Synthesis", section "Altera Attribute".
+ attribute altera_attribute : string;
+ attribute altera_attribute of por_cnt_q : signal is "-name POWER_UP_LEVEL LOW";
+ attribute altera_attribute of por_n_q : signal is "-name POWER_UP_LEVEL LOW";
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process por_cnt
+ --
+ -- Purpose:
+ -- Generate a power-on reset for the specifiec number of clocks.
+ --
+ por_cnt: process (clk_i)
+ begin
+ if clk_i'event and clk_i = '1' then
+ if por_cnt_q = delay_g-1 then
+ por_n_q <= '1';
+ else
+ por_cnt_q <= por_cnt_q + 1;
+ end if;
+ end if;
+ end process por_cnt;
+ --
+ -----------------------------------------------------------------------------
+
+ por_n_o <= por_n_q;
+
+end cyclone;
tags/rel_1_2/rtl/tech/cyclone/t400_por.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/generic/generic_ram-c.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/generic/generic_ram-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/generic/generic_ram-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- Parametrizable, generic RAM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration generic_ram_rtl_c0 of generic_ram is
+
+ for rtl
+ end for;
+
+end generic_ram_rtl_c0;
tags/rel_1_2/rtl/tech/generic/generic_ram-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/generic/generic_ram.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/generic/generic_ram.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/generic/generic_ram.vhd (revision 180)
@@ -0,0 +1,94 @@
+-------------------------------------------------------------------------------
+--
+-- Parametrizable, generic RAM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity generic_ram is
+
+ generic (
+ addr_width_g : integer := 10;
+ data_width_g : integer := 8
+ );
+ port (
+ clk_i : in std_logic;
+ a_i : in std_logic_vector(addr_width_g-1 downto 0);
+ we_i : in std_logic;
+ d_i : in std_logic_vector(data_width_g-1 downto 0);
+ d_o : out std_logic_vector(data_width_g-1 downto 0)
+ );
+
+end generic_ram;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of generic_ram is
+
+ type mem_t is array (natural range 0 to 2**addr_width_g-1) of
+ std_logic_vector(d_i'range);
+ signal mem_q : mem_t
+ -- pragma translate_off
+ := (others => (others => '0'))
+ -- pragma translate_on
+ ;
+
+begin
+
+ mem: process (clk_i)
+ begin
+
+ if clk_i'event and clk_i = '1' then
+ if we_i = '1' then
+ mem_q(to_integer(unsigned(a_i))) <= d_i;
+ end if;
+
+ d_o <= mem_q(to_integer(unsigned(a_i)));
+ end if;
+
+ end process mem;
+
+end rtl;
tags/rel_1_2/rtl/tech/generic/generic_ram.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/generic/generic_ram_ena-c.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/generic/generic_ram_ena-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/generic/generic_ram_ena-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- Parametrizable, generic RAM with enable.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration generic_ram_ena_rtl_c0 of generic_ram_ena is
+
+ for rtl
+ end for;
+
+end generic_ram_ena_rtl_c0;
tags/rel_1_2/rtl/tech/generic/generic_ram_ena-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/tech/generic/generic_ram_ena.vhd
===================================================================
--- tags/rel_1_2/rtl/tech/generic/generic_ram_ena.vhd (nonexistent)
+++ tags/rel_1_2/rtl/tech/generic/generic_ram_ena.vhd (revision 180)
@@ -0,0 +1,97 @@
+-------------------------------------------------------------------------------
+--
+-- Parametrizable, generic RAM with enable.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity generic_ram_ena is
+
+ generic (
+ addr_width_g : integer := 10;
+ data_width_g : integer := 8
+ );
+ port (
+ clk_i : in std_logic;
+ a_i : in std_logic_vector(addr_width_g-1 downto 0);
+ we_i : in std_logic;
+ ena_i : in std_logic;
+ d_i : in std_logic_vector(data_width_g-1 downto 0);
+ d_o : out std_logic_vector(data_width_g-1 downto 0)
+ );
+
+end generic_ram_ena;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of generic_ram_ena is
+
+ type mem_t is array (natural range 0 to 2**addr_width_g-1) of
+ std_logic_vector(d_i'range);
+ signal mem_q : mem_t
+ -- pragma translate_off
+ := (others => (others => '0'))
+ -- pragma translate_on
+ ;
+
+begin
+
+ mem: process (clk_i)
+ begin
+
+ if clk_i'event and clk_i = '1' then
+ if ena_i = '1' then
+ if we_i = '1' then
+ mem_q(to_integer(unsigned(a_i))) <= d_i;
+ end if;
+
+ d_o <= mem_q(to_integer(unsigned(a_i)));
+ end if;
+
+ end if;
+ end process mem;
+
+end rtl;
tags/rel_1_2/rtl/tech/generic/generic_ram_ena.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_in.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_in.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_in.vhd (revision 180)
@@ -0,0 +1,166 @@
+-------------------------------------------------------------------------------
+--
+-- The IN port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_pack.all;
+
+entity t400_io_in is
+
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ icyc_en_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in io_in_op_t;
+ en1_i : in std_logic;
+ -- Port Interface ---------------------------------------------------------
+ io_in_i : in dw_t;
+ in_o : out dw_t;
+ int_o : out boolean
+ );
+
+end t400_io_in;
+
+
+architecture rtl of t400_io_in is
+
+ constant idx_in3_c : natural := 2;
+ constant idx_in0_c : natural := 1;
+ constant idx_int_c : natural := 0;
+
+ type neg_edge_t is array (natural range 1 downto 0) of
+ std_logic_vector(2 downto 0);
+ signal neg_edge_q : neg_edge_t;
+ signal neg_edge_s : std_logic_vector(2 downto 0);
+
+ signal il_q : std_logic_vector(1 downto 0);
+ signal int_q,
+ int_icyc_q : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements the sequential elements.
+ --
+ seq: process (ck_i, por_i)
+ variable neg_edge_v : std_logic_vector(2 downto 0);
+ begin
+ if por_i then
+ neg_edge_q <= (others => (others => '0'));
+ il_q <= (others => '0');
+ int_q <= false;
+ int_icyc_q <= false;
+
+ elsif ck_i'event and ck_i = '1' then
+ -- negative edge detector filp-flops ------------------------------------
+ neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
+ neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
+ neg_edge_v(idx_int_c) := to_X01(io_in_i(1));
+
+ if in_en_i then
+ neg_edge_q(0) <= neg_edge_v;
+ neg_edge_q(1) <= neg_edge_q(0) or neg_edge_v;
+ end if;
+
+ -- IL latches -----------------------------------------------------------
+ if in_en_i then
+ if neg_edge_q(1)(idx_in3_c) = '1' and
+ ((neg_edge_q(0)(idx_in3_c) or neg_edge_v(idx_in3_c)) = '0') then
+ il_q(1) <= '1';
+ end if;
+ if neg_edge_q(1)(idx_in0_c) = '1' and
+ ((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
+ il_q(0) <= '1';
+ end if;
+ end if;
+
+ -- Interrupt trigger ----------------------------------------------------
+ if in_en_i then
+ if neg_edge_q(1)(idx_int_c) = '1' and
+ ((neg_edge_q(0)(idx_int_c) or neg_edge_v(idx_int_c)) = '0') then
+ int_q <= true;
+ end if;
+ end if;
+ if icyc_en_i then
+ -- delay interrupt request until end of current instruction
+ -- this ensures that the interrupt is valid for a full instruction
+ -- (i.e. the next one)
+ int_icyc_q <= int_q;
+ end if;
+
+ if ck_en_i then
+ if op_i = IOIN_INIL then
+ il_q <= (others => '0');
+ end if;
+
+ if op_i = IOIN_INTACK then
+ int_q <= false;
+ int_icyc_q <= false;
+ end if;
+ end if;
+
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ in_o <= il_q(1) & "00" & il_q(0)
+ when op_i = IOIN_INIL else
+ io_in_i;
+ int_o <= int_icyc_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_io_in.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410_notri.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410_notri.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410_notri.vhd (revision 180)
@@ -0,0 +1,227 @@
+-------------------------------------------------------------------------------
+--
+-- T410/411 controller toplevel without tri-states.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t410_notri is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+
+end t410_notri;
+
+
+use work.t400_core_comp_pack.t400_core;
+use work.t400_tech_comp_pack.t400_por;
+use work.t400_tech_comp_pack.generic_ram_ena;
+
+architecture struct of t410_notri is
+
+ component t410_rom
+ port (
+ ck_i : in std_logic;
+ addr_i : in std_logic_vector(8 downto 0);
+ data_o : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ signal por_n_s : std_logic;
+
+ signal pm_addr_s : std_logic_vector(9 downto 0);
+ signal pm_data_s : std_logic_vector(7 downto 0);
+
+ signal dm_addr_s : std_logic_vector(5 downto 0);
+ signal dm_we_s : std_logic;
+ signal dm_data_to_core_s,
+ dm_data_from_core_s : std_logic_vector(3 downto 0);
+
+ signal gnd4_s : std_logic_vector(3 downto 0);
+
+begin
+
+ gnd4_s <= (others => '0');
+
+ -----------------------------------------------------------------------------
+ -- T400 core
+ -----------------------------------------------------------------------------
+ core_b : t400_core
+ generic map (
+ opt_type_g => t400_opt_type_410_c,
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => opt_cko_g,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_microbus_g => t400_opt_no_microbus_c,
+ opt_d_out_type_3_g => opt_d_out_type_3_g,
+ opt_d_out_type_2_g => opt_d_out_type_2_g,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => opt_g_out_type_3_g,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ por_n_i => por_n_s,
+ reset_n_i => reset_n_i,
+ cko_i => cko_i,
+ pm_addr_o => pm_addr_s,
+ pm_data_i => pm_data_s,
+ dm_addr_o => dm_addr_s,
+ dm_we_o => dm_we_s,
+ dm_data_o => dm_data_from_core_s,
+ dm_data_i => dm_data_to_core_s,
+ io_l_i => io_l_i,
+ io_l_o => io_l_o,
+ io_l_en_o => io_l_en_o,
+ io_d_o => io_d_o,
+ io_d_en_o => io_d_en_o,
+ io_g_i => io_g_i,
+ io_g_o => io_g_o,
+ io_g_en_o => io_g_en_o,
+ io_in_i => gnd4_s,
+ si_i => si_i,
+ so_o => so_o,
+ so_en_o => so_en_o,
+ sk_o => sk_o,
+ sk_en_o => sk_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Program memory
+ -----------------------------------------------------------------------------
+ pmem_b : t410_rom
+ port map (
+ ck_i => ck_i,
+ addr_i => pm_addr_s(8 downto 0),
+ data_o => pm_data_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Data memory
+ -----------------------------------------------------------------------------
+ dmem_b : generic_ram_ena
+ generic map (
+ addr_width_g => 5,
+ data_width_g => 4
+ )
+ port map (
+ clk_i => ck_i,
+ a_i => dm_addr_s(4 downto 0),
+ we_i => dm_we_s,
+ ena_i => ck_en_i,
+ d_i => dm_data_from_core_s,
+ d_o => dm_data_to_core_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Power-on reset circuit
+ -----------------------------------------------------------------------------
+ por_b : t400_por
+ generic map (
+ delay_g => 4,
+ cnt_width_g => 2
+ )
+ port map (
+ clk_i => ck_i,
+ por_n_o => por_n_s
+ );
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t410_notri.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t400_system_comp_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t400_system_comp_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t400_system_comp_pack-p.vhd (revision 180)
@@ -0,0 +1,252 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+package t400_system_comp_pack is
+
+ component t410_notri
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+ end component;
+
+ component t410
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+ end component;
+
+ component t411
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(1 downto 0);
+ io_g_b : inout std_logic_vector(2 downto 0)
+ );
+ end component;
+
+ component t420_notri
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c;
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+ end component;
+
+ component t420
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+ end component;
+
+ component t421
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_8_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+ end component;
+
+end t400_system_comp_pack;
tags/rel_1_2/rtl/vhdl/system/t400_system_comp_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420_notri.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420_notri.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420_notri.vhd (revision 180)
@@ -0,0 +1,226 @@
+-------------------------------------------------------------------------------
+--
+-- T420/421 controller toplevel without tri-states.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t420_notri is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c;
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+
+end t420_notri;
+
+
+use work.t400_core_comp_pack.t400_core;
+use work.t400_tech_comp_pack.t400_por;
+use work.t400_tech_comp_pack.generic_ram_ena;
+
+architecture struct of t420_notri is
+
+ component t420_rom
+ port (
+ ck_i : in std_logic;
+ addr_i : in std_logic_vector(9 downto 0);
+ data_o : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ signal por_n_s : std_logic;
+
+ signal pm_addr_s : std_logic_vector(9 downto 0);
+ signal pm_data_s : std_logic_vector(7 downto 0);
+
+ signal dm_addr_s : std_logic_vector(5 downto 0);
+ signal dm_we_s : std_logic;
+ signal dm_data_to_core_s,
+ dm_data_from_core_s : std_logic_vector(3 downto 0);
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- T400 core
+ -----------------------------------------------------------------------------
+ core_b : t400_core
+ generic map (
+ opt_type_g => opt_type_g,
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => opt_cko_g,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_microbus_g => opt_microbus_g,
+ opt_d_out_type_3_g => opt_d_out_type_3_g,
+ opt_d_out_type_2_g => opt_d_out_type_2_g,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => opt_g_out_type_3_g,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ por_n_i => por_n_s,
+ reset_n_i => reset_n_i,
+ cko_i => cko_i,
+ pm_addr_o => pm_addr_s,
+ pm_data_i => pm_data_s,
+ dm_addr_o => dm_addr_s,
+ dm_we_o => dm_we_s,
+ dm_data_o => dm_data_from_core_s,
+ dm_data_i => dm_data_to_core_s,
+ io_l_i => io_l_i,
+ io_l_o => io_l_o,
+ io_l_en_o => io_l_en_o,
+ io_d_o => io_d_o,
+ io_d_en_o => io_d_en_o,
+ io_g_i => io_g_i,
+ io_g_o => io_g_o,
+ io_g_en_o => io_g_en_o,
+ io_in_i => io_in_i,
+ si_i => si_i,
+ so_o => so_o,
+ so_en_o => so_en_o,
+ sk_o => sk_o,
+ sk_en_o => sk_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Program memory
+ -----------------------------------------------------------------------------
+ pmem_b : t420_rom
+ port map (
+ ck_i => ck_i,
+ addr_i => pm_addr_s,
+ data_o => pm_data_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Data memory
+ -----------------------------------------------------------------------------
+ dmem_b : generic_ram_ena
+ generic map (
+ addr_width_g => 6,
+ data_width_g => 4
+ )
+ port map (
+ clk_i => ck_i,
+ a_i => dm_addr_s,
+ we_i => dm_we_s,
+ ena_i => ck_en_i,
+ d_i => dm_data_from_core_s,
+ d_o => dm_data_to_core_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Power-on reset circuit
+ -----------------------------------------------------------------------------
+ por_b : t400_por
+ generic map (
+ delay_g => 4,
+ cnt_width_g => 2
+ )
+ port map (
+ clk_i => ck_i,
+ por_n_o => por_n_s
+ );
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t420_notri.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410_rom-struct-a.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410_rom-struct-a.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410_rom-struct-a.vhd (revision 180)
@@ -0,0 +1,65 @@
+-------------------------------------------------------------------------------
+--
+-- T410/411 ROM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+architecture struct of t410_rom is
+
+ component rom_t41x
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(8 downto 0);
+ D : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+begin
+
+ rom_b : rom_t41x
+ port map (
+ Clk => ck_i,
+ A => addr_i,
+ D => data_o
+ );
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t410_rom-struct-a.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420_rom-struct-a.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420_rom-struct-a.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420_rom-struct-a.vhd (revision 180)
@@ -0,0 +1,65 @@
+-------------------------------------------------------------------------------
+--
+-- T420/421 ROM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+architecture struct of t420_rom is
+
+ component rom_t42x
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(9 downto 0);
+ D : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+begin
+
+ rom_b : rom_t42x
+ port map (
+ Clk => ck_i,
+ A => addr_i,
+ D => data_o
+ );
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t420_rom-struct-a.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410-c.vhd (revision 180)
@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+--
+-- T410 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+configuration t410_struct_c0 of t410 is
+
+ for struct
+
+ for t410_notri_b: t410_notri
+ use configuration work.t410_notri_struct_c0;
+ end for;
+
+ end for;
+
+end t410_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t410-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t411-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t411-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t411-c.vhd (revision 180)
@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+--
+-- T411 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+configuration t411_struct_c0 of t411 is
+
+ for struct
+
+ for t410_notri_b: t410_notri
+ use configuration work.t410_notri_struct_c0;
+ end for;
+
+ end for;
+
+end t411_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t411-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420-c.vhd (revision 180)
@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+--
+-- T420 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+configuration t420_struct_c0 of t420 is
+
+ for struct
+
+ for t420_notri_b: t420_notri
+ use configuration work.t420_notri_struct_c0;
+ end for;
+
+ end for;
+
+end t420_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t420-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t421-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t421-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t421-c.vhd (revision 180)
@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+--
+-- T421 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+configuration t421_struct_c0 of t421 is
+
+ for struct
+
+ for t420_notri_b: t420_notri
+ use configuration work.t420_notri_struct_c0;
+ end for;
+
+ end for;
+
+end t421_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t421-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410_notri-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410_notri-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410_notri-c.vhd (revision 180)
@@ -0,0 +1,35 @@
+-------------------------------------------------------------------------------
+--
+-- T410/411 controller toplevel without tri-states.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t410_notri_struct_c0 of t410_notri is
+
+ for struct
+
+ for core_b: t400_core
+ use configuration work.t400_core_struct_c0;
+ end for;
+
+ for pmem_b: t410_rom
+ use configuration work.t410_rom_struct_c0;
+ end for;
+
+ for dmem_b: generic_ram_ena
+ use configuration work.generic_ram_ena_rtl_c0;
+ end for;
+
+ for por_b: t400_por
+ use configuration work.t400_por_rtl_c0;
+ end for;
+
+ end for;
+
+end t410_notri_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t410_notri-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420_notri-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420_notri-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420_notri-c.vhd (revision 180)
@@ -0,0 +1,35 @@
+-------------------------------------------------------------------------------
+--
+-- T420/421 controller toplevel without tri-states.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t420_notri_struct_c0 of t420_notri is
+
+ for struct
+
+ for core_b: t400_core
+ use configuration work.t400_core_struct_c0;
+ end for;
+
+ for pmem_b: t420_rom
+ use configuration work.t420_rom_struct_c0;
+ end for;
+
+ for dmem_b: generic_ram_ena
+ use configuration work.generic_ram_ena_rtl_c0;
+ end for;
+
+ for por_b: t400_por
+ use configuration work.t400_por_rtl_c0;
+ end for;
+
+ end for;
+
+end t420_notri_struct_c0;
tags/rel_1_2/rtl/vhdl/system/t420_notri-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410_rom-e.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410_rom-e.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410_rom-e.vhd (revision 180)
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- T410/411 ROM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t410_rom is
+
+ port (
+ ck_i : in std_logic;
+ addr_i : in std_logic_vector(8 downto 0);
+ data_o : out std_logic_vector(7 downto 0)
+ );
+
+end t410_rom;
tags/rel_1_2/rtl/vhdl/system/t410_rom-e.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t410.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t410.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t410.vhd (revision 180)
@@ -0,0 +1,188 @@
+-------------------------------------------------------------------------------
+--
+-- T410 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t410 is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+
+end t410;
+
+
+use work.t400_system_comp_pack.t410_notri;
+
+architecture struct of t410 is
+
+ signal io_l_from_t410_s,
+ io_l_en_s : std_logic_vector(7 downto 0);
+ signal io_d_from_t410_s,
+ io_d_en_s : std_logic_vector(3 downto 0);
+ signal io_g_to_t410_s,
+ io_g_from_t410_s,
+ io_g_en_s : std_logic_vector(3 downto 0);
+
+ signal so_s,
+ so_en_s : std_logic;
+ signal sk_s,
+ sk_en_s : std_logic;
+
+ signal gnd_s : std_logic;
+
+begin
+
+ gnd_s <= '0';
+
+ -----------------------------------------------------------------------------
+ -- T410 without tri-states
+ -----------------------------------------------------------------------------
+ t410_notri_b : t410_notri
+ generic map (
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => t400_opt_cko_crystal_c,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_d_out_type_3_g => opt_d_out_type_3_g,
+ opt_d_out_type_2_g => opt_d_out_type_2_g,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => opt_g_out_type_3_g,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ reset_n_i => reset_n_i,
+ cko_i => gnd_s,
+ io_l_i => io_l_b,
+ io_l_o => io_l_from_t410_s,
+ io_l_en_o => io_l_en_s,
+ io_d_o => io_d_from_t410_s,
+ io_d_en_o => io_d_en_s,
+ io_g_i => io_g_b,
+ io_g_o => io_g_from_t410_s,
+ io_g_en_o => io_g_en_s,
+ si_i => si_i,
+ so_o => so_s,
+ so_en_o => so_en_s,
+ sk_o => sk_s,
+ sk_en_o => sk_en_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Tri-states for output drivers
+ -----------------------------------------------------------------------------
+ io_l_tri: for idx in 7 downto 0 generate
+ io_l_b(idx) <= io_l_from_t410_s(idx)
+ when io_l_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_d_tri: for idx in 3 downto 0 generate
+ io_d_o(idx) <= io_d_from_t410_s(idx)
+ when io_d_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_g_tri: for idx in 3 downto 0 generate
+ io_g_b(idx) <= io_g_from_t410_s(idx)
+ when io_g_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ so_o <= so_s
+ when so_en_s = '1' else
+ 'Z';
+ --
+ sk_o <= sk_s
+ when sk_en_s = '1' else
+ 'Z';
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t410.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420_rom-e.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420_rom-e.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420_rom-e.vhd (revision 180)
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- T420/421 ROM.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t420_rom is
+
+ port (
+ ck_i : in std_logic;
+ addr_i : in std_logic_vector(9 downto 0);
+ data_o : out std_logic_vector(7 downto 0)
+ );
+
+end t420_rom;
tags/rel_1_2/rtl/vhdl/system/t420_rom-e.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t411.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t411.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t411.vhd (revision 180)
@@ -0,0 +1,186 @@
+-------------------------------------------------------------------------------
+--
+-- T411 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t411 is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(1 downto 0);
+ io_g_b : inout std_logic_vector(2 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+
+end t411;
+
+
+use work.t400_system_comp_pack.t410_notri;
+
+architecture struct of t411 is
+
+ signal io_l_from_t410_s,
+ io_l_en_s : std_logic_vector(7 downto 0);
+ signal io_d_from_t410_s,
+ io_d_en_s : std_logic_vector(3 downto 0);
+ signal io_g_to_t410_s,
+ io_g_from_t410_s,
+ io_g_en_s : std_logic_vector(3 downto 0);
+
+ signal so_s,
+ so_en_s : std_logic;
+ signal sk_s,
+ sk_en_s : std_logic;
+
+ signal gnd_s : std_logic;
+
+begin
+
+ gnd_s <= '0';
+
+ -----------------------------------------------------------------------------
+ -- T411 without tri-states
+ -----------------------------------------------------------------------------
+ t410_notri_b : t410_notri
+ generic map (
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => t400_opt_cko_crystal_c,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_d_out_type_3_g => t400_opt_out_type_std_c,
+ opt_d_out_type_2_g => t400_opt_out_type_std_c,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => t400_opt_out_type_std_c,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ reset_n_i => reset_n_i,
+ cko_i => gnd_s,
+ io_l_i => io_l_b,
+ io_l_o => io_l_from_t410_s,
+ io_l_en_o => io_l_en_s,
+ io_d_o => io_d_from_t410_s,
+ io_d_en_o => io_d_en_s,
+ io_g_i => io_g_to_t410_s,
+ io_g_o => io_g_from_t410_s,
+ io_g_en_o => io_g_en_s,
+ si_i => si_i,
+ so_o => so_s,
+ so_en_o => so_en_s,
+ sk_o => sk_s,
+ sk_en_o => sk_en_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Tri-states for output drivers
+ -----------------------------------------------------------------------------
+ io_l_tri: for idx in 7 downto 0 generate
+ io_l_b(idx) <= io_l_from_t410_s(idx)
+ when io_l_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_d_tri: for idx in 1 downto 0 generate
+ io_d_o(idx) <= io_d_from_t410_s(idx)
+ when io_d_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_g_tri: for idx in 2 downto 0 generate
+ io_g_b(idx) <= io_g_from_t410_s(idx)
+ when io_g_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ io_g_to_t410_s <= io_g_from_t410_s(3) & io_g_b;
+ --
+ so_o <= so_s
+ when so_en_s = '1' else
+ 'Z';
+ --
+ sk_o <= sk_s
+ when sk_en_s = '1' else
+ 'Z';
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t411.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t420.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t420.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t420.vhd (revision 180)
@@ -0,0 +1,190 @@
+-------------------------------------------------------------------------------
+--
+-- T420 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t420 is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_8_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+
+end t420;
+
+
+use work.t400_system_comp_pack.t420_notri;
+
+architecture struct of t420 is
+
+ signal io_l_from_t420_s,
+ io_l_en_s : std_logic_vector(7 downto 0);
+ signal io_d_from_t420_s,
+ io_d_en_s : std_logic_vector(3 downto 0);
+ signal io_g_from_t420_s,
+ io_g_en_s : std_logic_vector(3 downto 0);
+
+ signal so_s,
+ so_en_s : std_logic;
+ signal sk_s,
+ sk_en_s : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- T420 without tri-states
+ -----------------------------------------------------------------------------
+ t420_notri_b : t420_notri
+ generic map (
+ opt_type_g => t400_opt_type_420_c,
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => opt_cko_g,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_microbus_g => opt_microbus_g,
+ opt_d_out_type_3_g => opt_d_out_type_3_g,
+ opt_d_out_type_2_g => opt_d_out_type_2_g,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => opt_g_out_type_3_g,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ reset_n_i => reset_n_i,
+ cko_i => cko_i,
+ io_l_i => io_l_b,
+ io_l_o => io_l_from_t420_s,
+ io_l_en_o => io_l_en_s,
+ io_d_o => io_d_from_t420_s,
+ io_d_en_o => io_d_en_s,
+ io_g_i => io_g_b,
+ io_g_o => io_g_from_t420_s,
+ io_g_en_o => io_g_en_s,
+ io_in_i => io_in_i,
+ si_i => si_i,
+ so_o => so_s,
+ so_en_o => so_en_s,
+ sk_o => sk_s,
+ sk_en_o => sk_en_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Tri-states for output drivers
+ -----------------------------------------------------------------------------
+ io_l_tri: for idx in 7 downto 0 generate
+ io_l_b(idx) <= io_l_from_t420_s(idx)
+ when io_l_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_d_tri: for idx in 3 downto 0 generate
+ io_d_o(idx) <= io_d_from_t420_s(idx)
+ when io_d_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_g_tri: for idx in 3 downto 0 generate
+ io_g_b(idx) <= io_g_from_t420_s(idx)
+ when io_g_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ so_o <= so_s
+ when so_en_s = '1' else
+ 'Z';
+ --
+ sk_o <= sk_s
+ when sk_en_s = '1' else
+ 'Z';
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t420.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/system/t421.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/system/t421.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/system/t421.vhd (revision 180)
@@ -0,0 +1,192 @@
+-------------------------------------------------------------------------------
+--
+-- T421 system toplevel.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t421 is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_8_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ io_l_b : inout std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_g_b : inout std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ sk_o : out std_logic
+ );
+
+end t421;
+
+
+use work.t400_system_comp_pack.t420_notri;
+
+architecture struct of t421 is
+
+ signal io_l_from_t420_s,
+ io_l_en_s : std_logic_vector(7 downto 0);
+ signal io_d_from_t420_s,
+ io_d_en_s : std_logic_vector(3 downto 0);
+ signal io_g_from_t420_s,
+ io_g_en_s : std_logic_vector(3 downto 0);
+
+ signal so_s,
+ so_en_s : std_logic;
+ signal sk_s,
+ sk_en_s : std_logic;
+
+ signal vdd4_s : std_logic_vector(3 downto 0);
+
+begin
+
+ vdd4_s <= (others => '1');
+
+ -----------------------------------------------------------------------------
+ -- T420 without tri-states in T421 configuration
+ -----------------------------------------------------------------------------
+ t420_notri_b : t420_notri
+ generic map (
+ opt_type_g => t400_opt_type_421_c,
+ opt_ck_div_g => opt_ck_div_g,
+ opt_cko_g => opt_cko_g,
+ opt_l_out_type_7_g => opt_l_out_type_7_g,
+ opt_l_out_type_6_g => opt_l_out_type_6_g,
+ opt_l_out_type_5_g => opt_l_out_type_5_g,
+ opt_l_out_type_4_g => opt_l_out_type_4_g,
+ opt_l_out_type_3_g => opt_l_out_type_3_g,
+ opt_l_out_type_2_g => opt_l_out_type_2_g,
+ opt_l_out_type_1_g => opt_l_out_type_1_g,
+ opt_l_out_type_0_g => opt_l_out_type_0_g,
+ opt_microbus_g => t400_opt_no_microbus_c,
+ opt_d_out_type_3_g => opt_d_out_type_3_g,
+ opt_d_out_type_2_g => opt_d_out_type_2_g,
+ opt_d_out_type_1_g => opt_d_out_type_1_g,
+ opt_d_out_type_0_g => opt_d_out_type_0_g,
+ opt_g_out_type_3_g => opt_g_out_type_3_g,
+ opt_g_out_type_2_g => opt_g_out_type_2_g,
+ opt_g_out_type_1_g => opt_g_out_type_1_g,
+ opt_g_out_type_0_g => opt_g_out_type_0_g,
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_i,
+ reset_n_i => reset_n_i,
+ cko_i => cko_i,
+ io_l_i => io_l_b,
+ io_l_o => io_l_from_t420_s,
+ io_l_en_o => io_l_en_s,
+ io_d_o => io_d_from_t420_s,
+ io_d_en_o => io_d_en_s,
+ io_g_i => io_g_b,
+ io_g_o => io_g_from_t420_s,
+ io_g_en_o => io_g_en_s,
+ io_in_i => vdd4_s,
+ si_i => si_i,
+ so_o => so_s,
+ so_en_o => so_en_s,
+ sk_o => sk_s,
+ sk_en_o => sk_en_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Tri-states for output drivers
+ -----------------------------------------------------------------------------
+ io_l_tri: for idx in 7 downto 0 generate
+ io_l_b(idx) <= io_l_from_t420_s(idx)
+ when io_l_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_d_tri: for idx in 3 downto 0 generate
+ io_d_o(idx) <= io_d_from_t420_s(idx)
+ when io_d_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ io_g_tri: for idx in 3 downto 0 generate
+ io_g_b(idx) <= io_g_from_t420_s(idx)
+ when io_g_en_s(idx) = '1' else
+ 'Z';
+ end generate;
+ --
+ so_o <= so_s
+ when so_en_s = '1' else
+ 'Z';
+ --
+ sk_o <= sk_s
+ when sk_en_s = '1' else
+ 'Z';
+
+end struct;
tags/rel_1_2/rtl/vhdl/system/t421.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_timer-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_timer-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_timer-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The timer unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_timer_rtl_c0 of t400_timer is
+
+ for rtl
+ end for;
+
+end t400_timer_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_timer-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_core_comp_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_core_comp_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_core_comp_pack-p.vhd (revision 180)
@@ -0,0 +1,72 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+package t400_core_comp_pack is
+
+ component t400_core
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c;
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ por_n_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ pm_addr_o : out std_logic_vector(9 downto 0);
+ pm_data_i : in std_logic_vector(7 downto 0);
+ dm_addr_o : out std_logic_vector(5 downto 0);
+ dm_we_o : out std_logic;
+ dm_data_o : out std_logic_vector(3 downto 0);
+ dm_data_i : in std_logic_vector(3 downto 0);
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+ end component;
+
+end t400_core_comp_pack;
tags/rel_1_2/rtl/vhdl/t400_core_comp_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_reset-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_reset-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_reset-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The reset generation unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_reset_rtl_c0 of t400_reset is
+
+ for rtl
+ end for;
+
+end t400_reset_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_reset-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The Program memory controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_pmem_ctrl_rtl_c0 of t400_pmem_ctrl is
+
+ for rtl
+ end for;
+
+end t400_pmem_ctrl_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_pack-p.vhd (revision 180)
@@ -0,0 +1,82 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package t400_io_pack is
+
+ function io_out_f(dat : in std_logic;
+ opt : in integer) return std_logic;
+
+ function io_en_f (en : in std_logic;
+ dat : in std_logic;
+ opt : in integer) return std_logic;
+
+end t400_io_pack;
+
+
+use work.t400_opt_pack.all;
+
+package body t400_io_pack is
+
+ function io_out_f(dat : in std_logic;
+ opt : in integer) return std_logic is
+ variable result_v : std_logic;
+ begin
+ result_v := '-';
+
+ case opt is
+ -- Open drain type output drivers ---------------------------------------
+ when t400_opt_out_type_od_c =>
+ result_v := '0';
+
+ -- Push/pull type output drivers ----------------------------------------
+ when t400_opt_out_type_std_c |
+ t400_opt_out_type_led_c |
+ t400_opt_out_type_pp_c =>
+ result_v := dat;
+
+ when others =>
+ null;
+ end case;
+
+ return result_v;
+ end io_out_f;
+
+
+ function io_en_f (en : in std_logic;
+ dat : in std_logic;
+ opt : in integer) return std_logic is
+ variable result_v : std_logic;
+ begin
+ result_v := '0';
+
+ case opt is
+ -- Open drain type output drivers ---------------------------------------
+ when t400_opt_out_type_od_c =>
+ if en = '1' and dat = '0' then
+ result_v := '1';
+ end if;
+
+ -- Push/pull type output drivers ----------------------------------------
+ when t400_opt_out_type_std_c |
+ t400_opt_out_type_led_c |
+ t400_opt_out_type_pp_c =>
+ result_v := en;
+
+ when others =>
+ null;
+ end case;
+
+ return result_v;
+ end io_en_f;
+
+end t400_io_pack;
tags/rel_1_2/rtl/vhdl/t400_io_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl.vhd (revision 180)
@@ -0,0 +1,244 @@
+-------------------------------------------------------------------------------
+--
+-- The Data memory controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_dmem_ctrl is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ dmem_op_i : in dmem_op_t;
+ b_op_i : in b_op_t;
+ dec_data_i : in dec_data_t;
+ a_i : in dw_t;
+ q_high_i : in dw_t;
+ b_o : out b_t;
+ -- Data Memory Interface --------------------------------------------------
+ dm_addr_o : out dm_addr_t;
+ dm_data_i : in dw_t;
+ dm_data_o : out dw_t;
+ dm_we_o : out std_logic
+ );
+
+end t400_dmem_ctrl;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_dmem_ctrl is
+
+ signal br_q : unsigned(br_range_t);
+ signal bd_q : unsigned(bd_range_t);
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process b_reg
+ --
+ -- Purpose:
+ -- Implements the B register.
+ --
+ b_reg: process (ck_i, por_i)
+ begin
+ if por_i then
+ br_q <= (others => '0');
+ bd_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ br_q <= (others => '0');
+ bd_q <= (others => '0');
+
+ elsif ck_en_i then
+ case b_op_i is
+ -- Set Bd from accumulator ------------------------------------------
+ when B_SET_BD =>
+ bd_q <= unsigned(a_i);
+
+ -- Set Br from accumulator ------------------------------------------
+ when B_SET_BR =>
+ br_q <= unsigned(a_i(1 downto 0));
+
+ -- Set Br and Bd from decoder data ----------------------------------
+ when B_SET_B =>
+ br_q <= unsigned(dec_data_i(br_range_t));
+ bd_q <= unsigned(dec_data_i(bd_range_t));
+
+ -- Set Br and Bd from decoder data, increment value for Bd ----------
+ when B_SET_B_INC =>
+ br_q <= unsigned(dec_data_i(br_range_t));
+ bd_q <= unsigned(dec_data_i(bd_range_t)) + 1;
+
+ -- XOR Br with decoder data -----------------------------------------
+ when B_XOR_BR =>
+ br_q <= br_q xor unsigned(dec_data_i(br_range_t));
+
+ -- Increment Bd -----------------------------------------------------
+ when B_INC_BD =>
+ bd_q <= bd_q + 1;
+
+ -- Increment Bd -----------------------------------------------------
+ when B_DEC_BD =>
+ bd_q <= bd_q - 1;
+
+ when others =>
+ null;
+ end case;
+
+ end if;
+ end if;
+ end process b_reg;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process data_mux
+ --
+ -- Purpose:
+ -- Multiplexes the data for writing to the memory.
+ --
+ data_mux: process (dmem_op_i,
+ br_q, bd_q,
+ a_i,
+ q_high_i,
+ dec_data_i,
+ dm_data_i,
+ ck_en_i)
+ variable dm_addr_v : dm_addr_t;
+ variable dm_data_v : dw_t;
+ variable dm_we_v : std_logic;
+ variable bd_v : std_logic_vector(2 downto 0);
+ begin
+ -- default assignment
+ dm_addr_v(br_range_t) := std_logic_vector(br_q);
+ dm_addr_v(bd_range_t) := std_logic_vector(bd_q);
+ dm_data_v := (others => '0');
+ dm_we_v := '0';
+
+ case dmem_op_i is
+ -- Read data memory, indexed by B ---------------------------------------
+ when DMEM_RB =>
+ null;
+
+ -- Write data memory, indexed by B, source is Q -------------------------
+ when DMEM_WB_SRC_Q =>
+ dm_we_v := '1';
+ dm_data_v := q_high_i;
+
+ -- Write data memory, indexed by B, source is decoder data --------------
+ when DMEM_WB_SRC_DEC =>
+ dm_we_v := '1';
+ dm_data_v := dec_data_i(bd_range_t);
+
+ -- Write data memory, indexed by B, source is accumulator ---------------
+ when DMEM_WB_SRC_A =>
+ dm_we_v := '1';
+ dm_data_v := a_i;
+
+ -- Read data memory, indexed by decoder data ----------------------------
+ when DMEM_RDEC =>
+ dm_addr_v := dec_data_i(br_range_t'high downto 0);
+
+ -- Write data memory, indexed by decoder data, source is accumulator ----
+ when DMEM_WDEC_SRC_A =>
+ dm_we_v := '1';
+ dm_addr_v := dec_data_i(br_range_t'high downto 0);
+ dm_data_v := a_i;
+
+ -- Write data memory, indexed by B, set bit -----------------------------
+ when DMEM_WB_SET_BIT =>
+ dm_we_v := '1';
+ dm_data_v := dm_data_i or dec_data_i(dw_range_t);
+
+ -- Write data memory, indexed by B, reset bit ---------------------------
+ when DMEM_WB_RES_BIT =>
+ dm_we_v := '1';
+ dm_data_v := dm_data_i and not dec_data_i(dw_range_t);
+
+ when others =>
+ null;
+ end case;
+
+ -- adjust address vector for 41xL family members
+ if opt_type_g = t400_opt_type_410_c then
+ dm_addr_v := '0' & dm_addr_v(br_range_t) &
+ dm_addr_v(bd_range_t'high-1 downto 0);
+ end if;
+
+ dm_addr_o <= dm_addr_v;
+
+ if ck_en_i then
+ dm_we_o <= dm_we_v;
+ else
+ dm_we_o <= '0';
+ end if;
+ dm_data_o <= dm_data_v;
+ end process data_mux;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ b_o(br_range_t) <= std_logic_vector(br_q);
+ b_o(bd_range_t) <= std_logic_vector(bd_q);
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_skip.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_skip.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_skip.vhd (revision 180)
@@ -0,0 +1,217 @@
+-------------------------------------------------------------------------------
+--
+-- The skip unit.
+-- Skip conditions are checked here and communicated to the decoder unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_skip is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in skip_op_t;
+ dec_data_i : in dec_data_t;
+ carry_i : in std_logic;
+ c_i : in std_logic;
+ bd_i : in dw_t;
+ is_lbi_i : in boolean;
+ skip_o : out boolean;
+ skip_lbi_o : out boolean;
+ -- Data Interface ---------------------------------------------------------
+ a_i : in dw_t;
+ m_i : in dw_t;
+ g_i : in dw_t;
+ tim_c_i : in boolean
+ );
+
+end t400_skip;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_skip is
+
+ signal skip_q,
+ skip_next_q : boolean;
+ signal skip_lbi_q : boolean;
+
+ signal skip_int_q : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process skip
+ --
+ -- Purpose:
+ -- Implements the skip logic.
+ --
+ skip: process (ck_i, por_i)
+ variable t420_type_v : boolean;
+ begin
+ if por_i then
+ skip_next_q <= false;
+ skip_q <= false;
+ skip_lbi_q <= false;
+ skip_int_q <= false;
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ skip_next_q <= false;
+ skip_q <= false;
+ skip_lbi_q <= false;
+ skip_int_q <= false;
+
+ elsif ck_en_i then
+ t420_type_v := opt_type_g = t400_opt_type_420_c;
+
+ if ck_en_i then
+ case op_i is
+ -- update skip information ----------------------------------------
+ when SKIP_UPDATE =>
+ skip_q <= skip_next_q;
+ -- also reset skip_next flag
+ skip_next_q <= false;
+
+ -- reset skip-on-lbi flag when this was not an LBI
+ if not is_lbi_i then
+ skip_lbi_q <= false;
+ end if;
+
+ -- skip always ----------------------------------------------------
+ when SKIP_NOW =>
+ skip_next_q <= true;
+
+ -- skip on carry --------------------------------------------------
+ when SKIP_CARRY =>
+ skip_next_q <= carry_i = '1';
+
+ -- skip on C ------------------------------------------------------
+ when SKIP_C =>
+ skip_next_q <= c_i = '1';
+
+ -- skip on BD underflow ------------------------------------------
+ when SKIP_BD_UFLOW =>
+ skip_next_q <= unsigned(bd_i) = 15;
+
+ -- skip on BD overflow -------------------------------------------
+ when SKIP_BD_OFLOW =>
+ skip_next_q <= unsigned(bd_i) = 0;
+
+ -- skip on LBI instruction ----------------------------------------
+ when SKIP_LBI =>
+ skip_lbi_q <= true;
+
+ -- skip on A and M equal ------------------------------------------
+ when SKIP_A_M =>
+ skip_next_q <= unsigned(a_i) = unsigned(m_i);
+
+ -- skip on G zero -------------------------------------------------
+ when SKIP_G_ZERO =>
+ skip_next_q <= unsigned(g_i) = 0;
+
+ -- skip on G bit --------------------------------------------------
+ when SKIP_G_BIT =>
+ skip_next_q <= unsigned(g_i and dec_data_i(dw_range_t)) = 0;
+
+ -- skip on M bit --------------------------------------------------
+ when SKIP_M_BIT =>
+ skip_next_q <= unsigned(m_i and dec_data_i(dw_range_t)) = 0;
+
+ -- skip on timer carry --------------------------------------------
+ when SKIP_TIMER =>
+ skip_next_q <= tim_c_i;
+ null;
+
+ -- push skip state when vectoring to interrupt routine ------------
+ when SKIP_PUSH =>
+ if t420_type_v then
+ -- save next skip flag
+ skip_int_q <= skip_next_q;
+ skip_next_q <= false;
+ -- never skip first instruction of interrupt routine
+ skip_q <= false;
+ end if;
+
+ -- pop skip state for RET from interrupt routine ------------------
+ when SKIP_POP =>
+ if t420_type_v then
+ -- push'ed info must be pop'ed to skip_next_q as pop'ing
+ -- happens during RET of interrupt routine
+ -- skip info is valid for next instruction
+ skip_next_q <= skip_int_q;
+ skip_int_q <= false;
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process skip;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ skip_o <= skip_q;
+ skip_lbi_o <= skip_lbi_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_skip.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_core-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_core-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_core-c.vhd (revision 180)
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------------
+--
+-- T400 Microcontroller Core
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_core_struct_c0 of t400_core is
+
+ for struct
+
+ for clkgen_b: t400_clkgen
+ use configuration work.t400_clkgen_rtl_c0;
+ end for;
+
+ for reset_b: t400_reset
+ use configuration work.t400_reset_rtl_c0;
+ end for;
+
+ for pmem_ctrl_b: t400_pmem_ctrl
+ use configuration work.t400_pmem_ctrl_rtl_c0;
+ end for;
+
+ for dmem_ctrl_b: t400_dmem_ctrl
+ use configuration work.t400_dmem_ctrl_rtl_c0;
+ end for;
+
+ for decoder_b: t400_decoder
+ use configuration work.t400_decoder_rtl_c0;
+ end for;
+
+ for skip_b: t400_skip
+ use configuration work.t400_skip_rtl_c0;
+ end for;
+
+ for alu_b: t400_alu
+ use configuration work.t400_alu_rtl_c0;
+ end for;
+
+ for stack_b: t400_stack
+ use configuration work.t400_stack_rtl_c0;
+ end for;
+
+ for io_l_b: t400_io_l
+ use configuration work.t400_io_l_rtl_c0;
+ end for;
+
+ for io_d_b: t400_io_d
+ use configuration work.t400_io_d_rtl_c0;
+ end for;
+
+ for io_g_b: t400_io_g
+ use configuration work.t400_io_g_rtl_c0;
+ end for;
+
+ for use_in
+ for io_in_b: t400_io_in
+ use configuration work.t400_io_in_rtl_c0;
+ end for;
+ end for;
+
+ for sio_b: t400_sio
+ use configuration work.t400_sio_rtl_c0;
+ end for;
+
+ for use_tim
+ for timer_b: t400_timer
+ use configuration work.t400_timer_rtl_c0;
+ end for;
+ end for;
+
+ end for;
+
+end t400_core_struct_c0;
tags/rel_1_2/rtl/vhdl/t400_core-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_sio-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_sio-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_sio-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The serial input/output unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_sio_rtl_c0 of t400_sio is
+
+ for rtl
+ end for;
+
+end t400_sio_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_sio-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_pack-p.vhd (revision 180)
@@ -0,0 +1,119 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package t400_pack is
+
+ -- Byte ---------------------------------------------------------------------
+ subtype byte_t is std_logic_vector(7 downto 0);
+
+ -- Data word ----------------------------------------------------------------
+ subtype dw_t is std_logic_vector(3 downto 0);
+
+ -- Misc ranges --------------------------------------------------------------
+ subtype dw_range_t is natural range dw_t'range;
+ subtype b_range_t is natural range 5 downto 0;
+ subtype br_range_t is natural range 5 downto 4;
+ subtype bd_range_t is natural range 3 downto 0;
+
+ -- B address ----------------------------------------------------------------
+ subtype b_t is std_logic_vector(b_range_t);
+ subtype br_t is std_logic_vector(br_range_t);
+ subtype bd_t is std_logic_vector(bd_range_t);
+
+
+ -- Program counter ----------------------------------------------------------
+ subtype pc_t is unsigned(9 downto 0);
+
+ -- Data memory address vector -----------------------------------------------
+ subtype dm_addr_t is std_logic_vector(5 downto 0);
+
+ -- Decoder data -------------------------------------------------------------
+ subtype dec_data_t is std_logic_vector(pc_t'range);
+
+ -- Program counter operations -----------------------------------------------
+ type pc_op_t is (PC_NONE,
+ PC_INC_PC,
+ PC_LOAD_6, PC_LOAD_7, PC_LOAD_8, PC_LOAD,
+ PC_POP,
+ PC_LOAD_A_M,
+ PC_INT);
+
+ -- Data memory controller operations ----------------------------------------
+ type dmem_op_t is (DMEM_RB,
+ DMEM_WB_SRC_Q, DMEM_WB_SRC_DEC, DMEM_WB_SRC_A,
+ DMEM_RDEC,
+ DMEM_WB_SET_BIT, DMEM_WB_RES_BIT,
+ DMEM_WDEC_SRC_A);
+ type b_op_t is (B_NONE,
+ B_SET_BD, B_SET_BR,
+ B_SET_B, B_SET_B_INC,
+ B_XOR_BR,
+ B_INC_BD,
+ B_DEC_BD);
+
+ -- Stack operations ---------------------------------------------------------
+ type stack_op_t is (STACK_NONE,
+ STACK_PUSH,
+ STACK_POP);
+
+ -- ALU operations -----------------------------------------------------------
+ type alu_op_t is (ALU_NONE,
+ ALU_CLRA,
+ ALU_LOAD_M,
+ ALU_LOAD_Q, ALU_LOAD_G, ALU_LOAD_IN, ALU_LOAD_IL,
+ ALU_LOAD_BR, ALU_LOAD_BD,
+ ALU_LOAD_SIO,
+ ALU_ADD, ALU_ADD_10, ALU_ADD_C, ALU_ADD_DEC,
+ ALU_COMP,
+ ALU_RC, ALU_SC,
+ ALU_XOR);
+
+ -- Skip operations ----------------------------------------------------------
+ type skip_op_t is (SKIP_NONE,
+ SKIP_UPDATE,
+ SKIP_NOW,
+ SKIP_CARRY, SKIP_C,
+ SKIP_BD_UFLOW, SKIP_BD_OFLOW,
+ SKIP_LBI,
+ SKIP_A_M,
+ SKIP_G_ZERO, SKIP_G_BIT,
+ SKIP_M_BIT,
+ SKIP_TIMER,
+ SKIP_PUSH, SKIP_POP);
+
+ -- IO L port operations -----------------------------------------------------
+ type io_l_op_t is (IOL_NONE,
+ IOL_LOAD_AM, IOL_LOAD_PM,
+ IOL_OUTPUT_L,
+ IOL_OUTPUT_Q);
+
+ -- IO D port operations -----------------------------------------------------
+ type io_d_op_t is (IOD_NONE,
+ IOD_LOAD);
+
+ -- IO G port operations -----------------------------------------------------
+ type io_g_op_t is (IOG_NONE,
+ IOG_LOAD_M,
+ IOG_LOAD_DEC);
+
+ -- IO IN port operations ----------------------------------------------------
+ type io_in_op_t is (IOIN_NONE,
+ IOIN_INIL,
+ IOIN_INTACK);
+
+ -- SIO operations -----------------------------------------------------------
+ type sio_op_t is (SIO_NONE,
+ SIO_LOAD);
+
+end t400_pack;
tags/rel_1_2/rtl/vhdl/t400_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_timer.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_timer.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_timer.vhd (revision 180)
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+--
+-- The timer unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_pack.all;
+
+entity t400_timer is
+
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ icyc_en_i : in boolean;
+ -- Skip Interface ---------------------------------------------------------
+ op_i : in skip_op_t;
+ c_o : out boolean
+ );
+
+end t400_timer;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_timer is
+
+ signal cnt_q : unsigned(9 downto 0);
+ signal c_q : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements the sequential elements:
+ -- * timer counter
+ -- * carry (underflow) marker flag
+ --
+ seq: process (ck_i, por_i)
+ begin
+ if por_i then
+ cnt_q <= (others => '1');
+ c_q <= false;
+
+ elsif ck_i'event and ck_i = '1' then
+ if icyc_en_i then
+ if cnt_q = 0 then
+ -- counter underflow:
+ -- * reload counter
+ -- * set marker flag
+ cnt_q <= (others => '1');
+ c_q <= true;
+ else
+ cnt_q <= cnt_q - 1;
+ end if;
+ end if;
+
+ if ck_en_i and op_i = SKIP_TIMER then
+ c_q <= false;
+ end if;
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ c_o <= c_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_timer.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_reset.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_reset.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_reset.vhd (revision 180)
@@ -0,0 +1,138 @@
+-------------------------------------------------------------------------------
+--
+-- The reset generation unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t400_reset is
+
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ icyc_en_i : in boolean;
+ por_i : in boolean;
+ -- Reset Interface --------------------------------------------------------
+ reset_n_i : in std_logic;
+ res_o : out boolean
+ );
+
+end t400_reset;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_reset is
+
+ type res_state_t is (IDLE,
+ RES1, RES2,
+ RES_ACTIVE);
+ signal res_state_q : res_state_t;
+ signal res_q : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process res_fsm
+ --
+ -- Purpose:
+ -- Implements the reset timing/controlling FSM.
+ -- User's Guide chapter 2.3 requires that reset_n_i has to be low for
+ -- at least 3 instruction cycle times until it initializes the CPU.
+ --
+ res_fsm: process (ck_i, por_i)
+ begin
+ if por_i then
+ res_state_q <= IDLE;
+ res_q <= false;
+
+ elsif ck_i'event and ck_i = '1' then
+ res_q <= false;
+ if icyc_en_i then
+ case res_state_q is
+ when IDLE =>
+ if reset_n_i = '0' then
+ res_state_q <= RES1;
+ end if;
+
+ when RES1 =>
+ if reset_n_i = '0' then
+ res_state_q <= RES2;
+ else
+ res_state_q <= IDLE;
+ end if;
+
+ when RES2 =>
+ if reset_n_i = '0' then
+ res_state_q <= RES_ACTIVE;
+ else
+ res_state_q <= IDLE;
+ end if;
+
+ when RES_ACTIVE =>
+ res_q <= true;
+ if reset_n_i = '1' then
+ res_state_q <= IDLE;
+ end if;
+
+ when others =>
+ res_state_q <= IDLE;
+
+ end case;
+
+ end if;
+
+ end if;
+ end process res_fsm;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ res_o <= res_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_reset.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl.vhd (revision 180)
@@ -0,0 +1,183 @@
+------------------------------------------------------------------------------
+--
+-- The Program memory controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_pmem_ctrl is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ a_i : in dw_t;
+ m_i : in dw_t;
+ -- Control Interface ------------------------------------------------------
+ op_i : in pc_op_t;
+ dec_data_i : in dec_data_t;
+ -- Stack Interface --------------------------------------------------------
+ pc_o : out pc_t;
+ pc_i : in pc_t;
+ -- Program Memory Interface -----------------------------------------------
+ pm_addr_o : out pc_t
+ );
+
+end t400_pmem_ctrl;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+-- pragma translate_off
+use work.tb_pack.tb_pc_s;
+-- pragma translate_on
+
+architecture rtl of t400_pmem_ctrl is
+
+ signal pc_q : pc_t;
+ signal last_pc_s : pc_t;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Determine last program counter address
+ -----------------------------------------------------------------------------
+ last_pc_s <= to_unsigned(16#1ff#, pc_t'length)
+ when opt_type_g = t400_opt_type_410_c else
+ to_unsigned(16#3ff#, pc_t'length);
+
+
+ -----------------------------------------------------------------------------
+ -- Process pc
+ --
+ -- Purpose:
+ -- Implements the program counter.
+ --
+ pc: process (ck_i, por_i)
+ begin
+ if por_i then
+ pc_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ pc_q <= (others => '0');
+
+ elsif ck_en_i then
+ -- determine PC update mode
+ case op_i is
+ -- increment program counter ----------------------------------------
+ when PC_INC_PC =>
+ if pc_q = last_pc_s then
+ -- roll over
+ pc_q <= (others => '0');
+ else
+ pc_q <= pc_q + 1;
+ end if;
+
+ -- Load lower 6 bits from program memory data -----------------------
+ when PC_LOAD_6 =>
+ pc_q(5 downto 0) <= unsigned(dec_data_i(5 downto 0));
+
+ -- Load lower 7 bits from program memory data -----------------------
+ when PC_LOAD_7 =>
+ pc_q(6 downto 0) <= unsigned(dec_data_i(6 downto 0));
+
+ -- Load lower 8 bits from program memory data -----------------------
+ when PC_LOAD_8 =>
+ pc_q(7 downto 0) <= unsigned(dec_data_i(7 downto 0));
+
+ -- Load all bits from program memory data ---------------------------
+ when PC_LOAD =>
+ pc_q <= unsigned(dec_data_i);
+
+ -- pop program counter from stack -----------------------------------
+ when PC_POP =>
+ pc_q <= pc_i;
+
+ -- update program counter for LQID instruction ----------------------
+ when PC_LOAD_A_M =>
+ pc_q(7 downto 4) <= unsigned(a_i);
+ pc_q(3 downto 0) <= unsigned(m_i);
+
+ -- load interrupt vector --------------------------------------------
+ when PC_INT =>
+ if opt_type_g = t400_opt_type_420_c then
+ -- load address 0x100, i.e. skip first instruction at
+ -- vector address 0x0ff which has to be a NOP :-)
+ pc_q <= (8 => '1', others => '0');
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+ end if;
+ end process pc;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -- pragma translate_off
+ -- instrument interrupt testbench
+ tb_pc_s <= pc_q;
+ -- pragma translate_on
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ pc_o <= pc_q;
+ pm_addr_o <= pc_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_pmem_ctrl.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_clkgen-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_clkgen-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_clkgen-c.vhd (revision 180)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- The clock generation unit.
+-- PHI1 clock and input/output clock enables are generated here.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_clkgen_rtl_c0 of t400_clkgen is
+
+ for rtl
+ end for;
+
+end t400_clkgen_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_clkgen-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_stack-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_stack-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_stack-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The stack unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_stack_rtl_c0 of t400_stack is
+
+ for rtl
+ end for;
+
+end t400_stack_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_stack-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_decoder-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_decoder-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_decoder-c.vhd (revision 180)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- The decoder unit.
+-- Implements the instruction opcodes and controls all units of the T400 core.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_decoder_rtl_c0 of t400_decoder is
+
+ for rtl
+ end for;
+
+end t400_decoder_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_decoder-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_core.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_core.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_core.vhd (revision 180)
@@ -0,0 +1,523 @@
+-------------------------------------------------------------------------------
+--
+-- T400 Microcontroller Core
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t400_core is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c;
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c;
+ opt_cko_g : integer := t400_opt_cko_crystal_c;
+ opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c;
+ opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ ck_i : in std_logic;
+ ck_en_i : in std_logic;
+ por_n_i : in std_logic;
+ reset_n_i : in std_logic;
+ cko_i : in std_logic;
+ pm_addr_o : out std_logic_vector(9 downto 0);
+ pm_data_i : in std_logic_vector(7 downto 0);
+ dm_addr_o : out std_logic_vector(5 downto 0);
+ dm_we_o : out std_logic;
+ dm_data_o : out std_logic_vector(3 downto 0);
+ dm_data_i : in std_logic_vector(3 downto 0);
+ io_l_i : in std_logic_vector(7 downto 0);
+ io_l_o : out std_logic_vector(7 downto 0);
+ io_l_en_o : out std_logic_vector(7 downto 0);
+ io_d_o : out std_logic_vector(3 downto 0);
+ io_d_en_o : out std_logic_vector(3 downto 0);
+ io_g_i : in std_logic_vector(3 downto 0);
+ io_g_o : out std_logic_vector(3 downto 0);
+ io_g_en_o : out std_logic_vector(3 downto 0);
+ io_in_i : in std_logic_vector(3 downto 0);
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+
+end t400_core;
+
+
+use work.t400_pack.all;
+use work.t400_comp_pack.all;
+
+architecture struct of t400_core is
+
+ signal ck_en_s : boolean;
+ signal por_s : boolean;
+ signal res_s : boolean;
+
+ signal phi1_s : std_logic;
+ signal out_en_s : boolean;
+ signal in_en_s : boolean;
+ signal icyc_en_s : boolean;
+
+ signal pm_addr_s : pc_t;
+
+ signal a_s : dw_t;
+ signal dec_data_s : dec_data_t;
+
+ signal pc_to_stack_s,
+ pc_from_stack_s : pc_t;
+
+ signal q_s : byte_t;
+ signal b_s : b_t;
+
+ signal c_s,
+ carry_s : std_logic;
+
+ signal sio_s : dw_t;
+
+ signal pc_op_s : pc_op_t;
+ signal stack_op_s : stack_op_t;
+ signal dmem_op_s : dmem_op_t;
+ signal b_op_s : b_op_t;
+ signal skip_op_s : skip_op_t;
+ signal alu_op_s : alu_op_t;
+ signal io_l_op_s : io_l_op_t;
+ signal io_d_op_s : io_d_op_t;
+ signal io_g_op_s : io_g_op_t;
+ signal io_in_op_s : io_in_op_t;
+ signal sio_op_s : sio_op_t;
+ signal is_lbi_s : boolean;
+ signal en_s : dw_t;
+
+ signal skip_s,
+ skip_lbi_s : boolean;
+ signal tim_c_s : boolean;
+
+ signal in_s : dw_t;
+ signal int_s : boolean;
+
+ signal io_g_s : std_logic_vector(io_g_i'range);
+
+ signal cs_n_s,
+ rd_n_s,
+ wr_n_s : std_logic;
+
+begin
+
+ ck_en_s <= ck_en_i = '1';
+ por_s <= por_n_i = '0';
+
+ io_g_s <= to_X01(io_g_i);
+
+ -----------------------------------------------------------------------------
+ -- Clock generator
+ -----------------------------------------------------------------------------
+ clkgen_b : t400_clkgen
+ generic map (
+ opt_ck_div_g => opt_ck_div_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ phi1_o => phi1_s,
+ out_en_o => out_en_s,
+ in_en_o => in_en_s,
+ icyc_en_o => icyc_en_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Reset module
+ -----------------------------------------------------------------------------
+ reset_b : t400_reset
+ port map (
+ ck_i => ck_i,
+ icyc_en_i => icyc_en_s,
+ por_i => por_s,
+ reset_n_i => reset_n_i,
+ res_o => res_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Program memory controller
+ -----------------------------------------------------------------------------
+ pmem_ctrl_b : t400_pmem_ctrl
+ generic map (
+ opt_type_g => opt_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ a_i => a_s,
+ m_i => dm_data_i,
+ op_i => pc_op_s,
+ dec_data_i => dec_data_s,
+ pc_o => pc_to_stack_s,
+ pc_i => pc_from_stack_s,
+ pm_addr_o => pm_addr_s
+ );
+ --
+ pm_addr_o <= std_logic_vector(pm_addr_s);
+
+
+ -----------------------------------------------------------------------------
+ -- Data memory controller
+ -----------------------------------------------------------------------------
+ dmem_ctrl_b : t400_dmem_ctrl
+ generic map (
+ opt_type_g => opt_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ dmem_op_i => dmem_op_s,
+ b_op_i => b_op_s,
+ dec_data_i => dec_data_s,
+ a_i => a_s,
+ q_high_i => q_s(7 downto 4),
+ b_o => b_s,
+ dm_addr_o => dm_addr_o,
+ dm_data_i => dm_data_i,
+ dm_data_o => dm_data_o,
+ dm_we_o => dm_we_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Decoder
+ -----------------------------------------------------------------------------
+ decoder_b : t400_decoder
+ generic map (
+ opt_type_g => opt_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ out_en_i => out_en_s,
+ in_en_i => in_en_s,
+ icyc_en_i => icyc_en_s,
+ pc_op_o => pc_op_s,
+ stack_op_o => stack_op_s,
+ dmem_op_o => dmem_op_s,
+ b_op_o => b_op_s,
+ skip_op_o => skip_op_s,
+ alu_op_o => alu_op_s,
+ io_l_op_o => io_l_op_s,
+ io_d_op_o => io_d_op_s,
+ io_g_op_o => io_g_op_s,
+ io_in_op_o => io_in_op_s,
+ sio_op_o => sio_op_s,
+ dec_data_o => dec_data_s,
+ en_o => en_s,
+ skip_i => skip_s,
+ skip_lbi_i => skip_lbi_s,
+ is_lbi_o => is_lbi_s,
+ int_i => int_s,
+ pm_addr_i => pm_addr_s,
+ pm_data_i => pm_data_i
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Skip logic
+ -----------------------------------------------------------------------------
+ skip_b : t400_skip
+ generic map (
+ opt_type_g => opt_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ op_i => skip_op_s,
+ dec_data_i => dec_data_s,
+ carry_i => carry_s,
+ c_i => c_s,
+ bd_i => b_s(bd_range_t),
+ is_lbi_i => is_lbi_s,
+ skip_o => skip_s,
+ skip_lbi_o => skip_lbi_s,
+ a_i => a_s,
+ m_i => dm_data_i,
+ g_i => io_g_s,
+ tim_c_i => tim_c_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- ALU
+ -----------------------------------------------------------------------------
+ alu_b : t400_alu
+ generic map (
+ opt_cko_g => opt_cko_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ cko_i => cko_i,
+ op_i => alu_op_s,
+ m_i => dm_data_i,
+ dec_data_i => dec_data_s,
+ q_low_i => q_s(3 downto 0),
+ b_i => b_s,
+ g_i => io_g_s,
+ in_i => in_s,
+ sio_i => sio_s,
+ a_o => a_s,
+ carry_o => carry_s,
+ c_o => c_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Stack module
+ -----------------------------------------------------------------------------
+ stack_b : t400_stack
+ generic map (
+ opt_type_g => opt_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ op_i => stack_op_s,
+ pc_i => pc_to_stack_s,
+ pc_o => pc_from_stack_s
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- IO L module
+ -----------------------------------------------------------------------------
+ cs_n_s <= io_in_i(2);
+ rd_n_s <= io_in_i(1);
+ wr_n_s <= io_in_i(3);
+ --
+ io_l_b : t400_io_l
+ generic map (
+ opt_out_type_7_g => opt_l_out_type_7_g,
+ opt_out_type_6_g => opt_l_out_type_6_g,
+ opt_out_type_5_g => opt_l_out_type_5_g,
+ opt_out_type_4_g => opt_l_out_type_4_g,
+ opt_out_type_3_g => opt_l_out_type_3_g,
+ opt_out_type_2_g => opt_l_out_type_2_g,
+ opt_out_type_1_g => opt_l_out_type_1_g,
+ opt_out_type_0_g => opt_l_out_type_0_g,
+ opt_microbus_g => opt_microbus_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ in_en_i => in_en_s,
+ op_i => io_l_op_s,
+ en2_i => en_s(2),
+ m_i => dm_data_i,
+ a_i => a_s,
+ pm_data_i => pm_data_i,
+ q_o => q_s,
+ cs_n_i => cs_n_s,
+ rd_n_i => rd_n_s,
+ wr_n_i => wr_n_s,
+ io_l_i => io_l_i,
+ io_l_o => io_l_o,
+ io_l_en_o => io_l_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- IO D module
+ -----------------------------------------------------------------------------
+ io_d_b : t400_io_d
+ generic map (
+ opt_out_type_3_g => opt_d_out_type_3_g,
+ opt_out_type_2_g => opt_d_out_type_2_g,
+ opt_out_type_1_g => opt_d_out_type_1_g,
+ opt_out_type_0_g => opt_d_out_type_0_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ op_i => io_d_op_s,
+ bd_i => b_s(bd_range_t),
+ io_d_o => io_d_o,
+ io_d_en_o => io_d_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- IO G module
+ -----------------------------------------------------------------------------
+ io_g_b : t400_io_g
+ generic map (
+ opt_out_type_3_g => opt_g_out_type_3_g,
+ opt_out_type_2_g => opt_g_out_type_2_g,
+ opt_out_type_1_g => opt_g_out_type_1_g,
+ opt_out_type_0_g => opt_g_out_type_0_g,
+ opt_microbus_g => opt_microbus_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ cs_n_i => cs_n_s,
+ wr_n_i => wr_n_s,
+ op_i => io_g_op_s,
+ m_i => dm_data_i,
+ dec_data_i => dec_data_s,
+ io_g_o => io_g_o,
+ io_g_en_o => io_g_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- IO IN module
+ -----------------------------------------------------------------------------
+ use_in: if opt_type_g = t400_opt_type_420_c generate
+ io_in_b : t400_io_in
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ icyc_en_i => icyc_en_s,
+ in_en_i => in_en_s,
+ op_i => io_in_op_s,
+ en1_i => en_s(1),
+ io_in_i => io_in_i,
+ in_o => in_s,
+ int_o => int_s
+ );
+ end generate;
+
+ no_in: if opt_type_g /= t400_opt_type_420_c generate
+ in_s <= (others => '0');
+ int_s <= false;
+ end generate;
+
+
+ -----------------------------------------------------------------------------
+ -- SIO module
+ -----------------------------------------------------------------------------
+ sio_b : t400_sio
+ generic map (
+ opt_so_output_type_g => opt_so_output_type_g,
+ opt_sk_output_type_g => opt_sk_output_type_g
+ )
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ res_i => res_s,
+ phi1_i => phi1_s,
+ out_en_i => out_en_s,
+ in_en_i => in_en_s,
+ op_i => sio_op_s,
+ en0_i => en_s(0),
+ en3_i => en_s(3),
+ a_i => a_s,
+ c_i => c_s,
+ sio_o => sio_s,
+ si_i => si_i,
+ so_o => so_o,
+ so_en_o => so_en_o,
+ sk_o => sk_o,
+ sk_en_o => sk_en_o
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Timer module
+ -----------------------------------------------------------------------------
+ use_tim: if opt_type_g = t400_opt_type_420_c or
+ opt_type_g = t400_opt_type_421_c generate
+ timer_b : t400_timer
+ port map (
+ ck_i => ck_i,
+ ck_en_i => ck_en_s,
+ por_i => por_s,
+ icyc_en_i => icyc_en_s,
+ op_i => skip_op_s,
+ c_o => tim_c_s
+ );
+ end generate;
+
+ notim: if opt_type_g /= t400_opt_type_420_c and
+ opt_type_g /= t400_opt_type_421_c generate
+ tim_c_s <= false;
+ end generate;
+
+end struct;
tags/rel_1_2/rtl/vhdl/t400_core.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_comp_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_comp_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_comp_pack-p.vhd (revision 180)
@@ -0,0 +1,351 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+package t400_comp_pack is
+
+ component t400_clkgen
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ -- Clock Interface ------------------------------------------------------
+ phi1_o : out std_logic;
+ out_en_o : out boolean;
+ in_en_o : out boolean;
+ icyc_en_o : out boolean
+ );
+ end component;
+
+ component t400_reset
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ icyc_en_i : in boolean;
+ -- Reset Interface ------------------------------------------------------
+ por_i : in boolean;
+ reset_n_i : in std_logic;
+ res_o : out boolean
+ );
+ end component;
+
+ component t400_stack
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ -- Stack Control Interface ----------------------------------------------
+ op_i : in stack_op_t;
+ -- Program Counter Interface --------------------------------------------
+ pc_i : in pc_t;
+ pc_o : out pc_t
+ );
+ end component;
+
+ component t400_pmem_ctrl
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ a_i : in dw_t;
+ m_i : in dw_t;
+ -- Control Interface ----------------------------------------------------
+ op_i : in pc_op_t;
+ dec_data_i : in dec_data_t;
+ -- Stack Interface ------------------------------------------------------
+ pc_o : out pc_t;
+ pc_i : in pc_t;
+ -- Program Memory Interface ---------------------------------------------
+ pm_addr_o : out pc_t
+ );
+ end component;
+
+ component t400_alu
+ generic (
+ opt_cko_g : integer := t400_opt_cko_crystal_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ cko_i : in std_logic;
+ -- Control Interface ----------------------------------------------------
+ op_i : in alu_op_t;
+ -- Data Interface -------------------------------------------------------
+ m_i : in dw_t;
+ dec_data_i : in dec_data_t;
+ q_low_i : in dw_t;
+ b_i : in b_t;
+ g_i : in dw_t;
+ in_i : in dw_t;
+ sio_i : in dw_t;
+ a_o : out dw_t;
+ carry_o : out std_logic;
+ c_o : out std_logic
+ );
+ end component;
+
+ component t400_dmem_ctrl
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ dmem_op_i : in dmem_op_t;
+ b_op_i : in b_op_t;
+ dec_data_i : in dec_data_t;
+ a_i : in dw_t;
+ q_high_i : in dw_t;
+ b_o : out b_t;
+ -- Data Memory Interface ------------------------------------------------
+ dm_addr_o : out dm_addr_t;
+ dm_data_i : in dw_t;
+ dm_data_o : out dw_t;
+ dm_we_o : out std_logic
+ );
+ end component;
+
+ component t400_decoder
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ out_en_i : in boolean;
+ in_en_i : in boolean;
+ icyc_en_i : in boolean;
+ -- Module Control Interface ---------------------------------------------
+ pc_op_o : out pc_op_t;
+ stack_op_o : out stack_op_t;
+ dmem_op_o : out dmem_op_t;
+ b_op_o : out b_op_t;
+ skip_op_o : out skip_op_t;
+ alu_op_o : out alu_op_t;
+ io_l_op_o : out io_l_op_t;
+ io_d_op_o : out io_d_op_t;
+ io_g_op_o : out io_g_op_t;
+ io_in_op_o : out io_in_op_t;
+ sio_op_o : out sio_op_t;
+ dec_data_o : out dec_data_t;
+ en_o : out dw_t;
+ -- Skip Interface -------------------------------------------------------
+ skip_i : in boolean;
+ skip_lbi_i : in boolean;
+ is_lbi_o : out boolean;
+ int_i : in boolean;
+ -- Program Memory Interface ---------------------------------------------
+ pm_addr_i : in pc_t;
+ pm_data_i : in byte_t
+ );
+ end component;
+
+ component t400_skip
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ op_i : in skip_op_t;
+ dec_data_i : in dec_data_t;
+ carry_i : in std_logic;
+ c_i : in std_logic;
+ bd_i : in dw_t;
+ is_lbi_i : in boolean;
+ skip_o : out boolean;
+ skip_lbi_o : out boolean;
+ -- Data Interface -------------------------------------------------------
+ a_i : in dw_t;
+ m_i : in dw_t;
+ g_i : in dw_t;
+ tim_c_i : in boolean
+ );
+ end component;
+
+ component t400_io_l
+ generic (
+ opt_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ op_i : in io_l_op_t;
+ en2_i : in std_logic;
+ m_i : in dw_t;
+ a_i : in dw_t;
+ pm_data_i : in byte_t;
+ q_o : out byte_t;
+ -- Microbus Interface ---------------------------------------------------
+ cs_n_i : in std_logic;
+ rd_n_i : in std_logic;
+ wr_n_i : in std_logic;
+ -- Port L Interface -----------------------------------------------------
+ io_l_i : in byte_t;
+ io_l_o : out byte_t;
+ io_l_en_o : out byte_t
+ );
+ end component;
+
+ component t400_io_d
+ generic (
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ op_i : in io_d_op_t;
+ bd_i : in bd_t;
+ -- Port D Interface -----------------------------------------------------
+ io_d_o : out dw_t;
+ io_d_en_o : out dw_t
+ );
+ end component;
+
+ component t400_io_g
+ generic (
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ cs_n_i : in std_logic;
+ wr_n_i : in std_logic;
+ -- Control Interface ----------------------------------------------------
+ op_i : in io_g_op_t;
+ m_i : in dw_t;
+ dec_data_i : in dec_data_t;
+ -- Port G Interface -----------------------------------------------------
+ io_g_o : out dw_t;
+ io_g_en_o : out dw_t
+ );
+ end component;
+
+ component t400_io_in
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ icyc_en_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ op_i : in io_in_op_t;
+ en1_i : in std_logic;
+ -- Port Interface -------------------------------------------------------
+ io_in_i : in dw_t;
+ in_o : out dw_t;
+ int_o : out boolean
+ );
+ end component;
+
+ component t400_sio
+ generic (
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ phi1_i : in std_logic;
+ out_en_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ----------------------------------------------------
+ op_i : in sio_op_t;
+ en0_i : in std_logic;
+ en3_i : in std_logic;
+ -- SIO Interface --------------------------------------------------------
+ a_i : in dw_t;
+ c_i : in std_logic;
+ sio_o : out dw_t;
+ -- Pad Interface --------------------------------------------------------
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+ end component;
+
+ component t400_timer
+ port (
+ -- System Interface -----------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ icyc_en_i : in boolean;
+ -- Skip Interface -------------------------------------------------------
+ op_i : in skip_op_t;
+ c_o : out boolean
+ );
+ end component;
+
+end t400_comp_pack;
tags/rel_1_2/rtl/vhdl/t400_comp_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_d-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_d-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_d-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The D port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_io_d_rtl_c0 of t400_io_d is
+
+ for rtl
+ end for;
+
+end t400_io_d_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_io_d-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_sio.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_sio.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_sio.vhd (revision 180)
@@ -0,0 +1,289 @@
+-------------------------------------------------------------------------------
+--
+-- The serial input/output unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_pack.all;
+use work.t400_opt_pack.all;
+
+entity t400_sio is
+
+ generic (
+ opt_so_output_type_g : integer := t400_opt_out_type_std_c;
+ opt_sk_output_type_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ phi1_i : in std_logic;
+ out_en_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in sio_op_t;
+ en0_i : in std_logic;
+ en3_i : in std_logic;
+ -- SIO Interface ----------------------------------------------------------
+ a_i : in dw_t;
+ c_i : in std_logic;
+ sio_o : out dw_t;
+ -- Pad Interface ----------------------------------------------------------
+ si_i : in std_logic;
+ so_o : out std_logic;
+ so_en_o : out std_logic;
+ sk_o : out std_logic;
+ sk_en_o : out std_logic
+ );
+
+end t400_sio;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+use work.t400_io_pack.all;
+
+architecture rtl of t400_sio is
+
+ signal si_q : std_logic;
+ type si_flt_t is (SI_LOW_0, SI_LOW_1,
+ SI_HIGH_0, SI_HIGH_1);
+ signal si_flt_s,
+ si_flt_q : si_flt_t;
+ signal si_0_ok_s,
+ si_1_ok_s : boolean;
+ signal si_0_ok_q,
+ si_1_ok_q : boolean;
+ signal dec_sio_s : boolean;
+
+ signal new_sio_s,
+ sio_q : unsigned(dw_range_t);
+ signal skl_q : std_logic;
+ signal phi1_en_q : std_logic;
+
+ signal so_s,
+ sk_s : std_logic;
+
+ signal vdd_s : std_logic;
+
+begin
+
+ vdd_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements the sequential elements.
+ --
+ seq: process (ck_i, por_i)
+ begin
+ if por_i then
+ sio_q <= (others => '0');
+ skl_q <= '1';
+ phi1_en_q <= '1';
+ si_q <= '1';
+ si_flt_q <= SI_LOW_0;
+ si_0_ok_q <= false;
+ si_1_ok_q <= false;
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ skl_q <= '1';
+ phi1_en_q <= '1';
+ else
+ if in_en_i then
+ -- sample asynchronous SI input
+ si_q <= si_i;
+ end if;
+
+ if out_en_i then
+ -- SI filter FSM
+ si_flt_q <= si_flt_s;
+ -- SI low/high markers
+ si_0_ok_q <= si_0_ok_s;
+ si_1_ok_q <= si_1_ok_s;
+ end if;
+
+ -- SIO shift register / counter
+ if op_i = SIO_LOAD and ck_en_i then
+ -- parallel update has priority
+ sio_q <= unsigned(a_i);
+ skl_q <= c_i;
+
+ else
+ sio_q <= new_sio_s;
+ end if;
+
+ if ck_en_i then
+ -- delay enable of PHI1 by one clock cycle
+ -- this prevents glitches on sk_o when enabling/disabling
+ -- sk_o as a clock output
+ phi1_en_q <= skl_q;
+ end if;
+
+ end if;
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process new_sio
+ --
+ -- Purpose:
+ -- Calculates the new value of SIO.
+ -- Splitting this from the sequential process is required to deliver
+ -- the transient new value of SIO to sio_o upon reading SIO.
+ --
+ new_sio: process (out_en_i,
+ en0_i,
+ sio_q,
+ si_q,
+ dec_sio_s)
+ begin
+ -- default value
+ new_sio_s <= sio_q;
+
+ if out_en_i then
+ if en0_i = '0' then
+ -- shift register mode
+ new_sio_s(3 downto 1) <= sio_q(2 downto 0);
+ new_sio_s(0) <= si_q;
+
+ else
+ -- counter mode
+ if dec_sio_s then
+ new_sio_s <= sio_q - 1;
+ end if;
+
+ end if;
+ end if;
+ end process new_sio;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process si_sample
+ --
+ -- Purpose:
+ -- Implements the low pass filter on SI for low and high levels.
+ --
+ si_sample: process (si_q,
+ si_flt_q,
+ si_0_ok_q, si_1_ok_q)
+ begin
+ -- default assignments
+ si_flt_s <= si_flt_q;
+ si_0_ok_s <= si_0_ok_q;
+ si_1_ok_s <= si_1_ok_q;
+ dec_sio_s <= false;
+
+ case si_flt_q is
+ when SI_LOW_0 =>
+ if si_q = '0' then
+ si_flt_s <= SI_LOW_1;
+ else
+ si_flt_s <= SI_HIGH_0;
+ end if;
+
+ when SI_LOW_1 =>
+ if si_q = '0' then
+ si_0_ok_s <= true; -- enough '0' on SI
+
+ if not si_0_ok_q and si_1_ok_q then
+ -- decrement counter if durations of high and low phases
+ -- were long enough
+ dec_sio_s <= true;
+ end if;
+ else
+ si_flt_s <= SI_HIGH_0;
+ si_1_ok_s <= false; -- restart measuring
+ end if;
+
+ when SI_HIGH_0 =>
+ si_1_ok_s <= false; -- restart marker
+ if si_q = '1' then
+ si_flt_s <= SI_HIGH_1;
+ else
+ si_flt_s <= SI_LOW_0;
+ end if;
+
+ when SI_HIGH_1 =>
+ if si_q = '1' then
+ si_1_ok_s <= true; -- enough '1' on SI
+ else
+ si_flt_s <= SI_LOW_0;
+ si_0_ok_s <= false; -- restart measuring
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end process si_sample;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ sio_o <= std_logic_vector(new_sio_s);
+ so_s <= en3_i and (en0_i or sio_q(3));
+ sk_s <= phi1_en_q and (en0_i or phi1_i);
+ so_o <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
+ so_en_o <= io_en_f (en => vdd_s,
+ dat => so_s, opt => opt_so_output_type_g);
+ sk_o <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
+ sk_en_o <= io_en_f (en => vdd_s,
+ dat => sk_s, opt => opt_sk_output_type_g);
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_sio.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_g-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_g-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_g-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The G port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_io_g_rtl_c0 of t400_io_g is
+
+ for rtl
+ end for;
+
+end t400_io_g_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_io_g-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_opt_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_opt_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_opt_pack-p.vhd (revision 180)
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+package t400_opt_pack is
+
+ -- Chip type option ---------------------------------------------------------
+ constant t400_opt_type_420_c : integer := 0;
+ constant t400_opt_type_421_c : integer := 1;
+ constant t400_opt_type_410_c : integer := 2;
+
+ -- Clock divider option -----------------------------------------------------
+ constant t400_opt_ck_div_32_c : integer := 3;
+ constant t400_opt_ck_div_16_c : integer := 2;
+ constant t400_opt_ck_div_8_c : integer := 1;
+ constant t400_opt_ck_div_4_c : integer := 0;
+
+ -- CKO pin function option --------------------------------------------------
+ constant t400_opt_cko_crystal_c : integer := 0;
+ constant t400_opt_cko_gpi_c : integer := 1;
+
+ -- Output type option -------------------------------------------------------
+ constant t400_opt_out_type_std_c : integer := 0;
+ constant t400_opt_out_type_od_c : integer := 1;
+ constant t400_opt_out_type_led_c : integer := 2;
+ constant t400_opt_out_type_pp_c : integer := 3;
+
+ -- Microbus option ----------------------------------------------------------
+ constant t400_opt_no_microbus_c : integer := 0;
+ constant t400_opt_microbus_c : integer := 1;
+
+end t400_opt_pack;
tags/rel_1_2/rtl/vhdl/t400_opt_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_mnemonic_pack-p.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_mnemonic_pack-p.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_mnemonic_pack-p.vhd (revision 180)
@@ -0,0 +1,301 @@
+-------------------------------------------------------------------------------
+--
+-- $Id$
+--
+-- Copyright (c) 2008, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+use work.t400_pack.byte_t;
+
+package t400_mnemonic_pack is
+
+ -- Mnemonics ----------------------------------------------------------------
+ type mnemonic_t is (-- Arithmetic instructions
+ MN_ASC,
+ MN_ADD,
+ MN_ADT,
+ MN_AISC,
+ MN_CASC,
+ MN_CLRA,
+ MN_COMP,
+ MN_NOP,
+ MN_C,
+ MN_XOR,
+ -- Transfer of control instructions
+ MN_JID,
+ MN_JMP,
+ MN_JP_JSRP,
+ MN_JSR,
+ MN_RET,
+ MN_RETSK,
+ -- Memory reference instructions
+ MN_LD,
+ MN_LDD_XAD,
+ MN_LQID,
+ MN_RMB,
+ MN_SMB,
+ MN_STII,
+ MN_X,
+ MN_XDS,
+ MN_XIS,
+ -- Register reference instructions
+ MN_CAB,
+ MN_CBA,
+ MN_LBI,
+ MN_XABR,
+ -- Test instructions
+ MN_SKC,
+ MN_SKE,
+ MN_SKMBZ,
+ MN_SKT,
+ -- Input/output instructions
+ MN_EXT,
+ MN_XAS);
+
+ type mnemonic_rec_t is
+ record
+ mnemonic : mnemonic_t;
+ multi_byte : boolean;
+ end record;
+
+ function decode_opcode_f(opcode : in byte_t;
+ opt_type : in integer) return
+ mnemonic_rec_t;
+
+end t400_mnemonic_pack;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.t400_opt_type_410_c;
+
+package body t400_mnemonic_pack is
+
+ function decode_opcode_f(opcode : in byte_t;
+ opt_type : in integer) return
+ mnemonic_rec_t is
+ variable t41x_type_v : boolean;
+ variable mnemonic_v : mnemonic_t;
+ variable multi_byte_v : boolean;
+ variable result_v : mnemonic_rec_t;
+ begin
+ -- default assignment
+ mnemonic_v := MN_NOP;
+ multi_byte_v := false;
+ -- determine type
+ t41x_type_v := opt_type = t400_opt_type_410_c;
+
+ case opcode is
+ -- Mnemonic ASC----------------------------------------------------------
+ when "00110000" =>
+ mnemonic_v := MN_ASC;
+
+ -- Mnemonic ADD ---------------------------------------------------------
+ when "00110001" =>
+ mnemonic_v := MN_ADD;
+
+ -- Mnemonic ADT ---------------------------------------------------------
+ when "01001010" =>
+ if not t41x_type_v then
+ mnemonic_v := MN_ADT;
+ end if;
+
+ -- Mnemonic AISC --------------------------------------------------------
+ when "01010001" | "01010010" | "01010011" |
+ "01010100" | "01010101" | "01010110" | "01010111" |
+ "01011000" | "01011001" | "01011010" | "01011011" |
+ "01011100" | "01011101" | "01011110" | "01011111" =>
+ mnemonic_v := MN_AISC;
+
+ -- Mnemonic CASC --------------------------------------------------------
+ when "00010000" =>
+ if not t41x_type_v then
+ mnemonic_v := MN_CASC;
+ end if;
+
+ -- Mnemonic CLRA --------------------------------------------------------
+ when "00000000" =>
+ mnemonic_v := MN_CLRA;
+
+ -- Mnemonic COMP --------------------------------------------------------
+ when "01000000" =>
+ mnemonic_v := MN_COMP;
+
+ -- Mnemonic NOP ---------------------------------------------------------
+ when "01000100" =>
+ mnemonic_v := MN_NOP;
+
+ -- Mnemonic C -----------------------------------------------------------
+ when "00110010" | -- RC
+ "00100010" => -- SC
+ mnemonic_v := MN_C;
+
+ -- Mnemonic XOR ---------------------------------------------------------
+ when "00000010" =>
+ mnemonic_v := MN_XOR;
+
+ -- Mnemonic JID ---------------------------------------------------------
+ when "11111111" =>
+ mnemonic_v := MN_JID;
+
+ -- Mnemonic JMP ---------------------------------------------------------
+ when "01100000" | "01100001" | "01100010" | "01100011" =>
+ mnemonic_v := MN_JMP;
+ multi_byte_v := true;
+
+ -- Mnemonic JP_JSRP -----------------------------------------------------
+ when "10000000" | "10000001" | "10000010" | "10000011" |
+ "10000100" | "10000101" | "10000110" | "10000111" |
+ "10001000" | "10001001" | "10001010" | "10001011" |
+ "10001100" | "10001101" | "10001110" | "10001111" |
+ "10010000" | "10010001" | "10010010" | "10010011" |
+ "10010100" | "10010101" | "10010110" | "10010111" |
+ "10011000" | "10011001" | "10011010" | "10011011" |
+ "10011100" | "10011101" | "10011110" | "10011111" |
+ "10100000" | "10100001" | "10100010" | "10100011" |
+ "10100100" | "10100101" | "10100110" | "10100111" |
+ "10101000" | "10101001" | "10101010" | "10101011" |
+ "10101100" | "10101101" | "10101110" | "10101111" |
+ "10110000" | "10110001" | "10110010" | "10110011" |
+ "10110100" | "10110101" | "10110110" | "10110111" |
+ "10111000" | "10111001" | "10111010" | "10111011" |
+ "10111100" | "10111101" | "10111110" |
+ "11000000" | "11000001" | "11000010" | "11000011" |
+ "11000100" | "11000101" | "11000110" | "11000111" |
+ "11001000" | "11001001" | "11001010" | "11001011" |
+ "11001100" | "11001101" | "11001110" | "11001111" |
+ "11010000" | "11010001" | "11010010" | "11010011" |
+ "11010100" | "11010101" | "11010110" | "11010111" |
+ "11011000" | "11011001" | "11011010" | "11011011" |
+ "11011100" | "11011101" | "11011110" | "11011111" |
+ "11100000" | "11100001" | "11100010" | "11100011" |
+ "11100100" | "11100101" | "11100110" | "11100111" |
+ "11101000" | "11101001" | "11101010" | "11101011" |
+ "11101100" | "11101101" | "11101110" | "11101111" |
+ "11110000" | "11110001" | "11110010" | "11110011" |
+ "11110100" | "11110101" | "11110110" | "11110111" |
+ "11111000" | "11111001" | "11111010" | "11111011" |
+ "11111100" | "11111101" | "11111110" =>
+ mnemonic_v := MN_JP_JSRP;
+
+ -- Mnemonic JSR ---------------------------------------------------------
+ when "01101000" | "01101001" | "01101010" | "01101011" =>
+ mnemonic_v := MN_JSR;
+ multi_byte_v := true;
+
+ -- Mnemonic RET ---------------------------------------------------------
+ when "01001000" =>
+ mnemonic_v := MN_RET;
+
+ -- Mnemonic RETSK -------------------------------------------------------
+ when "01001001" =>
+ mnemonic_v := MN_RETSK;
+
+ -- Mnemonic LD ----------------------------------------------------------
+ when "00000101" | "00010101" | "00100101" | "00110101" =>
+ mnemonic_v := MN_LD;
+
+ -- Mnemonic LDD_XAD -----------------------------------------------------
+ when "00100011" =>
+ mnemonic_v := MN_LDD_XAD;
+ multi_byte_v := true;
+
+ -- Mnemonic LQID --------------------------------------------------------
+ when "10111111" =>
+ mnemonic_v := MN_LQID;
+
+ -- Mnemonic RMB ---------------------------------------------------------
+ when "01001100" | "01000101" | "01000010" | "01000011" =>
+ mnemonic_v := MN_RMB;
+
+ -- Mnemonic SMB ---------------------------------------------------------
+ when "01001101" | "01000111" | "01000110" | "01001011" =>
+ mnemonic_v := MN_SMB;
+
+ -- Mnemonic STII --------------------------------------------------------
+ when "01110000" | "01110001" | "01110010" | "01110011" |
+ "01110100" | "01110101" | "01110110" | "01110111" |
+ "01111000" | "01111001" | "01111010" | "01111011" |
+ "01111100" | "01111101" | "01111110" | "01111111" =>
+ mnemonic_v := MN_STII;
+
+ -- Mnemonic X -----------------------------------------------------------
+ when "00000110" | "00010110" | "00100110" | "00110110" =>
+ mnemonic_v := MN_X;
+
+ -- Mnemonic XDS ---------------------------------------------------------
+ when "00000111" | "00010111" | "00100111" | "00110111" =>
+ mnemonic_v := MN_XDS;
+
+ -- Mnemonic XIS ---------------------------------------------------------
+ when "00000100" | "00010100" | "00100100" | "00110100" =>
+ mnemonic_v := MN_XIS;
+
+ -- Mnemonic CAB ---------------------------------------------------------
+ when "01010000" =>
+ mnemonic_v := MN_CAB;
+
+ -- Mnemonic CBA ---------------------------------------------------------
+ when "01001110" =>
+ mnemonic_v := MN_CBA;
+
+ -- Mnemonic LBI ---------------------------------------------------------
+ when "00001000" | "00001001" | "00001010" | "00001011" |
+ "00001100" | "00001101" | "00001110" | "00001111" |
+ "00011000" | "00011001" | "00011010" | "00011011" |
+ "00011100" | "00011101" | "00011110" | "00011111" |
+ "00101000" | "00101001" | "00101010" | "00101011" |
+ "00101100" | "00101101" | "00101110" | "00101111" |
+ "00111000" | "00111001" | "00111010" | "00111011" |
+ "00111100" | "00111101" | "00111110" | "00111111" =>
+ mnemonic_v := MN_LBI;
+
+ -- Mnemonic XABR --------------------------------------------------------
+ when "00010010" =>
+ if not t41x_type_v then
+ mnemonic_v := MN_XABR;
+ end if;
+
+ -- Mnemonic SKC ---------------------------------------------------------
+ when "00100000" =>
+ mnemonic_v := MN_SKC;
+
+ -- Mnemonic SKE ---------------------------------------------------------
+ when "00100001" =>
+ mnemonic_v := MN_SKE;
+
+ -- Mnemonic SKMBZ -------------------------------------------------------
+ when "00000001" | "00010001" | "00000011" | "00010011" =>
+ mnemonic_v := MN_SKMBZ;
+
+ -- Mnemonic SKT ---------------------------------------------------------
+ when "01000001" =>
+ if not t41x_type_v then
+ mnemonic_v := MN_SKT;
+ end if;
+
+ -- Mnemonic XAS ---------------------------------------------------------
+ when "01001111" =>
+ mnemonic_v := MN_XAS;
+
+ -- Mnemonic EXT ---------------------------------------------------------
+ when "00110011" =>
+ mnemonic_v := MN_EXT;
+ multi_byte_v := true;
+
+
+ when others =>
+ null;
+ end case;
+
+ result_v.mnemonic := mnemonic_v;
+ result_v.multi_byte := multi_byte_v;
+
+ return result_v;
+ end;
+
+end t400_mnemonic_pack;
tags/rel_1_2/rtl/vhdl/t400_mnemonic_pack-p.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_alu-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_alu-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_alu-c.vhd (revision 180)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- The Arithmetic Logic Unit (ALU).
+-- It contains the accumulator and the C flag.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_alu_rtl_c0 of t400_alu is
+
+ for rtl
+ end for;
+
+end t400_alu_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_alu-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_l-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_l-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_l-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The L port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_io_l_rtl_c0 of t400_io_l is
+
+ for rtl
+ end for;
+
+end t400_io_l_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_io_l-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_clkgen.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_clkgen.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_clkgen.vhd (revision 180)
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+--
+-- The clock generation unit.
+-- PHI1 clock and input/output clock enables are generated here.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+
+entity t400_clkgen is
+
+ generic (
+ opt_ck_div_g : integer := t400_opt_ck_div_16_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ -- Clock Interface --------------------------------------------------------
+ phi1_o : out std_logic;
+ out_en_o : out boolean;
+ in_en_o : out boolean;
+ icyc_en_o : out boolean
+ );
+
+end t400_clkgen;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_clkgen is
+
+ subtype ck_div_t is unsigned(5 downto 0);
+ type ck_div_a_t is array(natural range t400_opt_ck_div_32_c
+ downto t400_opt_ck_div_4_c) of
+ ck_div_t;
+ -- reload values for the CK dividing counter
+ constant ck_div_a_c : ck_div_a_t := (
+ t400_opt_ck_div_32_c => to_unsigned(31, ck_div_t'length),
+ t400_opt_ck_div_16_c => to_unsigned(15, ck_div_t'length),
+ t400_opt_ck_div_8_c => to_unsigned( 7, ck_div_t'length),
+ t400_opt_ck_div_4_c => to_unsigned( 3, ck_div_t'length));
+
+ signal ck_div_cnt_q : ck_div_t;
+ signal ck_div_zero_s,
+ ck_div_half_s : boolean;
+ signal phi1_q : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process ck_div
+ --
+ -- Purpose:
+ -- Divide the incoming clock on ck_i and generate the derived clock
+ -- enable for the core.
+ --
+ ck_div: process (ck_i, por_i)
+ begin
+ if por_i then
+ ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
+ phi1_q <= '0';
+
+ elsif ck_i'event and ck_i = '1' then
+ if ck_en_i then
+ if ck_div_zero_s then
+ ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
+ phi1_q <= '0';
+ else
+ ck_div_cnt_q <= ck_div_cnt_q - 1;
+
+ if ck_div_half_s then
+ phi1_q <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+
+ end process ck_div;
+ --
+ ck_div_zero_s <= ck_div_cnt_q = 0;
+ ck_div_half_s <= ck_div_cnt_q = SHIFT_RIGHT(ck_div_a_c(opt_ck_div_g), 1) + 1;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ phi1_o <= phi1_q;
+ -- Instruction cycle enable
+ icyc_en_o <= ck_en_i and ck_div_zero_s;
+ -- Output update enable
+ out_en_o <= ck_en_i and ck_div_zero_s;
+ -- Input sample enable
+ in_en_o <= ck_en_i and ck_div_half_s;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_clkgen.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_stack.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_stack.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_stack.vhd (revision 180)
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+--
+-- The stack unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_stack is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ -- Stack Control Interface ------------------------------------------------
+ op_i : in stack_op_t;
+ -- Program Counter Interface ----------------------------------------------
+ pc_i : in pc_t;
+ pc_o : out pc_t
+ );
+
+end t400_stack;
+
+
+-- pragma translate_off
+use work.tb_pack.tb_sa_s;
+-- pragma translate_on
+
+architecture rtl of t400_stack is
+
+ signal sa_q,
+ sb_q,
+ sc_q : pc_t;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process stack
+ --
+ -- Purpose:
+ -- Implements the stack consisting of SA, SB, SC.
+ -- SC is skipped when it's a 41xL.
+ --
+ stack: process (ck_i, por_i)
+ variable t41x_type_v : boolean;
+ begin
+ if por_i then
+ sa_q <= (others => '0');
+ sb_q <= (others => '0');
+ sc_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ -- determine type
+ t41x_type_v := opt_type_g = t400_opt_type_410_c;
+
+ if ck_en_i then
+ case op_i is
+ when STACK_PUSH =>
+ sa_q <= pc_i;
+ sb_q <= sa_q;
+ if not t41x_type_v then
+ sc_q <= sb_q;
+ else
+ sc_q <= (others => '0');
+ end if;
+
+ when STACK_POP =>
+ sa_q <= sb_q;
+ if not t41x_type_v then
+ sb_q <= sc_q;
+ end if;
+
+ when others =>
+ null;
+
+ end case;
+ end if;
+ end if;
+ end process stack;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -- pragma translate_off
+ -- instrument interrupt testbench
+ tb_sa_s <= sa_q;
+ -- pragma translate_on
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ pc_o <= sa_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_stack.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_decoder.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_decoder.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_decoder.vhd (revision 180)
@@ -0,0 +1,858 @@
+-------------------------------------------------------------------------------
+--
+-- The decoder unit.
+-- Implements the instruction opcodes and controls all units of the T400 core.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_decoder is
+
+ generic (
+ opt_type_g : integer := t400_opt_type_420_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ out_en_i : in boolean;
+ in_en_i : in boolean;
+ icyc_en_i : in boolean;
+ -- Module Control Interface -----------------------------------------------
+ pc_op_o : out pc_op_t;
+ stack_op_o : out stack_op_t;
+ dmem_op_o : out dmem_op_t;
+ b_op_o : out b_op_t;
+ skip_op_o : out skip_op_t;
+ alu_op_o : out alu_op_t;
+ io_l_op_o : out io_l_op_t;
+ io_d_op_o : out io_d_op_t;
+ io_g_op_o : out io_g_op_t;
+ io_in_op_o : out io_in_op_t;
+ sio_op_o : out sio_op_t;
+ dec_data_o : out dec_data_t;
+ en_o : out dw_t;
+ -- Skip Interface ---------------------------------------------------------
+ skip_i : in boolean;
+ skip_lbi_i : in boolean;
+ is_lbi_o : out boolean;
+ int_i : in boolean;
+ -- Program Memory Interface -----------------------------------------------
+ pm_addr_i : in pc_t;
+ pm_data_i : in byte_t
+ );
+
+end t400_decoder;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+use work.t400_mnemonic_pack.all;
+
+architecture rtl of t400_decoder is
+
+ signal cyc_cnt_q : unsigned(2 downto 0);
+ signal ibyte1_q,
+ ibyte2_q : byte_t;
+
+ signal opcode_s : byte_t;
+ signal second_cyc_q : boolean;
+ signal mnemonic_rec_s : mnemonic_rec_t;
+ signal mnemonic_s,
+ mnemonic_q : mnemonic_t;
+ signal multi_byte_s,
+ multi_byte_q : boolean;
+ signal last_cycle_s : boolean;
+ signal force_mc_s : boolean;
+
+ signal en_q : dw_t;
+ signal set_en_s : boolean;
+ signal ack_int_s : boolean;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Theory of operation:
+ --
+ -- a) One instruction cycle lasts at least 4 ck_i cycles.
+ -- b) PC for instruction/parameter fetch must be valid during cycle 2.
+ -- => cycle 2 is the opcode fetch cycle
+ -- c) Cycle 3 is the opcode decode cycle.
+ -- => opcode_s is valid with cycle 3
+ -- d) mnemonic_q is then valid with cycle 0 until end of instruction.
+ -- So is ibyte1_q.
+ -- e) PC for is incremented during last instruction cycle.
+ -- => fetch of either new instruction or second instruction byte
+ -- f) Second instruction byte is saved in ibyte2_q for cycle 0.
+ -- Valid until end of instruction.
+ --
+ -- Constraints:
+ --
+ -- a) PC of next instruction must be pushed in cycle 0 or 1.
+ -- b) PC for next instruction must be poped latest in cycle 1.
+ -- c) PC for next instruction can only be calculated latest in cycle 1.
+ -- d) IO output is enabled by out_en_i
+ -- e) IO inputs are sampled with in_en_i
+ --
+ -- d) and e) are required for proper timing in relation to phi1
+ -- (SK clock/sync output).
+ --
+ -- Conventions:
+ --
+ -- a) ALU operations take place in cycle 1.
+ --
+ -----------------------------------------------------------------------------
+
+ last_cycle_s <= (not multi_byte_q and
+ not second_cyc_q and not force_mc_s)
+ or
+ second_cyc_q;
+
+
+ -----------------------------------------------------------------------------
+ -- Process seq
+ --
+ -- Purpose:
+ -- Implements the various sequential elements.
+ -- Cycle counter:
+ -- It identifies the execution cycle of the
+ -- current instruction.
+ -- Instruction registers:
+ -- They save the first and second byte of an instruction for
+ -- further processing.
+ -- New instruction flag:
+ -- Indicates when a new instruction is fetched from the program
+ -- memory. Implemented as a flip-flop to control the multiplexer
+ -- which saves power by gating the combinational opcode decoder.
+ -- Mnemonic register:
+ -- Latches the decoded mnemonic of the current instruction.
+ -- Multi byte flag:
+ -- Latches the decoded multi byte status information.
+ --
+ seq: process (ck_i, por_i)
+ begin
+ if por_i then
+ cyc_cnt_q <= to_unsigned(1, cyc_cnt_q'length);
+ second_cyc_q <= false;
+ ibyte1_q <= (others => '0');
+ ibyte2_q <= (others => '0');
+ mnemonic_q <= MN_CLRA;
+ multi_byte_q <= false;
+ en_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ mnemonic_q <= MN_CLRA;
+ multi_byte_q <= false;
+ cyc_cnt_q <= (others => '0');
+ en_q <= (others => '0');
+
+ elsif ck_en_i then
+ -- cycle counter ------------------------------------------------------
+ if icyc_en_i then
+ -- new instruction cycle started
+ cyc_cnt_q <= (others => '0');
+ elsif cyc_cnt_q /= 4 then
+ cyc_cnt_q <= cyc_cnt_q + 1;
+ end if;
+
+ -- second cycle flag --------------------------------------------------
+ if icyc_en_i then
+ if not last_cycle_s then
+ second_cyc_q <= true;
+ else
+ second_cyc_q <= false;
+ end if;
+ end if;
+
+ -- instruction byte 1 and mnemonic info -------------------------------
+ if icyc_en_i and last_cycle_s then
+ if not ack_int_s then
+ -- update instruction descriptors in normal mode
+ ibyte1_q <= pm_data_i;
+ mnemonic_q <= mnemonic_s;
+ multi_byte_q <= multi_byte_s;
+ else
+ -- force NOP instruction when vectoring to interrupt routine
+ ibyte1_q <= "01000100";
+ mnemonic_q <= MN_NOP;
+ multi_byte_q <= false;
+ end if;
+ end if;
+
+ -- instruction byte 2 -------------------------------------------------
+ if icyc_en_i and not last_cycle_s then
+ ibyte2_q <= pm_data_i;
+ end if;
+
+ -- EN register --------------------------------------------------------
+ if set_en_s then
+ en_q <= ibyte2_q(dw_range_t);
+ elsif ack_int_s then
+ -- reset interrupt enable when INT has been acknowledged
+ en_q(1) <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process seq;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Opcode multiplexer
+ -----------------------------------------------------------------------------
+ opcode_s <= pm_data_i
+ when icyc_en_i else
+ ibyte1_q;
+
+ -----------------------------------------------------------------------------
+ -- Opcode decoder table
+ --
+ mnemonic_rec_s <= decode_opcode_f(opcode => opcode_s,
+ opt_type => opt_type_g);
+ --
+ mnemonic_s <= mnemonic_rec_s.mnemonic;
+ multi_byte_s <= mnemonic_rec_s.multi_byte;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process decoder_ctrl
+ --
+ -- Purpose:
+ -- Implements the controlling logic of the decoder module.
+ --
+ decoder_ctrl: process (icyc_en_i,
+ out_en_i, in_en_i,
+ cyc_cnt_q,
+ mnemonic_q, second_cyc_q, last_cycle_s,
+ ibyte1_q, ibyte2_q,
+ skip_i, skip_lbi_i,
+ en_q, int_i,
+ pm_addr_i, pm_data_i)
+ variable cyc_v : natural range 0 to 4;
+ variable t41x_type_v,
+ t420_type_v : boolean;
+ variable en_int_v : boolean;
+ begin
+ -- default assignments
+ pc_op_o <= PC_NONE;
+ stack_op_o <= STACK_NONE;
+ dmem_op_o <= DMEM_RB; -- default is read via B
+ b_op_o <= B_NONE;
+ skip_op_o <= SKIP_NONE;
+ alu_op_o <= ALU_NONE;
+ io_l_op_o <= IOL_NONE;
+ io_d_op_o <= IOD_NONE;
+ io_g_op_o <= IOG_NONE;
+ io_in_op_o <= IOIN_NONE;
+ sio_op_o <= SIO_NONE;
+ dec_data_o <= (others => '0');
+ is_lbi_o <= false;
+ set_en_s <= false;
+ force_mc_s <= false;
+ en_int_v := true;
+ ack_int_s <= false;
+ cyc_v := to_integer(cyc_cnt_q);
+ -- determine type
+ t41x_type_v := opt_type_g = t400_opt_type_410_c;
+ t420_type_v := opt_type_g = t400_opt_type_420_c;
+
+ if icyc_en_i then
+ -- immediately increment program counter
+ -- this happens at two occasions:
+ -- a) right before new mnemonic becomes valid
+ -- b) before the second instruction cycle begins
+ pc_op_o <= PC_INC_PC;
+ end if;
+
+ if icyc_en_i and last_cycle_s then
+ -- update skip state when last instruction cycle ends
+ skip_op_o <= SKIP_UPDATE;
+ end if;
+
+ -- skip instruction execution
+ if not skip_i then
+ -- implement instruction control
+ case mnemonic_q is
+ -- Mnemonic ASC -------------------------------------------------------
+ when MN_ASC =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_ADD_C;
+ skip_op_o <= SKIP_CARRY;
+ end if;
+
+ -- Mnemonic ADD -------------------------------------------------------
+ when MN_ADD =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_ADD;
+ end if;
+
+ -- Mnemonic ADT -------------------------------------------------------
+ when MN_ADT =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_ADD_10;
+ end if;
+
+ -- Mnemonic AISC ------------------------------------------------------
+ when MN_AISC =>
+ dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
+ if cyc_v = 1 then
+ alu_op_o <= ALU_ADD_DEC;
+ skip_op_o <= SKIP_CARRY;
+ end if;
+
+ -- Mnemonic CASC ------------------------------------------------------
+ when MN_CASC =>
+ case cyc_v is
+ when 0 =>
+ alu_op_o <= ALU_COMP;
+ when 1 =>
+ alu_op_o <= ALU_ADD_C;
+ skip_op_o <= SKIP_CARRY;
+ when others =>
+ null;
+ end case;
+
+ -- Mnemonic CLRA ------------------------------------------------------
+ when MN_CLRA =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_CLRA;
+ end if;
+
+ -- Mnemonic COMP ------------------------------------------------------
+ when MN_COMP =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_COMP;
+ end if;
+
+ -- Mnemonic NOP -------------------------------------------------------
+ when MN_NOP =>
+ -- do nothing
+ null;
+
+ -- Mnemonic C ---------------------------------------------------------
+ when MN_C =>
+ if cyc_v = 1 then
+ if ibyte1_q(4) = '1' then
+ alu_op_o <= ALU_RC;
+ else
+ alu_op_o <= ALU_SC;
+ end if;
+ end if;
+
+ -- Mnemonic XOR -------------------------------------------------------
+ when MN_XOR =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_XOR;
+ end if;
+
+ -- Mnemonic JID -------------------------------------------------------
+ when MN_JID =>
+ force_mc_s <= true;
+ en_int_v := false;
+ dec_data_o(byte_t'range) <= pm_data_i;
+ if cyc_v = 1 then
+ if not second_cyc_q then
+ -- first cycle: load PC from A and M
+ pc_op_o <= PC_LOAD_A_M;
+ else
+ -- second cycle: load PC from program memory
+ pc_op_o <= PC_LOAD_8;
+ end if;
+ end if;
+
+ if icyc_en_i and not second_cyc_q then
+ -- do not increment PC for second instruction cycle
+ pc_op_o <= PC_NONE;
+ end if;
+
+ -- Mnemonic JMP -------------------------------------------------------
+ when MN_JMP =>
+ en_int_v := false;
+ dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
+ if second_cyc_q and cyc_v = 1 then
+ pc_op_o <= PC_LOAD;
+ end if;
+
+ -- Mnemonic JP_JSRP ---------------------------------------------------
+ when MN_JP_JSRP =>
+ en_int_v := false;
+ -- universal decoder data
+ dec_data_o <= '0' & "01" & ibyte1_q(6 downto 0);
+ if cyc_v = 1 then
+ if pm_addr_i(9 downto 7) = "001" then
+ -- JP within pages 2 & 3
+ pc_op_o <= PC_LOAD_7;
+ elsif ibyte1_q(6) = '1' then
+ -- JP outside of pages 2 & 3
+ pc_op_o <= PC_LOAD_6;
+ else
+ -- JSRP to page 2
+ pc_op_o <= PC_LOAD;
+ stack_op_o <= STACK_PUSH;
+ end if;
+ end if;
+
+ -- Mnemonic JSR -------------------------------------------------------
+ when MN_JSR =>
+ en_int_v := false;
+ dec_data_o <= ibyte1_q(1) & ibyte1_q(0) & ibyte2_q;
+ if second_cyc_q and cyc_v = 1 then
+ pc_op_o <= PC_LOAD;
+ stack_op_o <= STACK_PUSH;
+ end if;
+
+ -- Mnemonic RET -------------------------------------------------------
+ when MN_RET =>
+ en_int_v := false;
+ if cyc_v = 1 then
+ pc_op_o <= PC_POP;
+ stack_op_o <= STACK_POP;
+
+ if t420_type_v then
+ -- always restore skip state in case this was an interrupt
+ skip_op_o <= SKIP_POP;
+ end if;
+ end if;
+
+ -- Mnemonic RETSK -----------------------------------------------------
+ when MN_RETSK =>
+ en_int_v := false;
+ if cyc_v = 1 then
+ pc_op_o <= PC_POP;
+ stack_op_o <= STACK_POP;
+ skip_op_o <= SKIP_NOW;
+ end if;
+
+ -- Mnemonic LD --------------------------------------------------------
+ when MN_LD =>
+ dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
+ if cyc_v = 1 then
+ alu_op_o <= ALU_LOAD_M;
+ b_op_o <= B_XOR_BR;
+ end if;
+
+ -- Mnemonic LDD_XAD ---------------------------------------------------
+ when MN_LDD_XAD =>
+ -- preload decoder data
+ dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
+
+ if second_cyc_q then
+ case ibyte2_q(7 downto 6) is
+ -- LDD
+ when "00" =>
+ if not t41x_type_v then
+ case cyc_v is
+ when 1 =>
+ dmem_op_o <= DMEM_RDEC;
+ when 2 =>
+ alu_op_o <= ALU_LOAD_M;
+ when others =>
+ null;
+ end case;
+ end if;
+ -- XAD
+ when "10" =>
+ if not t41x_type_v or
+ unsigned(ibyte2_q(b_range_t)) = 63 then
+ case cyc_v is
+ when 1 =>
+ dmem_op_o <= DMEM_RDEC;
+ when 2 =>
+ alu_op_o <= ALU_LOAD_M;
+ dmem_op_o <= DMEM_WDEC_SRC_A;
+ when others =>
+ null;
+ end case;
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Mnemonic LQID ------------------------------------------------------
+ when MN_LQID =>
+ force_mc_s <= true;
+ en_int_v := false;
+ if not second_cyc_q then
+ -- first cycle: push PC and set PC from A/M,
+ -- read IOL from program memory
+ if cyc_v = 1 then
+ stack_op_o <= STACK_PUSH;
+ pc_op_o <= PC_LOAD_A_M;
+ end if;
+
+ if out_en_i then
+ io_l_op_o <= IOL_LOAD_PM;
+ end if;
+ else
+ if cyc_v = 1 then
+ -- second cycle: pop PC
+ stack_op_o <= STACK_POP;
+ pc_op_o <= PC_POP;
+ end if;
+ end if;
+
+ if icyc_en_i and not second_cyc_q then
+ -- do not increment PC for second instruction cycle
+ pc_op_o <= PC_NONE;
+ end if;
+
+ -- Mnemonic RMB -------------------------------------------------------
+ when MN_RMB =>
+ if cyc_v = 1 then
+ dmem_op_o <= DMEM_WB_RES_BIT;
+ -- select bit to be reset
+ case ibyte1_q(dw_range_t) is
+ when "1100" =>
+ dec_data_o(dw_range_t) <= "0001";
+ when "0101" =>
+ dec_data_o(dw_range_t) <= "0010";
+ when "0010" =>
+ dec_data_o(dw_range_t) <= "0100";
+ when "0011" =>
+ dec_data_o(dw_range_t) <= "1000";
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Mnemonic SMB -------------------------------------------------------
+ when MN_SMB =>
+ if cyc_v = 1 then
+ dmem_op_o <= DMEM_WB_SET_BIT;
+ -- select bit to be set
+ case ibyte1_q(dw_range_t) is
+ when "1101" =>
+ dec_data_o(dw_range_t) <= "0001";
+ when "0111" =>
+ dec_data_o(dw_range_t) <= "0010";
+ when "0110" =>
+ dec_data_o(dw_range_t) <= "0100";
+ when "1011" =>
+ dec_data_o(dw_range_t) <= "1000";
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Mnemonic STII ------------------------------------------------------
+ when MN_STII =>
+ dec_data_o(dw_range_t) <= ibyte1_q(dw_range_t);
+ if cyc_v = 1 then
+ dmem_op_o <= DMEM_WB_SRC_DEC;
+ b_op_o <= B_INC_BD;
+ end if;
+
+ -- Mnemonic X ---------------------------------------------------------
+ when MN_X =>
+ dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
+ if cyc_v = 1 then
+ alu_op_o <= ALU_LOAD_M;
+ dmem_op_o <= DMEM_WB_SRC_A;
+ b_op_o <= B_XOR_BR;
+ end if;
+
+ -- Mnemonic XDS -------------------------------------------------------
+ when MN_XDS =>
+ dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
+ case cyc_v is
+ when 1 =>
+ alu_op_o <= ALU_LOAD_M;
+ dmem_op_o <= DMEM_WB_SRC_A;
+ b_op_o <= B_DEC_BD;
+ when 2 =>
+ b_op_o <= B_XOR_BR;
+ skip_op_o <= SKIP_BD_UFLOW;
+ when others =>
+ null;
+ end case;
+
+ -- Mnemonic XIS -------------------------------------------------------
+ when MN_XIS =>
+ dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
+ case cyc_v is
+ when 1 =>
+ alu_op_o <= ALU_LOAD_M;
+ dmem_op_o <= DMEM_WB_SRC_A;
+ b_op_o <= B_INC_BD;
+ when 2 =>
+ b_op_o <= B_XOR_BR;
+ skip_op_o <= SKIP_BD_OFLOW;
+ when others =>
+ null;
+ end case;
+
+ -- Mnemonic CAB -------------------------------------------------------
+ when MN_CAB =>
+ if cyc_v = 1 then
+ b_op_o <= B_SET_BD;
+ end if;
+
+ -- Mnemonic CBA -------------------------------------------------------
+ when MN_CBA =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_LOAD_BD;
+ end if;
+
+ -- Mnemonic LBI -------------------------------------------------------
+ when MN_LBI =>
+ is_lbi_o <= true;
+ en_int_v := false;
+ dec_data_o(br_range_t) <= ibyte1_q(br_range_t);
+ dec_data_o(bd_range_t) <= ibyte1_q(bd_range_t);
+ if cyc_v = 1 and not skip_lbi_i then
+ -- increment Bd by 1
+ b_op_o <= B_SET_B_INC;
+ skip_op_o <= SKIP_LBI;
+ end if;
+
+ -- Mnemonic XABR ------------------------------------------------------
+ when MN_XABR =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_LOAD_BR;
+ b_op_o <= B_SET_BR;
+ end if;
+
+ -- Mnemonic SKC -------------------------------------------------------
+ when MN_SKC =>
+ if cyc_v = 1 then
+ skip_op_o <= SKIP_C;
+ end if;
+
+ -- Mnemonic SKE -------------------------------------------------------
+ when MN_SKE =>
+ if cyc_v = 1 then
+ skip_op_o <= SKIP_A_M;
+ end if;
+
+ -- Mnemonic SKMBZ -----------------------------------------------------
+ when MN_SKMBZ =>
+ if cyc_v = 1 then
+ skip_op_o <= SKIP_M_BIT;
+ -- select bit to be checked
+ case ibyte1_q is
+ when "00000001" =>
+ dec_data_o(dw_range_t) <= "0001";
+ when "00010001" =>
+ dec_data_o(dw_range_t) <= "0010";
+ when "00000011" =>
+ dec_data_o(dw_range_t) <= "0100";
+ when "00010011" =>
+ dec_data_o(dw_range_t) <= "1000";
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Mnemonic SKT -------------------------------------------------------
+ when MN_SKT =>
+ if cyc_v = 1 then
+ skip_op_o <= SKIP_TIMER;
+ end if;
+
+ -- Mnemonic XAS -------------------------------------------------------
+ when MN_XAS =>
+ if out_en_i then
+ sio_op_o <= SIO_LOAD;
+ alu_op_o <= ALU_LOAD_SIO;
+ end if;
+
+ -- Mnemonic EXT -------------------------------------------------------
+ when MN_EXT =>
+ if second_cyc_q then
+ case ibyte2_q is
+ -- CAMQ
+ when "00111100" =>
+ if out_en_i then
+ io_l_op_o <= IOL_LOAD_AM;
+ end if;
+ -- CQMA
+ when "00101100" =>
+ if not t41x_type_v and in_en_i then
+ io_l_op_o <= IOL_OUTPUT_Q;
+ alu_op_o <= ALU_LOAD_Q;
+ dmem_op_o <= DMEM_WB_SRC_Q;
+ end if;
+ -- SKGZ
+ when "00100001" =>
+ if in_en_i then
+ skip_op_o <= SKIP_G_ZERO;
+ end if;
+ -- SKGBZ
+ when "00000001" =>
+ if in_en_i then
+ skip_op_o <= SKIP_G_BIT;
+ dec_data_o(dw_range_t) <= "0001";
+ end if;
+ when "00010001" =>
+ if in_en_i then
+ skip_op_o <= SKIP_G_BIT;
+ dec_data_o(dw_range_t) <= "0010";
+ end if;
+ when "00000011" =>
+ if in_en_i then
+ skip_op_o <= SKIP_G_BIT;
+ dec_data_o(dw_range_t) <= "0100";
+ end if;
+ when "00010011" =>
+ if in_en_i then
+ skip_op_o <= SKIP_G_BIT;
+ dec_data_o(dw_range_t) <= "1000";
+ end if;
+ -- ING
+ when "00101010" =>
+ if cyc_v = 1 then
+ alu_op_o <= ALU_LOAD_G;
+ end if;
+ -- INL
+ when "00101110" =>
+ if in_en_i then
+ io_l_op_o <= IOL_OUTPUT_L;
+ alu_op_o <= ALU_LOAD_Q;
+ dmem_op_o <= DMEM_WB_SRC_Q;
+ end if;
+ -- ININ
+ when "00101000" =>
+ if not t41x_type_v and in_en_i then
+ alu_op_o <= ALU_LOAD_IN;
+ end if;
+ -- INIL
+ when "00101001" =>
+ if not t41x_type_v and in_en_i then
+ alu_op_o <= ALU_LOAD_IL;
+ io_in_op_o <= IOIN_INIL;
+ end if;
+ -- OBD
+ when "00111110" =>
+ if out_en_i then
+ io_d_op_o <= IOD_LOAD;
+ end if;
+ -- OMG
+ when "00111010" =>
+ if out_en_i then
+ io_g_op_o <= IOG_LOAD_M;
+ end if;
+ -- multiple codes
+ when others =>
+ -- apply default decoder output, largest required vector
+ dec_data_o(b_range_t) <= ibyte2_q(b_range_t);
+ -- LBI
+ if ibyte2_q(7 downto 6) = "10" and not t41x_type_v then
+ is_lbi_o <= true;
+ en_int_v := false;
+ if cyc_v > 0 and not skip_lbi_i then
+ b_op_o <= B_SET_B;
+ skip_op_o <= SKIP_LBI;
+ end if;
+ end if;
+ -- LEI
+ if ibyte2_q(7 downto 4) = "0110" and in_en_i then
+ -- dec_data_o applied by default
+ set_en_s <= true;
+
+ -- acknowledge pending interrupt when EN(1) is not
+ -- enabled - will clear them until interrupts are
+ -- enabled with EN(1) = '1'
+ if en_q(1) = '0' then
+ io_in_op_o <= IOIN_INTACK;
+ end if;
+ end if;
+ -- OGI
+ if ibyte2_q(7 downto 4) = "0101" and out_en_i and
+ not t41x_type_v then
+ -- dec_data_o applied by default
+ io_g_op_o <= IOG_LOAD_DEC;
+ end if;
+ end case;
+ end if;
+
+ when others =>
+ null;
+ end case;
+ end if;
+
+
+ -- Interrupt handling -----------------------------------------------------
+ if t420_type_v and
+ en_q(1) = '1' and int_i and en_int_v then
+ if last_cycle_s then
+ if cyc_v = 1 then
+ stack_op_o <= STACK_PUSH;
+ end if;
+ if icyc_en_i then
+ ack_int_s <= true;
+ io_in_op_o <= IOIN_INTACK;
+ pc_op_o <= PC_INT;
+ -- push skip state that was determined by current instruction
+ -- and will be valid for the next instruction which is delayed
+ -- by the interrupt
+ skip_op_o <= SKIP_PUSH;
+ end if;
+ end if;
+ end if;
+
+ end process decoder_ctrl;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ en_o <= en_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_decoder.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_d.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_d.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_d.vhd (revision 180)
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+--
+-- The D port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_io_d is
+
+ generic (
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in io_d_op_t;
+ bd_i : in bd_t;
+ -- Port D Interface -------------------------------------------------------
+ io_d_o : out dw_t;
+ io_d_en_o : out dw_t
+ );
+
+end t400_io_d;
+
+
+use work.t400_io_pack.all;
+
+architecture rtl of t400_io_d is
+
+ signal d_q : dw_t;
+
+ signal vdd_s : std_logic;
+
+begin
+
+ vdd_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- Process d_reg
+ --
+ -- Purpose:
+ -- Implements the D output register.
+ --
+ d_reg: process (ck_i, por_i)
+ begin
+ if por_i then
+ d_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ d_q <= (others => '0');
+
+ elsif ck_en_i then
+ if op_i = IOD_LOAD then
+ d_q <= bd_i;
+ end if;
+ end if;
+
+ end if;
+ end process d_reg;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process out_driver
+ --
+ -- Purpose:
+ -- Implements the output driver data and enable.
+ --
+ out_driver: process (d_q,
+ vdd_s)
+ begin
+ -- bit 3
+ io_d_o(3) <= io_out_f(dat => d_q(3),
+ opt => opt_out_type_3_g);
+ io_d_en_o(3) <= io_en_f (en => vdd_s, dat => d_q(3),
+ opt => opt_out_type_3_g);
+
+ -- bit 2
+ io_d_o(2) <= io_out_f(dat => d_q(2),
+ opt => opt_out_type_2_g);
+ io_d_en_o(2) <= io_en_f (en => vdd_s, dat => d_q(2),
+ opt => opt_out_type_2_g);
+
+ -- bit 1
+ io_d_o(1) <= io_out_f(dat => d_q(1),
+ opt => opt_out_type_1_g);
+ io_d_en_o(1) <= io_en_f (en => vdd_s, dat => d_q(1),
+ opt => opt_out_type_1_g);
+
+ -- bit 0
+ io_d_o(0) <= io_out_f(dat => d_q(0),
+ opt => opt_out_type_0_g);
+ io_d_en_o(0) <= io_en_f (en => vdd_s, dat => d_q(0),
+ opt => opt_out_type_0_g);
+
+ end process out_driver;
+ --
+ -----------------------------------------------------------------------------
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_io_d.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_in-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_in-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_in-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The IN port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_io_in_rtl_c0 of t400_io_in is
+
+ for rtl
+ end for;
+
+end t400_io_in_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_io_in-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_g.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_g.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_g.vhd (revision 180)
@@ -0,0 +1,169 @@
+-------------------------------------------------------------------------------
+--
+-- The G port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_io_g is
+
+ generic (
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in io_g_op_t;
+ m_i : in dw_t;
+ dec_data_i : in dec_data_t;
+ cs_n_i : in std_logic;
+ wr_n_i : in std_logic;
+ -- Port G Interface -------------------------------------------------------
+ io_g_o : out dw_t;
+ io_g_en_o : out dw_t
+ );
+
+end t400_io_g;
+
+
+use work.t400_io_pack.all;
+
+architecture rtl of t400_io_g is
+
+ signal g_q : dw_t;
+
+ signal vdd_s : std_logic;
+
+begin
+
+ vdd_s <= '1';
+
+ -----------------------------------------------------------------------------
+ -- Process g_reg
+ --
+ -- Purpose:
+ -- Implements the G output register.
+ --
+ g_reg: process (ck_i, por_i)
+ begin
+ if por_i then
+ g_q <= (others => '0');
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ g_q <= (others => '0');
+
+ elsif ck_en_i then
+ case op_i is
+ when IOG_LOAD_M =>
+ g_q <= m_i;
+ when IOG_LOAD_DEC =>
+ g_q <= dec_data_i(dw_range_t);
+ when others =>
+ null;
+ end case;
+
+ end if;
+
+ -- reset G(0) in MICROBUS operation upon write
+ if opt_microbus_g = t400_opt_microbus_c and
+ cs_n_i = '0' and wr_n_i = '0' then
+ g_q(0) <= '0';
+ end if;
+ end if;
+ end process g_reg;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process out_driver
+ --
+ -- Purpose:
+ -- Implements the output driver data and enable.
+ --
+ out_driver: process (g_q,
+ vdd_s)
+ begin
+ -- bit 3
+ io_g_o(3) <= io_out_f(dat => g_q(3),
+ opt => opt_out_type_3_g);
+ io_g_en_o(3) <= io_en_f (en => vdd_s, dat => g_q(3),
+ opt => opt_out_type_3_g);
+
+ -- bit 2
+ io_g_o(2) <= io_out_f(dat => g_q(2),
+ opt => opt_out_type_2_g);
+ io_g_en_o(2) <= io_en_f (en => vdd_s, dat => g_q(2),
+ opt => opt_out_type_2_g);
+
+ -- bit 1
+ io_g_o(1) <= io_out_f(dat => g_q(1),
+ opt => opt_out_type_1_g);
+ io_g_en_o(1) <= io_en_f (en => vdd_s, dat => g_q(1),
+ opt => opt_out_type_1_g);
+
+ -- bit 0
+ io_g_o(0) <= io_out_f(dat => g_q(0),
+ opt => opt_out_type_0_g);
+ io_g_en_o(0) <= io_en_f (en => vdd_s, dat => g_q(0),
+ opt => opt_out_type_0_g);
+
+ end process out_driver;
+ --
+ -----------------------------------------------------------------------------
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_io_g.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_alu.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_alu.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_alu.vhd (revision 180)
@@ -0,0 +1,250 @@
+-------------------------------------------------------------------------------
+--
+-- The Arithmetic Logic Unit (ALU).
+-- It contains the accumulator and the C flag.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_pack.all;
+use work.t400_opt_pack.all;
+
+entity t400_alu is
+
+ generic (
+ opt_cko_g : integer := t400_opt_cko_crystal_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ res_i : in boolean;
+ cko_i : in std_logic;
+ -- Control Interface ------------------------------------------------------
+ op_i : in alu_op_t;
+ -- Data Interface ---------------------------------------------------------
+ m_i : in dw_t;
+ dec_data_i : in dec_data_t;
+ q_low_i : in dw_t;
+ b_i : in b_t;
+ g_i : in dw_t;
+ in_i : in dw_t;
+ sio_i : in dw_t;
+ a_o : out dw_t;
+ carry_o : out std_logic;
+ c_o : out std_logic
+ );
+
+end t400_alu;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of t400_alu is
+
+ subtype alu_dw_t is unsigned(dw_t'high+1 downto 0);
+ signal alu_result_s : alu_dw_t;
+
+ signal a_q : dw_t;
+ signal c_q : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process regs
+ --
+ -- Purpose:
+ -- Implements the sequential registers of the ALU:
+ -- * A - accumulator
+ -- * C - carry flag
+ --
+ regs: process (ck_i, por_i)
+ begin
+ if por_i then
+ a_q <= (others => '0');
+ c_q <= '0';
+
+ elsif ck_i'event and ck_i = '1' then
+ if res_i then
+ -- synchronous reset upon external reset event
+ a_q <= (others => '0');
+ c_q <= '0';
+
+ elsif ck_en_i then
+ -- update accumulator
+ case op_i is
+ when ALU_CLRA |
+ ALU_ADD |
+ ALU_ADD_10 |
+ ALU_ADD_C |
+ ALU_ADD_DEC |
+ ALU_COMP |
+ ALU_XOR =>
+ a_q <= std_logic_vector(alu_result_s(dw_t'range));
+ when ALU_LOAD_M =>
+ a_q <= m_i;
+ when ALU_LOAD_Q =>
+ a_q <= q_low_i;
+ when ALU_LOAD_G =>
+ a_q <= g_i;
+ when ALU_LOAD_IN =>
+ a_q <= in_i;
+ when ALU_LOAD_IL =>
+ a_q(3) <= in_i(3);
+ if opt_cko_g = t400_opt_cko_gpi_c then
+ a_q(2) <= cko_i;
+ else
+ a_q(2) <= '1';
+ end if;
+ a_q(1) <= '0';
+ a_q(0) <= in_i(0);
+ when ALU_LOAD_BR =>
+ a_q(3 downto 2) <= (others => '0');
+ a_q(1 downto 0) <= b_i(br_range_t);
+ when ALU_LOAD_BD =>
+ a_q <= b_i(bd_range_t);
+ when ALU_LOAD_SIO =>
+ a_q <= sio_i;
+ when others =>
+ null;
+ end case;
+
+ -- update C flag upon the following instructions
+ case op_i is
+ -- carry result of addition -----------------------------------------
+ when ALU_ADD_C =>
+ c_q <= alu_result_s(alu_dw_t'high);
+
+ -- reset C flag -----------------------------------------------------
+ when ALU_RC =>
+ c_q <= '0';
+
+ -- set C flag -------------------------------------------------------
+ when ALU_SC =>
+ c_q <= '1';
+
+ when others =>
+ null;
+ end case;
+ end if;
+ end if;
+ end process regs;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Process dp
+ --
+ -- Purpose:
+ -- Implements the ALU's data path.
+ --
+ dp: process (op_i,
+ a_q,
+ m_i,
+ dec_data_i,
+ c_q)
+ variable in1_v,
+ in2_v,
+ in3_v,
+ add_v, xor_v : alu_dw_t;
+ begin
+ -- prepare adder
+ in1_v := '0' & unsigned(a_q);
+ if op_i = ALU_ADD_10 then
+ in2_v := to_unsigned(10, alu_dw_t'length);
+ elsif op_i = ALU_ADD_DEC then
+ in2_v := '0' & unsigned(dec_data_i(dw_t'range));
+ else
+ in2_v := '0' & unsigned(m_i);
+ end if;
+ if op_i = ALU_ADD_C then
+ in3_v := (others => '0');
+ in3_v(0) := c_q;
+ else
+ in3_v := (others => '0');
+ end if;
+ add_v := in1_v + in2_v + in3_v;
+
+ -- prepare exclusive or
+ xor_v := in1_v xor in2_v;
+
+ case op_i is
+ -- ALU operation: Clear accumulator -------------------------------------
+ when ALU_CLRA =>
+ alu_result_s <= (others => '0');
+
+ -- ALU operation: Add to accumulator ------------------------------------
+ when ALU_ADD |
+ ALU_ADD_10 |
+ ALU_ADD_C |
+ ALU_ADD_DEC =>
+ alu_result_s <= add_v;
+
+ -- ALU operation: Complement accumulator --------------------------------
+ when ALU_COMP =>
+ alu_result_s <= '0' & not unsigned(a_q);
+
+ -- ALU operation: XOR to accumulator ------------------------------------
+ when ALU_XOR =>
+ alu_result_s <= xor_v;
+
+ when others =>
+ alu_result_s <= (others => '-');
+ end case;
+ end process dp;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Output mapping
+ -----------------------------------------------------------------------------
+ a_o <= a_q;
+ carry_o <= alu_result_s(alu_dw_t'high);
+ c_o <= c_q;
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_alu.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_io_l.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_io_l.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_io_l.vhd (revision 180)
@@ -0,0 +1,215 @@
+-------------------------------------------------------------------------------
+--
+-- The L port controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t400/
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.t400_opt_pack.all;
+use work.t400_pack.all;
+
+entity t400_io_l is
+
+ generic (
+ opt_out_type_7_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_6_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_5_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_4_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_3_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_2_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_1_g : integer := t400_opt_out_type_std_c;
+ opt_out_type_0_g : integer := t400_opt_out_type_std_c;
+ opt_microbus_g : integer := t400_opt_no_microbus_c
+ );
+ port (
+ -- System Interface -------------------------------------------------------
+ ck_i : in std_logic;
+ ck_en_i : in boolean;
+ por_i : in boolean;
+ in_en_i : in boolean;
+ -- Control Interface ------------------------------------------------------
+ op_i : in io_l_op_t;
+ en2_i : in std_logic;
+ m_i : in dw_t;
+ a_i : in dw_t;
+ pm_data_i : in byte_t;
+ q_o : out byte_t;
+ -- Microbus Interface -----------------------------------------------------
+ cs_n_i : in std_logic;
+ rd_n_i : in std_logic;
+ wr_n_i : in std_logic;
+ -- Port L Interface -------------------------------------------------------
+ io_l_i : in byte_t;
+ io_l_o : out byte_t;
+ io_l_en_o : out byte_t
+ );
+
+end t400_io_l;
+
+
+use work.t400_io_pack.all;
+
+architecture rtl of t400_io_l is
+
+ signal q_q : byte_t;
+
+ signal en2_s : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Process q_reg
+ --
+ -- Purpose:
+ -- Implements the Q register.
+ --
+ q_reg: process (ck_i, por_i)
+ begin
+ if por_i then
+ q_q <= (others => '0');
+ elsif ck_i'event and ck_i = '1' then
+ if ck_en_i then
+ case op_i is
+ -- Load Q from accumulator and data memory --------------------------
+ when IOL_LOAD_AM =>
+ q_q(7 downto 4) <= a_i;
+ q_q(3 downto 0) <= m_i;
+
+ -- Load Q from program memory ---------------------------------------
+ when IOL_LOAD_PM =>
+ q_q <= pm_data_i;
+
+ when others =>
+ null;
+ end case;
+ end if;
+
+ -- Microbus functionality
+ if opt_microbus_g = t400_opt_microbus_c and
+ cs_n_i = '0' and wr_n_i = '0' then
+ q_q <= to_X01(io_l_i);
+ end if;
+ end if;
+ end process q_reg;
+ --
+ -----------------------------------------------------------------------------
+
+
+ -----------------------------------------------------------------------------
+ -- Multiplexer providing read data to the system.
+ -----------------------------------------------------------------------------
+ q_o <= to_X01(io_l_i)
+ when op_i = IOL_OUTPUT_L else
+ q_q;
+
+
+ -----------------------------------------------------------------------------
+ -- Dedicated output enable when in Microbus mode
+ -----------------------------------------------------------------------------
+ en2_s <= cs_n_i nor rd_n_i
+ when opt_microbus_g = t400_opt_microbus_c else
+ en2_i;
+
+ -----------------------------------------------------------------------------
+ -- Process out_driver
+ --
+ -- Purpose:
+ -- Implements the output driver data and enable.
+ --
+ out_driver: process (en2_s,
+ q_q)
+ begin
+ -- bit 7
+ io_l_o(7) <= io_out_f(dat => q_q(7),
+ opt => opt_out_type_7_g);
+ io_l_en_o(7) <= io_en_f (en => en2_s, dat => q_q(7),
+ opt => opt_out_type_7_g);
+
+ -- bit 6
+ io_l_o(6) <= io_out_f(dat => q_q(6),
+ opt => opt_out_type_6_g);
+ io_l_en_o(6) <= io_en_f (en => en2_s, dat => q_q(6),
+ opt => opt_out_type_6_g);
+
+ -- bit 5
+ io_l_o(5) <= io_out_f(dat => q_q(5),
+ opt => opt_out_type_5_g);
+ io_l_en_o(5) <= io_en_f (en => en2_s, dat => q_q(5),
+ opt => opt_out_type_5_g);
+
+ -- bit 4
+ io_l_o(4) <= io_out_f(dat => q_q(4),
+ opt => opt_out_type_4_g);
+ io_l_en_o(4) <= io_en_f (en => en2_s, dat => q_q(4),
+ opt => opt_out_type_4_g);
+
+ -- bit 3
+ io_l_o(3) <= io_out_f(dat => q_q(3),
+ opt => opt_out_type_3_g);
+ io_l_en_o(3) <= io_en_f (en => en2_s, dat => q_q(3),
+ opt => opt_out_type_3_g);
+
+ -- bit 2
+ io_l_o(2) <= io_out_f(dat => q_q(2),
+ opt => opt_out_type_2_g);
+ io_l_en_o(2) <= io_en_f (en => en2_s, dat => q_q(2),
+ opt => opt_out_type_2_g);
+
+ -- bit 1
+ io_l_o(1) <= io_out_f(dat => q_q(1),
+ opt => opt_out_type_1_g);
+ io_l_en_o(1) <= io_en_f (en => en2_s, dat => q_q(1),
+ opt => opt_out_type_1_g);
+
+ -- bit 0
+ io_l_o(0) <= io_out_f(dat => q_q(0),
+ opt => opt_out_type_0_g);
+ io_l_en_o(0) <= io_en_f (en => en2_s, dat => q_q(0),
+ opt => opt_out_type_0_g);
+
+ end process out_driver;
+ --
+ -----------------------------------------------------------------------------
+
+end rtl;
tags/rel_1_2/rtl/vhdl/t400_io_l.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_skip-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_skip-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_skip-c.vhd (revision 180)
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- The skip unit.
+-- Skip conditions are checked here and communicated to the decoder unit.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_skip_rtl_c0 of t400_skip is
+
+ for rtl
+ end for;
+
+end t400_skip_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_skip-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl-c.vhd
===================================================================
--- tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl-c.vhd (nonexistent)
+++ tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl-c.vhd (revision 180)
@@ -0,0 +1,18 @@
+-------------------------------------------------------------------------------
+--
+-- The Data memory controller.
+--
+-- $Id$
+--
+-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved
+--
+-------------------------------------------------------------------------------
+
+configuration t400_dmem_ctrl_rtl_c0 of t400_dmem_ctrl is
+
+ for rtl
+ end for;
+
+end t400_dmem_ctrl_rtl_c0;
tags/rel_1_2/rtl/vhdl/t400_dmem_ctrl-c.vhd
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/CHANGELOG
===================================================================
--- tags/rel_1_2/CHANGELOG (nonexistent)
+++ tags/rel_1_2/CHANGELOG (revision 180)
@@ -0,0 +1,31 @@
+
+Change log for the T400 uController core
+========================================
+Version: $Id$
+
+
+Release 1.1
+-----------
+
+* code optimizations in the decoder to reduce LUT usage with
+ Xilinx ISE/XST.
+
+* synthesis templates for QuartusII and ISE.
+
+* updated version of hex2rom utility for RTL ROM generation
+ (keeps compatibility with QuartusII 7.2).
+
+
+Release 1.0
+-----------
+
+* Production test plus related testbench added.
+
+* Bugfix for
+ "Timer skipped in T421 configuration"
+
+* T421 system and testbench added.
+
+* T410 system and testbench added.
+
+* Regression test suite environment enhanced for T421 system.
tags/rel_1_2/CHANGELOG
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sim/rtl_sim/Makefile
===================================================================
--- tags/rel_1_2/sim/rtl_sim/Makefile (nonexistent)
+++ tags/rel_1_2/sim/rtl_sim/Makefile (revision 180)
@@ -0,0 +1,461 @@
+##############################################################################
+#
+# Makefile for the T400 Core project.
+#
+# $Id$
+#
+# The dependencies for all VHDL source files are stored here.
+#
+# Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
+#
+# All rights reserved
+#
+##############################################################################
+
+
+PROJECT_DIR = ../..
+RTL_DIR = $(PROJECT_DIR)/rtl/vhdl
+TECH_DIR = $(PROJECT_DIR)/rtl/tech/cyclone
+GTECH_DIR = $(PROJECT_DIR)/rtl/tech/generic
+SYSTEM_DIR = $(RTL_DIR)/system
+BENCH_DIR = $(PROJECT_DIR)/bench/vhdl
+
+ANALYZE=ghdl -a --std=87 --workdir=work
+ELABORATE=ghdl -e -Wl,-s --std=87 --workdir=work
+
+.PHONY: all
+all: work elaborate
+
+work:
+ mkdir work
+
+
+##############################################################################
+# Technology dependent parts
+#
+work/t400_tech_comp_pack-p.o: $(PROJECT_DIR)/rtl/tech/t400_tech_comp_pack-p.vhd
+ $(ANALYZE) $<
+
+work/t400_por.o: $(TECH_DIR)/t400_por.vhd
+ $(ANALYZE) $<
+work/t400_por-c.o: $(TECH_DIR)/t400_por-c.vhd \
+ work/t400_por.o
+ $(ANALYZE) $<
+
+work/generic_ram.o: $(GTECH_DIR)/generic_ram.vhd
+ $(ANALYZE) $<
+work/generic_ram-c.o: $(GTECH_DIR)/generic_ram-c.vhd \
+ work/generic_ram.o
+ $(ANALYZE) $<
+
+work/generic_ram_ena.o: $(GTECH_DIR)/generic_ram_ena.vhd
+ $(ANALYZE) $<
+work/generic_ram_ena-c.o: $(GTECH_DIR)/generic_ram_ena-c.vhd \
+ work/generic_ram_ena.o
+ $(ANALYZE) $<
+#
+##############################################################################
+
+
+##############################################################################
+# T400 Core
+#
+work/t400_opt_pack-p.o: $(RTL_DIR)/t400_opt_pack-p.vhd
+ $(ANALYZE) $<
+
+work/t400_pack-p.o: $(RTL_DIR)/t400_pack-p.vhd
+ $(ANALYZE) $<
+
+work/t400_comp_pack-p.o: $(RTL_DIR)/t400_comp_pack-p.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+
+work/t400_io_pack-p.o: $(RTL_DIR)/t400_io_pack-p.vhd \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+
+work/t400_clkgen.o: $(RTL_DIR)/t400_clkgen.vhd \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+work/t400_clkgen-c.o: $(RTL_DIR)/t400_clkgen-c.vhd \
+ work/t400_clkgen.o
+ $(ANALYZE) $<
+
+work/t400_reset.o: $(RTL_DIR)/t400_reset.vhd \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+work/t400_reset-c.o: $(RTL_DIR)/t400_reset-c.vhd \
+ work/t400_reset.o
+ $(ANALYZE) $<
+
+work/t400_stack.o: $(RTL_DIR)/t400_stack.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/tb_pack-p.o
+ $(ANALYZE) $<
+work/t400_stack-c.o: $(RTL_DIR)/t400_stack-c.vhd \
+ work/t400_stack.o
+ $(ANALYZE) $<
+
+work/t400_pmem_ctrl.o: $(RTL_DIR)/t400_pmem_ctrl.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/tb_pack-p.o
+ $(ANALYZE) $<
+work/t400_pmem_ctrl-c.o: $(RTL_DIR)/t400_pmem_ctrl-c.vhd \
+ work/t400_pmem_ctrl.o
+ $(ANALYZE) $<
+
+work/t400_alu.o: $(RTL_DIR)/t400_alu.vhd \
+ work/t400_pack-p.o \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+work/t400_alu-c.o: $(RTL_DIR)/t400_alu-c.vhd \
+ work/t400_alu.o
+ $(ANALYZE) $<
+
+work/t400_dmem_ctrl.o: $(RTL_DIR)/t400_dmem_ctrl.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+work/t400_dmem_ctrl-c.o: $(RTL_DIR)/t400_dmem_ctrl-c.vhd \
+ work/t400_dmem_ctrl.o
+ $(ANALYZE) $<
+
+work/t400_skip.o: $(RTL_DIR)/t400_skip.vhd \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+work/t400_skip-c.o: $(RTL_DIR)/t400_skip-c.vhd \
+ work/t400_skip.o
+ $(ANALYZE) $<
+
+work/t400_mnemonic_pack-p.o: $(RTL_DIR)/t400_mnemonic_pack-p.vhd \
+ work/t400_pack-p.o \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+
+work/t400_decoder.o: $(RTL_DIR)/t400_decoder.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/t400_mnemonic_pack-p.o
+ $(ANALYZE) $<
+work/t400_decoder-c.o: $(RTL_DIR)/t400_decoder-c.vhd \
+ work/t400_decoder.o
+ $(ANALYZE) $<
+
+work/t400_io_l.o: $(RTL_DIR)/t400_io_l.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/t400_io_pack-p.o
+ $(ANALYZE) $<
+work/t400_io_l-c.o: $(RTL_DIR)/t400_io_l-c.vhd \
+ work/t400_io_l.o
+ $(ANALYZE) $<
+
+work/t400_io_d.o: $(RTL_DIR)/t400_io_d.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/t400_io_pack-p.o
+ $(ANALYZE) $<
+work/t400_io_d-c.o: $(RTL_DIR)/t400_io_d-c.vhd \
+ work/t400_io_d.o
+ $(ANALYZE) $<
+
+work/t400_io_g.o: $(RTL_DIR)/t400_io_g.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/t400_io_pack-p.o
+ $(ANALYZE) $<
+work/t400_io_g-c.o: $(RTL_DIR)/t400_io_g-c.vhd \
+ work/t400_io_g.o
+ $(ANALYZE) $<
+
+work/t400_io_in.o: $(RTL_DIR)/t400_io_in.vhd \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+work/t400_io_in-c.o: $(RTL_DIR)/t400_io_in-c.vhd \
+ work/t400_io_in.o
+ $(ANALYZE) $<
+
+work/t400_sio.o: $(RTL_DIR)/t400_sio.vhd \
+ work/t400_pack-p.o \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+work/t400_sio-c.o: $(RTL_DIR)/t400_sio-c.vhd \
+ work/t400_sio.o
+ $(ANALYZE) $<
+
+work/t400_timer.o: $(RTL_DIR)/t400_timer.vhd \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+work/t400_timer-c.o: $(RTL_DIR)/t400_timer-c.vhd \
+ work/t400_timer.o
+ $(ANALYZE) $<
+
+work/t400_core.o: $(RTL_DIR)/t400_core.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_pack-p.o \
+ work/t400_comp_pack-p.o
+ $(ANALYZE) $<
+work/t400_core-c.o: $(RTL_DIR)/t400_core-c.vhd \
+ work/t400_clkgen-c.o \
+ work/t400_reset-c.o \
+ work/t400_pmem_ctrl-c.o \
+ work/t400_dmem_ctrl-c.o \
+ work/t400_decoder-c.o \
+ work/t400_skip-c.o \
+ work/t400_alu-c.o \
+ work/t400_stack-c.o \
+ work/t400_io_l-c.o \
+ work/t400_io_d-c.o \
+ work/t400_io_g-c.o \
+ work/t400_io_in-c.o \
+ work/t400_sio-c.o \
+ work/t400_timer-c.o \
+ work/t400_core.o
+ $(ANALYZE) $<
+
+work/t400_core_comp_pack-p.o: $(RTL_DIR)/t400_core_comp_pack-p.vhd \
+ work/t400_opt_pack-p.o
+ $(ANALYZE) $<
+#
+##############################################################################
+
+
+##############################################################################
+# T400 Systems
+#
+work/t410_rom-e.o: $(SYSTEM_DIR)/t410_rom-e.vhd
+ $(ANALYZE) $<
+work/t420_rom-e.o: $(SYSTEM_DIR)/t420_rom-e.vhd
+ $(ANALYZE) $<
+
+work/t410_notri.o: $(SYSTEM_DIR)/t410_notri.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_core_comp_pack-p.o \
+ work/t400_tech_comp_pack-p.o
+ $(ANALYZE) $<
+work/t410_notri-c.o: $(SYSTEM_DIR)/t410_notri-c.vhd \
+ work/t400_core-c.o \
+ work/generic_ram_ena-c.o \
+ work/t410_rom-lpm-c.o \
+ work/t400_por-c.o \
+ work/t410_notri.o
+ $(ANALYZE) $<
+
+work/t420_notri.o: $(SYSTEM_DIR)/t420_notri.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_core_comp_pack-p.o \
+ work/t400_tech_comp_pack-p.o
+ $(ANALYZE) $<
+work/t420_notri-c.o: $(SYSTEM_DIR)/t420_notri-c.vhd \
+ work/t400_core-c.o \
+ work/generic_ram_ena-c.o \
+ work/t420_rom-lpm-c.o \
+ work/t400_por-c.o \
+ work/t420_notri.o
+ $(ANALYZE) $<
+
+work/t400_system_comp_pack-p.o: $(SYSTEM_DIR)/t400_system_comp_pack-p.vhd
+ $(ANALYZE) $<
+
+work/t410.o: $(SYSTEM_DIR)/t410.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/t410-c.o: $(SYSTEM_DIR)/t410-c.vhd \
+ work/t410_notri-c.o \
+ work/t410.o
+ $(ANALYZE) $<
+
+work/t411.o: $(SYSTEM_DIR)/t411.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/t411-c.o: $(SYSTEM_DIR)/t411-c.vhd \
+ work/t410_notri-c.o \
+ work/t411.o
+ $(ANALYZE) $<
+
+work/t420.o: $(SYSTEM_DIR)/t420.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/t420-c.o: $(SYSTEM_DIR)/t420-c.vhd \
+ work/t420_notri-c.o \
+ work/t420.o
+ $(ANALYZE) $<
+
+work/t421.o: $(SYSTEM_DIR)/t421.vhd \
+ work/t400_opt_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/t421-c.o: $(SYSTEM_DIR)/t421-c.vhd \
+ work/t420_notri-c.o \
+ work/t421.o
+ $(ANALYZE) $<
+#
+##############################################################################
+
+
+##############################################################################
+# Testbenches
+#
+work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd \
+ work/t400_pack-p.o
+ $(ANALYZE) $<
+
+work/lpm_rom.o: $(BENCH_DIR)/lpm_rom.vhd
+ $(ANALYZE) $<
+
+work/lpm_ram_dq.o: $(BENCH_DIR)/lpm_ram_dq.vhd
+ $(ANALYZE) $<
+
+work/t410_rom-lpm-a.o: $(BENCH_DIR)/t410_rom-lpm-a.vhd \
+ work/t410_rom-e.o
+ $(ANALYZE) $<
+work/t410_rom-lpm-c.o: $(BENCH_DIR)/t410_rom-lpm-c.vhd \
+ work/lpm_rom.o \
+ work/t410_rom-lpm-a.o
+ $(ANALYZE) $<
+
+work/t420_rom-lpm-a.o: $(BENCH_DIR)/t420_rom-lpm-a.vhd \
+ work/t420_rom-e.o
+ $(ANALYZE) $<
+work/t420_rom-lpm-c.o: $(BENCH_DIR)/t420_rom-lpm-c.vhd \
+ work/lpm_rom.o \
+ work/t420_rom-lpm-a.o
+ $(ANALYZE) $<
+
+work/tb_elems.o: $(BENCH_DIR)/tb_elems.vhd
+ $(ANALYZE) $<
+work/tb_elems-c.o: $(BENCH_DIR)/tb_elems-c.vhd \
+ work/tb_elems.o
+ $(ANALYZE) $<
+
+work/tb_t410.o: $(BENCH_DIR)/tb_t410.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_t410-c.o: $(BENCH_DIR)/tb_t410-c.vhd \
+ work/t410-c.o \
+ work/tb_elems-c.o \
+ work/tb_t410.o
+ $(ANALYZE) $<
+
+work/tb_t411.o: $(BENCH_DIR)/tb_t411.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_t411-c.o: $(BENCH_DIR)/tb_t411-c.vhd \
+ work/t411-c.o \
+ work/tb_elems-c.o \
+ work/tb_t411.o
+ $(ANALYZE) $<
+
+work/tb_t420.o: $(BENCH_DIR)/tb_t420.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_t420-c.o: $(BENCH_DIR)/tb_t420-c.vhd \
+ work/t420-c.o \
+ work/tb_elems-c.o \
+ work/tb_t420.o
+ $(ANALYZE) $<
+
+work/tb_t421.o: $(BENCH_DIR)/tb_t421.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_t421-c.o: $(BENCH_DIR)/tb_t421-c.vhd \
+ work/t421-c.o \
+ work/tb_elems-c.o \
+ work/tb_t421.o
+ $(ANALYZE) $<
+
+work/tb_int.o: $(BENCH_DIR)/tb_int.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_int-c.o: $(BENCH_DIR)/tb_int-c.vhd \
+ work/t420-c.o \
+ work/tb_elems-c.o \
+ work/tb_int.o
+ $(ANALYZE) $<
+
+work/tb_microbus.o: $(BENCH_DIR)/tb_microbus.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_microbus-c.o: $(BENCH_DIR)/tb_microbus-c.vhd \
+ work/t420-c.o \
+ work/tb_elems-c.o \
+ work/tb_microbus.o
+ $(ANALYZE) $<
+
+work/tb_prod.o: $(BENCH_DIR)/tb_prod.vhd \
+ work/t400_opt_pack-p.o \
+ work/tb_pack-p.o \
+ work/t400_system_comp_pack-p.o
+ $(ANALYZE) $<
+work/tb_prod-c.o: $(BENCH_DIR)/tb_prod-c.vhd \
+ work/t420-c.o \
+ work/tb_elems-c.o \
+ work/tb_prod.o
+ $(ANALYZE) $<
+#
+##############################################################################
+
+
+.PHONY: elaborate
+elaborate: tb_t410_behav_c0 tb_t411_behav_c0 \
+ tb_t420_behav_c0 tb_t421_behav_c0 \
+ tb_int_behav_c0 tb_microbus_behav_c0 tb_prod_behav_c0
+
+tb_t410_behav_c0: work/tb_t410-c.o
+ $(ELABORATE) $@
+
+tb_t411_behav_c0: work/tb_t411-c.o
+ $(ELABORATE) $@
+
+tb_t420_behav_c0: work/tb_t420-c.o
+ $(ELABORATE) $@
+
+tb_t421_behav_c0: work/tb_t421-c.o
+ $(ELABORATE) $@
+
+tb_int_behav_c0: work/tb_int-c.o
+ $(ELABORATE) $@
+
+tb_microbus_behav_c0: work/tb_microbus-c.o
+ $(ELABORATE) $@
+
+tb_prod_behav_c0: work/tb_prod-c.o
+ $(ELABORATE) $@
+
+
+.PHONY: analyze
+analyze: work \
+ work/tb_t410-c.o work/tb_t411-c.o \
+ work/tb_t420-c.o work/tb_t421-c.o \
+ work/tb_int-c.o work/tb_microbus-c.o work/tb_prod-c.o
+
+
+.PHONY: clean
+clean:
+ rm -rf *~ UNUSED *hex \
+ tb_t410_behav_c0 \
+ tb_t411_behav_c0 \
+ tb_t420_behav_c0 \
+ tb_t421_behav_c0 \
+ tb_int_behav_c0 \
+ tb_microbus_behav_c0 \
+ tb_prod_behav_c0 \
+ work
tags/rel_1_2/sim/rtl_sim/Makefile
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/include/pass_fail.asm
===================================================================
--- tags/rel_1_2/sw/verif/include/pass_fail.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/include/pass_fail.asm (revision 180)
@@ -0,0 +1,56 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Provides pass/fail signalling via port L.
+ ;;
+ ;; Result value is expected in accumuator.
+ ;;
+ ;; Signalling on L:
+ ;; 0x0R
+ ;; 0xaR
+ ;; 0x5R
+ ;; 0x0R -> pass
+ ;; 0xfR -> fail
+ ;;
+
+ ;; catch spurious code execution
+ jmp fail
+
+pass:
+ lei 0x4
+ ;; save result to M
+ x 0x0
+ ;; output 0x0R to Q
+ clra
+ camq
+ ;; output 0xaR to Q
+ aisc 0xa
+ camq
+ ;; output 0x5R to Q
+ clra
+ aisc 0x5
+ camq
+ ;; output 0x0R to Q
+ clra
+ camq
+ jp .
+
+fail:
+ lei 0x4
+ ;; save result to M
+ x 0x0
+ ;; output 0x0R to Q
+ clra
+ camq
+ ;; output 0xaR to Q
+ aisc 0xa
+ camq
+ ;; output 0x5R to Q
+ clra
+ aisc 0x5
+ camq
+ ;; output 0xfR to Q
+ clra
+ aisc 0xf
+ camq
+ jp .
tags/rel_1_2/sw/verif/include/pass_fail.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/include/int_macros.inc
===================================================================
--- tags/rel_1_2/sw/verif/include/int_macros.inc (nonexistent)
+++ tags/rel_1_2/sw/verif/include/int_macros.inc (revision 180)
@@ -0,0 +1,110 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Defines macros for interrupt tests.
+ ;;
+
+ ;; -------------------------------------------------------------------
+ ;; Save current A, M and C to M(3,15), M(3,14) and M(3,13).
+ ;;
+save_a_m_c MACRO
+ xad 3, 15 ; save A to M(3,15)
+
+ x 0 ; save current M
+ xad 3, 14 ; to M(3,14)
+
+ smb 0x0 ; save C
+ skc ; to M(3,13)
+ rmb 0x0 ;
+ x 0 ;
+ xad 3, 13 ;
+ ENDM
+
+
+ ;; -------------------------------------------------------------------
+ ;; Check SA against specified address
+ ;;
+check_sa MACRO addr
+ ;; request nibble 0 of SA
+ ogi 0x0
+ inl
+ ;; check this nibble
+ x 0
+ clra
+ IF addr & 0xf <> 0
+ aisc addr & 0xf
+ ENDIF
+ ske
+ jmp fail
+
+ ;; request nibble 1 of SA
+ ogi 0x1
+ inl
+ ;; check this nibble
+ x 0
+ clra
+ IF addr & 0x0f0 <> 0
+ aisc (addr >> 4) & 0xf
+ ENDIF
+ ske
+ jmp fail
+
+ ;; request nibble 2 of SA
+ ogi 0x2
+ inl
+ ;; check this nibble
+ x 0
+ clra
+ IF addr & 0xf00 <> 0
+ aisc (addr >> 8) & 0xf
+ ENDIF
+ ske
+ jmp fail
+
+ ENDM
+
+
+ ;; -------------------------------------------------------------------
+ ;; Restore C, M and A from M(3,13), M(3,14) and M(3,15)
+ ;;
+restore_c_m_a MACRO
+ xad 3, 13 ; restore C
+ x 0 ; from M(3,13)
+ rc ;
+ skmbz 0x0 ;
+ sc ;
+
+ xad 3, 14 ; restore current M
+ x 0 ; from M(3,14)
+
+ xad 3, 15 ; restore A
+ ENDM
+
+
+ ;; -------------------------------------------------------------------
+ ;; Flag that interrupt occured in M(3,12).1
+ ;;
+int_flag_set MACRO
+ clra
+ aisc 0x1
+ xad 3, 12
+ ENDM
+
+ ;; -------------------------------------------------------------------
+ ;; Clear 'interrupt occured' flag
+ ;;
+int_flag_clear MACRO
+ clra
+ xad 3, 12
+ ENDM
+
+ ;; -------------------------------------------------------------------
+ ;; Check interrupt occurence
+ ;;
+int_flag_check MACRO
+ lbi 3, 12
+ skmbz 0x0
+ jp +
+ jmp fail ; no interrupt!
++ lbi 0, 0
+ ENDM
tags/rel_1_2/sw/verif/include/int_macros.inc
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/include/int_pass_fail.asm
===================================================================
--- tags/rel_1_2/sw/verif/include/int_pass_fail.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/include/int_pass_fail.asm (revision 180)
@@ -0,0 +1,53 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Provides pass/fail signalling via port D for interrupt tests.
+ ;;
+ ;; Signalling on D:
+ ;; 0x1
+ ;; 0x2
+ ;; 0x4
+ ;; 0x8
+ ;; 0xf -> pass
+ ;; 0x0 -> fail
+ ;;
+
+ ;; catch spurious code execution
+ jmp fail
+
+PROLOGUE MACRO
+ ;; output 0x1 on D
+ clra
+ aisc 0x1
+ cab
+ obd
+ ;; output 0x2 on D
+ aisc 0x1
+ cab
+ obd
+ ;; output 0x4 on D
+ aisc 0x2
+ cab
+ obd
+ ;; output 0x8 on D
+ aisc 0x4
+ cab
+ obd
+ ENDM
+
+
+pass:
+ PROLOGUE
+ ;; output 0xf to D
+ aisc 0x7
+ cab
+ obd
+ jp .
+
+fail:
+ PROLOGUE
+ ;; output 0x0 to D
+ clra
+ cab
+ obd
+ jp .
tags/rel_1_2/sw/verif/include/int_pass_fail.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/include/Makefile.core
===================================================================
--- tags/rel_1_2/sw/verif/include/Makefile.core (nonexistent)
+++ tags/rel_1_2/sw/verif/include/Makefile.core (revision 180)
@@ -0,0 +1,45 @@
+
+SIM_DIR = $(PROJECT_DIR)/sim/rtl_sim
+VERIF_DIR = $(PROJECT_DIR)/sw/verif
+
+# determine allowed targets
+TARGETS = $(wildcard t4* int mb prod)
+
+.PHONY: all
+all: $(TARGETS)
+
+.PHONY: t41x
+t41x: $(SIM_DIR)/rom_41x.hex
+
+.PHONY: t42x
+t42x: $(SIM_DIR)/rom_42x.hex
+
+.PHONY: t420
+t420: t42x
+
+.PHONY: int
+int: t42x
+
+.PHONY: mb
+mb: t42x
+
+.PHONY: prod
+prod: t42x
+
+$(SIM_DIR)/rom_41x.hex: $(MODULE)_41x.p
+ p2hex $< $@
+
+$(SIM_DIR)/rom_42x.hex: $(MODULE)_42x.p
+ p2hex $< $@
+
+$(MODULE)_41x.p: $(MODULE).asm
+ asl -i $(VERIF_DIR)/include -cpu COP410 -L \
+ -o $(MODULE)_41x.p -olist $(MODULE)_41x.lst $<
+
+$(MODULE)_42x.p: $(MODULE).asm
+ asl -i $(VERIF_DIR)/include -cpu COP420 -L \
+ -o $(MODULE)_42x.p -olist $(MODULE)_42x.lst $<
+
+.PHONY: clean
+clean:
+ rm -f *.p *~ *.lst
Index: tags/rel_1_2/sw/verif/include/Makefile
===================================================================
--- tags/rel_1_2/sw/verif/include/Makefile (nonexistent)
+++ tags/rel_1_2/sw/verif/include/Makefile (revision 180)
@@ -0,0 +1,3 @@
+MODULE = test
+
+include $(PROJECT_DIR)/sw/verif/include/Makefile.core
Index: tags/rel_1_2/sw/verif/black_box/skgbz/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/skgbz/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/skgbz/test.asm (revision 180)
@@ -0,0 +1,115 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKGBZ instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; output 0x0 on G
+ x 0x0
+ omg
+ ;; check G0
+ skgbz 0x0
+ jmp fail
+ ;; check G1
+ skgbz 0x1
+ jmp fail
+ ;; check G2
+ skgbz 0x2
+ jmp fail
+ ;; check G3
+ skgbz 0x3
+ jmp fail
+
+ ;; output 0x1 on G
+ clra
+ aisc 0x1
+ x 0x0
+ omg
+ ;; check G0
+ skgbz 0x0
+ jmp ok_0
+ jmp fail
+ok_0:
+ ;; check G1
+ skgbz 0x1
+ jmp fail
+ ;; check G2
+ skgbz 0x2
+ jmp fail
+ ;; check G3
+ skgbz 0x3
+ jmp fail
+
+ ;; output 0x2 on G
+ clra
+ aisc 0x2
+ x 0x0
+ omg
+ ;; check G0
+ skgbz 0x0
+ jmp fail
+ ;; check G1
+ skgbz 0x1
+ jmp ok_1
+ jmp fail
+ok_1:
+ ;; check G2
+ skgbz 0x2
+ jmp fail
+ ;; check G3
+ skgbz 0x3
+ jmp fail
+
+ ;; output 0x4 on G
+ clra
+ aisc 0x4
+ x 0x0
+ omg
+ ;; check G0
+ skgbz 0x0
+ jmp fail
+ ;; check G1
+ skgbz 0x1
+ jmp fail
+ ;; check G2
+ skgbz 0x2
+ jmp ok_2
+ jmp fail
+ok_2:
+ ;; check G3
+ skgbz 0x3
+ jmp fail
+
+ ;; output 0x1 on G to break monitoring sequence
+ ;; on T411L
+ clra
+ aisc 0x1
+ x 0x0
+ omg
+
+ ;; output 0x8 on G
+ clra
+ aisc 0x8
+ x 0x0
+ omg
+ ;; check G0
+ skgbz 0x0
+ jmp fail
+ ;; check G1
+ skgbz 0x1
+ jmp fail
+ ;; check G2
+ skgbz 0x2
+ jmp fail
+ ;; check G3
+ skgbz 0x3
+ jmp pass
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/skgbz/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/skgbz/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skgbz/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/rmb_smb/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/rmb_smb/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/rmb_smb/test.asm (revision 180)
@@ -0,0 +1,90 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the RMB and SMB instructions.
+ ;; Starting with 0 in M, all bits are set and then reset.
+ ;; All intermediate values are checked.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+
+ ;; *******************************************************************
+ ;; Set bits
+ ;;
+
+ ;; clear M
+ X 0x0
+ clra
+
+ ;; set bit 0
+ smb 0x0
+ aisc 0x1
+ ske
+ jmp fail
+
+ ;; set bit 1
+ smb 0x1
+ aisc 0x2
+ ske
+ jmp fail
+
+ ;; set bit 2
+ smb 0x2
+ aisc 0x4
+ ske
+ jmp fail
+
+ ;; set bit 3
+ smb 0x3
+ aisc 0x8
+ ske
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; Reset bits
+ ;;
+
+ ;; reset bit 0
+ rmb 0x0
+ comp
+ aisc 0x1
+ comp
+ ske
+ jmp fail
+
+ ;; reset bit 1
+ rmb 0x1
+ comp
+ aisc 0x2
+ comp
+ ske
+ jmp fail
+
+ ;; reset bit 2
+ rmb 0x2
+ comp
+ aisc 0x4
+ comp
+ ske
+ jmp fail
+
+ ;; reset bit 3
+ rmb 0x3
+ comp
+ aisc 0x8
+ comp
+ ske
+ jmp fail
+
+
+ ;; test passed
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/rmb_smb/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/rmb_smb/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/rmb_smb/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/clra/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/clra/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/clra/test.asm (revision 180)
@@ -0,0 +1,31 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the CLRA instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M0 with 0x0
+ rmb 0x3
+ rmb 0x2
+ rmb 0x1
+ rmb 0x0
+
+ ;; test for initial 0 in a
+ ske
+ jmp fail
+
+ ;; test for clearing all bits in a
+ aisc 0xf
+ clra
+ ske
+ jmp fail
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/clra/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/clra/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/clra/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skmbz/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/skmbz/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/skmbz/test.asm (revision 180)
@@ -0,0 +1,51 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKGMZ instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload two ram digits with test data
+ lbi 0, 0
+ stii 0x5
+ lbi 0, 9
+ stii 0xa
+
+ ;; check SKBMZs on 0x5
+ lbi 0, 0
+ skmbz 0
+ jp ok_5_0
+ jmp fail
+ok_5_0:
+ skmbz 1
+ jmp fail
+ skmbz 2
+ jp ok_5_2
+ jmp fail
+ok_5_2:
+ skmbz 3
+ jmp fail
+
+ ;; check SKMBZ on 0xa
+ lbi 0, 9
+ skmbz 0
+ jmp fail
+ skmbz 1
+ jp ok_a_1
+ jmp fail
+ok_a_1:
+ skmbz 2
+ jmp fail
+ skmbz 3
+ jp ok_a_3
+ jmp fail
+ok_a_3:
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/skmbz/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/skmbz/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skmbz/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/rc_sc/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/rc_sc/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/rc_sc/test.asm (revision 180)
@@ -0,0 +1,46 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the RC and SC instructions.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M with 0x8
+ smb 0x3
+ rmb 0x2
+ rmb 0x1
+ rmb 0x0
+
+ ;; check initial value of C
+ skc
+ jmp ok_res
+ jmp fail
+ok_res:
+
+ sc
+ skc
+ jmp fail
+
+ rc
+ skc
+ jmp ok_rc
+ jmp fail
+ok_rc:
+
+ asc
+ asc
+ nop
+ skc
+ jmp fail
+
+ rc
+ skc
+ jmp pass
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/rc_sc/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/rc_sc/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/rc_sc/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/lqid/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/lqid/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/lqid/test.asm (revision 180)
@@ -0,0 +1,329 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the LQID and INL instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload reference data
+ lbi 0, 0
+ stii 0x0
+ lbi 0, 9
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+
+ lbi 1, 0
+ stii 0x8
+ lbi 1, 9
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+
+
+load MACRO addr, noadd
+ lbi 2, 0
+ stii addr & 0x0f
+ clra
+ IF noadd <> 1
+ aisc (addr >> 4) & 0x0f
+ ENDIF
+ lbi 2, 0
+ lqid
+ inl
+ ENDM
+
+ ;; enable Q output to L
+ lei 0x4
+
+ ;;
+ load read_block_0_55, 0
+ lbi 0, 8 + 5
+ ske
+ jmp fail
+ lbi 2, 0
+ ske
+ jmp fail
+
+ ;;
+ load read_block_0_aa, 0
+ lbi 1, 0xa
+ ske
+ jmp fail
+ lbi 2, 0
+ ske
+ jmp fail
+
+ ;;
+ load read_block_0_0f, 0
+ lbi 1, 0xf
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ ske
+ jmp fail
+
+ ;;
+ load read_block_0_f0, 0
+ lbi 0, 0
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+
+ jmp block_1
+
+
+ ;; -------------------------------------------------------------------
+ ;; Block 0 testdata
+ ;;
+ org 0x064
+read_block_0_55:
+ db 0x55
+
+ org 0x071
+read_block_0_aa:
+ db 0xaa
+
+ org 0x0a9
+read_block_0_0f:
+ db 0x0f
+
+ org 0x0ff
+read_block_0_f0:
+ db 0xf0
+
+
+ ;; -------------------------------------------------------------------
+ ;; Block 1 testdata
+ ;;
+ org 0x105
+read_block_1_68:
+ db 0x68
+
+ org 0x120
+read_block_1_b1:
+ db 0xb1
+
+ org 0x17e
+read_block_1_04:
+ db 0x04
+
+ org 0x1c2
+read_block_1_db:
+ db 0xdb
+
+
+ org 0x128
+block_1:
+ ;;
+ load read_block_1_68, 1
+ lbi 1, 0
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x6
+ ske
+ jmp fail
+
+ ;;
+ load read_block_1_b1, 0
+ lbi 0, 8 + 1
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0xb
+ ske
+ jmp fail
+
+ ;;
+ load read_block_1_04, 0
+ lbi 0, 8 + 4
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ ske
+ jmp fail
+
+ ;;
+ load read_block_1_db, 0
+ lbi 1, 0xb
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0xd
+ ske
+ jmp fail
+
+
+ IF MOMCPUNAME <> "COP420"
+ jmp pass
+ ELSEIF
+ jmp block_2
+ ENDIF
+
+
+ org 0x180
+ include "pass_fail.asm"
+
+
+ IF MOMCPUNAME = "COP420"
+
+ ;; -------------------------------------------------------------------
+ ;; Block 2 testdata
+ ;;
+ org 0x211
+read_block_2_34:
+ db 0x34
+
+ org 0x237
+read_block_2_91:
+ db 0x91
+
+ org 0x254
+read_block_2_89:
+ db 0x89
+
+ org 0x296
+read_block_2_3c:
+ db 0x3c
+
+
+ org 0x2b0
+block_2:
+ ;;
+ load read_block_2_34, 0
+ lbi 0, 8 + 4
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+
+ ;;
+ load read_block_2_91, 0
+ lbi 0, 8 + 1
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x9
+ ske
+ jmp fail
+
+ ;;
+ load read_block_2_89, 0
+ lbi 1, 9
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x8
+ ske
+ jmp fail
+
+ ;;
+ load read_block_2_3c, 0
+ lbi 1, 0xc
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+
+ jmp block_3
+
+
+ ;; -------------------------------------------------------------------
+ ;; Block 3 testdata
+ ;;
+ org 0x300
+read_block_3_76:
+ db 0x76
+
+ org 0x34b
+read_block_3_33:
+ db 0x33
+
+ org 0x3a4
+read_block_3_e9:
+ db 0xe9
+
+ org 0x3e0
+read_block_3_9d:
+ db 0x9d
+
+
+ org 0x350
+block_3:
+ ;;
+ load read_block_3_76, 1
+ lbi 0, 8 + 6
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x7
+ ske
+ jmp fail
+
+ ;;
+ load read_block_3_33, 0
+ lbi 0, 8 + 3
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+
+ ;;
+ load read_block_3_e9, 0
+ lbi 1, 9
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0xe
+ ske
+ jmp fail
+
+ ;;
+ load read_block_3_9d, 0
+ lbi 1, 0xd
+ ske
+ jmp fail
+ lbi 2, 0
+ clra
+ aisc 0x9
+ ske
+ jmp fail
+
+ jmp pass
+
+ ENDIF
tags/rel_1_2/sw/verif/black_box/lqid/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/lqid/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/lqid/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xds/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xds/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xds/test.asm (revision 180)
@@ -0,0 +1,530 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XDS instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+
+ ;; *******************************************************************
+ ;; XOR 0
+ jsr init_ram
+
+ ;; xor 0 in digit 0
+ lbi 0, 0
+ jsr init_bd
+ ;;
+ xds 0 ; 0, 3 = 0x3
+ ;;
+ cba
+ xds 0 ; 0, 2 = 0x2
+ ;;
+ cba
+ xds 0 ; 0, 1 = 0x1
+ ;;
+ cba
+ xds 0 ; 0, 0 = 0x0
+ jmp fail
+
+ ;; xor 0 in digit 1
+ lbi 1, 0
+ jsr init_bd
+ ;;
+ aisc 1 << 2
+ xds 0 ; 1, 3 = 0x7
+ ;;
+ cba
+ aisc 1 << 2
+ xds 0 ; 1, 2 = 0x6
+ ;;
+ cba
+ aisc 1 << 2
+ xds 0 ; 1, 1 = 0x5
+ ;;
+ cba
+ aisc 1 << 2
+ xds 0 ; 1, 0 = 0x4
+ jmp fail
+
+ ;; xor 0 in digit 2
+ lbi 2, 0
+ jsr init_bd
+ ;;
+ aisc 2 << 2
+ xds 0 ; 2, 3 = 0xb
+ ;;
+ cba
+ aisc 2 << 2
+ xds 0 ; 2, 2 = 0xa
+ ;;
+ cba
+ aisc 2 << 2
+ xds 0 ; 2, 1 = 0x9
+ ;;
+ cba
+ aisc 2 << 2
+ xds 0 ; 2, 0 = 0x8
+ jmp fail
+
+ ;; xor 0 in digit 3
+ lbi 3, 0
+ jsr init_bd
+ ;;
+ aisc 3 << 2
+ xds 0 ; 3, 3 = 0xf
+ ;;
+ cba
+ aisc 3 << 2
+ xds 0 ; 3, 2 = 0xe
+ ;;
+ cba
+ aisc 3 << 2
+ xds 0 ; 3, 1 = 0xd
+ ;;
+ cba
+ aisc 3 << 2
+ xds 0 ; 3, 0 = 0xc
+ jmp fail
+ ;; check remaining Br == 3
+ clra
+ cab
+ aisc 0xc
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 1
+ jsr init_ram
+
+ ;;
+ ;; xor 1 in digit 0 & 1
+ ;;
+ lbi 0, 0
+ jsr init_bd
+ ;;
+ xds 1 ; 0, 3 = 0x3
+ ;;
+ cba
+ aisc 1 << 2
+ xds 1 ; 1, 2 = 0x6
+ ;;
+ cba
+ xds 1 ; 0, 1 = 0x1
+ ;;
+ cba
+ aisc 1 << 2
+ xds 1 ; 1, 0 = 0x4
+ jmp fail
+ ;; check remaining Br == 0
+ clra
+ cab
+ aisc 0xf ; RAM init value
+ ske
+ jmp fail
+ ;; reload to Br = 1
+ lbi 1, 0
+ jsr init_bd
+ ;;
+ aisc 1 << 2
+ xds 1 ; 1, 3 = 0x7
+ ;;
+ cba
+ xds 1 ; 0, 2 = 0x2
+ ;;
+ cba
+ aisc 1 << 2
+ xds 1 ; 1, 1 = 0x5
+ ;;
+ cba
+ xds 1 ; 0, 0 = 0x0
+ jmp fail
+ ;; check remaining Br == 1
+ clra
+ cab
+ aisc 0x4
+ ske
+ jmp fail
+
+ ;;
+ ;; xor 1 in digit 2 & 3
+ ;;
+ lbi 2, 0
+ jsr init_bd
+ ;;
+ aisc 2 << 2
+ xds 1 ; 2, 3 = 0xb
+ ;;
+ cba
+ aisc 3 << 2
+ xds 1 ; 3, 2 = 0xe
+ ;;
+ cba
+ aisc 2 << 2
+ xds 1 ; 2, 1 = 0x9
+ ;;
+ cba
+ aisc 3 << 2
+ xds 1 ; 3, 0 = 0xc
+ jmp fail
+ ;; check remaining Br == 2
+ clra
+ cab
+ aisc 0x7 ; RAM init value
+ ske
+ jmp fail
+ ;; reload to Br = 3
+ lbi 3, 0
+ jsr init_bd
+ ;;
+ aisc 3 << 2
+ xds 1 ; 3, 3 = 0xf
+ ;;
+ cba
+ aisc 2 << 2
+ xds 1 ; 2, 2 = 0xa
+ ;;
+ cba
+ aisc 3 << 2
+ xds 1 ; 3, 1 = 0xd
+ ;;
+ cba
+ aisc 2 << 2
+ xds 1 ; 2, 0 = 0x8
+ jmp fail
+ ;; check remaining Br == 3
+ clra
+ cab
+ aisc 0xc
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 2
+ jsr init_ram
+
+ ;;
+ ;; xor 2 in digit 0 & 2
+ ;;
+ lbi 0, 0
+ jsr init_bd
+ ;;
+ xds 2 ; 0, 3 = 0x3
+ ;;
+ cba
+ aisc 2 << 2
+ xds 2 ; 2, 2 = 0xa
+ ;;
+ cba
+ xds 2 ; 0, 1 = 0x1
+ ;;
+ cba
+ aisc 2 << 2
+ xds 2 ; 2, 0 = 0x8
+ jmp fail
+ ;; check remainig Br == 0
+ clra
+ cab
+ aisc 0xf ; RAM init value
+ ske
+ jmp fail
+ ;; reload to Br == 2
+ lbi 2, 0
+ jsr init_bd
+ ;;
+ aisc 2 << 2
+ xds 2 ; 2, 3 = 0xb
+ ;;
+ cba
+ xds 2 ; 0, 2 = 0x2
+ ;;
+ cba
+ aisc 2 << 2
+ xds 2 ; 2, 1 = 0x9
+ ;;
+ cba
+ xds 2 ; 0, 0 = 0x0
+ jmp fail
+ ;; check remainig Br == 2
+ clra
+ cab
+ aisc 0x8
+ ske
+ jmp fail
+
+ ;;
+ ;; xor 2 in digit 1 & 3
+ ;;
+ lbi 1, 0
+ jsr init_bd
+ ;;
+ aisc 1 << 2
+ xds 2 ; 1, 3 = 0x7
+ ;;
+ cba
+ aisc 3 << 2
+ xds 2 ; 3, 2 = 0xe
+ ;;
+ cba
+ aisc 1 << 2
+ xds 2 ; 1, 1 = 0x5
+ ;;
+ cba
+ aisc 3 << 2
+ xds 2 ; 3, 0 = 0xc
+ jmp fail
+ ;; check remaining Br == 1
+ clra
+ cab
+ aisc 0xc ; RAM init value
+ ske
+ jmp fail
+ ;; reload to Br = 3
+ lbi 3, 0
+ jsr init_bd
+ ;;
+ aisc 3 << 2
+ xds 2 ; 3, 3 = 0xf
+ ;;
+ cba
+ aisc 1 << 2
+ xds 2 ; 1, 2 = 0x6
+ ;;
+ cba
+ aisc 3 << 2
+ xds 2 ; 3, 1 = 0xd
+ ;;
+ cba
+ aisc 1 << 2
+ xds 2 ; 1, 0 = 0x4
+ jmp fail
+ ;; check remaining Br == 3
+ clra
+ cab
+ aisc 0xc
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 3
+ jsr init_ram
+
+ ;;
+ ;; xor 3 in digit 0 & 3
+ ;;
+ lbi 0, 0
+ jsr init_bd
+ ;;
+ xds 3 ; 0, 3 = 0x3
+ ;;
+ cba
+ aisc 3 << 2
+ xds 3 ; 3, 2 = 0xe
+ ;;
+ cba
+ xds 3 ; 0, 1 = 0x1
+ ;;
+ cba
+ aisc 3 << 2
+ xds 3 ; 3, 0 = 0xc
+ jmp fail
+ ;; check remaining BR == 0
+ clra
+ cab
+ aisc 0xf ; RAM init value
+ ske
+ jmp fail
+ ;; reload BR = 3
+ lbi 3, 0
+ jsr init_bd
+ ;;
+ aisc 3 << 2
+ xds 3 ; 3, 3 = 0xf
+ ;;
+ cba
+ xds 3 ; 0, 2 = 0x2
+ ;;
+ cba
+ aisc 3 << 2
+ xds 3 ; 3, 1 = 0xb
+ ;;
+ cba
+ xds 3 ; 0, 0 = 0x0
+ jmp fail
+ ;; check remaining BR == 3
+ clra
+ cab
+ aisc 0xc
+ ske
+ jmp fail
+
+ ;;
+ ;; xor 3 in digit 1 & 2
+ ;;
+ lbi 1, 0
+ jsr init_bd
+ ;;
+ aisc 1 << 2
+ xds 3 ; 1, 3 = 0x7
+ ;;
+ cba
+ aisc 2 << 2
+ xds 3 ; 2, 2 = 0xa
+ ;;
+ cba
+ aisc 1 << 2
+ xds 3 ; 1, 1 = 0x5
+ ;;
+ cba
+ aisc 2 << 2
+ xds 3 ; 2, 0 = 0x8
+ jmp fail
+ ;; check remaining BR == 1
+ clra
+ cab
+ aisc 0xc ; RAM init value
+ ske
+ jmp fail
+ ;; reload BR = 2
+ lbi 2, 0
+ jsr init_bd
+ ;;
+ aisc 2 << 2
+ xds 3 ; 2, 3 = 0xb
+ ;;
+ cba
+ aisc 1 << 2
+ xds 3 ; 1, 2 = 0x6
+ ;;
+ cba
+ aisc 2 << 2
+ xds 3 ; 2, 1 = 0x9
+ ;;
+ cba
+ aisc 1 << 2
+ xds 3 ; 1, 0 = 0x5
+ jmp fail
+ ;; check remaining BR == 2
+ clra
+ cab
+ aisc 0x8
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ jmp pass
+
+
+
+
+ org 0x158
+
+ ;; initializes Bd to 3
+init_bd:
+ clra
+ aisc 0x3
+ cab
+ ret
+
+
+ ;; preload digits of each data register
+init_ram:
+ ;; Br = 0
+ lbi 0, 0
+ stii 0xf
+ stii 0xe
+ stii 0xd
+ stii 0xb
+ ;; Br = 1
+ lbi 1, 0
+ stii 0xc
+ stii 0xa
+ stii 0x9
+ stii 0x8
+ ;; Br = 2
+ lbi 2, 0
+ stii 0x7
+ stii 0x6
+ stii 0x5
+ stii 0x4
+ ;; Br = 3
+ lbi 3, 0
+ stii 0x3
+ stii 0x2
+ stii 0x1
+ stii 0x0
+ ret
+
+
+check MACRO dig
+ ;; check dig, 0
+ clra
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ;; check 0, 1
+ clra
+ aisc 0x1
+ cab
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ;; check 0, 2
+ clra
+ aisc 0x2
+ cab
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ;; check 0, 3
+ clra
+ aisc 0x3
+ cab
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ENDM
+
+ ;; check contents of RAM entries
+check_ram:
+ ;; check digit 0
+ lbi 0, 0
+ check 0
+
+ ;; check digit 1
+ lbi 1, 0
+ check 1
+
+ ;; check digit 2
+ lbi 2, 0
+ check 2
+
+ ;; check digit 3
+ lbi 3, 0
+ check 3
+
+ ret
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xds/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xds/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xds/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ld/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/ld/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/ld/test.asm (revision 180)
@@ -0,0 +1,256 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the LD instruction.
+ ;; Br can't be observed directly via XABR on COP41x.
+ ;; Therefore, Br address os observed indirectly via memory content.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload for digit of each data register
+ ;; Br = 0 -> data = 0x1
+ lbi 0x0, 0x0
+ stii 0x1
+ ;; Br = 1 -> data = 0x2
+ lbi 0x1, 0x0
+ stii 0x2
+ ;; Br = 2 -> data = 0x3
+ lbi 0x2, 0x0
+ stii 0x3
+ ;; Br = 3 -> data = 0x4
+ lbi 0x3, 0x0
+ stii 0x4
+
+ ;; *******************************************************************
+ ;; XOR 0
+ ;;
+ ;; Br(0) xor 0
+ lbi 0x0, 0x0
+ ld 0x0
+ ske ; expect no change of Br
+ jmp fail
+
+ ;; Br(1) xor 0
+ lbi 0x1, 0x0
+ ld 0x0
+ ske ; expect no change of Br
+ jmp fail
+
+ ;; Br(2) xor 0
+ lbi 0x2, 0x0
+ ld 0x0
+ ske ; expect no change of Br
+ jmp fail
+
+ ;; Br(3) xor 0
+ lbi 0x3, 0x0
+ ld 0x0
+ ske ; expect no change of Br
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; XOR 1
+ ;;
+ ;; Br(0) xor 1
+ lbi 0x0, 0x0
+ ld 0x1
+ xad 3, 15 ; save load data
+ ;; expect 0x2 at current Br
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ ;; expect 0x1 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x1
+ ske
+ jmp fail
+
+ ;; Br(1) xor 1
+ lbi 0x1, 0x0
+ ld 0x1
+ xad 3, 15 ; save load data
+ ;; expect 0x1 at current Br
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ ;; expect 0x2 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xf
+ nop
+ ske
+ jmp fail
+
+ ;; Br(2) xor 1
+ lbi 0x2, 0x0
+ ld 0x1
+ xad 3, 15 ; save load data
+ ;; expect 0x4 at current Br
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ ;; expect 0x3 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x1
+ nop
+ ske
+ jmp fail
+
+ ;; Br(3) xor 1
+ lbi 0x3, 0x0
+ ld 0x1
+ xad 3, 15 ; save load data
+ ;; expect 0x3 at current Br
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ ;; expect 0x4 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xf
+ nop
+ ske
+ jmp fail
+
+ ;; *******************************************************************
+ ;; XOR 2
+ ;;
+ ;; Br(0) xor 2
+ lbi 0x0, 0x0
+ ld 0x2
+ xad 3, 15 ; save load data
+ ;; expect 0x3 at current Br
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ ;; expect 0x1 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x2
+ ske
+ jmp fail
+
+ ;; Br(1) xor 2
+ lbi 0x1, 0x0
+ ld 0x2
+ xad 3, 15 ; save load data
+ ;; expect 0x4 at current Br
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ ;; expect 0x2 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x2
+ ske
+ jmp fail
+
+ ;; Br(2) xor 2
+ lbi 0x2, 0x0
+ ld 0x2
+ xad 3, 15 ; save load data
+ ;; expect 0x1 at current Br
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ ;; expect 0x3 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xe
+ nop
+ ske
+ jmp fail
+
+ ;; Br(3) xor 2
+ lbi 0x3, 0x0
+ ld 0x2
+ xad 3, 15 ; save load data
+ ;; expect 0x2 at current Br
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ ;; expect 0x4 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xe
+ nop
+ ske
+ jmp fail
+
+ ;; *******************************************************************
+ ;; XOR 3
+ ;;
+ ;; Br(0) xor 3
+ lbi 0x0, 0x0
+ ld 0x3
+ xad 3, 15 ; save load data
+ ;; expect 0x4 at current Br
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ ;; expect 0x1 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x3
+ ske
+ jmp fail
+
+ ;; Br(1) xor 3
+ lbi 0x1, 0x0
+ ld 0x3
+ xad 3, 15 ; save load data
+ ;; expect 0x3 at current Br
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ ;; expect 0x2 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0x1
+ ske
+ jmp fail
+
+ ;; Br(2) xor 3
+ lbi 0x2, 0x0
+ ld 0x3
+ xad 3, 15 ; save load data
+ ;; expect 0x2 at current Br
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ ;; expect 0x3 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xf
+ nop
+ ske
+ jmp fail
+
+ ;; Br(3) xor 3
+ lbi 0x3, 0x0
+ ld 0x3
+ xad 3, 15 ; save load data
+ ;; expect 0x1 at current Br
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ ;; expect 0x4 in accumulator
+ xad 3, 15 ; restore load data
+ aisc 0xd
+ nop
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/ld/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/ld/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ld/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/pass/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/pass/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/pass/test.asm (revision 180)
@@ -0,0 +1,17 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Pass test.
+ ;; Always finds the pass mark.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ jmp pass
+
+
+ org 0x0c0
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/pass/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/pass/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/pass/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/asc/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/asc/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/asc/test.asm (revision 180)
@@ -0,0 +1,189 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the ASC instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M with 0x5
+ rmb 0x3
+ smb 0x2
+ rmb 0x1
+ smb 0x0
+
+ clra
+ rc
+ ;; test a0 + m5 + c0
+ asc
+ jmp ok_a0_m5_c0_carry
+ jmp fail
+ok_a0_m5_c0_carry:
+ skc
+ jmp ok_a0_m5_c0_c
+ jmp fail
+ok_a0_m5_c0_c:
+ ske
+ jmp fail
+
+ ;; test a5 + m5 + c0
+ asc
+ jmp ok_a5_m5_c0_carry
+ jmp fail
+ok_a5_m5_c0_carry:
+ skc
+ jmp ok_a5_m5_c0_c
+ jmp fail
+ok_a5_m5_c0_c:
+ aisc 16+5 - 10
+ nop
+ ske
+ jmp fail
+
+ rc
+ asc
+ ;; test a10 + m5 + c0
+ asc
+ jmp ok_a10_m5_c0_carry
+ jmp fail
+ok_a10_m5_c0_carry:
+ skc
+ jmp ok_a10_m5_c0_c
+ jmp fail
+ok_a10_m5_c0_c:
+ aisc 16+5 - 15
+ nop
+ ske
+ jmp fail
+
+ rc
+ asc
+ asc
+ ;; test a15 + m5 + c0
+ asc
+ jmp fail
+ skc
+ jmp fail
+ rc
+ aisc 16+5 - 20
+ nop
+ ske
+ jmp fail
+
+ sc
+ clra
+ ;; test a0 + m5 + c1
+ asc
+ jmp ok_a0_m5_c1_carry
+ jmp fail
+ok_a0_m5_c1_carry:
+ skc
+ jmp ok_a0_m5_c1_c
+ jmp fail
+ok_a0_m5_c1_c:
+ aisc 16+5 - 6
+ nop
+ ske
+ jmp fail
+
+ sc
+ ;; test a5 + m5 + c1
+ asc
+ jmp ok_a5_m5_c1_carry
+ jmp fail
+ok_a5_m5_c1_carry:
+ skc
+ jmp ok_a5_m5_c1_c
+ jmp fail
+ok_a5_m5_c1_c:
+ aisc 16+5 - 11
+ nop
+ ske
+ jmp fail
+
+ rc
+ asc
+ sc
+ ;; test a10 + m5 + c1
+ asc
+ jmp fail
+ skc
+ jmp fail
+ aisc 16+5 - 16
+ nop
+ ske
+ jmp fail
+
+ rc
+ asc
+ asc
+ sc
+ ;; test a15 + m5 + c1
+ asc
+ jmp fail
+ skc
+ jmp fail
+ ;; aisc 16+5 - 21
+ nop
+ ske
+ jmp fail
+
+
+ rc
+ aisc 0xa
+ x 0x0
+ clra
+ ;; test a0 + m15 + c0
+ asc
+ jmp ok_a0_m15_c0_carry
+ jmp fail
+ok_a0_m15_c0_carry:
+ skc
+ jmp ok_a0_m15_c0_c
+ jmp fail
+ok_a0_m15_c0_c:
+ ske
+ jmp fail
+
+ rc
+ ;; test a15 + m15 + c0
+ asc
+ jmp fail
+ skc
+ jmp fail
+ aisc 16+15 - 30
+ nop
+ ske
+ jmp fail
+
+ sc
+ clra
+ ;; test a0 + m15 + c1
+ asc
+ jmp fail
+ skc
+ jmp fail
+ aisc 16+15 - 16
+ nop
+ ske
+ jmp fail
+
+ sc
+ ;; test a15 + m15 + c1
+ asc
+ jmp fail
+ skc
+ jmp fail
+ ;; aisc 16+15 - 31
+ nop
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/asc/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/asc/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/asc/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jid/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/jid/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/jid/test.asm (revision 180)
@@ -0,0 +1,84 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the JID instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ aisc 0x6
+ x 0x0
+ clra
+ aisc 0x8
+ jid
+ jmp fail
+
+goon_1:
+ x 0x0
+ aisc 0x4
+ nop
+ x 0x0
+ jid
+ jmp fail
+
+goon_2:
+ x 0x0
+ aisc 0x2
+ x 0x0
+ jid
+ jmp fail
+goon_3:
+ x 0x0
+ aisc 0x1
+ x 0x0
+ jid
+ jmp fail
+
+goon_4:
+
+ jmp pass
+
+
+loc_fail:
+ jmp fail
+
+ org 0x080
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db goon_1
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db goon_2
+ db loc_fail
+ db goon_3
+ db goon_4
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+ db loc_fail
+
+ jmp fail
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/jid/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/jid/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jid/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/casc/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/casc/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/casc/test.asm (revision 180)
@@ -0,0 +1,91 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the CASC instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M0 with 0x5
+ rmb 0x3
+ smb 0x2
+ rmb 0x1
+ smb 0x0
+
+ rc
+ aisc 0xf
+ ;; test /(a15) + m5 + c0
+ casc
+ jmp ok_a15_m5_c0_carry
+ jmp fail
+ok_a15_m5_c0_carry:
+ skc
+ jmp ok_a15_m5_c0_c
+ jmp fail
+ok_a15_m5_c0_c:
+ ;; expect 0x5 as result
+ ske
+ jmp fail
+
+ sc
+ clra
+ aisc 0xa
+ ;; test /(a10) + m5 + c1
+ casc
+ jmp ok_a10_m5_c1_carry
+ jmp fail
+ok_a10_m5_c1_carry:
+ skc
+ jmp ok_a10_m5_c1_c
+ jmp fail
+ok_a10_m5_c1_c:
+ ;; expect 0xb as result
+ aisc 0xa
+ nop
+ ske
+ jmp fail
+
+ ;; preload M0 with 0xa
+ smb 0x3
+ rmb 0x2
+ smb 0x1
+ rmb 0x0
+ ;;
+ rc
+ clra
+ aisc 0x5
+ ;; test /(a5) + m10 + c0
+ casc
+ jmp fail
+ skc
+ jmp fail
+ ;; expect 0x4 as result
+ aisc 0x6
+ ske
+ jmp fail
+
+ ;; preload M0 with 0xf
+ smb 0x3
+ smb 0x2
+ smb 0x1
+ smb 0x0
+ ;;
+ sc
+ clra
+ ;; test /(a0) + m15 + c1
+ casc
+ jmp fail
+ skc
+ jmp fail
+ ;; expect 0xf as result
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/casc/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/casc/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/jp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/jp/test.asm (revision 180)
@@ -0,0 +1,217 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the JP instruction.
+ ;; Both for pages 2,3 and other pages.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ jmp page_0
+ jmp fail
+
+ org 0x030 - 2
+ jmp fail
+page_0:
+ jp page_0_loc
+ jmp fail
+page_0_loc:
+ jmp page_1
+ jmp fail
+
+ org 0x048 - 2
+ jmp fail
+page_1:
+ jp page_1_loc
+ jmp fail
+page_1_loc:
+ jmp page_4
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;;
+ org 0x080 - 2
+ jmp fail
+page_2:
+ jp page_3_1
+ jmp fail
+
+ org 0x08a - 2
+ jmp fail
+page_2_2:
+ jp page_3_3
+ jmp fail
+
+ org 0x093 - 2
+ jmp fail
+page_2_4:
+ jp page_3_5
+ jmp fail
+
+ org 0x09b - 2
+ jmp fail
+page_2_6:
+ jp page_3_7
+ jmp fail
+
+ org 0x0b9 - 2
+ jmp fail
+page_2_8:
+ jp page_3_9
+ jmp fail
+
+
+ org 0x0c5 - 2
+ jmp fail
+page_3_1:
+ jp page_2_2
+ jmp fail
+
+ org 0x0cd - 2
+ jmp fail
+page_3_3:
+ jp page_2_4
+ jmp fail
+
+ org 0x0d1 - 2
+ jmp fail
+page_3_5:
+ jp page_2_6
+ jmp fail
+
+ org 0x0da - 2
+ jmp fail
+page_3_7:
+ jp page_2_8
+ jmp fail
+
+ org 0x0e5 - 2
+ jmp fail
+page_3_9:
+ jmp pass
+ jmp fail
+
+
+ org 0x115 - 2
+ jmp fail
+page_4:
+ jp page_4_loc
+ jmp fail
+page_4_loc:
+ jmp page_5
+ jmp fail
+
+ include "pass_fail.asm"
+
+
+ org 0x15c - 2
+ jmp fail
+page_5:
+ jp page_5_loc
+ jmp fail
+page_5_loc:
+ jmp page_6
+ jmp fail
+
+ org 0x1a1 - 2
+ jmp fail
+page_6:
+ jp page_6_loc
+ jmp fail
+page_6_loc:
+ jmp page_7
+ jmp fail
+
+ org 0x1c9 - 2
+ jmp fail
+page_7:
+ jp page_7_loc
+ jmp fail
+page_7_loc:
+ IF MOMCPUNAME <> "COP410"
+ jmp page_8
+ ELSEIF
+ jmp page_2
+ ENDIF
+ jmp fail
+
+
+ IF MOMCPUNAME <> "COP410"
+
+ org 0x21e - 2
+ jmp fail
+page_8:
+ jp page_8_loc
+ jmp fail
+page_8_loc:
+ jmp page_9
+ jmp fail
+
+ org 0x263 - 2
+ jmp fail
+page_9:
+ jp page_9_loc
+ jmp fail
+page_9_loc:
+ jmp page_10
+ jmp fail
+
+ org 0x2a8 - 2
+ jmp fail
+page_10:
+ jp page_10_loc
+ jmp fail
+page_10_loc:
+ jmp page_11
+ jmp fail
+
+ org 0x2fa - 2
+ jmp fail
+page_11:
+ jp page_11_loc
+ jmp fail
+page_11_loc:
+ jmp page_12
+ jmp fail
+
+ org 0x327 - 2
+ jmp fail
+page_12:
+ jp page_12_loc
+ jmp fail
+page_12_loc:
+ jmp page_13
+ jmp fail
+
+ org 0x370 - 2
+ jmp fail
+page_13:
+ jp page_13_loc
+ jmp fail
+page_13_loc:
+ jmp page_14
+ jmp fail
+
+ org 0x3bb - 2
+ jmp fail
+page_14:
+ jp page_14_loc
+ jmp fail
+page_14_loc:
+ jmp page_15
+ jmp fail
+
+ org 0x3e9 - 2
+ jmp fail
+page_15:
+ jp page_15_loc
+ jmp fail
+page_15_loc:
+ jmp page_2
+ jmp fail
+
+ ENDIF
tags/rel_1_2/sw/verif/black_box/jp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/jp/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jp/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xad/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xad/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xad/test.asm (revision 180)
@@ -0,0 +1,254 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XAD instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; *******************************************************************
+ ;; Dedicated test for XAD 3, 15
+ ;;
+ lbi 0, 9
+ stii 0x02
+ stii 0x03
+
+ aisc 0x2
+ xad 3, 15
+ clra
+ aisc 0x3
+
+ xad 3, 15
+ ;; expect 0x2
+ lbi 0, 9
+ ske
+ jmp fail
+
+ xad 3, 15
+ ;; expect 0x3
+ lbi 0, 10
+ ske
+ jmp fail
+
+ IF MOMCPUNAME = "COP410"
+ jmp pass
+ ELSEIF
+
+
+ ;; macro for checking XAD on a complete register
+check MACRO register
+ lbi register, 0
+ ld 0
+ xad register, 1
+ xad register, 2
+ xad register, 3
+ xad register, 4
+ xad register, 5
+ xad register, 6
+ xad register, 7
+ xad register, 8
+ xad register, 9
+ xad register, 10
+ xad register, 11
+ xad register, 12
+ xad register, 13
+ xad register, 14
+ xad register, 15
+ xad register, 0
+
+ clra
+ lbi register, 1
+ ske ; expect 0 in digit 1
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 2
+ ske ; expect 1 in digit 2
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 3
+ ske ; expect 2 in digit 3
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 4
+ ske ; expect 3 in digit 4
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 5
+ ske ; expect 4 in digit 5
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 6
+ ske ; expect 5 in digit 6
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 7
+ ske ; expect 6 in digit 7
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 8
+ ske ; expect 7 in digit 8
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 9
+ ske ; expect 8 in digit 9
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 10
+ ske ; expect 9 in digit 10
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 11
+ ske ; expect 10 in digit 11
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 12
+ ske ; expect 11 in digit 12
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 13
+ ske ; expect 12 in digit 13
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 14
+ ske ; expect 13 in digit 14
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 15
+ ske ; expect 14 in digit 15
+ jmp fail
+ ;;
+ aisc 0x1
+ lbi register, 0
+ ske ; expect 15 in digit 0
+ jmp fail
+ ENDM
+
+
+
+ ;; prepare other registers
+ ;; register 1
+ lbi 1, 0
+ jsr clear_reg
+ ;; register 2
+ lbi 2, 0
+ jsr clear_reg
+ ;; register 3
+ lbi 3, 0
+ jsr clear_reg
+
+
+ ;; *******************************************************************
+ ;; Test XAD on register 0
+ ;;
+ lbi 0, 0
+ jsr init_reg
+ ;;
+ check 0
+
+
+ ;; *******************************************************************
+ ;; Test XAD on register 1
+ ;;
+ lbi 0, 0
+ jsr clear_reg
+ lbi 1, 0
+ jsr init_reg
+ ;;
+ check 1
+
+
+ ;; *******************************************************************
+ ;; Test XAD on register 2
+ ;;
+ lbi 1, 0
+ jsr clear_reg
+ lbi 2, 0
+ jsr init_reg
+ ;;
+ check 2
+
+
+ ;; *******************************************************************
+ ;; Test XAD on register 3
+ ;;
+ lbi 2, 0
+ jsr clear_reg
+ lbi 3, 0
+ jsr init_reg
+ ;;
+ check 3
+
+
+ jmp pass
+
+
+ ;;
+ ;; initialize current register with proper values
+ ;;
+init_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+ stii 0x8
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+ ret
+
+ ;;
+ ;; clear current register
+ ;;
+clear_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ ret
+
+ ENDIF
+
+
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xad/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xad/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xad/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ogi/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/ogi/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/ogi/test.asm (revision 180)
@@ -0,0 +1,30 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the OGI instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; output 1 on G
+ ogi 0x1
+
+ ;; output 2 on G
+ ogi 0x2
+
+ ;; output 4 on G
+ ogi 0x4
+
+ ;; output 8 on G
+ ogi 0x8
+
+ ;; output f on G
+ ogi 0xf
+
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/ogi/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/ogi/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/omg_ing/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/omg_ing/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/omg_ing/test.asm (revision 180)
@@ -0,0 +1,71 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the OMG and ING instructions.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; output 0 on G and check
+ ;; note: this is done before actually starting the
+ ;; sequence because 0 will end the sequence for
+ ;; the T411L flavour.
+ x 0x0
+ omg
+ clra
+ comp
+ ing
+ ske
+ jmp fail
+
+ ;; output 1 on G
+ clra
+ aisc 0x1
+ x 0x0
+ omg
+ ing
+ ske
+ jmp fail
+
+ ;; output 2 on G
+ clra
+ aisc 0x2
+ x 0x0
+ omg
+ ing
+ ske
+ jmp fail
+
+ ;; output 4 on G
+ clra
+ aisc 0x4
+ x 0x0
+ omg
+ ing
+ ske
+ jmp fail
+
+ ;; output 8 on G
+ ;; note: last action on COP411L
+ clra
+ aisc 0x8
+ x 0x0
+ omg
+ ing
+ ske
+ jmp fail
+
+ ;; output 0xf on G
+ clra
+ aisc 0xf
+ x 0x0
+ omg
+ ing
+ ske
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/omg_ing/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/omg_ing/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/omg_ing/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skc/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/skc/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/skc/test.asm (revision 180)
@@ -0,0 +1,25 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKC instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ skc
+ jmp ok_no_c
+ jmp fail
+
+ok_no_c:
+ sc
+ skc
+ jmp fail
+
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/skc/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/skc/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skc/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ske/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/ske/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/ske/test.asm (revision 180)
@@ -0,0 +1,60 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKE instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; test 0 == 0
+ x 0x0
+ clra
+ ske
+ jmp fail
+
+ ;; test 5 == 5
+ clra
+ aisc 0x5
+ x 0x0
+ ld 0x0
+ ske
+ jmp fail
+
+ ;; test a == a
+ clra
+ aisc 0xa
+ x 0x0
+ ld 0x0
+ ske
+ jmp fail
+
+ ;; test f == f
+ clra
+ aisc 0xf
+ x 0x0
+ ld 0x0
+ ske
+ jmp fail
+
+ ;; test 0 == f
+ clra
+ ske
+ jmp ok_0_ne_f
+ jmp fail
+
+ok_0_ne_f:
+ ;; test f == 0
+ x 0x0
+ ske
+ jmp ok_f_ne_0
+ jmp fail
+
+ok_f_ne_0:
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/ske/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/ske/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ske/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/lbi_short/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/lbi_short/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/lbi_short/test.asm (revision 180)
@@ -0,0 +1,299 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the LBI instruction (single byte).
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;;
+ ;; initialize 4 x 8 RAM digits
+ ;;
+
+ ;; register 0
+ stii 0x0
+ aisc 0x9
+ cab
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+
+ ;; register 1
+ ld 0x1
+ stii 0x4
+ cba
+ aisc 0x8
+ cab
+ stii 0x5
+ stii 0x6
+ stii 0x7
+ stii 0x8
+ stii 0x9
+ stii 0xa
+ stii 0xb
+
+ ;; register 2
+ ld 0x3
+ stii 0x8
+ cba
+ aisc 0x8
+ cab
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+
+ ;; register 3
+ ld 0x1
+ stii 0xc
+ cba
+ aisc 0x8
+ cab
+ stii 0xd
+ stii 0xe
+ stii 0xf
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+
+ jmp test_code
+
+
+ ;; subroutine page 2
+ org 0x80
+lbi_call_reg0:
+ lbi 0, 0
+ lbi 0, 9
+ lbi 0, 10
+ lbi 0, 11
+ lbi 0, 12
+ lbi 0, 13
+ lbi 0, 14
+ lbi 0, 15
+ ret
+lbi_call_reg1:
+ lbi 1, 0
+ lbi 1, 9
+ lbi 1, 10
+ lbi 1, 11
+ lbi 1, 12
+ lbi 1, 13
+ lbi 1, 14
+ lbi 1, 15
+ ret
+lbi_call_reg2:
+ lbi 2, 0
+ lbi 2, 9
+ lbi 2, 10
+ lbi 2, 11
+ lbi 2, 12
+ lbi 2, 13
+ lbi 2, 14
+ lbi 2, 15
+ ret
+lbi_call_reg3:
+ lbi 3, 0
+ lbi 3, 9
+ lbi 3, 10
+ lbi 3, 11
+ lbi 3, 12
+ lbi 3, 13
+ lbi 3, 14
+ lbi 3, 15
+ ret
+
+
+ org 0x100
+
+ ;;
+ ;; now test each register digit
+ ;;
+test_code:
+
+ ;; register 0
+ ;; digit 0
+ clra
+ jsrp lbi_call_reg0 + 0
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsrp lbi_call_reg0 + 1
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsrp lbi_call_reg0 + 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsrp lbi_call_reg0 + 3
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsrp lbi_call_reg0 + 4
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsrp lbi_call_reg0 + 5
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsrp lbi_call_reg0 + 6
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsrp lbi_call_reg0 + 7
+ ske
+ jmp fail
+
+ ;; register 1
+ ;; digit 0
+ clra
+ aisc 0x4
+ jsrp lbi_call_reg1 + 0
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsrp lbi_call_reg1 + 1
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsrp lbi_call_reg1 + 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsrp lbi_call_reg1 + 3
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsrp lbi_call_reg1 + 4
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsrp lbi_call_reg1 + 5
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsrp lbi_call_reg1 + 6
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsrp lbi_call_reg1 + 7
+ ske
+ jmp fail
+
+ ;; register 2
+ ;; digit 0
+ clra
+ aisc 0x8
+ jsrp lbi_call_reg2 + 0
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsrp lbi_call_reg2 + 1
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsrp lbi_call_reg2 + 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsrp lbi_call_reg2 + 3
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsrp lbi_call_reg2 + 4
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsrp lbi_call_reg2 + 5
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsrp lbi_call_reg2 + 6
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsrp lbi_call_reg2 + 7
+ ske
+ jmp fail
+
+ ;; register 3
+ ;; digit 0
+ clra
+ aisc 0xc
+ jsrp lbi_call_reg3 + 0
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsrp lbi_call_reg3 + 1
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsrp lbi_call_reg3 + 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsrp lbi_call_reg3 + 3
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ nop
+ jsrp lbi_call_reg3 + 4
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsrp lbi_call_reg3 + 5
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsrp lbi_call_reg3 + 6
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsrp lbi_call_reg3 + 7
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/lbi_short/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/lbi_short/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/lbi_short/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/lbi_long/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/lbi_long/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/lbi_long/test.asm (revision 180)
@@ -0,0 +1,535 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the LBI instruction (two byte).
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; register 0
+ ld 0x0
+ jsr clear_reg
+ ;; register 1
+ ld 0x1
+ jsr clear_reg
+ ;; register 2
+ ld 0x3
+ jsr clear_reg
+ ;; register 3
+ ld 0x1
+ jsr clear_reg
+
+ jmp test_code
+
+
+ ;; subroutines for combined long LBI
+ org 0x010
+lbi_call_reg0:
+ db 0x33, 0x80 ; lbi 0, 0
+ db 0x33, 0x81 ; lbi 0, 1
+ db 0x33, 0x82 ; lbi 0, 2
+ db 0x33, 0x83 ; lbi 0, 3
+ db 0x33, 0x84 ; lbi 0, 4
+ db 0x33, 0x85 ; lbi 0, 5
+ db 0x33, 0x86 ; lbi 0, 6
+ db 0x33, 0x87 ; lbi 0, 7
+ db 0x33, 0x88 ; lbi 0, 8
+ db 0x33, 0x89 ; lbi 0, 9
+ db 0x33, 0x8a ; lbi 0, 10
+ db 0x33, 0x8b ; lbi 0, 11
+ db 0x33, 0x8c ; lbi 0, 12
+ db 0x33, 0x8d ; lbi 0, 13
+ db 0x33, 0x8e ; lbi 0, 14
+ db 0x33, 0x8f ; lbi 0, 15
+ ret
+ jmp fail ; catch me if you can
+lbi_call_reg1:
+ db 0x33, 0x90 ; lbi 1, 0
+ db 0x33, 0x91 ; lbi 1, 1
+ db 0x33, 0x92 ; lbi 1, 2
+ db 0x33, 0x93 ; lbi 1, 3
+ db 0x33, 0x94 ; lbi 1, 4
+ db 0x33, 0x95 ; lbi 1, 5
+ db 0x33, 0x96 ; lbi 1, 6
+ db 0x33, 0x97 ; lbi 1, 7
+ db 0x33, 0x98 ; lbi 1, 8
+ db 0x33, 0x99 ; lbi 1, 9
+ db 0x33, 0x9a ; lbi 1, 10
+ db 0x33, 0x9b ; lbi 1, 11
+ db 0x33, 0x9c ; lbi 1, 12
+ db 0x33, 0x9d ; lbi 1, 13
+ db 0x33, 0x9e ; lbi 1, 14
+ db 0x33, 0x9f ; lbi 1, 15
+ ret
+ jmp fail ; catch me if you can
+lbi_call_reg2:
+ db 0x33, 0xa0 ; lbi 2, 0
+ db 0x33, 0xa1 ; lbi 2, 1
+ db 0x33, 0xa2 ; lbi 2, 2
+ db 0x33, 0xa3 ; lbi 2, 3
+ db 0x33, 0xa4 ; lbi 2, 4
+ db 0x33, 0xa5 ; lbi 2, 5
+ db 0x33, 0xa6 ; lbi 2, 6
+ db 0x33, 0xa7 ; lbi 2, 7
+ db 0x33, 0xa8 ; lbi 2, 8
+ db 0x33, 0xa9 ; lbi 2, 9
+ db 0x33, 0xaa ; lbi 2, 10
+ db 0x33, 0xab ; lbi 2, 11
+ db 0x33, 0xac ; lbi 2, 12
+ db 0x33, 0xad ; lbi 2, 13
+ db 0x33, 0xae ; lbi 2, 14
+ db 0x33, 0xaf ; lbi 2, 15
+ ret
+ jmp fail ; catch me if you can
+lbi_call_reg3:
+ db 0x33, 0xb0 ; lbi 3, 0
+ db 0x33, 0xb1 ; lbi 3, 1
+ db 0x33, 0xb2 ; lbi 3, 2
+ db 0x33, 0xb3 ; lbi 3, 3
+ db 0x33, 0xb4 ; lbi 3, 4
+ db 0x33, 0xb5 ; lbi 3, 5
+ db 0x33, 0xb6 ; lbi 3, 6
+ db 0x33, 0xb7 ; lbi 3, 7
+ db 0x33, 0xb8 ; lbi 3, 8
+ db 0x33, 0xb9 ; lbi 3, 9
+ db 0x33, 0xba ; lbi 3, 10
+ db 0x33, 0xbb ; lbi 3, 11
+ db 0x33, 0xbc ; lbi 3, 12
+ db 0x33, 0xbd ; lbi 3, 13
+ db 0x33, 0xbe ; lbi 3, 14
+ db 0x33, 0xbf ; lbi 3, 15
+ ret
+ jmp fail ; catch me if you can
+
+
+ ;;
+ ;; now test each register digit
+ ;;
+test_code:
+
+ ;; *******************************************************************
+ ;; register 0
+ ;;
+ ;; initialize all digits of register
+ ;;
+ ld 0x3 ; r: 3 -> 0
+ jsr init_reg
+
+
+ ;; digit 0
+ clra
+ jsr lbi_call_reg0 + 0 * 2
+ ske
+ jmp fail
+ ;; digit 1
+ aisc 0x1
+ jsr lbi_call_reg0 + 1 * 2
+ ske
+ jmp fail
+ ;; digit 2
+ aisc 0x1
+ jsr lbi_call_reg0 + 2 * 2
+ ske
+ jmp fail
+ ;; digit 3
+ aisc 0x1
+ jsr lbi_call_reg0 + 3 * 2
+ ske
+ jmp fail
+ ;; digit 4
+ aisc 0x1
+ jsr lbi_call_reg0 + 4 * 2
+ ske
+ jmp fail
+ ;; digit 5
+ aisc 0x1
+ jsr lbi_call_reg0 + 5 * 2
+ ske
+ jmp fail
+ ;; digit 6
+ aisc 0x1
+ jsr lbi_call_reg0 + 6 * 2
+ ske
+ jmp fail
+ ;; digit 7
+ aisc 0x1
+ jsr lbi_call_reg0 + 7 * 2
+ ske
+ jmp fail
+ ;; digit 8
+ aisc 0x1
+ jsr lbi_call_reg0 + 8 * 2
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsr lbi_call_reg0 + 9 * 2
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsr lbi_call_reg0 + 10 * 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsr lbi_call_reg0 + 11 * 2
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsr lbi_call_reg0 + 12 * 2
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsr lbi_call_reg0 + 13 * 2
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsr lbi_call_reg0 + 14 * 2
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsr lbi_call_reg0 + 15 * 2
+ ske
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; register 1
+ ;;
+ ;; initialize all digits of register
+ ;;
+ ld 0x0 ; r: 0 -> 0
+ jsr clear_reg
+ ld 0x1 ; r: 0 -> 1
+ jsr init_reg
+
+
+ ;; digit 0
+ clra
+ jsr lbi_call_reg1 + 0 * 2
+ ske
+ jmp fail
+ ;; digit 1
+ aisc 0x1
+ jsr lbi_call_reg1 + 1 * 2
+ ske
+ jmp fail
+ ;; digit 2
+ aisc 0x1
+ jsr lbi_call_reg1 + 2 * 2
+ ske
+ jmp fail
+ ;; digit 3
+ aisc 0x1
+ jsr lbi_call_reg1 + 3 * 2
+ ske
+ jmp fail
+ ;; digit 4
+ aisc 0x1
+ jsr lbi_call_reg1 + 4 * 2
+ ske
+ jmp fail
+ ;; digit 5
+ aisc 0x1
+ jsr lbi_call_reg1 + 5 * 2
+ ske
+ jmp fail
+ ;; digit 6
+ aisc 0x1
+ jsr lbi_call_reg1 + 6 * 2
+ ske
+ jmp fail
+ ;; digit 7
+ aisc 0x1
+ jsr lbi_call_reg1 + 7 * 2
+ ske
+ jmp fail
+ ;; digit 8
+ aisc 0x1
+ jsr lbi_call_reg1 + 8 * 2
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsr lbi_call_reg1 + 9 * 2
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsr lbi_call_reg1 + 10 * 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsr lbi_call_reg1 + 11 * 2
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsr lbi_call_reg1 + 12 * 2
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsr lbi_call_reg1 + 13 * 2
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsr lbi_call_reg1 + 14 * 2
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsr lbi_call_reg1 + 15 * 2
+ ske
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; register 2
+ ;;
+ ;; initialize all digits of register
+ ;;
+ ld 0x0 ; r: 1 -> 1
+ jsr clear_reg
+ ld 0x3 ; r: 1 -> 2
+ jsr init_reg
+
+
+ ;; digit 0
+ clra
+ jsr lbi_call_reg2 + 0 * 2
+ ske
+ jmp fail
+ ;; digit 1
+ aisc 0x1
+ jsr lbi_call_reg2 + 1 * 2
+ ske
+ jmp fail
+ ;; digit 2
+ aisc 0x1
+ jsr lbi_call_reg2 + 2 * 2
+ ske
+ jmp fail
+ ;; digit 3
+ aisc 0x1
+ jsr lbi_call_reg2 + 3 * 2
+ ske
+ jmp fail
+ ;; digit 4
+ aisc 0x1
+ jsr lbi_call_reg2 + 4 * 2
+ ske
+ jmp fail
+ ;; digit 5
+ aisc 0x1
+ jsr lbi_call_reg2 + 5 * 2
+ ske
+ jmp fail
+ ;; digit 6
+ aisc 0x1
+ jsr lbi_call_reg2 + 6 * 2
+ ske
+ jmp fail
+ ;; digit 7
+ aisc 0x1
+ jsr lbi_call_reg2 + 7 * 2
+ ske
+ jmp fail
+ ;; digit 8
+ aisc 0x1
+ jsr lbi_call_reg2 + 8 * 2
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsr lbi_call_reg2 + 9 * 2
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsr lbi_call_reg2 + 10 * 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsr lbi_call_reg2 + 11 * 2
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsr lbi_call_reg2 + 12 * 2
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsr lbi_call_reg2 + 13 * 2
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsr lbi_call_reg2 + 14 * 2
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsr lbi_call_reg2 + 15 * 2
+ ske
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; register 3
+ ;;
+ ;; initialize all digits of register
+ ;;
+ ld 0x0 ; r: 2 -> 2
+ jsr clear_reg
+ ld 0x1 ; r: 2 -> 3
+ jsr init_reg
+
+
+ ;; digit 0
+ clra
+ jsr lbi_call_reg3 + 0 * 2
+ ske
+ jmp fail
+ ;; digit 1
+ aisc 0x1
+ jsr lbi_call_reg3 + 1 * 2
+ ske
+ jmp fail
+ ;; digit 2
+ aisc 0x1
+ jsr lbi_call_reg3 + 2 * 2
+ ske
+ jmp fail
+ ;; digit 3
+ aisc 0x1
+ jsr lbi_call_reg3 + 3 * 2
+ ske
+ jmp fail
+ ;; digit 4
+ aisc 0x1
+ jsr lbi_call_reg3 + 4 * 2
+ ske
+ jmp fail
+ ;; digit 5
+ aisc 0x1
+ jsr lbi_call_reg3 + 5 * 2
+ ske
+ jmp fail
+ ;; digit 6
+ aisc 0x1
+ jsr lbi_call_reg3 + 6 * 2
+ ske
+ jmp fail
+ ;; digit 7
+ aisc 0x1
+ jsr lbi_call_reg3 + 7 * 2
+ ske
+ jmp fail
+ ;; digit 8
+ aisc 0x1
+ jsr lbi_call_reg3 + 8 * 2
+ ske
+ jmp fail
+ ;; digit 9
+ aisc 0x1
+ jsr lbi_call_reg3 + 9 * 2
+ ske
+ jmp fail
+ ;; digit 10
+ aisc 0x1
+ jsr lbi_call_reg3 + 10 * 2
+ ske
+ jmp fail
+ ;; digit 11
+ aisc 0x1
+ jsr lbi_call_reg3 + 11 * 2
+ ske
+ jmp fail
+ ;; digit 12
+ aisc 0x1
+ jsr lbi_call_reg3 + 12 * 2
+ ske
+ jmp fail
+ ;; digit 13
+ aisc 0x1
+ jsr lbi_call_reg3 + 13 * 2
+ ske
+ jmp fail
+ ;; digit 14
+ aisc 0x1
+ jsr lbi_call_reg3 + 14 * 2
+ ske
+ jmp fail
+ ;; digit 15
+ aisc 0x1
+ jsr lbi_call_reg3 + 15 * 2
+ ske
+ jmp fail
+
+
+
+ jmp pass
+
+
+ ;;
+ ;; initialize current register with proper values
+ ;;
+init_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+ stii 0x8
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+ ret
+
+ ;;
+ ;; clear current register
+ ;;
+clear_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ ret
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/lbi_long/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/lbi_long/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jmp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/jmp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/jmp/test.asm (revision 180)
@@ -0,0 +1,49 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the JMP instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ jmp block_0
+
+
+ org 0x00d
+ jmp fail
+block_0:
+ jmp block_1
+ jmp fail
+
+ org 0x10f
+ jmp fail
+block_1:
+ IF MOMCPUNAME <> "COP410"
+ jmp block_2
+ ELSEIF
+ jmp pass
+ ENDIF
+ jmp fail
+
+ org 0x120
+ include "pass_fail.asm"
+
+
+ IF MOMCPUNAME <> "COP410"
+
+ org 0x21f
+ jmp fail
+block_2:
+ jmp block_3
+ jmp fail
+
+ org 0x32f
+ jmp fail
+block_3:
+ jmp pass
+ jmp fail
+
+ ENDIF
tags/rel_1_2/sw/verif/black_box/jmp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/jmp/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jmp/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/add/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/add/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/add/test.asm (revision 180)
@@ -0,0 +1,146 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the ADD instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M0 with 0x1
+ rmb 0x3
+ rmb 0x2
+ rmb 0x1
+ smb 0x0
+
+ ;; test a0 + m1
+ add
+ ske
+ jmp fail
+
+ ;; test a1 + m1
+ add
+ aisc 16+1 - 2
+ nop
+ ske
+ jmp fail
+
+ aisc 2-1
+ ;; test a2 + m1
+ add
+ aisc 16+1 - 3
+ nop
+ ske
+ jmp fail
+
+ aisc 3-1
+ ;; test a3 + m1
+ add
+ aisc 16+1 - 4
+ nop
+ ske
+ jmp fail
+
+ aisc 4-1
+ ;; test a4 + m1
+ add
+ aisc 16+1 - 5
+ nop
+ ske
+ jmp fail
+
+ aisc 5-1
+ ;; test a5 + m1
+ add
+ aisc 16+1 - 6
+ nop
+ ske
+ jmp fail
+
+ aisc 6-1
+ ;; test a6 + m1
+ add
+ aisc 16+1 - 7
+ nop
+ ske
+ jmp fail
+
+ aisc 7-1
+ ;; test a7 + m1
+ add
+ aisc 16+1 - 8
+ nop
+ ske
+ jmp fail
+
+ aisc 8-1
+ ;; test a8 + m1
+ add
+ aisc 16+1 - 9
+ nop
+ ske
+ jmp fail
+
+ aisc 9-1
+ ;; test a9 + m1
+ add
+ aisc 16+1 - 10
+ nop
+ ske
+ jmp fail
+
+ aisc 10-1
+ ;; test a10 + m1
+ add
+ aisc 16+1 - 11
+ nop
+ ske
+ jmp fail
+
+ aisc 11-1
+ ;; test a11 + m1
+ add
+ aisc 16+1 - 12
+ nop
+ ske
+ jmp fail
+
+ aisc 12-1
+ ;; test a12 + m1
+ add
+ aisc 16+1 - 13
+ nop
+ ske
+ jmp fail
+
+ aisc 13-1
+ ;; test a13 + m1
+ add
+ aisc 16+1 - 14
+ nop
+ ske
+ jmp fail
+
+ aisc 14-1
+ ;; test a14 + m1
+ add
+ aisc 16+1 - 15
+ nop
+ ske
+ jmp fail
+
+ aisc 15-1
+ ;; test a15 + m1
+ add
+ aisc 16+1 - 16
+ nop
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/add/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/add/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/add/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/retsk/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/retsk/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/retsk/test.asm (revision 180)
@@ -0,0 +1,142 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the RETSK instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+page_0:
+ jsr target
+ jmp fail
+ jmp page_1
+
+ org 0x045 - 2
+ jmp fail
+page_1:
+ jsr target
+ jmp fail
+ jmp page_2
+
+ org 0x09a - 2
+ jmp fail
+page_2:
+ jsr target
+ jmp fail
+ jmp page_3
+
+ org 0x0dd - 2
+ jmp fail
+page_3:
+ jsr target
+ jmp fail
+ jmp page_4
+
+ org 0x130 - 2
+ jmp fail
+page_4:
+ jsr target
+ jmp fail
+ jmp page_5
+
+ org 0x164 - 2
+ jmp fail
+page_5:
+ jsr target
+ jmp fail
+ jmp page_6
+
+ org 0x1ac - 2
+ jmp fail
+page_6:
+ jsr target
+ jmp fail
+ jmp page_7
+
+ org 0x1e1 - 2
+ jmp fail
+page_7:
+ jsr target
+ jmp fail
+ IF MOMCPUNAME <> "COP410"
+ jmp page_8
+ ELSEIF
+ jmp pass
+ ENDIF
+
+
+ ;; *******************************************************************
+ ;; Subroutine target, execute RET
+ ;;
+ org 0x012 - 2
+ jmp fail
+target:
+ retsk
+ ;;
+ ;; *******************************************************************
+
+ include "pass_fail.asm"
+
+
+ IF MOMCPUNAME <> "COP410"
+
+ org 0x205 - 2
+ jmp fail
+page_8:
+ jsr target
+ jmp fail
+ jmp page_9
+
+ org 0x246 - 2
+ jmp fail
+page_9:
+ jsr target
+ jmp fail
+ jmp page_a
+
+ org 0x270 - 2
+ jmp fail
+page_a:
+ jsr target
+ jmp fail
+ jmp page_b
+
+ org 0x2f0 - 2
+ jmp fail
+page_b:
+ jsr target
+ jmp fail
+ jmp page_c
+
+ org 0x311 - 2
+ jmp fail
+page_c:
+ jsr target
+ jmp fail
+ jmp page_d
+
+ org 0x35c - 2
+ jmp fail
+page_d:
+ jsr target
+ jmp fail
+ jmp page_e
+
+ org 0x3b3 - 2
+ jmp fail
+page_e:
+ jsr target
+ jmp fail
+ jmp page_f
+
+ org 0x3c8 - 2
+ jmp fail
+page_f:
+ jsr target
+ jmp fail
+ jmp pass
+
+ ENDIF
tags/rel_1_2/sw/verif/black_box/retsk/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/retsk/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/retsk/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/cab_cba/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/cab_cba/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/cab_cba/test.asm (revision 180)
@@ -0,0 +1,192 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the CAB & CBA instructions.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload data memory with mismtach values
+ stii 0xf
+ stii 0xe
+ stii 0xd
+ stii 0xc
+ stii 0xb
+ stii 0xa
+ stii 0x9
+ stii 0x8
+ stii 0x7
+ stii 0x6
+ stii 0x5
+ stii 0x4
+ stii 0x3
+ stii 0x2
+ stii 0x1
+ stii 0x0
+
+ ;; test value 0
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 1
+ clra
+ aisc 0x1
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 2
+ clra
+ aisc 0x2
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 3
+ clra
+ aisc 0x3
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 4
+ clra
+ aisc 0x4
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 5
+ clra
+ aisc 0x5
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 6
+ clra
+ aisc 0x6
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 7
+ clra
+ aisc 0x7
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 8
+ clra
+ aisc 0x8
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 9
+ clra
+ aisc 0x9
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 10
+ clra
+ aisc 0xa
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 11
+ clra
+ aisc 0xb
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 12
+ clra
+ aisc 0xc
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 13
+ clra
+ aisc 0xd
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 14
+ clra
+ aisc 0xe
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+ ;; test value 15
+ clra
+ aisc 0xf
+ nop
+ cab
+ x 0x0
+ cba
+ ske
+ jmp fail
+
+
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/cab_cba/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/cab_cba/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/cab_cba/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ret/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/ret/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/ret/test.asm (revision 180)
@@ -0,0 +1,126 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the RET instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+page_0:
+ jsr target
+ jmp page_1
+
+ org 0x045 - 2
+ jmp fail
+page_1:
+ jsr target
+ jmp page_2
+
+ org 0x09a - 2
+ jmp fail
+page_2:
+ jsr target
+ jmp page_3
+
+ org 0x0dd - 2
+ jmp fail
+page_3:
+ jsr target
+ jmp page_4
+
+ org 0x130 - 2
+ jmp fail
+page_4:
+ jsr target
+ jmp page_5
+
+ org 0x164 - 2
+ jmp fail
+page_5:
+ jsr target
+ jmp page_6
+
+ org 0x1ac - 2
+ jmp fail
+page_6:
+ jsr target
+ jmp page_7
+
+ org 0x1e1 - 2
+ jmp fail
+page_7:
+ jsr target
+ IF MOMCPUNAME <> "COP410"
+ jmp page_8
+ ELSEIF
+ jmp pass
+ ENDIF
+
+
+ ;; *******************************************************************
+ ;; Subroutine target, execute RET
+ ;;
+ org 0x012 - 2
+ jmp fail
+target:
+ ret
+ ;;
+ ;; *******************************************************************
+
+ include "pass_fail.asm"
+
+
+ IF MOMCPUNAME <> "COP410"
+
+ org 0x205 - 2
+ jmp fail
+page_8:
+ jsr target
+ jmp page_9
+
+ org 0x246 - 2
+ jmp fail
+page_9:
+ jsr target
+ jmp page_a
+
+ org 0x270 - 2
+ jmp fail
+page_a:
+ jsr target
+ jmp page_b
+
+ org 0x2f0 - 2
+ jmp fail
+page_b:
+ jsr target
+ jmp page_c
+
+ org 0x311 - 2
+ jmp fail
+page_c:
+ jsr target
+ jmp page_d
+
+ org 0x35c - 2
+ jmp fail
+page_d:
+ jsr target
+ jmp page_e
+
+ org 0x3b3 - 2
+ jmp fail
+page_e:
+ jsr target
+ jmp page_f
+
+ org 0x3c8 - 2
+ jmp fail
+page_f:
+ jsr target
+ jmp pass
+
+ ENDIF
tags/rel_1_2/sw/verif/black_box/ret/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/ret/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ret/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xas/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xas/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xas/test.asm (revision 180)
@@ -0,0 +1,217 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XAS instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; *******************************************************************
+ ;; Test counter functionality
+ ;;
+ lei 0x5
+ ;; enable counter
+ clra
+ camq
+
+ ;; clear SKL
+ xas
+ nop ; spend some time to let effect of SKL
+ nop ; falling edge pass by
+ nop ;
+
+ ;; -------------------------------------------------------------------
+ ;; step 1
+ ;; decrement counter from 1 to 0
+ ;; test SO by controlling SI via SO
+ ;;
+ ;; load 0x1 to counter
+ clra
+ aisc 0x1
+ xas
+ ;; decrement via SO
+ lei 0xd
+ nop ; ensure minimum '1' duration
+ lei 0x5
+ nop ;
+ nop ; ensure minimum '0' duration
+ nop ;
+ xas
+ ;; check for 0x0
+ xad 3, 15
+ clra
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ ;; -------------------------------------------------------------------
+ ;; step 2
+ ;; decrement counter from 0 to 0xf
+ ;; test SKL by controlling SI via SK
+ ;;
+ ;; set SKL to '1'
+ sc ; SKL = '1'
+ xas
+ ;; load 0x0 to counter, decrement via SK
+ clra
+ rc
+ xas
+ nop ;
+ nop ; ensure minimum '0' duration
+ nop ;
+ xas
+ ;; check for 0xf
+ xad 3, 15
+ clra
+ aisc 0xf
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+
+ ;; -------------------------------------------------------------------
+ ;; step 3
+ ;; check minimum high time on SI
+ ;;
+ ;; load 0x0 to counter
+ clra
+ xas
+ ;; clock on SI
+ lei 0xd
+ lei 0x5 ; high time too short
+ nop ;
+ nop ; ensure minimum '0' duration
+ nop ;
+ xas
+ ;; check for 0x0
+ xad 3, 15
+ clra
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ ;; -------------------------------------------------------------------
+ ;; step 4
+ ;; check minimum low time on SI
+ ;;
+ ;; load 0x0 to counter
+ clra
+ xas
+ ;; clock on SI
+ lei 0xd
+ nop ; ensure minimum '1' duration
+ lei 0x5
+ lei 0xd ; low time too short
+ xas
+ ;; check for 0x0
+ xad 3, 15
+ clra
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; Test shift register functionality
+ ;;
+ lei 0xc ; SO = SIO output
+ ;; enable shift register
+ aisc 0x1
+ camq
+
+ ;; shift out 0x5
+ aisc 0x4
+ sc
+ xas
+ ;;
+ nop ;
+ nop ; shift for four clocks on SK
+ rc ;
+ xas ; stop SK
+ ;; check for 0x2
+ xad 3, 15
+ clra
+ aisc 0x2
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ ;; shift out 0x0
+ clra
+ sc
+ xas
+ ;;
+ nop ;
+ nop ; shift for four clocks on SK
+ rc ;
+ xas ; stop SK
+ ;; check for 0x8
+ xad 3, 15
+ clra
+ aisc 0x8
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ ;; now disable SO and check that only '0' is shifted in
+ lei 0x4 ; SO = '0'
+ ;; shift out 0xf
+ clra
+ aisc 0xf
+ sc
+ xas
+ ;;
+ nop ;
+ nop ; shift for four clocks on SK
+ rc ;
+ xas ; stop SK
+ ;; check for 0x0
+ xad 3, 15
+ clra
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ ;; enable SO
+ lei 0xc
+ ;; shift out 0x1 to force SI to '1' via SO
+ clra
+ aisc 0x1
+ sc
+ xas
+ ;;
+ nop ;
+ nop ; shift for four clocks on SK
+ rc ;
+ xas ; stop SK
+ ;; shift out 0x0 with disabled SK
+ clra
+ xas
+ ;;
+ nop ;
+ nop ; shift for four clocks on SK
+ nop ;
+ xas
+ ;; check for 0xf
+ xad 3, 15
+ clra
+ aisc 0xf
+ x 0
+ xad 3, 15
+ ske
+ jmp fail
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xas/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xas/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xas/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/inil/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/inil/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/inil/test.asm (revision 180)
@@ -0,0 +1,107 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the INIL instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; check reset level of latches
+ inil
+ x 0
+ skmbz 3
+ jmp fail
+ skmbz 2 ; CKO
+ jmp fail
+ skmbz 0
+ jmp fail
+
+
+ ;; set IN to 0xf and recheck levels
+ ogi 0xf
+ nop
+ nop
+ inil
+ x 0
+ skmbz 3
+ jmp fail
+ skmbz 2 ; CKO
+ jp +
+ jmp fail
++ skmbz 0
+ jmp fail
+
+
+ ;; set IN0 to 0 and check that IL0 triggered
+ ogi 0xe
+ nop
+ inil
+ x 0
+ skmbz 3
+ jmp fail
+ skmbz 2 ; CKO
+ jp +
+ jmp fail
++ skmbz 0
+ jp +
+ jmp fail
++
+
+ jmp page_1
+ org 0x040
+page_1:
+
+ ;; set IN3 to 0 and check that IL1 triggered
+ ogi 0x6
+ nop
+ inil
+ x 0
+ skmbz 3
+ jp +
+ jmp fail
++ skmbz 2 ; CKO
+ jp +
+ jmp fail
++ skmbz 0
+ jmp fail
+
+
+ ;; reload IN3 to trigger both IL latches
+ ogi 0x9
+ ogi 0x0
+ nop
+ inil
+ x 0
+ skmbz 3
+ jp +
+ jmp fail
++ skmbz 2 ; CKO
+ jmp fail
+ skmbz 0
+ jp +
+ jmp fail
++
+
+
+ ;; check that INIL prevents setting of IL latches
+ ;; when both events occur at the same cycle
+ ogi 0x9
+ ogi 0x0
+ inil
+ x 0
+ skmbz 3
+ jmp fail
+ skmbz 2 ; CKO
+ jmp fail
+ skmbz 0
+ jmp fail
+
+
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/inil/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/inil/t420
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xabr/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xabr/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xabr/test.asm (revision 180)
@@ -0,0 +1,103 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XABR instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload digit 0 of all registers with different data
+ lbi 0, 0
+ stii 0x4
+ stii 0x0 ; register number
+ lbi 1, 0
+ stii 0x5
+ stii 0x1 ; register number
+ lbi 2, 0
+ stii 0x6
+ stii 0x2 ; register number
+ lbi 3, 0
+ stii 0x7
+ stii 0x3 ; register number
+
+
+ ;; *******************************************************************
+ ;; check Br -> A path of XABR
+ ;;
+ lbi 0, 0
+ xabr
+ lbi 0, 1
+ ske ; check against preloaded register number
+ jmp fail
+ ;;
+ lbi 1, 0
+ xabr
+ lbi 1, 1
+ ske ; check against preloaded register number
+ jmp fail
+ ;;
+ lbi 2, 0
+ xabr
+ lbi 2, 1
+ ske ; check against preloaded register number
+ jmp fail
+ ;;
+ lbi 3, 0
+ xabr
+ lbi 3, 1
+ ske ; check against preloaded register number
+ jmp fail
+
+
+ ;; *******************************************************************
+ ;; check A -> Br path of XABR
+ ;;
+ lbi 0, 0 ; set Bd
+
+ ;; check for Br = 3
+ clra
+ aisc 0x3
+ xabr
+ ;; expect 0x7 @ 3, 0
+ clra
+ aisc 0x7
+ ske
+ jmp fail
+
+ ;; check for Br = 2
+ clra
+ aisc 0x2
+ xabr
+ ;; expect 0x6 @ 2, 0
+ clra
+ aisc 0x6
+ ske
+ jmp fail
+
+ ;; check for Br = 1
+ clra
+ aisc 0x1
+ xabr
+ ;; expect 0x5 @ 1, 0
+ clra
+ aisc 0x5
+ ske
+ jmp fail
+
+ ;; check for Br = 0
+ clra
+ xabr
+ ;; expect 0x4 @ 0, 0
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+
+
+ jmp pass
+
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xabr/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xabr/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/inin/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/inin/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/inin/test.asm (revision 180)
@@ -0,0 +1,71 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the ININ instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload reference data
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+ stii 0x8
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+
+ ;; output 0 on G and check
+ ogi 0x0
+ inin
+ lbi 0, 0
+ ske
+ jmp fail
+
+ ;; output 8 on G and check
+ ogi 0x8
+ inin
+ lbi 0, 8
+ ske
+ jmp fail
+
+ ;; output 1 on G and check
+ ogi 0x1
+ inin
+ lbi 0, 1
+ ske
+ jmp fail
+
+ ;; output 4 on G and check
+ ogi 0x4
+ inin
+ lbi 0, 4
+ ske
+ jmp fail
+
+ ;; output 15 on G and check
+ ogi 0xf
+ inin
+ lbi 0, 15
+ ske
+ jmp fail
+
+
+
+ jmp pass
+
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/inin/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/inin/t420
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jsr/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/jsr/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/jsr/test.asm (revision 180)
@@ -0,0 +1,130 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the JSR instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload data memory with jsr target values
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+
+ cab
+ jsr target_0
+ ;;
+ aisc 0x1
+ cab
+ clra
+ jsr target_1
+ ;;
+ aisc 0x2
+ cab
+ clra
+ jsr target_2
+ ;;
+ aisc 0x3
+ cab
+ clra
+ jsr target_3
+ ;;
+ IF MOMCPUNAME <> "COP410"
+ aisc 0x4
+ cab
+ clra
+ jsr target_4
+ ;;
+ aisc 0x5
+ cab
+ clra
+ jsr target_5
+ ;;
+ aisc 0x6
+ cab
+ clra
+ jsr target_6
+ ;;
+ aisc 0x7
+ cab
+ clra
+ jsr target_7
+ ENDIF
+
+ jmp pass
+
+ ;; subroutine targets
+ org 0x06f
+target_0:
+ ske
+ jmp fail
+ ret
+ ;;
+ org 0x09e
+target_1:
+ aisc 0x1
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x12d
+target_2:
+ aisc 0x2
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x13c
+target_3:
+ aisc 0x3
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ IF MOMCPUNAME <> "COP410"
+ org 0x24b
+target_4:
+ aisc 0x4
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x2da
+target_5:
+ aisc 0x5
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x369
+target_6:
+ aisc 0x6
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x378
+target_7:
+ aisc 0x7
+ ske
+ jmp fail
+ clra
+ ret
+ ENDIF
+
+ org 0x1d0
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/jsr/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/jsr/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jsr/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/comp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/comp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/comp/test.asm (revision 180)
@@ -0,0 +1,32 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the COMP instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M0 with 0x8
+ smb 0x3
+ rmb 0x2
+ rmb 0x1
+ rmb 0x0
+
+ ld 0x0
+ ;; test for 8 in a
+ ske
+ jmp fail
+
+ ;; test for complementing all bits in a
+ comp
+ aisc 0x1
+ ske
+ jmp fail
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/comp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/comp/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/comp/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skt/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/skt/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/skt/test.asm (revision 180)
@@ -0,0 +1,69 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKT instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; timer not elapsed right after power-on reset
+ skt
+ jp ok_1
+ jmp fail
+ok_1:
+
+
+ ;; preload timeout value
+ stii 0x4
+ stii 0x0
+ stii 0x0
+
+ ;; *******************************************************************
+ ;; Poll for timer flag with and time out after a while.
+ ;;
+poll_loop:
+ ;; decrement timeout counter
+ lbi 0, 2
+ sc
+ clra
+ aisc 0x1
+ casc ; M(0, 2) - 1
+ jp proc_digit_1
+ x 0
+ jp dec_finished
+
+proc_digit_1:
+ xds 0 ; A loads 0 from M
+ sc
+ aisc 0x1
+ casc ; M(0, 1) - 1
+ jp proc_digit_0
+ x 0
+ jp dec_finished
+
+proc_digit_0:
+ xds 0 ; A loads 0 from M
+ sc
+ aisc 0x1
+ casc ; M(0, 0) - 1
+ jmp fail ; TIMEOUT!
+ x 0
+dec_finished:
+
+ ;; poll timer flag
+ skt
+ jp poll_loop
+
+ ;; check that last skt cleared the flag
+ skt
+ jp ok_2
+ jmp fail
+ok_2:
+
+
+ jmp pass
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/skt/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/skt/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/ldd/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/ldd/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/ldd/test.asm (revision 180)
@@ -0,0 +1,149 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the LDD instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ ;; macro for checking a digit
+check_d MACRO reg, digit
+ lbi (reg ! 3), ~digit & 0xf ; select inverse digit
+ ldd reg, digit
+ lbi reg, digit
+ ske
+ jmp fail
+ ENDM
+
+
+ ;; macro for checking LDD on a complete register
+check_r MACRO reg
+ check_d reg, 0
+ check_d reg, 1
+ check_d reg, 2
+ check_d reg, 3
+ check_d reg, 4
+ check_d reg, 5
+ check_d reg, 6
+ check_d reg, 7
+ check_d reg, 8
+ check_d reg, 9
+ check_d reg, 10
+ check_d reg, 11
+ check_d reg, 12
+ check_d reg, 13
+ check_d reg, 14
+ check_d reg, 15
+ ENDM
+
+
+ org 0x00
+ clra
+
+
+ ;; prepare other registers
+ ;; register 1
+ lbi 1, 0
+ jsr clear_reg
+ ;; register 2
+ lbi 2, 0
+ jsr clear_reg
+ ;; register 3
+ lbi 3, 0
+ jsr clear_reg
+
+
+ ;; *******************************************************************
+ ;; Test LDD on register 0
+ ;;
+ lbi 0, 0
+ jsr init_reg
+ ;;
+ check_r 0
+
+
+ ;; *******************************************************************
+ ;; Test LDD on register 1
+ ;;
+ lbi 0, 0
+ jsr clear_reg
+ lbi 1, 0
+ jsr init_reg
+ ;;
+ check_r 1
+
+
+ ;; *******************************************************************
+ ;; Test LDD on register 2
+ ;;
+ lbi 1, 0
+ jsr clear_reg
+ lbi 2, 0
+ jsr init_reg
+ ;;
+ check_r 2
+
+ ;; *******************************************************************
+ ;; Test LDD on register 3
+ ;;
+ lbi 2, 0
+ jsr clear_reg
+ lbi 3, 0
+ jsr init_reg
+ ;;
+ check_r 3
+
+
+ jmp pass
+
+
+
+ ;; initialize current register with proper values
+ ;;
+init_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+ stii 0x8
+ stii 0x9
+ stii 0xa
+ stii 0xb
+ stii 0xc
+ stii 0xd
+ stii 0xe
+ stii 0xf
+ ret
+
+ ;;
+ ;; clear current register
+ ;;
+clear_reg:
+ clra
+ cab
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ stii 0x0
+ ret
+
+ org 0x380
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/ldd/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/ldd/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xis/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xis/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xis/test.asm (revision 180)
@@ -0,0 +1,411 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XIS instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+
+ ;; *******************************************************************
+ ;; XOR 0
+ jsr init_ram
+
+ ;; xor 0 in digit 0
+ lbi 0, 14
+ ;;
+ cba
+ comp
+ xis 0 ; 0, 0xe = 0x1
+ ;;
+ cba
+ comp
+ xis 0 ; 0, 0xf = 0x0
+ jmp fail
+
+ ;; xor 0 in digit 1
+ lbi 1, 14
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 0 ; 1, 0xe = 0x5
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 0 ; 1, 0xf = 0x4
+ jmp fail
+
+ ;; xor 0 in digit 2
+ lbi 2, 14
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 0 ; 2, 0xe = 0x9
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 0 ; 2, 0xf = 0x8
+ jmp fail
+
+ ;; xor 0 in digit 3
+ lbi 3, 14
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 0 ; 3, 0xe = 0xd
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 0 ; 3, 0xf = 0xc
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 1
+ jsr init_ram
+
+ ;;
+ ;; xor 1 in digit 0 & 1
+ ;;
+ lbi 0, 14
+ ;;
+ cba
+ comp
+ xis 1 ; 0, 0xe = 0x1
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 1 ; 1, 0xf = 0x4
+ jmp fail
+ ;; check remaining Br == 0
+ clra
+ cab
+ aisc 0x3 ; marker value
+ ske
+ jmp fail
+ ;; reload to Br = 1
+ lbi 1, 14
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 1 ; 1, 0xe = 0x5
+ ;;
+ cba
+ comp
+ xis 1 ; 0, 0xf = 0x0
+ jmp fail
+ ;; check remaining Br == 1
+ clra
+ cab
+ aisc 0x7 ; marker value
+ ske
+ jmp fail
+ jmp pass
+
+ ;;
+ ;; xor 1 in digit 2 & 3
+ ;;
+ lbi 2, 14
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 1 ; 2, 0xe = 0x9
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 1 ; 3, 0xf = 0xc
+ jmp fail
+ ;; check remaining Br == 2
+ clra
+ cab
+ aisc 0xb ; marker value
+ ske
+ jmp fail
+ ;; reload to Br = 3
+ lbi 3, 14
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 1 ; 3, 0xe = 0xc
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 1 ; 2, 0xf = 0x8
+ jmp fail
+ ;; check remaining BR == 3
+ clra
+ cab
+ aisc 0xf ; marker value
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 2
+ jsr init_ram
+
+ ;;
+ ;; xor 2 in digit 0 & 2
+ ;;
+ lbi 0, 14
+ ;;
+ cba
+ comp
+ xis 2 ; 0, 0xe = 0x1
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 2 ; 2, 0xf = 0x8
+ jmp fail
+ ;; check remainig Br == 0
+ clra
+ cab
+ aisc 0xb ; marker value
+ ske
+ jmp fail
+ ;; reload to Br == 2
+ lbi 2, 14
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 2 ; 2, 0xe = 0x9
+ ;;
+ cba
+ comp
+ xis 2 ; 0, 0xf = 0x0
+ jmp fail
+ ;; check remainig Br == 2
+ clra
+ cab
+ aisc 0x3 ; marker value
+ ske
+ jmp fail
+
+ ;;
+ ;; xor 2 in digit 1 & 3
+ ;;
+ lbi 1, 14
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 2 ; 1, 0xe = 0x5
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 2 ; 3, 0xf = 0xc
+ jmp fail
+ ;; check remaining Br == 1
+ clra
+ cab
+ aisc 0x7 ; marker value
+ ske
+ jmp fail
+ ;; reload to Br = 3
+ lbi 3, 14
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 2 ; 3, 0xe = 0xd
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 2 ; 1, 0xf = 0x4
+ jmp fail
+ ;; check remaining Br == 3
+ clra
+ cab
+ aisc 0xf ; marker value
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ ;; *******************************************************************
+ ;; XOR 3
+ jsr init_ram
+
+ ;;
+ ;; xor 3 in digit 0 & 3
+ ;;
+ lbi 0, 14
+ ;;
+ cba
+ comp
+ xis 3 ; 0, 0xe = 0x1
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 3 ; 3, 0xf = 0xc
+ jmp fail
+ ;; check remaining BR == 0
+ clra
+ cab
+ aisc 0x3 ; marker value
+ ske
+ jmp fail
+ ;; reload BR = 3
+ lbi 3, 14
+ ;;
+ cba
+ comp
+ aisc 3 << 2
+ xis 3 ; 3, 0xe = 0xd
+ ;;
+ cba
+ comp
+ xis 3 ; 0, 0xf = 0x0
+ jmp fail
+ ;; check remaining BR == 3
+ clra
+ cab
+ aisc 0xf ; marker value
+ ske
+ jmp fail
+
+ ;;
+ ;; xor 3 in digit 1 & 2
+ ;;
+ lbi 1, 14
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 3 ; 1, 0xe = 0x5
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 3 ; 2, 0xf = 0x8
+ jmp fail
+ ;; check remaining BR == 1
+ clra
+ cab
+ aisc 0x7 ; marker value
+ ske
+ jmp fail
+ ;; reload BR = 2
+ lbi 2, 14
+ ;;
+ cba
+ comp
+ aisc 2 << 2
+ xis 3 ; 2, 0xe = 0x9
+ ;;
+ cba
+ comp
+ aisc 1 << 2
+ xis 3 ; 1, 0xf = 0x4
+ jmp fail
+ ;; check remaining BR == 2
+ clra
+ cab
+ aisc 0xb ; marker value
+ ske
+ jmp fail
+
+ jsr check_ram
+
+
+ jmp pass
+
+
+
+
+ org 0x150
+
+ ;; preload digits of each data register
+init_ram:
+ ;; Br = 0
+ lbi 0, 14
+ stii 0x3
+ stii 0x2
+ stii 0x3 ; marker value
+ ;; Br = 1
+ lbi 1, 14
+ stii 0x7
+ stii 0x6
+ stii 0x7 ; marker value
+ ;; Br = 2
+ lbi 2, 14
+ stii 0xb
+ stii 0xa
+ stii 0xb ; marker value
+ ;; Br = 3
+ lbi 3, 14
+ stii 0xf
+ stii 0xe
+ stii 0xf ; marker value
+ ret
+
+
+check MACRO dig
+ ;; check dig, 14
+ clra
+ aisc 0xe
+ cab
+ comp
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ;; check 0, 15
+ clra
+ aisc 0xf
+ cab
+ comp
+ IF dig > 0
+ aisc dig << 2
+ ENDIF
+ ske
+ jmp fail
+ ENDM
+
+ ;; check contents of RAM entries
+check_ram:
+ ;; check digit 0
+ lbi 0, 0
+ check 0
+
+ ;; check digit 1
+ lbi 1, 0
+ check 1
+
+ ;; check digit 2
+ lbi 2, 0
+ check 2
+
+ ;; check digit 3
+ lbi 3, 0
+ check 3
+
+ ret
+
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xis/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xis/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xis/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/obd/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/obd/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/obd/test.asm (revision 180)
@@ -0,0 +1,41 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the OBD instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; output 1 on D
+ aisc 0x1
+ cab
+ obd
+
+ ;; output 2 on D
+ aisc 0x1
+ cab
+ obd
+
+ ;; output 4 on D
+ ;; note: last action on COP411L
+ aisc 0x2
+ cab
+ obd
+
+ ;; output 8 on D
+ aisc 0x4
+ cab
+ obd
+
+ ;; output 0xf on D
+ aisc 0x7
+ cab
+ obd
+
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/obd/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/obd/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/obd/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/x/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/x/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/x/test.asm (revision 180)
@@ -0,0 +1,379 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the X instruction.
+ ;; Br can't be observed directly via XABR on COP41x.
+ ;; Therefore, Br address is observed indirectly via memory content.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload a digit of each data register
+ ;; Br = 0 -> data = 0x1
+ lbi 0, 0
+ stii 0x1
+ ;; Br = 1 -> data = 0x2
+ lbi 1, 0
+ stii 0x2
+ ;; Br = 2 -> data = 0x3
+ lbi 2, 0
+ stii 0x3
+ ;; Br = 3 -> data = 0x4
+ lbi 3, 0
+ stii 0x4
+
+
+ ;; *******************************************************************
+ ;; XOR 0
+ ;;
+ ;; Br(0) xor 0
+ clra
+ aisc 0xf
+ lbi 0, 0
+ x 0x0
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x0
+ ;; expect 0x1 in M
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+
+ ;; Br(1) xor 0
+ clra
+ aisc 0xf
+ lbi 1, 0
+ x 0x0
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x0
+ ;; expect 0x2 in M
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+
+ ;; Br(2) xor 0
+ clra
+ aisc 0xf
+ lbi 2, 0
+ x 0x0
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x0
+ ;; expect 0x3 in M
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+
+ ;; Br(3) xor 0
+ clra
+ aisc 0xf
+ lbi 3, 0
+ x 0x0
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x0
+ ;; expect 0x4 in M
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+
+
+ clra
+ aisc 0xf
+ ;; *******************************************************************
+ ;; XOR 1
+ ;;
+ ;; Br(0) & Br(1) xor 1
+ lbi 0, 0
+ x 0x1 ; Br(0)=0xf, A=0x1, now Br(1)
+ xad 3, 15 ; save A
+ ;; expect 0x2 in M
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x1 ; Br(1)=0x1, A=0x2, now Br(0)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x1 ; Br(0)=0x2, A=0xf, now Br(1)
+ xad 3, 15 ; save A
+ ;; expect 0x1 in M
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x1 ; Br(1)=0xf, A=0x1, now Br(0)
+ x 0x1 ; Br(0)=0x1, A=0x2, now Br(1)
+ x 0x1 ; Br(1)=0x2, A=0xf, now Br(0)
+ ;; same memory & accumulator content as before
+
+ ;; Br(2) & Br(3) xor 1
+ lbi 2, 0
+ x 0x1 ; Br(2)=0xf, A=0x3, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x4 in M
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x1 ; Br(3)=0x3, A=0x4, now Br(2)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x1 ; Br(2)=0x4, A=0xf, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x3 in M
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x1 ; Br(3)=0xf, A=0x3, now Br(2)
+ x 0x1 ; Br(2)=0x3, A=0x4, now Br(3)
+ x 0x1 ; Br(3)=0x4, A=0xf, now Br(2)
+ ;; same memory & accumulator content as before
+
+ ;; now check that all
+ clra
+ lbi 0, 0
+ aisc 0x1
+ ske ; Br(0) == 1 ?
+ jmp fail
+ lbi 1, 0
+ aisc 0x1
+ ske ; Br(1) == 2 ?
+ jmp fail
+ lbi 2, 0
+ aisc 0x1
+ ske ; Br(2) == 3 ?
+ jmp fail
+ lbi 3, 0
+ aisc 0x1
+ ske ; Br(3) == 4 ?
+ jmp fail
+
+
+ clra
+ aisc 0xf
+ ;; *******************************************************************
+ ;; XOR 2
+ ;;
+ ;; Br(0) & Br(2) xor 2
+ lbi 0x0, 0x0
+ x 0x2 ; Br(0)=0xf, A=0x1, now Br(2)
+ xad 3, 15 ; save A
+ ;; expect 0x3 in M
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x2 ; Br(2)=0x1, A=0x3, now Br(0)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x2 ; Br(0)=0x3, A=0xf, now Br(2)
+ xad 3, 15 ; save A
+ ;; expect 0x1 in M
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x2 ; Br(2)=0xf, A=0x1, now Br(0)
+ x 0x2 ; Br(0)=0x1, A=0x3, now Br(2)
+ x 0x2 ; Br(2)=0x3, A=0xf, now Br(0)
+ ;; same memory & accumulator content as before
+
+ ;; Br(1) & Br(3) xor 2
+ lbi 0x1, 0x0
+ x 0x2 ; Br(1)=0xf, A=0x2, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x4 in M
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x2 ; Br(3)=0x2, A=0x4, now Br(1)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x2 ; Br(1)=0x4, A=0xf, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x2 in M
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x2 ; Br(3)=0xf, A=0x2, now Br(1)
+ x 0x2 ; Br(1)=0x2, A=0x4, now Br(3)
+ x 0x2 ; Br(3)=0x4, A=0xf, now Br(1)
+ ;; same memory & accumulator content as before
+
+ ;; now check that all
+ clra
+ lbi 0, 0
+ aisc 0x1
+ ske ; Br(0) == 1 ?
+ jmp fail
+ lbi 1, 0
+ aisc 0x1
+ ske ; Br(1) == 2 ?
+ jmp fail
+ lbi 2, 0
+ aisc 0x1
+ ske ; Br(2) == 3 ?
+ jmp fail
+ lbi 3, 0
+ aisc 0x1
+ ske ; Br(3) == 4 ?
+ jmp fail
+
+
+ clra
+ aisc 0xf
+ ;; *******************************************************************
+ ;; XOR 3
+ ;;
+ ;; Br(0) & Br(3) xor 3
+ lbi 0x0, 0x0
+ x 0x3 ; Br(0)=0xf, A=0x1, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x4 in M
+ clra
+ aisc 0x4
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x3 ; Br(3)=0x1, A=0x4, now Br(0)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x3 ; Br(0)=0x4, A=0xf, now Br(3)
+ xad 3, 15 ; save A
+ ;; expect 0x1 in M
+ clra
+ aisc 0x1
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x3 ; Br(3)=0xf, A=0x1, now Br(0)
+ x 0x3 ; Br(0)=0x1, A=0x4, now Br(3)
+ x 0x3 ; Br(3)=0x4, A=0xf, now Br(0)
+ ;; same memory & accumulator content as before
+
+ ;; Br(1) & Br(2) xor 3
+ lbi 0x1, 0x0
+ x 0x3 ; Br(1)=0xf, A=0x2, now Br(2)
+ xad 3, 15 ; save A
+ ;; expect 0x3 in M
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x3 ; Br(2)=0x2, A=0x3, now Br(1)
+ xad 3, 15 ; save A
+ ;; expect 0xf in M
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ x 0x3 ; Br(1)=0x3, A=0xf, now Br(2)
+ xad 3, 15 ; save A
+ ;; expect 0x2 in M
+ clra
+ aisc 0x2
+ ske
+ jmp fail
+ xad 3, 15 ; restore A
+ ;; swap all back
+ x 0x3 ; Br(2)=0xf, A=0x2, now Br(1)
+ x 0x3 ; Br(1)=0x2, A=0x3, now Br(2)
+ x 0x3 ; Br(2)=0x3, A=0xf, now Br(1)
+ ;; same memory & accumulator content as before
+
+ ;; now check that all
+ clra
+ lbi 0, 0
+ aisc 0x1
+ ske ; Br(0) == 1 ?
+ jmp fail
+ lbi 1, 0
+ aisc 0x1
+ ske ; Br(1) == 2 ?
+ jmp fail
+ lbi 2, 0
+ aisc 0x1
+ ske ; Br(2) == 3 ?
+ jmp fail
+ lbi 3, 0
+ aisc 0x1
+ ske ; Br(3) == 4 ?
+ jmp fail
+
+
+ jmp pass
+
+ org 0x1c0
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/x/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/x/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/x/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/adt/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/adt/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/adt/test.asm (revision 180)
@@ -0,0 +1,38 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the ADT instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M0 with 0xa
+ smb 0x3
+ rmb 0x2
+ smb 0x1
+ rmb 0x0
+
+ ;; test 0 + 10
+ adt
+ ske
+ jmp fail
+
+ ;; preload M0 with 0x4
+ rmb 0x3
+ smb 0x2
+ rmb 0x1
+ rmb 0x0
+
+ ;; test 0xa + 10
+ adt
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/adt/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/adt/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/stii/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/stii/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/stii/test.asm (revision 180)
@@ -0,0 +1,75 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the STII instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload data memory with jsrp target values
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+
+ ;; now scan through all 8 locations and check the contents
+ ;; check location 0, data 0
+ clra
+ cab
+ ske
+ jmp fail
+
+ ;; check location 1, data 1
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 2, data 2
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 3, data 3
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 4, data 4
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 5, data 5
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 6, data 6
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+ ;; check location 7, data 7
+ aisc 0x1
+ cab
+ ske
+ jmp fail
+
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/stii/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/stii/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/stii/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xor/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/xor/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/xor/test.asm (revision 180)
@@ -0,0 +1,64 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the XOR instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload M with 5
+ aisc 0x5
+ x 0x0
+ ;; preload A with 10
+ clra
+ aisc 0xa
+ ;; test a10 xor m5
+ xor
+ x 0x0
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+
+ ;; preload M with 10
+ clra
+ aisc 0xa
+ x 0x0
+ ;; preload A with 5
+ clra
+ aisc 0x5
+ ;; test a5 xor m10
+ xor
+ x 0x0
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+
+ ;; M has 15
+ ;; preload A with 0
+ clra
+ ;; test a0 xor m15
+ xor
+ ske
+ jmp fail
+
+ ;; preload M with 0
+ clra
+ x 0x0
+ ;; A now has 15
+ ;; test a15 xor m0
+ xor
+ x 0x0
+ clra
+ aisc 0xf
+ ske
+ jmp fail
+
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/xor/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/xor/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/xor/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skgz/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/skgz/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/skgz/test.asm (revision 180)
@@ -0,0 +1,72 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the SKGZ instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; output 0x1 on G
+ aisc 0x1
+ x 0x0
+ omg
+ ;; check no skip on 0x1
+ skgz
+ jmp ok_1
+ jmp fail
+ok_1:
+
+ ;; output 0x2 on G
+ clra
+ aisc 0x2
+ x 0x0
+ omg
+ ;; check no skip on 0x2
+ skgz
+ jmp ok_2
+ jmp fail
+ok_2:
+
+ ;; output 0x4 on G
+ clra
+ aisc 0x4
+ x 0x0
+ omg
+ ;; check no skip on 0x4
+ skgz
+ jmp ok_4
+ jmp fail
+ok_4:
+
+ ;; output 0x1 on G to break G monitoring sequence
+ clra
+ aisc 0x1
+ x 0x0
+ omg
+
+ ;; output 0x8 on G
+ clra
+ aisc 0x8
+ x 0x0
+ omg
+ ;; check no skip on 0x8
+ skgz
+ jmp ok_8
+ jmp fail
+ok_8:
+
+
+ ;; output 0x0 on G
+ clra
+ x 0x0
+ omg
+ ;; check skip on 0x0
+ skgz
+ jmp fail
+ jmp pass
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/skgz/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/skgz/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/skgz/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jsrp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/black_box/jsrp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/black_box/jsrp/test.asm (revision 180)
@@ -0,0 +1,128 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks the JSRP instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; preload data memory with jsrp target values
+ stii 0x0
+ stii 0x1
+ stii 0x2
+ stii 0x3
+ stii 0x4
+ stii 0x5
+ stii 0x6
+ stii 0x7
+
+ cab
+ jsrp target_0
+ ;;
+ aisc 0x1
+ cab
+ clra
+ jsrp target_1
+ ;;
+ aisc 0x2
+ cab
+ clra
+ jsrp target_2
+ ;;
+ aisc 0x3
+ cab
+ clra
+ jsrp target_3
+ ;;
+ aisc 0x4
+ cab
+ clra
+ jsrp target_4
+ ;;
+ aisc 0x5
+ cab
+ clra
+ jsrp target_5
+ ;;
+ aisc 0x6
+ cab
+ clra
+ jsrp target_6
+ ;;
+ aisc 0x7
+ cab
+ clra
+ jsrp target_7
+
+ jmp pass
+
+ ;; subroutine targets in page 2 & 3
+ org 0x080
+target_0:
+ ske
+ jmp fail
+ ret
+ ;;
+ org 0x088
+target_1:
+ aisc 0x1
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x090
+target_2:
+ aisc 0x2
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x098
+target_3:
+ aisc 0x3
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x0a0
+target_4:
+ aisc 0x4
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x0a8
+target_5:
+ aisc 0x5
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x0b0
+target_6:
+ aisc 0x6
+ ske
+ jmp fail
+ clra
+ ret
+ ;;
+ org 0x0b8
+target_7:
+ aisc 0x7
+ ske
+ jmp fail
+ clra
+ ret
+
+ jmp fail
+
+ org 0x100
+ include "pass_fail.asm"
tags/rel_1_2/sw/verif/black_box/jsrp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/black_box/jsrp/t41x
===================================================================
Index: tags/rel_1_2/sw/verif/black_box/jsrp/t42x
===================================================================
Index: tags/rel_1_2/sw/verif/system/microbus/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/system/microbus/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/system/microbus/test.asm (revision 180)
@@ -0,0 +1,71 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Test the MICROBUS functionality.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ ;; init counter with 0
+ xad 3, 15
+
+
+ ;;
+ ;; microbus data is written to RAM register 0&1, digits 0-11
+ ;;
+
+read_next_char:
+ ;; request data
+ ogi 0x1
+poll_write:
+ skgbz 0
+ jp poll_write
+
+ ;; read posted data
+ cqma
+ x 1 ; put A to R0, Q[3:0]
+ x 1 ; put M to R1, Q[7:4]
+
+ ;; check increment
+ ldd 3, 15
+ aisc 0x1
+ cab ; set new Bd
+ xad 3, 15
+ aisc 0x5 ; check for old Bd == 0xb
+ jmp read_next_char
+
+
+ ;;
+ ;; output received string
+ ;;
+
+ ;; init counter with 0
+ clra
+ cab
+ xad 3, 15
+
+write_next_char:
+ ld 1
+ ld 1 ; load A from R1, Q[7:4]
+ ; present M from R0, Q[3:0]
+ camq
+
+ ;; request read
+ ogi 0x1
+poll_read:
+ skgbz 0
+ jp poll_read
+
+ ;; check increment
+ ldd 3, 15
+ aisc 0x1
+ cab ; set new Bd
+ xad 3, 15
+ aisc 0x5 ; check for old Bd == 0xb
+ jmp write_next_char
+
+
+ jmp .
tags/rel_1_2/sw/verif/system/microbus/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/system/microbus/mb
===================================================================
Index: tags/rel_1_2/sw/verif/system/production_test/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/system/production_test/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/system/production_test/test.asm (revision 180)
@@ -0,0 +1,504 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Production test as proposed by
+ ;; "Testing of COP400 Familiy Devices"
+ ;; National Semiconductor
+ ;; COP Note 7
+ ;; April 1991
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+
+; INSTRUCTION RESULT COMMENTS
+
+ NOP ; NO CHANGE CHECK NOP & ALLOW TRANSIENT
+ ; CYCLE FOR MODE
+ OGI 9 ; G(0 > 9) NOT FOR 410L/411L
+ OGI 6 ; G(9 > 6) REVERSE ALL G STATES
+ STII 8 ; SET UP 0,0 FOR FUTURE
+ LBI 3, 13 ; B TO NEW POSITION (3, 13)
+ OBD ; D(0 > 13) CHECK D
+ CLRA ; MAKE SURE A = 0
+ XABR ; 3 > A;0 > Br
+ CAB ; MOVE 3 to Bd
+ OBD ; D(13 > 3) CHECK XABR CAB & D CHANGE
+ CLRA ; !
+ AISC 2 ; !FORCE A > 2
+ CAB ; 2 > Bd
+ OBD ; D(3 > 2) VERIFY 2 FROM A > Bd
+ STII 7 ; 7 > 0,2 & Bd > 3
+ OBD ; D(2 > 3) STII INCREMENTS Bd
+ CAB ; SEE THAT A STILL THE SAME
+ OMG ; G(6 > 7) OMB & RAM CHECK
+ CLRA
+ CAB ; B(0,0)
+ OMG ; G(7 > 8) TIE IN RAM, A & G OPERATION
+ SMB 0 ; SMB INST. CHECK
+ OMG ; G(8 > 9) :
+ SMB 1 ; :
+ OMG ; G(9 > 11) :
+ RMB 0 ; :
+ RMB 3 ; :
+ LD 0 ; :2 > A (modified AL)
+ CAB ; A = 2 > B
+ OMG ; G(11 > 7) OUTPUT M(0,2)
+ LD 1 ; M(0,2) > A; B > 1,2
+ XAD 0,0 ; A(7) < => M(0,0) 2
+ AISC 15 ; AISC CHECK; A = 1
+ LDD 0,0 ; CHECK SKIP OF 2 BYTE INST.
+ X 0 ; STORE 1
+ OMG ; G(7 > 1) VERIFY
+ LD 0 ; COPY1,2 BACK TO A
+ ADT ; ADD TEN
+ XDS 0 ; LEAVE 11 IN 1,2;GO 1, 1 WITH 1
+ XDS 0 ; LEAVE 1 IN 1,1;GO 1,0 W ?
+ OBD ; D(2 > 0) CHECK Bd MOVEMENT
+ STII 5 ; 5 > 1,0;Bd TO 1,1
+ CBA ; CHECK B > A
+ AISC 3 ; AISC CHECK 4 >A
+
+; INSTRUCTION RESULT COMMENTS
+
+ XDS 0 ; 1 > A; 4 > 1,1
+ OMG ; G(1 > 5) FROM 1,0
+ XDS 0 ; 5 > A; 1 > 1,0; Bd < 15 SKIP
+ LDD 0,0 ; SKIPPED !
+ OBD ; D(0 > 15)
+ AISC 4 ; 9 > A
+ X 0 ; 9 > 15
+ OMG ; G(5 > 9)
+ CLRA
+ COMP ; ONES TO A
+ XOR ; FLIP MEMORY
+ XIS 0 ; 6 > 1,15; 9 > A; Bd > 1,0
+ LDD 0,0 ; SKIP
+ AISC 8 ; A > 1 (added AL)
+ LDD 0,0 ; SKIP (added AL)
+ SKE
+ LBI 1,2 ; SKIP 2 WORD LBI (NOT IN 410)
+ OBD ; D(15 > 0) VERIFY WORD
+ SKE ; 11 NOT = 9
+ LBI 1,0 ; BACK TO 1,0
+ SMB 2 ; :
+ SKE ; :
+ RMB 2 ; :
+ SKE ; :CHECK BIT
+ SMB 3 ; :MANIPULATIONS
+ SKE ; :
+ LDD 0,0 ; :
+ X 3 ; Bd > 2,0
+ XAD 1,1 ; 9 > 1,1; 4 > A
+ XIS 1 ; 4 > 2,0; Bd > 3,1
+ ING ; INPUT G PORT
+ X 0 ; STORE
+
+; INSTRUCTION RESULT COMMENTS
+
+ CLRA
+ ASC ; CHECK ADD WITH CARRY
+ SC ; CHECK SET CARRY
+ SKC ; CHECK SKIP ON CARRY
+ LDD 0,0
+ X 0 ; STORE A
+ OMG ; G = 9 NO CHANGE
+ CLRA
+ ASC
+ X 0
+ OMG ; G(9 > 10) CARRY ADDS ONE TO MEMORY
+ CAMQ ; STORE A & M IN Q; 10,9
+ XDS 0 ; 9 > 3,1; 10 > A; Bd > 3,0
+ CQMA ; STORE 9 IN 3,0 (added AL)
+ OMG ; G(10 > 9)
+ LD 2 ; 9 > A; Bd > 1,0
+
+; INSTRUCTION RESULT COMMENTS
+
+ OMG ; G(9 > 1)
+ LD 3 ; 1 > A; Bd > 2,0
+ OMG ; G(1 > 4) (result corrected AL)
+ ADD ; ADD WITHOUT CARRY
+ X 0 ; STORE 3 IN 2,0
+ SC
+ LDD 0,0 ; 7 > A
+ CASC ; CHECK CASC
+ SKC
+ X 0 ; STORE 12
+ OMG ; G(4 > 14) (prev and current result corrected AL)
+ CLRA ; :
+ AISC 3 ; :
+ X 0 ; :
+ SC ; :CHECK
+ SKC ; :SKC/SC
+ X 0 ; :
+ OMG ; G(14 > 3) (prev result corrected AL)
+ RC ; :
+ SKC ; :CHECK
+ X 0 ; :RC
+ OMG ; G(3 > 14) :
+ LBI 0,0 ; :CHECK
+ LBI 1,15 ; ;SEQUENTIAL LBI'S
+ LBI 2,7 ; ALSO SKIPPED (LBI 2,7 NOT IN 410)
+ OMG ; G(14 > 7)
+ CQMA ; LOAD CONSTANTS FROM Q
+ OMG ; G(7 > 9) CHECK
+ X 0 ; :
+ OMG ; G(9 > 10) :
+ LEI 1
+ XAS ; STORE A - > S (9)
+ CLRA
+ AISC 7 ; :
+ SKGBZ 0 ; :
+ X 0 ; :CHECK
+ OMG ; :
+ SKGBZ 1 ; :
+ X 0 ; ;G BIT
+ OMG ; G (10 > 7) :
+ SKGBZ 2 ; :
+ X 0 ; :
+ OMG ; G(7 > 10) :TESTS
+ SKGBZ 3 ; :
+ X 0 ; :
+ OMG ; G(10 > 7) :
+
+; INSTRUCTION RESULT COMMENTS
+
+ SKGZ
+ X 0 ; :CHECK
+ OMG ; G(7 > 10) :
+ OGI 0 ; G(10 > 0) :G TEST
+ SKGZ ; :
+ X 0 ; :
+ OMG ; G(0 > 10) :
+ SKMBZ 0
+ X 0 ; CHECK MEMORY BIT TESTS
+ OMG ; NO CHANGE
+ SKMBZ 1
+
+; INSTRUCTION RESULT COMMENTS
+
+ X 0
+ OMG ; G(10 > 7) NO SKIP
+ SKMBZ 2
+ X 0 ; WON'T SKIP
+ OMG ; G(7 > 10)
+ INIL ; SEE THAT L LATCHES RESET
+ ININ ; ASSUME G - > I
+ SKE
+ X 1 ; Br > 1
+ OMG ; SHOULD BE EQUAL
+ INIL ; :
+ X 0 ; :
+ SKMBZ 3 ; :
+ OBD ; D(15 > 0) :INIL TEST
+ OGI 1 ; G(10 > 1) :(result added AL)
+ LBI 3,11 ; :
+ OGI 0 ; G(1 > 0) :(result added AL)
+ NOP ; (NOP added AL)
+ INIL ; :
+ X 0 ; :
+ SKMBZ 0 ; :
+ OBD ; D(0 > 11) :
+ NOP
+ XAS ; :
+ X 0 ; :XAS TEST
+ OMG ; G(10 > 9) :
+
+; INSTRUCTION RESULT COMMENTS
+
+ LBI 0,0 ; LOAD RAM WITH
+ STII 7 ; CONSTANTS USING
+ STII 14 ; STII
+ STII 5
+ STII 12
+ STII 3
+ STII 10
+ STII 1
+ STII 8
+ STII 15
+ STII 6
+ STII 13
+ STII 4
+ STII 11
+ STII 2
+ STII 9
+ STII 0
+ LBI 1,0
+ STII 7
+ STII 14
+ STII 5
+ STII 12
+ STII 3
+ STII 10
+ STII 1
+ STII 8
+ STII 15
+ STII 6
+ STII 13
+ STII 4
+ STII 11
+ STII 2
+ STII 9
+ STII 0
+ LBI 2,0
+ STII 7
+ STII 14
+ STII 5
+ STII 12
+ STII 3
+ STII 10
+ STII 1
+ STII 8
+ STII 15
+ STII 6
+ STII 13
+
+; INSTRUCTION RESULT COMMENTS
+
+ STII 4
+ STII 11
+
+; INSTRUCTION RESULT COMMENTS
+
+ STII 2
+ STII 9
+ STII 0
+ LBI 3,0
+ STII 7
+ STII 14
+ STII 5
+ STII 12
+ STII 3
+ STII 10
+ STII 1
+ STII 8
+ STII 15
+ STII 6
+ STII 13
+ STII 4
+ STII 11
+ STII 2
+ STII 9
+ STII 0
+
+; INSTRUCTION RESULT COMMENTS
+
+ LBI 0,0 ; CHECK FOR RAM DATA
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ NOP
+
+; INSTRUCTION RESULT COMMENTS
+
+ LBI 1,0 ; CHECK FOR RAM DATA
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+
+; INSTRUCTION RESULT COMMENTS
+
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ NOP
+
+; INSTRUCTION RESULT COMMENTS
+
+ LBI 2,0 ; CHECK FOR RAM DATA
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+
+; INSTRUCTION RESULT COMMENTS
+
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ NOP
+
+; INSTRUCTION RESULT COMMENTS
+
+ LBI 3,0 ; CHECK FOR RAM DATA
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ OMG ; OUTPUT DATA
+ LD 0 ; :
+ XIS 0 ; :MOVE TO NEXT DIGIT
+ NOP
+
+ jmp .
tags/rel_1_2/sw/verif/system/production_test/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/system/production_test/prod
===================================================================
Index: tags/rel_1_2/sw/verif/int/aisc/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/aisc/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/aisc/test.asm (revision 180)
@@ -0,0 +1,117 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on AISC.
+ ;; AISC is interrupted twice:
+ ;; 1) no carry, thus no skip
+ ;; 2) carry, skip after interrupt completion
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_030 = 0x01
+ clra
+ aisc 0x1
+ x 0
+
+ lei 0x02
+ jp int_mark_030
+
+ org 0x030
+int_mark_030:
+ nop
+ nop
+int_instr_030:
+ aisc 0xf
+ret_instr_030:
+ jp + ; must not be skipped!
+ jmp fail
++
+ ;; check result of AISC
+ xad 3, 0
+ clra
+ aisc 0xf
+ x 0
+ xad 3, 0
+ ske
+ jmp fail
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_0b0 = 0x2
+ clra
+ aisc 0x2
+ x 0
+
+ lei 0x02
+ jmp int_mark_0b0
+
+ org 0x0ae
+ jmp fail
+ org 0x0b0
+int_mark_0b0:
+ nop
+ nop
+int_instr_0b0:
+ aisc 0x1
+ret_instr_0b0:
+ jmp fail ; must be skipped!
+ ;; check result of AISC
+ xad 3, 0
+ clra
+ x 0
+ xad 3, 0
+ ske
+ jmp fail
+ ;; check whether interrupt really occured
+ int_flag_check
+ jmp pass
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+
+ int_flag_set
+
+ ;; access current M of main program
+ ldd 3, 14
+ x 0
+ skmbz 0x0
+ jp check_sa_030
+ skmbz 0x1
+ jp check_sa_0b0
+ jmp fail
+
+check_sa_030:
+ check_sa ret_instr_030
+ jmp int_finished
+check_sa_0b0:
+ check_sa ret_instr_0b0
+
+int_finished:
+ restore_c_m_a
+ ret
+ ;;
+ ;; *******************************************************************
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/aisc/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/aisc/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/skip_tci/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/skip_tci/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/skip_tci/test.asm (revision 180)
@@ -0,0 +1,51 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on a skipped "transfer of control" instruction.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ jsr jsr_target
+ jmp fail ; this one is skipped, but interrupted
+ret_instr:
+ int_flag_check
+ jmp pass
+
+
+ org 0x080
+jsr_target:
+ retsk
+
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/skip_tci/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/skip_tci/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/jid/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/jid/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/jid/test.asm (revision 180)
@@ -0,0 +1,64 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on JID.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+
+ ;; prepare JID
+ clra
+ x 0
+ clra
+ aisc 0x4
+
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ jid
+
+
+ ;; -------------------------------------------------------------------
+ ;; JID table
+ ;;
+ org 0x040
+ db 0x060
+
+
+ org 0x05e
+ jmp fail
+ org 0x060
+ nop
+ret_instr:
+ int_flag_check
+ jmp pass
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/jid/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/jid/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/jmp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/jmp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/jmp/test.asm (revision 180)
@@ -0,0 +1,47 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on JMP.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ jmp +
+
+
+ org 0x03d
+ jmp fail
+ org 0x03f
++ aisc 0xf
+ret_instr:
+ int_flag_check
+ jmp pass
+
+
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/jmp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/jmp/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/jsrp_retsk/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/jsrp_retsk/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/jsrp_retsk/test.asm (revision 180)
@@ -0,0 +1,109 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on JSRP and RETSK.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_1b0 = 0x01
+ clra
+ aisc 0x1
+ x 0
+
+ lei 0x02
+ jmp int_mark_1b0
+
+ org 0x1b0
+int_mark_1b0:
+ nop
+ nop
+int_instr_1b0:
+ jsrp prep_0b0
+ aisc 0x1 ; to be skipped by retsk
+ret_instr_0b0:
+ ;; check whether aisc has been skipped
+ x 0
+ clra
+ ske
+ jmp fail
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ jmp pass
+
+
+ org 0x090
+ jmp fail
+ org 0x092
+prep_0b0:
+ nop
+ret_instr_1b0:
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_0b0 = 0x2
+ clra
+ aisc 0x2
+ x 0
+
+ lei 0x02
+ jp int_mark_0b0
+
+ org 0x0ae
+ jmp fail
+ org 0x0b0
+int_mark_0b0:
+ nop
+ clra
+int_instr_0b0:
+ retsk
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+
+ int_flag_set
+
+ ;; access current M of main program
+ ldd 3, 14
+ x 0
+ skmbz 0x0
+ jp check_sa_1b0
+ skmbz 0x1
+ jp check_sa_0b0
+ jmp fail
+
+check_sa_1b0:
+ check_sa ret_instr_1b0
+ jmp int_finished
+check_sa_0b0:
+ check_sa ret_instr_0b0
+
+int_finished:
+ restore_c_m_a
+ ret
+ ;;
+ ;; *******************************************************************
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/jsrp_retsk/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/jsrp_retsk/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/lbi/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/lbi/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/lbi/test.asm (revision 180)
@@ -0,0 +1,128 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on LBI.
+ ;; LBI is interrupted twice:
+ ;; 1) short, 1 byte instruction
+ ;; 2) long, 2 byte instruction
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ ;; prepare RAM digits
+ lbi 0, 3
+ stii 0x3
+ lbi 0, 9
+ stii 0x9
+ lbi 0, 0 ; default RAM location
+
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_030 = 0x01
+ clra
+ aisc 0x1
+ x 0
+
+ lei 0x02
+ jp int_mark_030
+
+ org 0x030
+int_mark_030:
+ nop
+ nop
+int_instr_030:
+ lbi 0, 9 ; short LBI
+ nop
+ret_instr_030:
+ nop
+
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_0b0 = 0x2
+ clra
+ aisc 0x2
+ x 0
+
+ lei 0x02
+ jmp int_mark_0b0
+
+ org 0x0ae
+ jmp fail
+ org 0x0b0
+int_mark_0b0:
+ nop
+ nop
+int_instr_0b0:
+ lbi 0, 3 ; long LBI
+ nop
+ret_instr_0b0:
+ nop
+
+ ;; check whether interrupt really occured
+ int_flag_check
+ jmp pass
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+
+ int_flag_set
+
+ ;; read interrupt location selector
+ lbi 0, 0
+ ldd 0, 0
+ x 0
+ skmbz 0x0
+ jp check_sa_030
+ skmbz 0x1
+ jmp check_sa_0b0
+ jmp fail
+
+check_sa_030:
+ check_sa ret_instr_030
+ ;; check saved contents of 'current M'
+ ;; expect 0x9
+ lbi 3, 14
+ clra
+ aisc 0x9
+ ske
+ jmp fail
+ jmp int_finished
+
+check_sa_0b0:
+ check_sa ret_instr_0b0
+ ;; check saved contents of 'current M'
+ ;; expect 0x3
+ lbi 3, 14
+ clra
+ aisc 0x3
+ ske
+ jmp fail
+
+int_finished:
+ lbi 0, 0
+ restore_c_m_a
+ ret
+ ;;
+ ;; *******************************************************************
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/lbi/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/lbi/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/pass/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/pass/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/pass/test.asm (revision 180)
@@ -0,0 +1,30 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Pass interrupt test.
+ ;; Always finds the pass mark when there's an interrupt
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ org 0x00
+ clra
+
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+ nop
+ jmp fail
+
+
+ org 0x0ff
+ nop
+ jmp pass
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/pass/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/pass/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/skmbz/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/skmbz/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/skmbz/test.asm (revision 180)
@@ -0,0 +1,170 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on SKMBZ.
+ ;; AISC is interrupted twice:
+ ;; 1) no carry, thus no skip
+ ;; 2) carry, skip after interrupt completion
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_030 = 0x01
+ clra
+ aisc 0x1
+ x 0
+
+ lei 0x02
+ jp int_mark_030
+
+ org 0x030
+int_mark_030:
+ nop
+ nop
+int_instr_030:
+ skmbz 0x1
+ret_instr_030:
+ jmp fail ; must be skipped!
+
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_0b0 = 0x2
+ clra
+ aisc 0x2
+ x 0
+
+ lei 0x02
+ jmp int_mark_0b0
+
+ org 0x0ae
+ jmp fail
+ org 0x0b0
+int_mark_0b0:
+ nop
+ nop
+int_instr_0b0:
+ skmbz 0x1
+ret_instr_0b0:
+ jp + ; must not be skipped!
+ jmp fail ; must be skipped!
++
+
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_230 = 0x4
+ clra
+ aisc 0x4
+ x 0
+
+ lei 0x02
+ jmp int_mark_230
+
+ org 0x22e
+ jmp fail
+ org 0x230
+int_mark_230:
+ nop
+ skmbz 0x3
+int_instr_230:
+ jmp fail ; must be skipped
+ret_instr_230:
+
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_330 = 0x8
+ clra
+ aisc 0x8
+ x 0
+
+ lei 0x02
+ jmp int_mark_330
+
+ org 0x32e
+ jmp fail
+ org 0x330
+int_mark_330:
+ nop
+ skmbz 0x3
+int_instr_330:
+ jp + ; must not be skipped!
+ jmp fail
++
+ nop
+ret_instr_330:
+
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ jmp pass
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+
+ int_flag_set
+
+ ;; access current M of main program
+ ldd 3, 14
+ x 0
+ skmbz 0x0
+ jp check_sa_030
+ skmbz 0x1
+ jp check_sa_0b0
+ skmbz 0x2
+ jmp check_sa_230
+ skmbz 0x3
+ jmp check_sa_330
+ jmp fail
+
+check_sa_030:
+ check_sa ret_instr_030
+ jmp int_finished
+check_sa_0b0:
+ check_sa ret_instr_0b0
+ jmp int_finished
+check_sa_230:
+ check_sa ret_instr_230
+ jmp int_finished
+check_sa_330:
+ check_sa ret_instr_330
+
+int_finished:
+ restore_c_m_a
+ ret
+ ;;
+ ;; *******************************************************************
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/skmbz/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/skmbz/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/jsr_ret/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/jsr_ret/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/jsr_ret/test.asm (revision 180)
@@ -0,0 +1,104 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on JSR and RET.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_230 = 0x01
+ clra
+ aisc 0x1
+ x 0
+
+ lei 0x02
+ jmp int_mark_230
+
+ org 0x230
+int_mark_230:
+ nop
+ nop
+int_instr_230:
+ jsr prep_2b0
+ nop
+ret_instr_2b0:
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ jmp pass
+
+
+ org 0x290
+ jmp fail
+ org 0x292
+prep_2b0:
+ nop
+ret_instr_230:
+ ;; check whether interrupt really occured
+ int_flag_check
+
+ ;;
+ ;; prepare next interrupt
+ ;;
+ int_flag_clear
+ ;; write return instruction identifier to current M
+ ;; ret_instr_2b0 = 0x2
+ clra
+ aisc 0x2
+ x 0
+
+ lei 0x02
+ jp int_mark_2b0
+
+ org 0x2ae
+ jmp fail
+ org 0x2b0
+int_mark_2b0:
+ nop
+ nop
+int_instr_2b0:
+ ret
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+
+ int_flag_set
+
+ ;; access current M of main program
+ ldd 3, 14
+ x 0
+ skmbz 0x0
+ jp check_sa_230
+ skmbz 0x1
+ jp check_sa_2b0
+ jmp fail
+
+check_sa_230:
+ check_sa ret_instr_230
+ jmp int_finished
+check_sa_2b0:
+ check_sa ret_instr_2b0
+
+int_finished:
+ restore_c_m_a
+ ret
+ ;;
+ ;; *******************************************************************
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/jsr_ret/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/jsr_ret/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/sequence/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/sequence/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/sequence/test.asm (revision 180)
@@ -0,0 +1,58 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on a sequence of "transfer of control"
+ ;; instructions.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ jmp +
++ jp +
++ jsrp jsrp_target
+ jsr jsrp_target
+ lqid
+ nop
+ret_instr:
+ jmp +
+ org 0x040
++ int_flag_check
+ jmp pass
+
+
+ org 0x080
+jsrp_target:
+ ret
+
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/sequence/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/sequence/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/jp/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/jp/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/jp/test.asm (revision 180)
@@ -0,0 +1,47 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on JP.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ jp +
+
+
+ org 0x3c
+ jmp fail
+ org 0x3e
++ aisc 0xf
+ret_instr:
+ int_flag_check
+ jmp pass
+
+
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/jp/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/jp/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/lqid/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/lqid/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/lqid/test.asm (revision 180)
@@ -0,0 +1,74 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on LQID.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+
+ ;; prepare LQID
+ clra
+ comp
+ x 0
+ ld 0
+ camq
+ clra
+ x 0
+ clra
+ aisc 0x5
+
+ lei 0x06 ; also enable L output drivers
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ lqid
+ inl ; read data from LQID
+ ; lower nibble is OD from DUT
+ret_instr:
+ ;; disable L output drivers
+ lei 0x0
+ ;; and check for 0x5 in M
+ clra
+ aisc 0x5
+ ske
+ jmp fail
+
+ nop
+ int_flag_check
+ jmp pass
+
+
+ ;; -------------------------------------------------------------------
+ ;; LQID table
+ ;;
+ org 0x050
+ db 0x05f ; keep low nibble OD inactive
+
+
+ ;; *******************************************************************
+ ;; Interrupt routine
+ ;;
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/lqid/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/lqid/int
===================================================================
Index: tags/rel_1_2/sw/verif/int/nop/test.asm
===================================================================
--- tags/rel_1_2/sw/verif/int/nop/test.asm (nonexistent)
+++ tags/rel_1_2/sw/verif/int/nop/test.asm (revision 180)
@@ -0,0 +1,41 @@
+ ;; *******************************************************************
+ ;; $Id$
+ ;;
+ ;; Checks interrupt on NOP.
+ ;;
+
+ ;; the cpu type is defined on asl's command line
+
+ include "int_macros.inc"
+
+ org 0x00
+ clra
+
+ int_flag_clear
+ lei 0x02
+ jp int_mark
+
+ org 0x030
+int_mark:
+ nop
+ nop
+int_instr:
+ nop
+ret_instr:
+ int_flag_check
+ jmp pass
+
+
+ org 0x0fd
+ jmp fail
+int_routine:
+ nop
+ save_a_m_c
+ int_flag_set
+ check_sa ret_instr
+ restore_c_m_a
+ ret
+
+
+ org 0x200
+ include "int_pass_fail.asm"
tags/rel_1_2/sw/verif/int/nop/test.asm
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/verif/int/nop/int
===================================================================
Index: tags/rel_1_2/sw/run_regression.pl
===================================================================
--- tags/rel_1_2/sw/run_regression.pl (nonexistent)
+++ tags/rel_1_2/sw/run_regression.pl (revision 180)
@@ -0,0 +1,102 @@
+#!/usr/bin/perl -w
+#
+##############################################################################
+#
+# run_regression.pl
+#
+# $Id$
+#
+# Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
+#
+# All rights reserved
+#
+# ############################################################################
+#
+# Purpose:
+# ========
+#
+# Runs regression suite over all testcells found in $PROJECT_DIR/sw/verif.
+#
+# The testcells are identified by searching for the testbench identifiers
+# as defined below for %testbenches.
+# Then each testcell is built and executed with the specified testcells.
+#
+
+use strict;
+
+
+my $project_dir = $ENV{'PROJECT_DIR'};
+my $verif_dir = $project_dir.'/sw/verif';
+my $sim_dir = $project_dir.'/sim/rtl_sim';
+
+# the testbenches and their identifiers
+my %testbenches = ('t41x' => ['./tb_t410_behav_c0', './tb_t411_behav_c0'],
+ 't42x' => ['./tb_t420_behav_c0', './tb_t421_behav_c0'],
+ 't420' => ['./tb_t420_behav_c0'],
+ 'int' => ['./tb_int_behav_c0'],
+ 'mb' => ['./tb_microbus_behav_c0'],
+ 'prod' => ['./tb_prod_behav_c0']);
+my ($tb_name, $tb_exec);
+
+# identify the directories below $verif_dir containing test classes
+my @classes_dirs = ('black_box', 'int', 'system');
+
+my $dir;
+my %testdirs;
+
+# common GHDL options
+my $ghdl_options = '--assert-level=error';
+
+
+##############################################################################
+# find all test directories for all the testbenches
+#
+foreach $dir (@classes_dirs) {
+ $dir = $verif_dir.'/'.$dir;
+
+ while (($tb_name, $tb_exec) = each(%testbenches)) {
+ my $elem;
+ my @dirs = `find $dir -type f -name $tb_name`;
+
+ foreach $elem (@dirs) {
+ $elem =~ s/\/[^\/]+$//;
+ $testdirs{$elem} = 1;
+ }
+ }
+}
+
+
+##############################################################################
+# run through all tests and execute the enabled testbenches
+#
+chdir($sim_dir);
+while (($dir, $tb_exec) = each(%testdirs)) {
+ # remove all previous hex files
+ system('rm -f *.hex');
+
+ chdir($dir);
+ print("Building $dir\n");
+ if (system('make all clean') == 0) {
+ my @execute_tbs;
+
+ # collect the testbenches to be executed
+ while (($tb_name, $tb_exec) = each(%testbenches)) {
+ if (-f $tb_name) {
+ push(@execute_tbs, $tb_name);
+ }
+ }
+
+ # and finally execute them
+ chdir($sim_dir);
+ foreach $tb_name (@execute_tbs) {
+ print("Executing for $tb_name\n");
+
+ foreach $tb_exec (@{$testbenches{$tb_name}}) {
+ print("Executing testbench $tb_exec\n");
+ system("$tb_exec $ghdl_options");
+ }
+ }
+ } else {
+ print("Build failed\n");
+ }
+}
tags/rel_1_2/sw/run_regression.pl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/sw/hex2rom/hex2rom.cpp
===================================================================
--- tags/rel_1_2/sw/hex2rom/hex2rom.cpp (nonexistent)
+++ tags/rel_1_2/sw/hex2rom/hex2rom.cpp (revision 180)
@@ -0,0 +1,960 @@
+//
+// Binary and intel/motorola hex to VHDL ROM converter
+//
+// Version : 0244
+//
+// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+//
+// All rights reserved
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Please report bugs to the author, but before you do so, please
+// make sure that this is not a derivative work and that
+// you have the latest version of this file.
+//
+// The latest version of this file can be found at:
+// http://www.opencores.org/cvsweb.shtml/t51/
+//
+// Limitations :
+// No support for wrapped intel segments
+// Requires stl to compile
+//
+// File history :
+//
+// 0146 : Initial release
+//
+// 0150 : Added binary read
+//
+// 0208 : Changed some errors to warnings
+//
+// 0215 : Added support for synchronous ROM
+//
+// 0220 : Changed array ROM format, added support for Xilinx .UCF generation
+//
+// 0221 : Fixed small .UCF generation for small ROMs
+//
+// 0244 : Added Leonardo .UCF option
+//
+// 28-Apr-2008 : Generate D for synchronous ROM in clocked process.
+//
+
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+#if !(defined(max)) && _MSC_VER
+ // VC fix
+ #define max __max
+#endif
+
+class MemBlock
+{
+public:
+ unsigned long m_startAddress;
+ vector m_bytes;
+};
+
+class File
+{
+public:
+ explicit File(const char *fileName, const char *mode)
+ {
+ m_file = fopen(fileName, mode);
+ if (m_file != NULL)
+ {
+ return;
+ }
+ string errorStr = "Error opening ";
+ errorStr += fileName;
+ errorStr += "\n";
+ throw errorStr;
+ }
+
+ ~File()
+ {
+ fclose(m_file);
+ }
+
+ // Read binary file
+ void ReadBin(unsigned long limit)
+ {
+ m_top = 0;
+
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = 0;
+
+ cerr << "Reading binary file\n";
+
+ int tmp = fgetc(m_file);
+
+ while (!feof(m_file))
+ {
+ m_chunks.back().m_bytes.push_back(tmp);
+
+ if (m_chunks.back().m_bytes.size() > limit + 1)
+ {
+ m_chunks.back().m_bytes.pop_back();
+ m_top = m_chunks.back().m_bytes.size() - 1;
+ cerr << "Ignoring data above address space!\n";
+ cerr << " Limit: " << limit << "\n";
+ return;
+ }
+
+ tmp = fgetc(m_file);
+ }
+
+ m_top = m_chunks.back().m_bytes.size() - 1;
+
+ if (!m_chunks.back().m_bytes.size())
+ {
+ cerr << "No data!\n";
+
+ m_chunks.pop_back();
+ }
+ }
+
+ // Read hex file
+ void ReadHex(unsigned long limit)
+ {
+ char szLine[1024];
+ bool formatDetected = false;
+ bool intel;
+ bool endSeen = false;
+ bool linear = true; // Only used for intel hex
+ unsigned long addressBase = 0; // Only used for intel hex
+ unsigned long dataRecords = 0; // Only used for s-record
+ while (!feof(m_file))
+ {
+ if (fgets(szLine, 1024, m_file) == 0)
+ {
+ if (ferror(m_file))
+ {
+ throw "Error reading input!\n";
+ }
+ continue;
+ }
+
+ if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
+ {
+ szLine[strlen(szLine) - 1] = 0;
+ }
+
+ if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
+ {
+ szLine[strlen(szLine) - 1] = 0;
+ }
+
+ if (strlen(szLine) == 1023)
+ {
+ throw "Hex file lines to long!\n";
+ }
+ // Ignore blank lines
+ if (szLine[0] == '\n')
+ {
+ continue;
+ }
+ // Detect format and warn if garbage lines are found
+ if (!formatDetected)
+ {
+ if (szLine[0] != ':' && szLine[0] != 'S')
+ {
+ cerr << "Ignoring garbage line!\n";
+ continue;
+ }
+ if (szLine[0] == 'S')
+ {
+ intel = false;
+ cerr << "Detected S-Record\n";
+ }
+ else
+ {
+ intel = true;
+ cerr << "Detected intel hex file\n";
+ }
+ formatDetected = true;
+ }
+ else if ((intel && szLine[0] != ':') ||
+ (!intel && szLine[0] != 'S'))
+ {
+ cerr << "Ignoring garbage line!\n";
+ continue;
+ }
+
+ if (endSeen)
+ {
+ throw "Hex line after end of file record!\n";
+ }
+
+ if (intel)
+ {
+ unsigned long dataBytes;
+ unsigned long startAddress;
+ unsigned long type;
+ if (sscanf(&szLine[1], "%2lx%4lx%2lx", &dataBytes, &startAddress, &type) != 3)
+ {
+ throw "Hex line beginning corrupt!\n";
+ }
+ // Check line length
+ if (szLine[11 + dataBytes * 2] != '\n' && szLine[11 + dataBytes * 2] != 0)
+ {
+ throw "Hex line length incorrect!\n";
+ }
+ // Check line checksum
+ unsigned char checkSum = 0;
+ unsigned long tmp;
+ for (unsigned int i = 0; i <= dataBytes + 4; ++i)
+ {
+ if (sscanf(&szLine[1 + i * 2], "%2lx", &tmp) != 1)
+ {
+ throw "Hex line data corrupt!\n";
+ }
+ checkSum += tmp;
+ }
+ if (checkSum != 0)
+ {
+ throw "Hex line checksum error!\n";
+ }
+
+ switch (type)
+ {
+ case 0:
+ // Data record
+ if (!linear)
+ {
+ // Segmented
+ unsigned long test = startAddress;
+ test += dataBytes;
+ if (test > 0xffff)
+ {
+ throw "Can't handle wrapped segments!\n";
+ }
+ }
+ if (!m_chunks.size() ||
+ m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
+ addressBase + startAddress)
+ {
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = addressBase + startAddress;
+ }
+ {
+ unsigned char i = 0;
+ for (i = 0; i < dataBytes; ++i)
+ {
+ sscanf(&szLine[9 + i * 2], "%2lx", &tmp);
+ if (addressBase + startAddress + i > limit)
+ {
+ cerr << "Ignoring data above address space!\n";
+ cerr << "Data address: " << addressBase + startAddress + i;
+ cerr << " Limit: " << limit << "\n";
+ if (!m_chunks.back().m_bytes.size())
+ {
+ m_chunks.pop_back();
+ }
+ continue;
+ }
+ m_chunks.back().m_bytes.push_back(tmp);
+ }
+ }
+ break;
+
+ case 1:
+ // End-of-file record
+ if (dataBytes != 0)
+ {
+ cerr << "Warning: End of file record not zero length!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: End of file record address not zero!\n";
+ }
+ endSeen = true;
+ break;
+
+ case 2:
+ // Extended segment address record
+ if (dataBytes != 2)
+ {
+ throw "Length field must be 2 in extended segment address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ throw "Address field must be zero in extended segment address record!\n";
+ }
+ sscanf(&szLine[9], "%4lx", &startAddress);
+ addressBase = startAddress << 4;
+ linear = false;
+ break;
+
+ case 3:
+ // Start segment address record
+ if (dataBytes != 4)
+ {
+ cerr << "Warning: Length field must be 4 in start segment address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: Address field must be zero in start segment address record!\n";
+ }
+ if (dataBytes == 4)
+ {
+ unsigned long ssa;
+ char ssaStr[16];
+ sscanf(&szLine[9], "%8lx", &ssa);
+ sprintf(ssaStr, "%08X\n", ssa);
+ cerr << "Segment start address (CS/IP): ";
+ cerr << ssaStr;
+ }
+ break;
+
+ case 4:
+ // Extended linear address record
+ if (dataBytes != 2)
+ {
+ throw "Length field must be 2 in extended linear address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ throw "Address field must be zero in extended linear address record!\n";
+ }
+ sscanf(&szLine[9], "%4lx", &startAddress);
+ addressBase = ((unsigned long)startAddress) << 16;
+ linear = true;
+ break;
+
+ case 5:
+ // Start linear address record
+ if (dataBytes != 4)
+ {
+ cerr << "Warning: Length field must be 4 in start linear address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: Address field must be zero in start linear address record!\n";
+ }
+ if (dataBytes == 4)
+ {
+ unsigned long lsa;
+ char lsaStr[16];
+ sscanf(&szLine[9], "%8lx", &lsa);
+ sprintf(lsaStr, "%08X\n", lsa);
+ cerr << "Linear start address: ";
+ cerr << lsaStr;
+ }
+ break;
+
+ default:
+ cerr << "Waring: Unknown record found!\n";
+ }
+ }
+ else
+ {
+ // S-record
+ unsigned long count;
+ char type;
+ if (sscanf(&szLine[1], "%c%2lx", &type, &count) != 2)
+ {
+ throw "Hex line beginning corrupt!\n";
+ }
+ // Check line length
+ if (szLine[4 + count * 2] != '\n' && szLine[4 + count * 2] != 0)
+ {
+ throw "Hex line length incorrect!\n";
+ }
+ // Check line checksum
+ unsigned char checkSum = 0;
+ unsigned long tmp;
+ for (unsigned int i = 0; i < count + 1; ++i)
+ {
+ if (sscanf(&szLine[2 + i * 2], "%2lx", &tmp) != 1)
+ {
+ throw "Hex line data corrupt!\n";
+ }
+ checkSum += tmp;
+ }
+ if (checkSum != 255)
+ {
+ throw "Hex line checksum error!\n";
+ }
+
+ switch (type)
+ {
+ case '0':
+ // Header record
+ {
+ char header[256];
+ unsigned char i = 0;
+ for (i = 0; i + 3 < count; ++i)
+ {
+ sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
+ header[i] = tmp;
+ }
+ header[i] = 0;
+ if (i > 0)
+ {
+ cerr << "Module name: " << header << "\n";
+ }
+ }
+ break;
+
+ case '1':
+ case '2':
+ case '3':
+ // Data record
+ {
+ dataRecords++;
+ unsigned long startAddress;
+ if (type == '1')
+ {
+ sscanf(&szLine[4], "%4lx", &startAddress);
+ }
+ else if (type == '2')
+ {
+ sscanf(&szLine[4], "%6lx", &startAddress);
+ }
+ else
+ {
+ sscanf(&szLine[4], "%8lx", &startAddress);
+ }
+
+ if (!m_chunks.size() ||
+ m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
+ startAddress)
+ {
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = startAddress;
+ }
+ unsigned char i = 0;
+ for (i = (type - '1'); i + 3 < count; ++i)
+ {
+ sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
+ if (startAddress + i > limit)
+ {
+ cerr << "Ignoring data above address space!\n";
+ cerr << "Data address: " << startAddress + i;
+ cerr << " Limit: " << limit << "\n";
+ if (!m_chunks.back().m_bytes.size())
+ {
+ m_chunks.pop_back();
+ }
+ continue;
+ }
+ m_chunks.back().m_bytes.push_back(tmp);
+ }
+ }
+ break;
+
+ case '5':
+ // Count record
+ {
+ unsigned long address;
+ sscanf(&szLine[4], "%4lx", &address);
+ if (address != dataRecords)
+ {
+ throw "Wrong number of data records!\n";
+ }
+ }
+ break;
+
+ case '7':
+ case '8':
+ case '9':
+ // Start address record
+ cerr << "Ignoring start address record!\n";
+ break;
+
+ default:
+ cerr << "Unknown record found!\n";
+ }
+ }
+ }
+ if (intel && !endSeen)
+ {
+ cerr << "No end of file record!\n";
+ }
+ if (!m_chunks.size())
+ {
+ throw "No data in file!\n";
+ }
+ vector::iterator vi;
+ m_top = 0;
+ for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
+ {
+ m_top = max(m_top, vi->m_startAddress + vi->m_bytes.size() - 1);
+ }
+ }
+
+ // Rather inefficient this one, fix sometime
+ bool GetByte(const unsigned long address, unsigned char &chr)
+ {
+ vector::iterator vi;
+
+ for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
+ {
+ if (vi->m_startAddress + vi->m_bytes.size() > address && vi->m_startAddress <= address)
+ {
+ break;
+ }
+ }
+ if (vi == m_chunks.end())
+ {
+ return false;
+ }
+ chr = vi->m_bytes[address - vi->m_startAddress];
+ return true;
+ }
+
+ bool BitString(const unsigned long address, const unsigned char bits, const bool lEndian, string &str)
+ {
+ bool ok = false;
+ long i;
+ unsigned char chr;
+ unsigned long data = 0;
+ unsigned long tmp;
+
+ if (lEndian)
+ {
+ for (i = 0; i < (bits + 7) / 8; ++i)
+ {
+ ok |= GetByte(address + i, chr);
+ tmp = chr;
+ data |= tmp << (8 * i);
+ }
+ }
+ else
+ {
+ for (i = 0; i < (bits + 7) / 8; ++i)
+ {
+ ok |= GetByte(address + i, chr);
+ tmp = chr;
+ data |= tmp << (8 * ((bits + 7) / 8 - i - 1));
+ }
+ }
+
+ if (!ok)
+ {
+ return false;
+ }
+
+ unsigned long mask = 1;
+
+ str = "";
+ for (i = 0; i < bits; i++)
+ {
+ if (data & mask)
+ {
+ str.insert(0,"1");
+ }
+ else
+ {
+ str.insert(0,"0");
+ }
+ mask <<= 1;
+ }
+ return true;
+ }
+
+ FILE *Handle() { return m_file; };
+ vector m_chunks;
+ unsigned long m_top;
+private:
+ FILE *m_file;
+};
+
+
+int main (int argc, char *argv[])
+{
+ cerr << "Hex to VHDL ROM converter by Daniel Wallner. Version 0244\n";
+
+ try
+ {
+ unsigned long aWidth;
+ unsigned long dWidth;
+ char endian;
+ char O = 0;
+
+ if (!(argc == 4 || argc == 5))
+ {
+ cerr << "\nUsage: hex2rom [-b] \n";
+ cerr << "\nIf the -b option is specified the file is read as a binary file\n";
+ cerr << "Hex input files must be intel hex or motorola s-record\n";
+ cerr << "\nThe format string has the format AEDOS where:\n";
+ cerr << " A = Address bits\n";
+ cerr << " E = Endianness, l or b\n";
+ cerr << " D = Data bits\n";
+ cerr << " O = ROM type: (one optional character)\n";
+ cerr << " z for tri-state output\n";
+ cerr << " a for array ROM\n";
+ cerr << " s for synchronous ROM\n";
+ cerr << " u for XST ucf\n";
+ cerr << " l for Leonardo ucf\n";
+ cerr << " S = SelectRAM usage in 1/16 parts (only used when O = u)\n";
+ cerr << "\nExample:\n";
+ cerr << " hex2rom test.hex Test_ROM 18b16z\n\n";
+ return -1;
+ }
+
+ string inFileName;
+ string outFileName;
+
+ unsigned long bytes;
+ unsigned long select = 0;
+
+ if (argc == 5)
+ {
+ if (strcmp(argv[1], "-b"))
+ {
+ throw "Error in arguments!\n";
+ }
+ }
+
+ int result;
+
+ result = sscanf(argv[argc - 1], "%lu%c%lu%c%lu", &aWidth, &endian, &dWidth, &O, &select);
+ if (result < 3)
+ {
+ throw "Error in output format argument!\n";
+ }
+
+ if (aWidth > 32 || (endian != 'l' && endian != 'b') || dWidth > 32 || (result > 3 && O != 'z' && O != 'a' && O != 's' && O != 'u' && O != 'l'))
+ {
+ throw "Error in output format argument!\n";
+ }
+ inFileName = argv[argc - 3];
+ outFileName = argv[argc - 2];
+
+ bytes = (dWidth + 7) / 8;
+
+ File inFile(inFileName.c_str(), "rb");
+
+ if (argc == 4)
+ {
+ inFile.ReadHex((1UL << aWidth) * bytes - 1);
+ }
+ else
+ {
+ inFile.ReadBin((1UL << aWidth) * bytes - 1);
+ }
+
+ string line;
+
+ unsigned long words = 1;
+ unsigned long i = inFile.m_top;
+ i /= bytes;
+
+ while (i != 0)
+ {
+ i >>= 1;
+ words <<= 1;
+ }
+
+ if (O != 'u' && O != 'l')
+ {
+ printf("-- This file was generated with hex2rom written by Daniel Wallner\n");
+ printf("\nlibrary IEEE;");
+ printf("\nuse IEEE.std_logic_1164.all;");
+ printf("\nuse IEEE.numeric_std.all;");
+ printf("\n\nentity %s is", outFileName.c_str());
+ printf("\n\tport(");
+ if (O == 'z')
+ {
+ printf("\n\t\tCE_n\t: in std_logic;", dWidth - 1);
+ printf("\n\t\tOE_n\t: in std_logic;", dWidth - 1);
+ }
+ if (O == 's')
+ {
+ printf("\n\t\tClk\t: in std_logic;", dWidth - 1);
+ }
+ printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
+ printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
+ printf("\n\t);");
+ printf("\nend %s;", outFileName.c_str());
+ printf("\n\narchitecture rtl of %s is", outFileName.c_str());
+ if (!O)
+ {
+ printf("\nbegin");
+ printf("\n\tprocess (A)");
+ printf("\n\tbegin");
+ printf("\n\t\tcase to_integer(unsigned(A)) is");
+ }
+ else if (O == 's')
+ {
+ printf("\nbegin");
+ printf("\n\tprocess (Clk)");
+ printf("\n\tbegin");
+ printf("\n\t\tif Clk'event and Clk = '1' then");
+ printf("\n\t\tcase to_integer(unsigned(A)) is");
+ }
+ else
+ {
+ printf("\n\tsubtype ROM_WORD is std_logic_vector(%d downto 0);", dWidth - 1);
+ printf("\n\ttype ROM_TABLE is array(0 to %d) of ROM_WORD;", words - 1);
+ printf("\n\tconstant ROM: ROM_TABLE := ROM_TABLE'(");
+ }
+
+ string str;
+ string strDC;
+ for (i = 0; i < dWidth; i++)
+ {
+ strDC.insert(0, "-");
+ }
+ for (i = 0; i < words; i++)
+ {
+ if (!inFile.BitString(i * bytes, dWidth, endian == 'l', str))
+ {
+ str = strDC;
+ }
+ if (!O || O == 's')
+ {
+ if (inFile.m_top / bytes >= i)
+ {
+ printf("\n\t\twhen %06d => D <= \"%s\";",i, str.c_str());
+ printf("\t-- 0x%04X", i * bytes);
+ }
+ }
+ else
+ {
+ printf("\n\t\t\"%s", str.c_str());
+ if (i != words - 1)
+ {
+ printf("\",");
+ }
+ else
+ {
+ printf("\");");
+ }
+ printf("\t-- 0x%04X", i * bytes);
+ }
+ }
+
+ if (!O || O == 's')
+ {
+ printf("\n\t\twhen others => D <= \"%s\";", strDC.c_str());
+ printf("\n\t\tend case;");
+ if (O == 's')
+ printf("\n\tend if;");
+ printf("\n\tend process;");
+ }
+ else
+ {
+ printf("\nbegin");
+ if (O == 'z')
+ {
+ printf("\n\tD <= ROM(to_integer(unsigned(A))) when CE_n = '0' and OE_n = '0' else (others => 'Z');");
+ }
+ else
+ {
+ printf("\n\tD <= ROM(to_integer(unsigned(A)));");
+ }
+ }
+ printf("\nend;\n");
+ }
+ else
+ {
+ unsigned long selectIter = 0;
+ unsigned long blockIter = 0;
+
+ if (!select)
+ {
+ blockIter = ((1UL << aWidth) + 511) / 512;
+ }
+ else if (select == 16)
+ {
+ selectIter = ((1UL << aWidth) + 15) / 16;
+ }
+ else
+ {
+ blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
+ selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
+ }
+
+ cerr << "Creating .ucf file with " << selectIter * bytes;
+ cerr << " LUTs and " << blockIter * bytes << " block RAMs\n";
+
+ unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
+
+ printf("# This file was generated with hex2rom written by Daniel Wallner\n");
+
+ for (i = 0; i < selectIter; i++)
+ {
+ unsigned long base = i * 16 * bytes;
+ unsigned long j;
+ unsigned char c;
+ unsigned long pos;
+
+ // Check that there is any actual data in segment
+ bool init = false;
+ for (pos = 0; pos < bytes * 16; pos++)
+ {
+ init = inFile.GetByte(base + pos, c);
+ if (init)
+ {
+ break;
+ }
+ }
+
+ if (init)
+ {
+ for (j = 0; j < dWidth; j++)
+ {
+ unsigned long bitMask = 1;
+ unsigned long bits = 0;
+
+ for (pos = 0; pos < 16; pos++)
+ {
+ unsigned long addr;
+
+ if (endian = 'l')
+ {
+ addr = base + bytes * pos + j / 8;
+ }
+ else
+ {
+ addr = base + bytes * pos + bytes - j / 8 - 1;
+ }
+
+ c = 0;
+ inFile.GetByte(addr, c);
+ if (c & (1 << (j % 8)))
+ {
+ bits |= bitMask;
+ }
+ bitMask <<= 1;
+ }
+
+ if (O == 'u')
+ {
+ if (selectIter == 1)
+ {
+ printf("\nINST *s%s%d INIT = %04X;", outFileName.c_str(), j, bits);
+ }
+ else
+ {
+ printf("\nINST *s%s%d%d INIT = %04X;", outFileName.c_str(), i, j, bits);
+ }
+ }
+ else
+ {
+ if (selectIter == 1)
+ {
+ printf("\nINST *sG1_%d_S%s INIT = %04X;", j, outFileName.c_str(), bits);
+ }
+ else
+ {
+ printf("\nINST *sG1_%d_sG2_%d_S%s INIT = %04X;", i, j, outFileName.c_str(), bits);
+ }
+ }
+ }
+ }
+ }
+
+ for (i = blockTotal - blockIter; i < blockTotal; i++)
+ {
+ unsigned long j;
+ for (j = 0; j < bytes; j++)
+ {
+ unsigned long k;
+ for (k = 0; k < 16; k++)
+ {
+ unsigned long base = i * 512 * bytes + k * 32 * bytes;
+ unsigned char c;
+ unsigned long pos;
+
+ // Check that there is any actual data in segment
+ bool init = false;
+ for (pos = 0; pos < 32; pos++)
+ {
+ init = inFile.GetByte(base + bytes * pos + j, c);
+ if (init)
+ {
+ break;
+ }
+ }
+
+ if (init)
+ {
+ if (O == 'u')
+ {
+ if (blockIter == 1)
+ {
+ printf("\nINST *b%s%d INIT_%02X = ", outFileName.c_str(), j, k);
+ }
+ else
+ {
+ printf("\nINST *b%s%d%d INIT_%02X = ", outFileName.c_str(), i, j, k);
+ }
+ }
+ else
+ {
+ if (blockIter == 1)
+ {
+ printf("\nINST *bG1_%d_B%s INIT_%02X = ", j, outFileName.c_str(), k);
+ }
+ else
+ {
+ printf("\nINST *bG1_%d_bG2_%d_B%s INIT_%02X = ", i, j, outFileName.c_str(), k);
+ }
+ }
+ for (pos = 0; pos < 32; pos++)
+ {
+ unsigned long addr;
+
+ if (endian = 'l')
+ {
+ addr = base + bytes * (31 - pos) + j;
+ }
+ else
+ {
+ addr = base + bytes * (31 - pos) + bytes - j - 1;
+ }
+
+ c = 0;
+ inFile.GetByte(addr, c);
+ printf("%02X", c);
+ }
+ printf(";");
+ }
+ }
+ }
+ }
+ printf("\n");
+ }
+ return 0;
+ }
+ catch (string error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ catch (const char *error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ return -1;
+}
Index: tags/rel_1_2/sw/init_project.template.sh
===================================================================
--- tags/rel_1_2/sw/init_project.template.sh (nonexistent)
+++ tags/rel_1_2/sw/init_project.template.sh (revision 180)
@@ -0,0 +1,14 @@
+##############################################################################
+#
+# Template script to set up all project-specific environemt variables.
+#
+# Copy this script to init_project.sh and fill in your local information.
+#
+# This script has to be sourced from the command line!
+# Do not run it as a 'usual' program, as this does not set the variables
+# in the current shell process.
+#
+##############################################################################
+
+export PROJECT_DIR=/t400
+export MAKEFILES=$PROJECT_DIR/sw/verif/include/Makefile
Index: tags/rel_1_2/syn/t421/xc3s1000/compile_project.tcl
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/compile_project.tcl (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/compile_project.tcl (revision 180)
@@ -0,0 +1,46 @@
+##############################################################################
+#
+# Generic project compile script
+#
+# $Id$
+#
+# Execute from within xtclsh.
+#
+# Environment variables:
+# $MODULE : Name of the toplevel project
+# -> mandatory <-
+# $BLD : Build directory where the project and all temporary files
+# are stored
+# -> optional, default is "bld" <-
+#
+##############################################################################
+
+# mandatory environment variable for project name: $MODULE
+if {[info exists env(MODULE)]} {
+ set PROJECT $env(MODULE)
+ puts "Info: Setting project name from \$MODULE: $PROJECT"
+} else {
+ puts "Error: Environment variable MODULE not set."
+ exit 1
+}
+
+# optional environment variable for build directory: $BLD
+# default is 'bld'
+puts -nonewline "Info: "
+if {[info exists env(BLD)]} {
+ set bld $env(BLD)
+ puts -nonewline "Setting build directory from \$BLD"
+} else {
+ set bld bld
+ puts -nonewline "Setting build directory to default"
+}
+puts ": $bld"
+
+cd $bld
+
+project open $PROJECT.ise
+
+puts "Starting design implementation..."
+process run "Generate Programming File"
+
+project close
tags/rel_1_2/syn/t421/xc3s1000/compile_project.tcl
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/syn/t421/xc3s1000/gen_ise_project.tcl
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/gen_ise_project.tcl (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/gen_ise_project.tcl (revision 180)
@@ -0,0 +1,160 @@
+###############################################################################
+#
+# $Id$
+#
+# Based on
+# Created by Phil Hays, Xilinx
+# Setup Xilinx environment, then run from Unix with "xtclsh dice.tcl"
+#
+# This Tcl script will implement a design and load it in the S3E FPGA on
+# the Spartan 3E Starter Kit Board
+#
+# There are two ucf files, one for pins and one for timing
+#
+###############################################################################
+# Contact : e-mail hotline@xilinx.com
+# phone + 1 800 255 7778
+#
+# Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
+# provided to you "as is". Xilinx and its licensors make and you
+# receive no warranties or conditions, express, implied,
+# statutory or otherwise, and Xilinx specifically disclaims any
+# implied warranties of merchantability, non-infringement, or
+# fitness for a particular purpose. Xilinx does not warrant that
+# the functions contained in these designs will meet your
+# requirements, or that the operation of these designs will be
+# uninterrupted or error free, or that defects in the Designs
+# will be corrected. Furthermore, Xilinx does not warrant or
+# make any representations regarding use or the results of the
+# use of the designs in terms of correctness, accuracy,
+# reliability, or otherwise.
+#
+# LIMITATION OF LIABILITY. In no event will Xilinx or its
+# licensors be liable for any loss of data, lost profits, cost
+# or procurement of substitute goods or services, or for any
+# special, incidental, consequential, or indirect damages
+# arising from the use or operation of the designs or
+# accompanying documentation, however caused and on any theory
+# of liability. This limitation will apply even if Xilinx
+# has been advised of the possibility of such damage. This
+# limitation shall apply not-withstanding the failure of the
+# essential purpose of any limited remedies herein.
+#
+# Copyright (c) 2006 Xilinx, Inc.
+# All rights reserved
+#
+###############################################################################
+# Version 1.0 - 19-Oct-2006
+# Initial version
+###############################################################################
+
+###############################################################################
+# MAIN
+###############################################################################
+# Modify the project settings for the specific design
+#
+# Make sure there are no files in the build directory that you may want to
+# keep, as this TCL script cleans that directory by default!
+###############################################################################
+
+# mandatory environment variable for project name: $MODULE
+if {[info exists env(MODULE)]} {
+ set PROJECT $env(MODULE)
+ puts "Info: Setting project name from \$MODULE: $PROJECT"
+} else {
+ puts "Error: Environment variable MODULE not set."
+ exit 1
+}
+
+# optional environment variable for build directory: $BLD
+# default is 'bld'
+puts -nonewline "Info: "
+if {[info exists env(BLD)]} {
+ set bld $env(BLD)
+ puts -nonewline "Setting build directory from \$BLD"
+} else {
+ set bld bld
+ puts -nonewline "Setting build directory to default"
+}
+puts ": $bld"
+
+# optional environment variable for source file compile list: $COMPILE_LIST
+# default is 'compile_list'
+puts -nonewline "Info: "
+if {[info exists env(COMPILE_LIST)]} {
+ set compile_list $env(COMPILE_LIST)
+ puts -nonewline "Setting source file compile list from \$COMPILE_LIST"
+} else {
+ set compile_list compile_list
+ puts -nonewline "Setting source file compile list to default"
+}
+puts ": $compile_list"
+
+if {[file exists $bld]} {
+ puts "Deleting all existing project files in '$bld'"
+ # Perhaps ask ok here??
+ # Or perhaps skip project creation if project exists??
+ file delete -force $bld
+}
+puts "Creating new project directory in '$bld'..."
+file mkdir $bld
+
+###############################################################################
+# Put two ucf file into one.
+# This could be made as complex as required, however for demonstration it is
+# just a simple copy.
+###############################################################################
+
+puts "Creating new UCF file..."
+
+set tempucf [file join $bld temp.ucf]
+set outfile [open $tempucf "w"]
+set infile [open "timing.ucf" "r"]
+while {![eof $infile]} {
+ puts $outfile [gets $infile]
+}
+close $infile
+close $outfile
+#
+puts "Creating new ISE project..."
+cd $bld
+project new $PROJECT.ise
+project set family spartan3
+project set device xc3s1000
+project set package fg456
+project set speed -4
+
+
+###############################################################################
+# Modify the xfile add argument for the source files in the design
+###############################################################################
+
+puts "Adding source files..."
+set infile [open "../compile_list" "r"]
+while {![eof $infile]} {
+ xfile add "../[gets $infile]"
+}
+xfile add temp.ucf
+
+
+###############################################################################
+# Set optional implementation options here. There is a problem with setting
+# project properties that at least one source must be added to the project
+# first. Therefore, the "project set" commands are after the "xfile add"
+# commands.
+###############################################################################
+
+puts "Setting project properties..."
+
+project set {Optimization Goal} Area -process {Synthesize - XST}
+project set {Optimization Effort} Normal -process {Synthesize - XST}
+#project set "Map Effort Level" High
+#project set {Perform Timing-Driven Packing and Placement} 1
+project set {Place & Route Effort Level (Overall)} Standard
+#project set "Other Place & Route Command Line Options" "-intsyle xflow"
+project set {Generate Post-Place & Route Static Timing Report} true
+project set {Report Unconstrained Paths} 10 -process {Generate Post-Place & Route Static Timing}
+project set {Report Type} {Verbose Report} -process {Generate Post-Place & Route Static Timing}
+project set {Create Binary Configuration File} 1 -process {Generate Programming File}
+
+project close
tags/rel_1_2/syn/t421/xc3s1000/gen_ise_project.tcl
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/syn/t421/xc3s1000/Makefile
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/Makefile (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/Makefile (revision 180)
@@ -0,0 +1,42 @@
+##############################################################################
+#
+# Generic Makefile for ISE projects
+#
+# $Id$
+#
+# Execute with 'make ', where target is one of
+# ise : build ISE project from
+# - files in compile_list
+# - project settings in timing.ucf and .ucf
+# - project settings applied in gen_ise_project.tcl
+# compile : compile ISE project by means of tcl script
+# compile_project.tcl
+# | all : run through all targets above
+#
+##############################################################################
+
+export MODULE := t421
+
+export COMPILE_LIST := compile_list
+SOURCE_FILES := $(shell cat $(COMPILE_LIST))
+export BLD := bld
+
+.PHONY: all
+all: $(BLD)/$(MODULE).bit
+
+.PHONY: ise
+ise: $(BLD)/$(MODULE).ise
+
+.PHONY: compile
+compile: $(BLD)/$(MODULE).bit
+
+$(BLD)/$(MODULE).ise: $(COMPILE_LIST) *.ucf gen_ise_project.tcl
+ xtclsh gen_ise_project.tcl
+
+$(BLD)/$(MODULE).bit: $(SOURCE_FILES) $(BLD)/$(MODULE).ise compile_project.tcl
+ xtclsh compile_project.tcl
+ touch $@
+
+.PHONY: clean
+clean:
+ rm -rf *~ bld
tags/rel_1_2/syn/t421/xc3s1000/Makefile
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/syn/t421/xc3s1000/compile_list
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/compile_list (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/compile_list (revision 180)
@@ -0,0 +1,30 @@
+../../../rtl/vhdl/t400_opt_pack-p.vhd
+../../../rtl/vhdl/t400_clkgen.vhd
+../../../rtl/vhdl/t400_reset.vhd
+../../../rtl/vhdl/t400_pack-p.vhd
+../../../rtl/vhdl/t400_pmem_ctrl.vhd
+../../../rtl/vhdl/t400_dmem_ctrl.vhd
+../../../rtl/vhdl/t400_comp_pack-p.vhd
+../../../rtl/vhdl/t400_mnemonic_pack-p.vhd
+../../../rtl/vhdl/t400_decoder.vhd
+../../../rtl/vhdl/t400_skip.vhd
+../../../rtl/vhdl/t400_alu.vhd
+../../../rtl/vhdl/t400_stack.vhd
+../../../rtl/vhdl/t400_io_pack-p.vhd
+../../../rtl/vhdl/t400_io_l.vhd
+../../../rtl/vhdl/t400_io_d.vhd
+../../../rtl/vhdl/t400_io_g.vhd
+../../../rtl/vhdl/t400_io_in.vhd
+../../../rtl/vhdl/t400_sio.vhd
+../../../rtl/vhdl/t400_timer.vhd
+../../../rtl/vhdl/t400_core.vhd
+../../../rtl/tech/generic/generic_ram_ena.vhd
+rom_t42x.vhd
+../../../rtl/vhdl/system/t420_rom-e.vhd
+../../../rtl/vhdl/system/t420_rom-struct-a.vhd
+../../../rtl/tech/spartan/t400_por.vhd
+../../../rtl/vhdl/t400_core_comp_pack-p.vhd
+../../../rtl/tech/t400_tech_comp_pack-p.vhd
+../../../rtl/vhdl/system/t420_notri.vhd
+../../../rtl/vhdl/system/t400_system_comp_pack-p.vhd
+../../../rtl/vhdl/system/t421.vhd
Index: tags/rel_1_2/syn/t421/xc3s1000/rom_t42x.vhd
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/rom_t42x.vhd (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/rom_t42x.vhd (revision 180)
@@ -0,0 +1,604 @@
+-- This file was generated with hex2rom written by Daniel Wallner
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rom_t42x is
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(9 downto 0);
+ D : out std_logic_vector(7 downto 0)
+ );
+end rom_t42x;
+
+architecture rtl of rom_t42x is
+begin
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ case to_integer(unsigned(A)) is
+ when 000000 => D <= "01000100"; -- 0x0000
+ when 000001 => D <= "00110011"; -- 0x0001
+ when 000002 => D <= "01011001"; -- 0x0002
+ when 000003 => D <= "00110011"; -- 0x0003
+ when 000004 => D <= "01010110"; -- 0x0004
+ when 000005 => D <= "01111000"; -- 0x0005
+ when 000006 => D <= "00111100"; -- 0x0006
+ when 000007 => D <= "00110011"; -- 0x0007
+ when 000008 => D <= "00111110"; -- 0x0008
+ when 000009 => D <= "00000000"; -- 0x0009
+ when 000010 => D <= "00010010"; -- 0x000A
+ when 000011 => D <= "01010000"; -- 0x000B
+ when 000012 => D <= "00110011"; -- 0x000C
+ when 000013 => D <= "00111110"; -- 0x000D
+ when 000014 => D <= "00000000"; -- 0x000E
+ when 000015 => D <= "01010010"; -- 0x000F
+ when 000016 => D <= "01010000"; -- 0x0010
+ when 000017 => D <= "00110011"; -- 0x0011
+ when 000018 => D <= "00111110"; -- 0x0012
+ when 000019 => D <= "01110111"; -- 0x0013
+ when 000020 => D <= "00110011"; -- 0x0014
+ when 000021 => D <= "00111110"; -- 0x0015
+ when 000022 => D <= "01010000"; -- 0x0016
+ when 000023 => D <= "00110011"; -- 0x0017
+ when 000024 => D <= "00111010"; -- 0x0018
+ when 000025 => D <= "00000000"; -- 0x0019
+ when 000026 => D <= "01010000"; -- 0x001A
+ when 000027 => D <= "00110011"; -- 0x001B
+ when 000028 => D <= "00111010"; -- 0x001C
+ when 000029 => D <= "01001101"; -- 0x001D
+ when 000030 => D <= "00110011"; -- 0x001E
+ when 000031 => D <= "00111010"; -- 0x001F
+ when 000032 => D <= "01000111"; -- 0x0020
+ when 000033 => D <= "00110011"; -- 0x0021
+ when 000034 => D <= "00111010"; -- 0x0022
+ when 000035 => D <= "01001100"; -- 0x0023
+ when 000036 => D <= "01000011"; -- 0x0024
+ when 000037 => D <= "00000101"; -- 0x0025
+ when 000038 => D <= "01010000"; -- 0x0026
+ when 000039 => D <= "00110011"; -- 0x0027
+ when 000040 => D <= "00111010"; -- 0x0028
+ when 000041 => D <= "00010101"; -- 0x0029
+ when 000042 => D <= "00100011"; -- 0x002A
+ when 000043 => D <= "10000000"; -- 0x002B
+ when 000044 => D <= "01011111"; -- 0x002C
+ when 000045 => D <= "00100011"; -- 0x002D
+ when 000046 => D <= "00000000"; -- 0x002E
+ when 000047 => D <= "00000110"; -- 0x002F
+ when 000048 => D <= "00110011"; -- 0x0030
+ when 000049 => D <= "00111010"; -- 0x0031
+ when 000050 => D <= "00000101"; -- 0x0032
+ when 000051 => D <= "01001010"; -- 0x0033
+ when 000052 => D <= "00000111"; -- 0x0034
+ when 000053 => D <= "00000111"; -- 0x0035
+ when 000054 => D <= "00110011"; -- 0x0036
+ when 000055 => D <= "00111110"; -- 0x0037
+ when 000056 => D <= "01110101"; -- 0x0038
+ when 000057 => D <= "01001110"; -- 0x0039
+ when 000058 => D <= "01010011"; -- 0x003A
+ when 000059 => D <= "00000111"; -- 0x003B
+ when 000060 => D <= "00110011"; -- 0x003C
+ when 000061 => D <= "00111010"; -- 0x003D
+ when 000062 => D <= "00000111"; -- 0x003E
+ when 000063 => D <= "00100011"; -- 0x003F
+ when 000064 => D <= "00000000"; -- 0x0040
+ when 000065 => D <= "00110011"; -- 0x0041
+ when 000066 => D <= "00111110"; -- 0x0042
+ when 000067 => D <= "01010100"; -- 0x0043
+ when 000068 => D <= "00000110"; -- 0x0044
+ when 000069 => D <= "00110011"; -- 0x0045
+ when 000070 => D <= "00111010"; -- 0x0046
+ when 000071 => D <= "00000000"; -- 0x0047
+ when 000072 => D <= "01000000"; -- 0x0048
+ when 000073 => D <= "00000010"; -- 0x0049
+ when 000074 => D <= "00000100"; -- 0x004A
+ when 000075 => D <= "00100011"; -- 0x004B
+ when 000076 => D <= "00000000"; -- 0x004C
+ when 000077 => D <= "01011000"; -- 0x004D
+ when 000078 => D <= "00100011"; -- 0x004E
+ when 000079 => D <= "00000000"; -- 0x004F
+ when 000080 => D <= "00100001"; -- 0x0050
+ when 000081 => D <= "00110011"; -- 0x0051
+ when 000082 => D <= "10010010"; -- 0x0052
+ when 000083 => D <= "00110011"; -- 0x0053
+ when 000084 => D <= "00111110"; -- 0x0054
+ when 000085 => D <= "00100001"; -- 0x0055
+ when 000086 => D <= "00011111"; -- 0x0056
+ when 000087 => D <= "01000110"; -- 0x0057
+ when 000088 => D <= "00100001"; -- 0x0058
+ when 000089 => D <= "01000010"; -- 0x0059
+ when 000090 => D <= "00100001"; -- 0x005A
+ when 000091 => D <= "01001011"; -- 0x005B
+ when 000092 => D <= "00100001"; -- 0x005C
+ when 000093 => D <= "00100011"; -- 0x005D
+ when 000094 => D <= "00000000"; -- 0x005E
+ when 000095 => D <= "00110110"; -- 0x005F
+ when 000096 => D <= "00100011"; -- 0x0060
+ when 000097 => D <= "10010001"; -- 0x0061
+ when 000098 => D <= "00010100"; -- 0x0062
+ when 000099 => D <= "00110011"; -- 0x0063
+ when 000100 => D <= "00101010"; -- 0x0064
+ when 000101 => D <= "00000110"; -- 0x0065
+ when 000102 => D <= "00000000"; -- 0x0066
+ when 000103 => D <= "00110000"; -- 0x0067
+ when 000104 => D <= "00100010"; -- 0x0068
+ when 000105 => D <= "00100000"; -- 0x0069
+ when 000106 => D <= "00100011"; -- 0x006A
+ when 000107 => D <= "00000000"; -- 0x006B
+ when 000108 => D <= "00000110"; -- 0x006C
+ when 000109 => D <= "00110011"; -- 0x006D
+ when 000110 => D <= "00111010"; -- 0x006E
+ when 000111 => D <= "00000000"; -- 0x006F
+ when 000112 => D <= "00110000"; -- 0x0070
+ when 000113 => D <= "00000110"; -- 0x0071
+ when 000114 => D <= "00110011"; -- 0x0072
+ when 000115 => D <= "00111010"; -- 0x0073
+ when 000116 => D <= "00110011"; -- 0x0074
+ when 000117 => D <= "00111100"; -- 0x0075
+ when 000118 => D <= "00000111"; -- 0x0076
+ when 000119 => D <= "00110011"; -- 0x0077
+ when 000120 => D <= "00101100"; -- 0x0078
+ when 000121 => D <= "00110011"; -- 0x0079
+ when 000122 => D <= "00111010"; -- 0x007A
+ when 000123 => D <= "00100101"; -- 0x007B
+ when 000124 => D <= "00110011"; -- 0x007C
+ when 000125 => D <= "00111010"; -- 0x007D
+ when 000126 => D <= "00110101"; -- 0x007E
+ when 000127 => D <= "00110011"; -- 0x007F
+ when 000128 => D <= "00111010"; -- 0x0080
+ when 000129 => D <= "00110001"; -- 0x0081
+ when 000130 => D <= "00000110"; -- 0x0082
+ when 000131 => D <= "00100010"; -- 0x0083
+ when 000132 => D <= "00100011"; -- 0x0084
+ when 000133 => D <= "00000000"; -- 0x0085
+ when 000134 => D <= "00010000"; -- 0x0086
+ when 000135 => D <= "00100000"; -- 0x0087
+ when 000136 => D <= "00000110"; -- 0x0088
+ when 000137 => D <= "00110011"; -- 0x0089
+ when 000138 => D <= "00111010"; -- 0x008A
+ when 000139 => D <= "00000000"; -- 0x008B
+ when 000140 => D <= "01010011"; -- 0x008C
+ when 000141 => D <= "00000110"; -- 0x008D
+ when 000142 => D <= "00100010"; -- 0x008E
+ when 000143 => D <= "00100000"; -- 0x008F
+ when 000144 => D <= "00000110"; -- 0x0090
+ when 000145 => D <= "00110011"; -- 0x0091
+ when 000146 => D <= "00111010"; -- 0x0092
+ when 000147 => D <= "00110010"; -- 0x0093
+ when 000148 => D <= "00100000"; -- 0x0094
+ when 000149 => D <= "00000110"; -- 0x0095
+ when 000150 => D <= "00110011"; -- 0x0096
+ when 000151 => D <= "00111010"; -- 0x0097
+ when 000152 => D <= "00001111"; -- 0x0098
+ when 000153 => D <= "00011110"; -- 0x0099
+ when 000154 => D <= "00110011"; -- 0x009A
+ when 000155 => D <= "10100111"; -- 0x009B
+ when 000156 => D <= "00110011"; -- 0x009C
+ when 000157 => D <= "00111010"; -- 0x009D
+ when 000158 => D <= "00110011"; -- 0x009E
+ when 000159 => D <= "00101100"; -- 0x009F
+ when 000160 => D <= "00110011"; -- 0x00A0
+ when 000161 => D <= "00111010"; -- 0x00A1
+ when 000162 => D <= "00000110"; -- 0x00A2
+ when 000163 => D <= "00110011"; -- 0x00A3
+ when 000164 => D <= "00111010"; -- 0x00A4
+ when 000165 => D <= "00110011"; -- 0x00A5
+ when 000166 => D <= "01100001"; -- 0x00A6
+ when 000167 => D <= "01001111"; -- 0x00A7
+ when 000168 => D <= "00000000"; -- 0x00A8
+ when 000169 => D <= "01010111"; -- 0x00A9
+ when 000170 => D <= "00110011"; -- 0x00AA
+ when 000171 => D <= "00000001"; -- 0x00AB
+ when 000172 => D <= "00000110"; -- 0x00AC
+ when 000173 => D <= "00110011"; -- 0x00AD
+ when 000174 => D <= "00111010"; -- 0x00AE
+ when 000175 => D <= "00110011"; -- 0x00AF
+ when 000176 => D <= "00010001"; -- 0x00B0
+ when 000177 => D <= "00000110"; -- 0x00B1
+ when 000178 => D <= "00110011"; -- 0x00B2
+ when 000179 => D <= "00111010"; -- 0x00B3
+ when 000180 => D <= "00110011"; -- 0x00B4
+ when 000181 => D <= "00000011"; -- 0x00B5
+ when 000182 => D <= "00000110"; -- 0x00B6
+ when 000183 => D <= "00110011"; -- 0x00B7
+ when 000184 => D <= "00111010"; -- 0x00B8
+ when 000185 => D <= "00110011"; -- 0x00B9
+ when 000186 => D <= "00010011"; -- 0x00BA
+ when 000187 => D <= "00000110"; -- 0x00BB
+ when 000188 => D <= "00110011"; -- 0x00BC
+ when 000189 => D <= "00111010"; -- 0x00BD
+ when 000190 => D <= "00110011"; -- 0x00BE
+ when 000191 => D <= "00100001"; -- 0x00BF
+ when 000192 => D <= "00000110"; -- 0x00C0
+ when 000193 => D <= "00110011"; -- 0x00C1
+ when 000194 => D <= "00111010"; -- 0x00C2
+ when 000195 => D <= "00110011"; -- 0x00C3
+ when 000196 => D <= "01010000"; -- 0x00C4
+ when 000197 => D <= "00110011"; -- 0x00C5
+ when 000198 => D <= "00100001"; -- 0x00C6
+ when 000199 => D <= "00000110"; -- 0x00C7
+ when 000200 => D <= "00110011"; -- 0x00C8
+ when 000201 => D <= "00111010"; -- 0x00C9
+ when 000202 => D <= "00000001"; -- 0x00CA
+ when 000203 => D <= "00000110"; -- 0x00CB
+ when 000204 => D <= "00110011"; -- 0x00CC
+ when 000205 => D <= "00111010"; -- 0x00CD
+ when 000206 => D <= "00010001"; -- 0x00CE
+ when 000207 => D <= "00000110"; -- 0x00CF
+ when 000208 => D <= "00110011"; -- 0x00D0
+ when 000209 => D <= "00111010"; -- 0x00D1
+ when 000210 => D <= "00000011"; -- 0x00D2
+ when 000211 => D <= "00000110"; -- 0x00D3
+ when 000212 => D <= "00110011"; -- 0x00D4
+ when 000213 => D <= "00111010"; -- 0x00D5
+ when 000214 => D <= "00110011"; -- 0x00D6
+ when 000215 => D <= "00101001"; -- 0x00D7
+ when 000216 => D <= "00110011"; -- 0x00D8
+ when 000217 => D <= "00101000"; -- 0x00D9
+ when 000218 => D <= "00100001"; -- 0x00DA
+ when 000219 => D <= "00010110"; -- 0x00DB
+ when 000220 => D <= "00110011"; -- 0x00DC
+ when 000221 => D <= "00111010"; -- 0x00DD
+ when 000222 => D <= "00110011"; -- 0x00DE
+ when 000223 => D <= "00101001"; -- 0x00DF
+ when 000224 => D <= "00000110"; -- 0x00E0
+ when 000225 => D <= "00010011"; -- 0x00E1
+ when 000226 => D <= "00110011"; -- 0x00E2
+ when 000227 => D <= "00111110"; -- 0x00E3
+ when 000228 => D <= "00110011"; -- 0x00E4
+ when 000229 => D <= "01010001"; -- 0x00E5
+ when 000230 => D <= "00111010"; -- 0x00E6
+ when 000231 => D <= "00110011"; -- 0x00E7
+ when 000232 => D <= "01010000"; -- 0x00E8
+ when 000233 => D <= "01000100"; -- 0x00E9
+ when 000234 => D <= "00110011"; -- 0x00EA
+ when 000235 => D <= "00101001"; -- 0x00EB
+ when 000236 => D <= "00000110"; -- 0x00EC
+ when 000237 => D <= "00000001"; -- 0x00ED
+ when 000238 => D <= "00110011"; -- 0x00EE
+ when 000239 => D <= "00111110"; -- 0x00EF
+ when 000240 => D <= "01000100"; -- 0x00F0
+ when 000241 => D <= "01001111"; -- 0x00F1
+ when 000242 => D <= "00000110"; -- 0x00F2
+ when 000243 => D <= "00110011"; -- 0x00F3
+ when 000244 => D <= "00111010"; -- 0x00F4
+ when 000245 => D <= "00001111"; -- 0x00F5
+ when 000246 => D <= "01110111"; -- 0x00F6
+ when 000247 => D <= "01111110"; -- 0x00F7
+ when 000248 => D <= "01110101"; -- 0x00F8
+ when 000249 => D <= "01111100"; -- 0x00F9
+ when 000250 => D <= "01110011"; -- 0x00FA
+ when 000251 => D <= "01111010"; -- 0x00FB
+ when 000252 => D <= "01110001"; -- 0x00FC
+ when 000253 => D <= "01111000"; -- 0x00FD
+ when 000254 => D <= "01111111"; -- 0x00FE
+ when 000255 => D <= "01110110"; -- 0x00FF
+ when 000256 => D <= "01111101"; -- 0x0100
+ when 000257 => D <= "01110100"; -- 0x0101
+ when 000258 => D <= "01111011"; -- 0x0102
+ when 000259 => D <= "01110010"; -- 0x0103
+ when 000260 => D <= "01111001"; -- 0x0104
+ when 000261 => D <= "01110000"; -- 0x0105
+ when 000262 => D <= "00011111"; -- 0x0106
+ when 000263 => D <= "01110111"; -- 0x0107
+ when 000264 => D <= "01111110"; -- 0x0108
+ when 000265 => D <= "01110101"; -- 0x0109
+ when 000266 => D <= "01111100"; -- 0x010A
+ when 000267 => D <= "01110011"; -- 0x010B
+ when 000268 => D <= "01111010"; -- 0x010C
+ when 000269 => D <= "01110001"; -- 0x010D
+ when 000270 => D <= "01111000"; -- 0x010E
+ when 000271 => D <= "01111111"; -- 0x010F
+ when 000272 => D <= "01110110"; -- 0x0110
+ when 000273 => D <= "01111101"; -- 0x0111
+ when 000274 => D <= "01110100"; -- 0x0112
+ when 000275 => D <= "01111011"; -- 0x0113
+ when 000276 => D <= "01110010"; -- 0x0114
+ when 000277 => D <= "01111001"; -- 0x0115
+ when 000278 => D <= "01110000"; -- 0x0116
+ when 000279 => D <= "00101111"; -- 0x0117
+ when 000280 => D <= "01110111"; -- 0x0118
+ when 000281 => D <= "01111110"; -- 0x0119
+ when 000282 => D <= "01110101"; -- 0x011A
+ when 000283 => D <= "01111100"; -- 0x011B
+ when 000284 => D <= "01110011"; -- 0x011C
+ when 000285 => D <= "01111010"; -- 0x011D
+ when 000286 => D <= "01110001"; -- 0x011E
+ when 000287 => D <= "01111000"; -- 0x011F
+ when 000288 => D <= "01111111"; -- 0x0120
+ when 000289 => D <= "01110110"; -- 0x0121
+ when 000290 => D <= "01111101"; -- 0x0122
+ when 000291 => D <= "01110100"; -- 0x0123
+ when 000292 => D <= "01111011"; -- 0x0124
+ when 000293 => D <= "01110010"; -- 0x0125
+ when 000294 => D <= "01111001"; -- 0x0126
+ when 000295 => D <= "01110000"; -- 0x0127
+ when 000296 => D <= "00111111"; -- 0x0128
+ when 000297 => D <= "01110111"; -- 0x0129
+ when 000298 => D <= "01111110"; -- 0x012A
+ when 000299 => D <= "01110101"; -- 0x012B
+ when 000300 => D <= "01111100"; -- 0x012C
+ when 000301 => D <= "01110011"; -- 0x012D
+ when 000302 => D <= "01111010"; -- 0x012E
+ when 000303 => D <= "01110001"; -- 0x012F
+ when 000304 => D <= "01111000"; -- 0x0130
+ when 000305 => D <= "01111111"; -- 0x0131
+ when 000306 => D <= "01110110"; -- 0x0132
+ when 000307 => D <= "01111101"; -- 0x0133
+ when 000308 => D <= "01110100"; -- 0x0134
+ when 000309 => D <= "01111011"; -- 0x0135
+ when 000310 => D <= "01110010"; -- 0x0136
+ when 000311 => D <= "01111001"; -- 0x0137
+ when 000312 => D <= "01110000"; -- 0x0138
+ when 000313 => D <= "00001111"; -- 0x0139
+ when 000314 => D <= "00110011"; -- 0x013A
+ when 000315 => D <= "00111010"; -- 0x013B
+ when 000316 => D <= "00000101"; -- 0x013C
+ when 000317 => D <= "00000100"; -- 0x013D
+ when 000318 => D <= "00110011"; -- 0x013E
+ when 000319 => D <= "00111010"; -- 0x013F
+ when 000320 => D <= "00000101"; -- 0x0140
+ when 000321 => D <= "00000100"; -- 0x0141
+ when 000322 => D <= "00110011"; -- 0x0142
+ when 000323 => D <= "00111010"; -- 0x0143
+ when 000324 => D <= "00000101"; -- 0x0144
+ when 000325 => D <= "00000100"; -- 0x0145
+ when 000326 => D <= "00110011"; -- 0x0146
+ when 000327 => D <= "00111010"; -- 0x0147
+ when 000328 => D <= "00000101"; -- 0x0148
+ when 000329 => D <= "00000100"; -- 0x0149
+ when 000330 => D <= "00110011"; -- 0x014A
+ when 000331 => D <= "00111010"; -- 0x014B
+ when 000332 => D <= "00000101"; -- 0x014C
+ when 000333 => D <= "00000100"; -- 0x014D
+ when 000334 => D <= "00110011"; -- 0x014E
+ when 000335 => D <= "00111010"; -- 0x014F
+ when 000336 => D <= "00000101"; -- 0x0150
+ when 000337 => D <= "00000100"; -- 0x0151
+ when 000338 => D <= "00110011"; -- 0x0152
+ when 000339 => D <= "00111010"; -- 0x0153
+ when 000340 => D <= "00000101"; -- 0x0154
+ when 000341 => D <= "00000100"; -- 0x0155
+ when 000342 => D <= "00110011"; -- 0x0156
+ when 000343 => D <= "00111010"; -- 0x0157
+ when 000344 => D <= "00000101"; -- 0x0158
+ when 000345 => D <= "00000100"; -- 0x0159
+ when 000346 => D <= "00110011"; -- 0x015A
+ when 000347 => D <= "00111010"; -- 0x015B
+ when 000348 => D <= "00000101"; -- 0x015C
+ when 000349 => D <= "00000100"; -- 0x015D
+ when 000350 => D <= "00110011"; -- 0x015E
+ when 000351 => D <= "00111010"; -- 0x015F
+ when 000352 => D <= "00000101"; -- 0x0160
+ when 000353 => D <= "00000100"; -- 0x0161
+ when 000354 => D <= "00110011"; -- 0x0162
+ when 000355 => D <= "00111010"; -- 0x0163
+ when 000356 => D <= "00000101"; -- 0x0164
+ when 000357 => D <= "00000100"; -- 0x0165
+ when 000358 => D <= "00110011"; -- 0x0166
+ when 000359 => D <= "00111010"; -- 0x0167
+ when 000360 => D <= "00000101"; -- 0x0168
+ when 000361 => D <= "00000100"; -- 0x0169
+ when 000362 => D <= "00110011"; -- 0x016A
+ when 000363 => D <= "00111010"; -- 0x016B
+ when 000364 => D <= "00000101"; -- 0x016C
+ when 000365 => D <= "00000100"; -- 0x016D
+ when 000366 => D <= "00110011"; -- 0x016E
+ when 000367 => D <= "00111010"; -- 0x016F
+ when 000368 => D <= "00000101"; -- 0x0170
+ when 000369 => D <= "00000100"; -- 0x0171
+ when 000370 => D <= "00110011"; -- 0x0172
+ when 000371 => D <= "00111010"; -- 0x0173
+ when 000372 => D <= "00000101"; -- 0x0174
+ when 000373 => D <= "00000100"; -- 0x0175
+ when 000374 => D <= "00110011"; -- 0x0176
+ when 000375 => D <= "00111010"; -- 0x0177
+ when 000376 => D <= "00000101"; -- 0x0178
+ when 000377 => D <= "00000100"; -- 0x0179
+ when 000378 => D <= "01000100"; -- 0x017A
+ when 000379 => D <= "00011111"; -- 0x017B
+ when 000380 => D <= "00110011"; -- 0x017C
+ when 000381 => D <= "00111010"; -- 0x017D
+ when 000382 => D <= "00000101"; -- 0x017E
+ when 000383 => D <= "00000100"; -- 0x017F
+ when 000384 => D <= "00110011"; -- 0x0180
+ when 000385 => D <= "00111010"; -- 0x0181
+ when 000386 => D <= "00000101"; -- 0x0182
+ when 000387 => D <= "00000100"; -- 0x0183
+ when 000388 => D <= "00110011"; -- 0x0184
+ when 000389 => D <= "00111010"; -- 0x0185
+ when 000390 => D <= "00000101"; -- 0x0186
+ when 000391 => D <= "00000100"; -- 0x0187
+ when 000392 => D <= "00110011"; -- 0x0188
+ when 000393 => D <= "00111010"; -- 0x0189
+ when 000394 => D <= "00000101"; -- 0x018A
+ when 000395 => D <= "00000100"; -- 0x018B
+ when 000396 => D <= "00110011"; -- 0x018C
+ when 000397 => D <= "00111010"; -- 0x018D
+ when 000398 => D <= "00000101"; -- 0x018E
+ when 000399 => D <= "00000100"; -- 0x018F
+ when 000400 => D <= "00110011"; -- 0x0190
+ when 000401 => D <= "00111010"; -- 0x0191
+ when 000402 => D <= "00000101"; -- 0x0192
+ when 000403 => D <= "00000100"; -- 0x0193
+ when 000404 => D <= "00110011"; -- 0x0194
+ when 000405 => D <= "00111010"; -- 0x0195
+ when 000406 => D <= "00000101"; -- 0x0196
+ when 000407 => D <= "00000100"; -- 0x0197
+ when 000408 => D <= "00110011"; -- 0x0198
+ when 000409 => D <= "00111010"; -- 0x0199
+ when 000410 => D <= "00000101"; -- 0x019A
+ when 000411 => D <= "00000100"; -- 0x019B
+ when 000412 => D <= "00110011"; -- 0x019C
+ when 000413 => D <= "00111010"; -- 0x019D
+ when 000414 => D <= "00000101"; -- 0x019E
+ when 000415 => D <= "00000100"; -- 0x019F
+ when 000416 => D <= "00110011"; -- 0x01A0
+ when 000417 => D <= "00111010"; -- 0x01A1
+ when 000418 => D <= "00000101"; -- 0x01A2
+ when 000419 => D <= "00000100"; -- 0x01A3
+ when 000420 => D <= "00110011"; -- 0x01A4
+ when 000421 => D <= "00111010"; -- 0x01A5
+ when 000422 => D <= "00000101"; -- 0x01A6
+ when 000423 => D <= "00000100"; -- 0x01A7
+ when 000424 => D <= "00110011"; -- 0x01A8
+ when 000425 => D <= "00111010"; -- 0x01A9
+ when 000426 => D <= "00000101"; -- 0x01AA
+ when 000427 => D <= "00000100"; -- 0x01AB
+ when 000428 => D <= "00110011"; -- 0x01AC
+ when 000429 => D <= "00111010"; -- 0x01AD
+ when 000430 => D <= "00000101"; -- 0x01AE
+ when 000431 => D <= "00000100"; -- 0x01AF
+ when 000432 => D <= "00110011"; -- 0x01B0
+ when 000433 => D <= "00111010"; -- 0x01B1
+ when 000434 => D <= "00000101"; -- 0x01B2
+ when 000435 => D <= "00000100"; -- 0x01B3
+ when 000436 => D <= "00110011"; -- 0x01B4
+ when 000437 => D <= "00111010"; -- 0x01B5
+ when 000438 => D <= "00000101"; -- 0x01B6
+ when 000439 => D <= "00000100"; -- 0x01B7
+ when 000440 => D <= "00110011"; -- 0x01B8
+ when 000441 => D <= "00111010"; -- 0x01B9
+ when 000442 => D <= "00000101"; -- 0x01BA
+ when 000443 => D <= "00000100"; -- 0x01BB
+ when 000444 => D <= "01000100"; -- 0x01BC
+ when 000445 => D <= "00101111"; -- 0x01BD
+ when 000446 => D <= "00110011"; -- 0x01BE
+ when 000447 => D <= "00111010"; -- 0x01BF
+ when 000448 => D <= "00000101"; -- 0x01C0
+ when 000449 => D <= "00000100"; -- 0x01C1
+ when 000450 => D <= "00110011"; -- 0x01C2
+ when 000451 => D <= "00111010"; -- 0x01C3
+ when 000452 => D <= "00000101"; -- 0x01C4
+ when 000453 => D <= "00000100"; -- 0x01C5
+ when 000454 => D <= "00110011"; -- 0x01C6
+ when 000455 => D <= "00111010"; -- 0x01C7
+ when 000456 => D <= "00000101"; -- 0x01C8
+ when 000457 => D <= "00000100"; -- 0x01C9
+ when 000458 => D <= "00110011"; -- 0x01CA
+ when 000459 => D <= "00111010"; -- 0x01CB
+ when 000460 => D <= "00000101"; -- 0x01CC
+ when 000461 => D <= "00000100"; -- 0x01CD
+ when 000462 => D <= "00110011"; -- 0x01CE
+ when 000463 => D <= "00111010"; -- 0x01CF
+ when 000464 => D <= "00000101"; -- 0x01D0
+ when 000465 => D <= "00000100"; -- 0x01D1
+ when 000466 => D <= "00110011"; -- 0x01D2
+ when 000467 => D <= "00111010"; -- 0x01D3
+ when 000468 => D <= "00000101"; -- 0x01D4
+ when 000469 => D <= "00000100"; -- 0x01D5
+ when 000470 => D <= "00110011"; -- 0x01D6
+ when 000471 => D <= "00111010"; -- 0x01D7
+ when 000472 => D <= "00000101"; -- 0x01D8
+ when 000473 => D <= "00000100"; -- 0x01D9
+ when 000474 => D <= "00110011"; -- 0x01DA
+ when 000475 => D <= "00111010"; -- 0x01DB
+ when 000476 => D <= "00000101"; -- 0x01DC
+ when 000477 => D <= "00000100"; -- 0x01DD
+ when 000478 => D <= "00110011"; -- 0x01DE
+ when 000479 => D <= "00111010"; -- 0x01DF
+ when 000480 => D <= "00000101"; -- 0x01E0
+ when 000481 => D <= "00000100"; -- 0x01E1
+ when 000482 => D <= "00110011"; -- 0x01E2
+ when 000483 => D <= "00111010"; -- 0x01E3
+ when 000484 => D <= "00000101"; -- 0x01E4
+ when 000485 => D <= "00000100"; -- 0x01E5
+ when 000486 => D <= "00110011"; -- 0x01E6
+ when 000487 => D <= "00111010"; -- 0x01E7
+ when 000488 => D <= "00000101"; -- 0x01E8
+ when 000489 => D <= "00000100"; -- 0x01E9
+ when 000490 => D <= "00110011"; -- 0x01EA
+ when 000491 => D <= "00111010"; -- 0x01EB
+ when 000492 => D <= "00000101"; -- 0x01EC
+ when 000493 => D <= "00000100"; -- 0x01ED
+ when 000494 => D <= "00110011"; -- 0x01EE
+ when 000495 => D <= "00111010"; -- 0x01EF
+ when 000496 => D <= "00000101"; -- 0x01F0
+ when 000497 => D <= "00000100"; -- 0x01F1
+ when 000498 => D <= "00110011"; -- 0x01F2
+ when 000499 => D <= "00111010"; -- 0x01F3
+ when 000500 => D <= "00000101"; -- 0x01F4
+ when 000501 => D <= "00000100"; -- 0x01F5
+ when 000502 => D <= "00110011"; -- 0x01F6
+ when 000503 => D <= "00111010"; -- 0x01F7
+ when 000504 => D <= "00000101"; -- 0x01F8
+ when 000505 => D <= "00000100"; -- 0x01F9
+ when 000506 => D <= "00110011"; -- 0x01FA
+ when 000507 => D <= "00111010"; -- 0x01FB
+ when 000508 => D <= "00000101"; -- 0x01FC
+ when 000509 => D <= "00000100"; -- 0x01FD
+ when 000510 => D <= "01000100"; -- 0x01FE
+ when 000511 => D <= "00111111"; -- 0x01FF
+ when 000512 => D <= "00110011"; -- 0x0200
+ when 000513 => D <= "00111010"; -- 0x0201
+ when 000514 => D <= "00000101"; -- 0x0202
+ when 000515 => D <= "00000100"; -- 0x0203
+ when 000516 => D <= "00110011"; -- 0x0204
+ when 000517 => D <= "00111010"; -- 0x0205
+ when 000518 => D <= "00000101"; -- 0x0206
+ when 000519 => D <= "00000100"; -- 0x0207
+ when 000520 => D <= "00110011"; -- 0x0208
+ when 000521 => D <= "00111010"; -- 0x0209
+ when 000522 => D <= "00000101"; -- 0x020A
+ when 000523 => D <= "00000100"; -- 0x020B
+ when 000524 => D <= "00110011"; -- 0x020C
+ when 000525 => D <= "00111010"; -- 0x020D
+ when 000526 => D <= "00000101"; -- 0x020E
+ when 000527 => D <= "00000100"; -- 0x020F
+ when 000528 => D <= "00110011"; -- 0x0210
+ when 000529 => D <= "00111010"; -- 0x0211
+ when 000530 => D <= "00000101"; -- 0x0212
+ when 000531 => D <= "00000100"; -- 0x0213
+ when 000532 => D <= "00110011"; -- 0x0214
+ when 000533 => D <= "00111010"; -- 0x0215
+ when 000534 => D <= "00000101"; -- 0x0216
+ when 000535 => D <= "00000100"; -- 0x0217
+ when 000536 => D <= "00110011"; -- 0x0218
+ when 000537 => D <= "00111010"; -- 0x0219
+ when 000538 => D <= "00000101"; -- 0x021A
+ when 000539 => D <= "00000100"; -- 0x021B
+ when 000540 => D <= "00110011"; -- 0x021C
+ when 000541 => D <= "00111010"; -- 0x021D
+ when 000542 => D <= "00000101"; -- 0x021E
+ when 000543 => D <= "00000100"; -- 0x021F
+ when 000544 => D <= "00110011"; -- 0x0220
+ when 000545 => D <= "00111010"; -- 0x0221
+ when 000546 => D <= "00000101"; -- 0x0222
+ when 000547 => D <= "00000100"; -- 0x0223
+ when 000548 => D <= "00110011"; -- 0x0224
+ when 000549 => D <= "00111010"; -- 0x0225
+ when 000550 => D <= "00000101"; -- 0x0226
+ when 000551 => D <= "00000100"; -- 0x0227
+ when 000552 => D <= "00110011"; -- 0x0228
+ when 000553 => D <= "00111010"; -- 0x0229
+ when 000554 => D <= "00000101"; -- 0x022A
+ when 000555 => D <= "00000100"; -- 0x022B
+ when 000556 => D <= "00110011"; -- 0x022C
+ when 000557 => D <= "00111010"; -- 0x022D
+ when 000558 => D <= "00000101"; -- 0x022E
+ when 000559 => D <= "00000100"; -- 0x022F
+ when 000560 => D <= "00110011"; -- 0x0230
+ when 000561 => D <= "00111010"; -- 0x0231
+ when 000562 => D <= "00000101"; -- 0x0232
+ when 000563 => D <= "00000100"; -- 0x0233
+ when 000564 => D <= "00110011"; -- 0x0234
+ when 000565 => D <= "00111010"; -- 0x0235
+ when 000566 => D <= "00000101"; -- 0x0236
+ when 000567 => D <= "00000100"; -- 0x0237
+ when 000568 => D <= "00110011"; -- 0x0238
+ when 000569 => D <= "00111010"; -- 0x0239
+ when 000570 => D <= "00000101"; -- 0x023A
+ when 000571 => D <= "00000100"; -- 0x023B
+ when 000572 => D <= "00110011"; -- 0x023C
+ when 000573 => D <= "00111010"; -- 0x023D
+ when 000574 => D <= "00000101"; -- 0x023E
+ when 000575 => D <= "00000100"; -- 0x023F
+ when 000576 => D <= "01000100"; -- 0x0240
+ when 000577 => D <= "01100010"; -- 0x0241
+ when 000578 => D <= "01000001"; -- 0x0242
+ when others => D <= "--------";
+ end case;
+ end if;
+ end process;
+end;
Index: tags/rel_1_2/syn/t421/xc3s1000/rom_42x.hex
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/rom_42x.hex (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/rom_42x.hex (revision 180)
@@ -0,0 +1,38 @@
+:100000004433593356783C333E001250333E00524D
+:1000100050333E77333E50333A0050333A4D333A03
+:1000200047333A4C430550333A1523805F2300068B
+:10003000333A054A0707333E754E5307333A0723D1
+:1000400000333E5406333A00400204230058230094
+:10005000213392333E211F462142214B212300367A
+:10006000239114332A0600302220230006333A005D
+:100070003006333A333C07332C333A25333A3533A1
+:100080003A3106222300102006333A00530622207C
+:1000900006333A322006333A0F1E33A7333A332C55
+:1000A000333A06333A33614F0057330106333A335C
+:1000B0001106333A330306333A331306333A332106
+:1000C00006333A3350332106333A0106333A1106E8
+:1000D000333A0306333A332933282116333A332986
+:1000E0000613333E33513A33504433290601333E2D
+:1000F000444F06333A0F777E757C737A71787F763A
+:100100007D747B7279701F777E757C737A71787FCE
+:10011000767D747B7279702F777E757C737A7178B7
+:100120007F767D747B7279703F777E757C737A7190
+:10013000787F767D747B7279700F333A0504333A99
+:100140000504333A0504333A0504333A0504333AD7
+:100150000504333A0504333A0504333A0504333AC7
+:100160000504333A0504333A0504333A0504333AB7
+:100170000504333A0504333A0504441F333A0504B1
+:10018000333A0504333A0504333A0504333A050497
+:10019000333A0504333A0504333A0504333A050487
+:1001A000333A0504333A0504333A0504333A050477
+:1001B000333A0504333A0504333A0504442F333AFD
+:1001C0000504333A0504333A0504333A0504333A57
+:1001D0000504333A0504333A0504333A0504333A47
+:1001E0000504333A0504333A0504333A0504333A37
+:1001F0000504333A0504333A0504333A0504443F11
+:10020000333A0504333A0504333A0504333A050416
+:10021000333A0504333A0504333A0504333A050406
+:10022000333A0504333A0504333A0504333A0504F6
+:10023000333A0504333A0504333A0504333A0504E6
+:03024000446241D4
+:00000001FF
Index: tags/rel_1_2/syn/t421/xc3s1000/timing.ucf
===================================================================
--- tags/rel_1_2/syn/t421/xc3s1000/timing.ucf (nonexistent)
+++ tags/rel_1_2/syn/t421/xc3s1000/timing.ucf (revision 180)
@@ -0,0 +1,6 @@
+################################################################################
+# Clock Constraints
+################################################################################
+
+NET "ck_i" TNM_NET = "ck_i";
+TIMESPEC "TS_ck_i" = PERIOD "ck_i" 250 ns;
Index: tags/rel_1_2/syn/t421/ep1c12/t421.qsf
===================================================================
--- tags/rel_1_2/syn/t421/ep1c12/t421.qsf (nonexistent)
+++ tags/rel_1_2/syn/t421/ep1c12/t421.qsf (revision 180)
@@ -0,0 +1,76 @@
+set_global_assignment -name TOP_LEVEL_ENTITY t421
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# t421_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:20:14 April 27, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_opt_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_clkgen.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_reset.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pmem_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_dmem_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_comp_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_mnemonic_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_decoder.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_skip.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_alu.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_stack.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_l.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_d.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_g.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_in.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_sio.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_timer.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/tech/generic/generic_ram_ena.vhd
+set_global_assignment -name VHDL_FILE rom_t42x.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-e.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-struct-a.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/tech/cyclone/t400_por.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core_comp_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/tech/t400_tech_comp_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_notri.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t400_system_comp_pack-p.vhd
+set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t421.vhd
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name VHDL_INPUT_VERSION VHDL87
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id ck_i
+set_instance_assignment -name CLOCK_SETTINGS ck_i -to ck_i
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
Index: tags/rel_1_2/syn/t421/ep1c12/rom_t42x.vhd
===================================================================
--- tags/rel_1_2/syn/t421/ep1c12/rom_t42x.vhd (nonexistent)
+++ tags/rel_1_2/syn/t421/ep1c12/rom_t42x.vhd (revision 180)
@@ -0,0 +1,604 @@
+-- This file was generated with hex2rom written by Daniel Wallner
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rom_t42x is
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(9 downto 0);
+ D : out std_logic_vector(7 downto 0)
+ );
+end rom_t42x;
+
+architecture rtl of rom_t42x is
+begin
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ case to_integer(unsigned(A)) is
+ when 000000 => D <= "01000100"; -- 0x0000
+ when 000001 => D <= "00110011"; -- 0x0001
+ when 000002 => D <= "01011001"; -- 0x0002
+ when 000003 => D <= "00110011"; -- 0x0003
+ when 000004 => D <= "01010110"; -- 0x0004
+ when 000005 => D <= "01111000"; -- 0x0005
+ when 000006 => D <= "00111100"; -- 0x0006
+ when 000007 => D <= "00110011"; -- 0x0007
+ when 000008 => D <= "00111110"; -- 0x0008
+ when 000009 => D <= "00000000"; -- 0x0009
+ when 000010 => D <= "00010010"; -- 0x000A
+ when 000011 => D <= "01010000"; -- 0x000B
+ when 000012 => D <= "00110011"; -- 0x000C
+ when 000013 => D <= "00111110"; -- 0x000D
+ when 000014 => D <= "00000000"; -- 0x000E
+ when 000015 => D <= "01010010"; -- 0x000F
+ when 000016 => D <= "01010000"; -- 0x0010
+ when 000017 => D <= "00110011"; -- 0x0011
+ when 000018 => D <= "00111110"; -- 0x0012
+ when 000019 => D <= "01110111"; -- 0x0013
+ when 000020 => D <= "00110011"; -- 0x0014
+ when 000021 => D <= "00111110"; -- 0x0015
+ when 000022 => D <= "01010000"; -- 0x0016
+ when 000023 => D <= "00110011"; -- 0x0017
+ when 000024 => D <= "00111010"; -- 0x0018
+ when 000025 => D <= "00000000"; -- 0x0019
+ when 000026 => D <= "01010000"; -- 0x001A
+ when 000027 => D <= "00110011"; -- 0x001B
+ when 000028 => D <= "00111010"; -- 0x001C
+ when 000029 => D <= "01001101"; -- 0x001D
+ when 000030 => D <= "00110011"; -- 0x001E
+ when 000031 => D <= "00111010"; -- 0x001F
+ when 000032 => D <= "01000111"; -- 0x0020
+ when 000033 => D <= "00110011"; -- 0x0021
+ when 000034 => D <= "00111010"; -- 0x0022
+ when 000035 => D <= "01001100"; -- 0x0023
+ when 000036 => D <= "01000011"; -- 0x0024
+ when 000037 => D <= "00000101"; -- 0x0025
+ when 000038 => D <= "01010000"; -- 0x0026
+ when 000039 => D <= "00110011"; -- 0x0027
+ when 000040 => D <= "00111010"; -- 0x0028
+ when 000041 => D <= "00010101"; -- 0x0029
+ when 000042 => D <= "00100011"; -- 0x002A
+ when 000043 => D <= "10000000"; -- 0x002B
+ when 000044 => D <= "01011111"; -- 0x002C
+ when 000045 => D <= "00100011"; -- 0x002D
+ when 000046 => D <= "00000000"; -- 0x002E
+ when 000047 => D <= "00000110"; -- 0x002F
+ when 000048 => D <= "00110011"; -- 0x0030
+ when 000049 => D <= "00111010"; -- 0x0031
+ when 000050 => D <= "00000101"; -- 0x0032
+ when 000051 => D <= "01001010"; -- 0x0033
+ when 000052 => D <= "00000111"; -- 0x0034
+ when 000053 => D <= "00000111"; -- 0x0035
+ when 000054 => D <= "00110011"; -- 0x0036
+ when 000055 => D <= "00111110"; -- 0x0037
+ when 000056 => D <= "01110101"; -- 0x0038
+ when 000057 => D <= "01001110"; -- 0x0039
+ when 000058 => D <= "01010011"; -- 0x003A
+ when 000059 => D <= "00000111"; -- 0x003B
+ when 000060 => D <= "00110011"; -- 0x003C
+ when 000061 => D <= "00111010"; -- 0x003D
+ when 000062 => D <= "00000111"; -- 0x003E
+ when 000063 => D <= "00100011"; -- 0x003F
+ when 000064 => D <= "00000000"; -- 0x0040
+ when 000065 => D <= "00110011"; -- 0x0041
+ when 000066 => D <= "00111110"; -- 0x0042
+ when 000067 => D <= "01010100"; -- 0x0043
+ when 000068 => D <= "00000110"; -- 0x0044
+ when 000069 => D <= "00110011"; -- 0x0045
+ when 000070 => D <= "00111010"; -- 0x0046
+ when 000071 => D <= "00000000"; -- 0x0047
+ when 000072 => D <= "01000000"; -- 0x0048
+ when 000073 => D <= "00000010"; -- 0x0049
+ when 000074 => D <= "00000100"; -- 0x004A
+ when 000075 => D <= "00100011"; -- 0x004B
+ when 000076 => D <= "00000000"; -- 0x004C
+ when 000077 => D <= "01011000"; -- 0x004D
+ when 000078 => D <= "00100011"; -- 0x004E
+ when 000079 => D <= "00000000"; -- 0x004F
+ when 000080 => D <= "00100001"; -- 0x0050
+ when 000081 => D <= "00110011"; -- 0x0051
+ when 000082 => D <= "10010010"; -- 0x0052
+ when 000083 => D <= "00110011"; -- 0x0053
+ when 000084 => D <= "00111110"; -- 0x0054
+ when 000085 => D <= "00100001"; -- 0x0055
+ when 000086 => D <= "00011111"; -- 0x0056
+ when 000087 => D <= "01000110"; -- 0x0057
+ when 000088 => D <= "00100001"; -- 0x0058
+ when 000089 => D <= "01000010"; -- 0x0059
+ when 000090 => D <= "00100001"; -- 0x005A
+ when 000091 => D <= "01001011"; -- 0x005B
+ when 000092 => D <= "00100001"; -- 0x005C
+ when 000093 => D <= "00100011"; -- 0x005D
+ when 000094 => D <= "00000000"; -- 0x005E
+ when 000095 => D <= "00110110"; -- 0x005F
+ when 000096 => D <= "00100011"; -- 0x0060
+ when 000097 => D <= "10010001"; -- 0x0061
+ when 000098 => D <= "00010100"; -- 0x0062
+ when 000099 => D <= "00110011"; -- 0x0063
+ when 000100 => D <= "00101010"; -- 0x0064
+ when 000101 => D <= "00000110"; -- 0x0065
+ when 000102 => D <= "00000000"; -- 0x0066
+ when 000103 => D <= "00110000"; -- 0x0067
+ when 000104 => D <= "00100010"; -- 0x0068
+ when 000105 => D <= "00100000"; -- 0x0069
+ when 000106 => D <= "00100011"; -- 0x006A
+ when 000107 => D <= "00000000"; -- 0x006B
+ when 000108 => D <= "00000110"; -- 0x006C
+ when 000109 => D <= "00110011"; -- 0x006D
+ when 000110 => D <= "00111010"; -- 0x006E
+ when 000111 => D <= "00000000"; -- 0x006F
+ when 000112 => D <= "00110000"; -- 0x0070
+ when 000113 => D <= "00000110"; -- 0x0071
+ when 000114 => D <= "00110011"; -- 0x0072
+ when 000115 => D <= "00111010"; -- 0x0073
+ when 000116 => D <= "00110011"; -- 0x0074
+ when 000117 => D <= "00111100"; -- 0x0075
+ when 000118 => D <= "00000111"; -- 0x0076
+ when 000119 => D <= "00110011"; -- 0x0077
+ when 000120 => D <= "00101100"; -- 0x0078
+ when 000121 => D <= "00110011"; -- 0x0079
+ when 000122 => D <= "00111010"; -- 0x007A
+ when 000123 => D <= "00100101"; -- 0x007B
+ when 000124 => D <= "00110011"; -- 0x007C
+ when 000125 => D <= "00111010"; -- 0x007D
+ when 000126 => D <= "00110101"; -- 0x007E
+ when 000127 => D <= "00110011"; -- 0x007F
+ when 000128 => D <= "00111010"; -- 0x0080
+ when 000129 => D <= "00110001"; -- 0x0081
+ when 000130 => D <= "00000110"; -- 0x0082
+ when 000131 => D <= "00100010"; -- 0x0083
+ when 000132 => D <= "00100011"; -- 0x0084
+ when 000133 => D <= "00000000"; -- 0x0085
+ when 000134 => D <= "00010000"; -- 0x0086
+ when 000135 => D <= "00100000"; -- 0x0087
+ when 000136 => D <= "00000110"; -- 0x0088
+ when 000137 => D <= "00110011"; -- 0x0089
+ when 000138 => D <= "00111010"; -- 0x008A
+ when 000139 => D <= "00000000"; -- 0x008B
+ when 000140 => D <= "01010011"; -- 0x008C
+ when 000141 => D <= "00000110"; -- 0x008D
+ when 000142 => D <= "00100010"; -- 0x008E
+ when 000143 => D <= "00100000"; -- 0x008F
+ when 000144 => D <= "00000110"; -- 0x0090
+ when 000145 => D <= "00110011"; -- 0x0091
+ when 000146 => D <= "00111010"; -- 0x0092
+ when 000147 => D <= "00110010"; -- 0x0093
+ when 000148 => D <= "00100000"; -- 0x0094
+ when 000149 => D <= "00000110"; -- 0x0095
+ when 000150 => D <= "00110011"; -- 0x0096
+ when 000151 => D <= "00111010"; -- 0x0097
+ when 000152 => D <= "00001111"; -- 0x0098
+ when 000153 => D <= "00011110"; -- 0x0099
+ when 000154 => D <= "00110011"; -- 0x009A
+ when 000155 => D <= "10100111"; -- 0x009B
+ when 000156 => D <= "00110011"; -- 0x009C
+ when 000157 => D <= "00111010"; -- 0x009D
+ when 000158 => D <= "00110011"; -- 0x009E
+ when 000159 => D <= "00101100"; -- 0x009F
+ when 000160 => D <= "00110011"; -- 0x00A0
+ when 000161 => D <= "00111010"; -- 0x00A1
+ when 000162 => D <= "00000110"; -- 0x00A2
+ when 000163 => D <= "00110011"; -- 0x00A3
+ when 000164 => D <= "00111010"; -- 0x00A4
+ when 000165 => D <= "00110011"; -- 0x00A5
+ when 000166 => D <= "01100001"; -- 0x00A6
+ when 000167 => D <= "01001111"; -- 0x00A7
+ when 000168 => D <= "00000000"; -- 0x00A8
+ when 000169 => D <= "01010111"; -- 0x00A9
+ when 000170 => D <= "00110011"; -- 0x00AA
+ when 000171 => D <= "00000001"; -- 0x00AB
+ when 000172 => D <= "00000110"; -- 0x00AC
+ when 000173 => D <= "00110011"; -- 0x00AD
+ when 000174 => D <= "00111010"; -- 0x00AE
+ when 000175 => D <= "00110011"; -- 0x00AF
+ when 000176 => D <= "00010001"; -- 0x00B0
+ when 000177 => D <= "00000110"; -- 0x00B1
+ when 000178 => D <= "00110011"; -- 0x00B2
+ when 000179 => D <= "00111010"; -- 0x00B3
+ when 000180 => D <= "00110011"; -- 0x00B4
+ when 000181 => D <= "00000011"; -- 0x00B5
+ when 000182 => D <= "00000110"; -- 0x00B6
+ when 000183 => D <= "00110011"; -- 0x00B7
+ when 000184 => D <= "00111010"; -- 0x00B8
+ when 000185 => D <= "00110011"; -- 0x00B9
+ when 000186 => D <= "00010011"; -- 0x00BA
+ when 000187 => D <= "00000110"; -- 0x00BB
+ when 000188 => D <= "00110011"; -- 0x00BC
+ when 000189 => D <= "00111010"; -- 0x00BD
+ when 000190 => D <= "00110011"; -- 0x00BE
+ when 000191 => D <= "00100001"; -- 0x00BF
+ when 000192 => D <= "00000110"; -- 0x00C0
+ when 000193 => D <= "00110011"; -- 0x00C1
+ when 000194 => D <= "00111010"; -- 0x00C2
+ when 000195 => D <= "00110011"; -- 0x00C3
+ when 000196 => D <= "01010000"; -- 0x00C4
+ when 000197 => D <= "00110011"; -- 0x00C5
+ when 000198 => D <= "00100001"; -- 0x00C6
+ when 000199 => D <= "00000110"; -- 0x00C7
+ when 000200 => D <= "00110011"; -- 0x00C8
+ when 000201 => D <= "00111010"; -- 0x00C9
+ when 000202 => D <= "00000001"; -- 0x00CA
+ when 000203 => D <= "00000110"; -- 0x00CB
+ when 000204 => D <= "00110011"; -- 0x00CC
+ when 000205 => D <= "00111010"; -- 0x00CD
+ when 000206 => D <= "00010001"; -- 0x00CE
+ when 000207 => D <= "00000110"; -- 0x00CF
+ when 000208 => D <= "00110011"; -- 0x00D0
+ when 000209 => D <= "00111010"; -- 0x00D1
+ when 000210 => D <= "00000011"; -- 0x00D2
+ when 000211 => D <= "00000110"; -- 0x00D3
+ when 000212 => D <= "00110011"; -- 0x00D4
+ when 000213 => D <= "00111010"; -- 0x00D5
+ when 000214 => D <= "00110011"; -- 0x00D6
+ when 000215 => D <= "00101001"; -- 0x00D7
+ when 000216 => D <= "00110011"; -- 0x00D8
+ when 000217 => D <= "00101000"; -- 0x00D9
+ when 000218 => D <= "00100001"; -- 0x00DA
+ when 000219 => D <= "00010110"; -- 0x00DB
+ when 000220 => D <= "00110011"; -- 0x00DC
+ when 000221 => D <= "00111010"; -- 0x00DD
+ when 000222 => D <= "00110011"; -- 0x00DE
+ when 000223 => D <= "00101001"; -- 0x00DF
+ when 000224 => D <= "00000110"; -- 0x00E0
+ when 000225 => D <= "00010011"; -- 0x00E1
+ when 000226 => D <= "00110011"; -- 0x00E2
+ when 000227 => D <= "00111110"; -- 0x00E3
+ when 000228 => D <= "00110011"; -- 0x00E4
+ when 000229 => D <= "01010001"; -- 0x00E5
+ when 000230 => D <= "00111010"; -- 0x00E6
+ when 000231 => D <= "00110011"; -- 0x00E7
+ when 000232 => D <= "01010000"; -- 0x00E8
+ when 000233 => D <= "01000100"; -- 0x00E9
+ when 000234 => D <= "00110011"; -- 0x00EA
+ when 000235 => D <= "00101001"; -- 0x00EB
+ when 000236 => D <= "00000110"; -- 0x00EC
+ when 000237 => D <= "00000001"; -- 0x00ED
+ when 000238 => D <= "00110011"; -- 0x00EE
+ when 000239 => D <= "00111110"; -- 0x00EF
+ when 000240 => D <= "01000100"; -- 0x00F0
+ when 000241 => D <= "01001111"; -- 0x00F1
+ when 000242 => D <= "00000110"; -- 0x00F2
+ when 000243 => D <= "00110011"; -- 0x00F3
+ when 000244 => D <= "00111010"; -- 0x00F4
+ when 000245 => D <= "00001111"; -- 0x00F5
+ when 000246 => D <= "01110111"; -- 0x00F6
+ when 000247 => D <= "01111110"; -- 0x00F7
+ when 000248 => D <= "01110101"; -- 0x00F8
+ when 000249 => D <= "01111100"; -- 0x00F9
+ when 000250 => D <= "01110011"; -- 0x00FA
+ when 000251 => D <= "01111010"; -- 0x00FB
+ when 000252 => D <= "01110001"; -- 0x00FC
+ when 000253 => D <= "01111000"; -- 0x00FD
+ when 000254 => D <= "01111111"; -- 0x00FE
+ when 000255 => D <= "01110110"; -- 0x00FF
+ when 000256 => D <= "01111101"; -- 0x0100
+ when 000257 => D <= "01110100"; -- 0x0101
+ when 000258 => D <= "01111011"; -- 0x0102
+ when 000259 => D <= "01110010"; -- 0x0103
+ when 000260 => D <= "01111001"; -- 0x0104
+ when 000261 => D <= "01110000"; -- 0x0105
+ when 000262 => D <= "00011111"; -- 0x0106
+ when 000263 => D <= "01110111"; -- 0x0107
+ when 000264 => D <= "01111110"; -- 0x0108
+ when 000265 => D <= "01110101"; -- 0x0109
+ when 000266 => D <= "01111100"; -- 0x010A
+ when 000267 => D <= "01110011"; -- 0x010B
+ when 000268 => D <= "01111010"; -- 0x010C
+ when 000269 => D <= "01110001"; -- 0x010D
+ when 000270 => D <= "01111000"; -- 0x010E
+ when 000271 => D <= "01111111"; -- 0x010F
+ when 000272 => D <= "01110110"; -- 0x0110
+ when 000273 => D <= "01111101"; -- 0x0111
+ when 000274 => D <= "01110100"; -- 0x0112
+ when 000275 => D <= "01111011"; -- 0x0113
+ when 000276 => D <= "01110010"; -- 0x0114
+ when 000277 => D <= "01111001"; -- 0x0115
+ when 000278 => D <= "01110000"; -- 0x0116
+ when 000279 => D <= "00101111"; -- 0x0117
+ when 000280 => D <= "01110111"; -- 0x0118
+ when 000281 => D <= "01111110"; -- 0x0119
+ when 000282 => D <= "01110101"; -- 0x011A
+ when 000283 => D <= "01111100"; -- 0x011B
+ when 000284 => D <= "01110011"; -- 0x011C
+ when 000285 => D <= "01111010"; -- 0x011D
+ when 000286 => D <= "01110001"; -- 0x011E
+ when 000287 => D <= "01111000"; -- 0x011F
+ when 000288 => D <= "01111111"; -- 0x0120
+ when 000289 => D <= "01110110"; -- 0x0121
+ when 000290 => D <= "01111101"; -- 0x0122
+ when 000291 => D <= "01110100"; -- 0x0123
+ when 000292 => D <= "01111011"; -- 0x0124
+ when 000293 => D <= "01110010"; -- 0x0125
+ when 000294 => D <= "01111001"; -- 0x0126
+ when 000295 => D <= "01110000"; -- 0x0127
+ when 000296 => D <= "00111111"; -- 0x0128
+ when 000297 => D <= "01110111"; -- 0x0129
+ when 000298 => D <= "01111110"; -- 0x012A
+ when 000299 => D <= "01110101"; -- 0x012B
+ when 000300 => D <= "01111100"; -- 0x012C
+ when 000301 => D <= "01110011"; -- 0x012D
+ when 000302 => D <= "01111010"; -- 0x012E
+ when 000303 => D <= "01110001"; -- 0x012F
+ when 000304 => D <= "01111000"; -- 0x0130
+ when 000305 => D <= "01111111"; -- 0x0131
+ when 000306 => D <= "01110110"; -- 0x0132
+ when 000307 => D <= "01111101"; -- 0x0133
+ when 000308 => D <= "01110100"; -- 0x0134
+ when 000309 => D <= "01111011"; -- 0x0135
+ when 000310 => D <= "01110010"; -- 0x0136
+ when 000311 => D <= "01111001"; -- 0x0137
+ when 000312 => D <= "01110000"; -- 0x0138
+ when 000313 => D <= "00001111"; -- 0x0139
+ when 000314 => D <= "00110011"; -- 0x013A
+ when 000315 => D <= "00111010"; -- 0x013B
+ when 000316 => D <= "00000101"; -- 0x013C
+ when 000317 => D <= "00000100"; -- 0x013D
+ when 000318 => D <= "00110011"; -- 0x013E
+ when 000319 => D <= "00111010"; -- 0x013F
+ when 000320 => D <= "00000101"; -- 0x0140
+ when 000321 => D <= "00000100"; -- 0x0141
+ when 000322 => D <= "00110011"; -- 0x0142
+ when 000323 => D <= "00111010"; -- 0x0143
+ when 000324 => D <= "00000101"; -- 0x0144
+ when 000325 => D <= "00000100"; -- 0x0145
+ when 000326 => D <= "00110011"; -- 0x0146
+ when 000327 => D <= "00111010"; -- 0x0147
+ when 000328 => D <= "00000101"; -- 0x0148
+ when 000329 => D <= "00000100"; -- 0x0149
+ when 000330 => D <= "00110011"; -- 0x014A
+ when 000331 => D <= "00111010"; -- 0x014B
+ when 000332 => D <= "00000101"; -- 0x014C
+ when 000333 => D <= "00000100"; -- 0x014D
+ when 000334 => D <= "00110011"; -- 0x014E
+ when 000335 => D <= "00111010"; -- 0x014F
+ when 000336 => D <= "00000101"; -- 0x0150
+ when 000337 => D <= "00000100"; -- 0x0151
+ when 000338 => D <= "00110011"; -- 0x0152
+ when 000339 => D <= "00111010"; -- 0x0153
+ when 000340 => D <= "00000101"; -- 0x0154
+ when 000341 => D <= "00000100"; -- 0x0155
+ when 000342 => D <= "00110011"; -- 0x0156
+ when 000343 => D <= "00111010"; -- 0x0157
+ when 000344 => D <= "00000101"; -- 0x0158
+ when 000345 => D <= "00000100"; -- 0x0159
+ when 000346 => D <= "00110011"; -- 0x015A
+ when 000347 => D <= "00111010"; -- 0x015B
+ when 000348 => D <= "00000101"; -- 0x015C
+ when 000349 => D <= "00000100"; -- 0x015D
+ when 000350 => D <= "00110011"; -- 0x015E
+ when 000351 => D <= "00111010"; -- 0x015F
+ when 000352 => D <= "00000101"; -- 0x0160
+ when 000353 => D <= "00000100"; -- 0x0161
+ when 000354 => D <= "00110011"; -- 0x0162
+ when 000355 => D <= "00111010"; -- 0x0163
+ when 000356 => D <= "00000101"; -- 0x0164
+ when 000357 => D <= "00000100"; -- 0x0165
+ when 000358 => D <= "00110011"; -- 0x0166
+ when 000359 => D <= "00111010"; -- 0x0167
+ when 000360 => D <= "00000101"; -- 0x0168
+ when 000361 => D <= "00000100"; -- 0x0169
+ when 000362 => D <= "00110011"; -- 0x016A
+ when 000363 => D <= "00111010"; -- 0x016B
+ when 000364 => D <= "00000101"; -- 0x016C
+ when 000365 => D <= "00000100"; -- 0x016D
+ when 000366 => D <= "00110011"; -- 0x016E
+ when 000367 => D <= "00111010"; -- 0x016F
+ when 000368 => D <= "00000101"; -- 0x0170
+ when 000369 => D <= "00000100"; -- 0x0171
+ when 000370 => D <= "00110011"; -- 0x0172
+ when 000371 => D <= "00111010"; -- 0x0173
+ when 000372 => D <= "00000101"; -- 0x0174
+ when 000373 => D <= "00000100"; -- 0x0175
+ when 000374 => D <= "00110011"; -- 0x0176
+ when 000375 => D <= "00111010"; -- 0x0177
+ when 000376 => D <= "00000101"; -- 0x0178
+ when 000377 => D <= "00000100"; -- 0x0179
+ when 000378 => D <= "01000100"; -- 0x017A
+ when 000379 => D <= "00011111"; -- 0x017B
+ when 000380 => D <= "00110011"; -- 0x017C
+ when 000381 => D <= "00111010"; -- 0x017D
+ when 000382 => D <= "00000101"; -- 0x017E
+ when 000383 => D <= "00000100"; -- 0x017F
+ when 000384 => D <= "00110011"; -- 0x0180
+ when 000385 => D <= "00111010"; -- 0x0181
+ when 000386 => D <= "00000101"; -- 0x0182
+ when 000387 => D <= "00000100"; -- 0x0183
+ when 000388 => D <= "00110011"; -- 0x0184
+ when 000389 => D <= "00111010"; -- 0x0185
+ when 000390 => D <= "00000101"; -- 0x0186
+ when 000391 => D <= "00000100"; -- 0x0187
+ when 000392 => D <= "00110011"; -- 0x0188
+ when 000393 => D <= "00111010"; -- 0x0189
+ when 000394 => D <= "00000101"; -- 0x018A
+ when 000395 => D <= "00000100"; -- 0x018B
+ when 000396 => D <= "00110011"; -- 0x018C
+ when 000397 => D <= "00111010"; -- 0x018D
+ when 000398 => D <= "00000101"; -- 0x018E
+ when 000399 => D <= "00000100"; -- 0x018F
+ when 000400 => D <= "00110011"; -- 0x0190
+ when 000401 => D <= "00111010"; -- 0x0191
+ when 000402 => D <= "00000101"; -- 0x0192
+ when 000403 => D <= "00000100"; -- 0x0193
+ when 000404 => D <= "00110011"; -- 0x0194
+ when 000405 => D <= "00111010"; -- 0x0195
+ when 000406 => D <= "00000101"; -- 0x0196
+ when 000407 => D <= "00000100"; -- 0x0197
+ when 000408 => D <= "00110011"; -- 0x0198
+ when 000409 => D <= "00111010"; -- 0x0199
+ when 000410 => D <= "00000101"; -- 0x019A
+ when 000411 => D <= "00000100"; -- 0x019B
+ when 000412 => D <= "00110011"; -- 0x019C
+ when 000413 => D <= "00111010"; -- 0x019D
+ when 000414 => D <= "00000101"; -- 0x019E
+ when 000415 => D <= "00000100"; -- 0x019F
+ when 000416 => D <= "00110011"; -- 0x01A0
+ when 000417 => D <= "00111010"; -- 0x01A1
+ when 000418 => D <= "00000101"; -- 0x01A2
+ when 000419 => D <= "00000100"; -- 0x01A3
+ when 000420 => D <= "00110011"; -- 0x01A4
+ when 000421 => D <= "00111010"; -- 0x01A5
+ when 000422 => D <= "00000101"; -- 0x01A6
+ when 000423 => D <= "00000100"; -- 0x01A7
+ when 000424 => D <= "00110011"; -- 0x01A8
+ when 000425 => D <= "00111010"; -- 0x01A9
+ when 000426 => D <= "00000101"; -- 0x01AA
+ when 000427 => D <= "00000100"; -- 0x01AB
+ when 000428 => D <= "00110011"; -- 0x01AC
+ when 000429 => D <= "00111010"; -- 0x01AD
+ when 000430 => D <= "00000101"; -- 0x01AE
+ when 000431 => D <= "00000100"; -- 0x01AF
+ when 000432 => D <= "00110011"; -- 0x01B0
+ when 000433 => D <= "00111010"; -- 0x01B1
+ when 000434 => D <= "00000101"; -- 0x01B2
+ when 000435 => D <= "00000100"; -- 0x01B3
+ when 000436 => D <= "00110011"; -- 0x01B4
+ when 000437 => D <= "00111010"; -- 0x01B5
+ when 000438 => D <= "00000101"; -- 0x01B6
+ when 000439 => D <= "00000100"; -- 0x01B7
+ when 000440 => D <= "00110011"; -- 0x01B8
+ when 000441 => D <= "00111010"; -- 0x01B9
+ when 000442 => D <= "00000101"; -- 0x01BA
+ when 000443 => D <= "00000100"; -- 0x01BB
+ when 000444 => D <= "01000100"; -- 0x01BC
+ when 000445 => D <= "00101111"; -- 0x01BD
+ when 000446 => D <= "00110011"; -- 0x01BE
+ when 000447 => D <= "00111010"; -- 0x01BF
+ when 000448 => D <= "00000101"; -- 0x01C0
+ when 000449 => D <= "00000100"; -- 0x01C1
+ when 000450 => D <= "00110011"; -- 0x01C2
+ when 000451 => D <= "00111010"; -- 0x01C3
+ when 000452 => D <= "00000101"; -- 0x01C4
+ when 000453 => D <= "00000100"; -- 0x01C5
+ when 000454 => D <= "00110011"; -- 0x01C6
+ when 000455 => D <= "00111010"; -- 0x01C7
+ when 000456 => D <= "00000101"; -- 0x01C8
+ when 000457 => D <= "00000100"; -- 0x01C9
+ when 000458 => D <= "00110011"; -- 0x01CA
+ when 000459 => D <= "00111010"; -- 0x01CB
+ when 000460 => D <= "00000101"; -- 0x01CC
+ when 000461 => D <= "00000100"; -- 0x01CD
+ when 000462 => D <= "00110011"; -- 0x01CE
+ when 000463 => D <= "00111010"; -- 0x01CF
+ when 000464 => D <= "00000101"; -- 0x01D0
+ when 000465 => D <= "00000100"; -- 0x01D1
+ when 000466 => D <= "00110011"; -- 0x01D2
+ when 000467 => D <= "00111010"; -- 0x01D3
+ when 000468 => D <= "00000101"; -- 0x01D4
+ when 000469 => D <= "00000100"; -- 0x01D5
+ when 000470 => D <= "00110011"; -- 0x01D6
+ when 000471 => D <= "00111010"; -- 0x01D7
+ when 000472 => D <= "00000101"; -- 0x01D8
+ when 000473 => D <= "00000100"; -- 0x01D9
+ when 000474 => D <= "00110011"; -- 0x01DA
+ when 000475 => D <= "00111010"; -- 0x01DB
+ when 000476 => D <= "00000101"; -- 0x01DC
+ when 000477 => D <= "00000100"; -- 0x01DD
+ when 000478 => D <= "00110011"; -- 0x01DE
+ when 000479 => D <= "00111010"; -- 0x01DF
+ when 000480 => D <= "00000101"; -- 0x01E0
+ when 000481 => D <= "00000100"; -- 0x01E1
+ when 000482 => D <= "00110011"; -- 0x01E2
+ when 000483 => D <= "00111010"; -- 0x01E3
+ when 000484 => D <= "00000101"; -- 0x01E4
+ when 000485 => D <= "00000100"; -- 0x01E5
+ when 000486 => D <= "00110011"; -- 0x01E6
+ when 000487 => D <= "00111010"; -- 0x01E7
+ when 000488 => D <= "00000101"; -- 0x01E8
+ when 000489 => D <= "00000100"; -- 0x01E9
+ when 000490 => D <= "00110011"; -- 0x01EA
+ when 000491 => D <= "00111010"; -- 0x01EB
+ when 000492 => D <= "00000101"; -- 0x01EC
+ when 000493 => D <= "00000100"; -- 0x01ED
+ when 000494 => D <= "00110011"; -- 0x01EE
+ when 000495 => D <= "00111010"; -- 0x01EF
+ when 000496 => D <= "00000101"; -- 0x01F0
+ when 000497 => D <= "00000100"; -- 0x01F1
+ when 000498 => D <= "00110011"; -- 0x01F2
+ when 000499 => D <= "00111010"; -- 0x01F3
+ when 000500 => D <= "00000101"; -- 0x01F4
+ when 000501 => D <= "00000100"; -- 0x01F5
+ when 000502 => D <= "00110011"; -- 0x01F6
+ when 000503 => D <= "00111010"; -- 0x01F7
+ when 000504 => D <= "00000101"; -- 0x01F8
+ when 000505 => D <= "00000100"; -- 0x01F9
+ when 000506 => D <= "00110011"; -- 0x01FA
+ when 000507 => D <= "00111010"; -- 0x01FB
+ when 000508 => D <= "00000101"; -- 0x01FC
+ when 000509 => D <= "00000100"; -- 0x01FD
+ when 000510 => D <= "01000100"; -- 0x01FE
+ when 000511 => D <= "00111111"; -- 0x01FF
+ when 000512 => D <= "00110011"; -- 0x0200
+ when 000513 => D <= "00111010"; -- 0x0201
+ when 000514 => D <= "00000101"; -- 0x0202
+ when 000515 => D <= "00000100"; -- 0x0203
+ when 000516 => D <= "00110011"; -- 0x0204
+ when 000517 => D <= "00111010"; -- 0x0205
+ when 000518 => D <= "00000101"; -- 0x0206
+ when 000519 => D <= "00000100"; -- 0x0207
+ when 000520 => D <= "00110011"; -- 0x0208
+ when 000521 => D <= "00111010"; -- 0x0209
+ when 000522 => D <= "00000101"; -- 0x020A
+ when 000523 => D <= "00000100"; -- 0x020B
+ when 000524 => D <= "00110011"; -- 0x020C
+ when 000525 => D <= "00111010"; -- 0x020D
+ when 000526 => D <= "00000101"; -- 0x020E
+ when 000527 => D <= "00000100"; -- 0x020F
+ when 000528 => D <= "00110011"; -- 0x0210
+ when 000529 => D <= "00111010"; -- 0x0211
+ when 000530 => D <= "00000101"; -- 0x0212
+ when 000531 => D <= "00000100"; -- 0x0213
+ when 000532 => D <= "00110011"; -- 0x0214
+ when 000533 => D <= "00111010"; -- 0x0215
+ when 000534 => D <= "00000101"; -- 0x0216
+ when 000535 => D <= "00000100"; -- 0x0217
+ when 000536 => D <= "00110011"; -- 0x0218
+ when 000537 => D <= "00111010"; -- 0x0219
+ when 000538 => D <= "00000101"; -- 0x021A
+ when 000539 => D <= "00000100"; -- 0x021B
+ when 000540 => D <= "00110011"; -- 0x021C
+ when 000541 => D <= "00111010"; -- 0x021D
+ when 000542 => D <= "00000101"; -- 0x021E
+ when 000543 => D <= "00000100"; -- 0x021F
+ when 000544 => D <= "00110011"; -- 0x0220
+ when 000545 => D <= "00111010"; -- 0x0221
+ when 000546 => D <= "00000101"; -- 0x0222
+ when 000547 => D <= "00000100"; -- 0x0223
+ when 000548 => D <= "00110011"; -- 0x0224
+ when 000549 => D <= "00111010"; -- 0x0225
+ when 000550 => D <= "00000101"; -- 0x0226
+ when 000551 => D <= "00000100"; -- 0x0227
+ when 000552 => D <= "00110011"; -- 0x0228
+ when 000553 => D <= "00111010"; -- 0x0229
+ when 000554 => D <= "00000101"; -- 0x022A
+ when 000555 => D <= "00000100"; -- 0x022B
+ when 000556 => D <= "00110011"; -- 0x022C
+ when 000557 => D <= "00111010"; -- 0x022D
+ when 000558 => D <= "00000101"; -- 0x022E
+ when 000559 => D <= "00000100"; -- 0x022F
+ when 000560 => D <= "00110011"; -- 0x0230
+ when 000561 => D <= "00111010"; -- 0x0231
+ when 000562 => D <= "00000101"; -- 0x0232
+ when 000563 => D <= "00000100"; -- 0x0233
+ when 000564 => D <= "00110011"; -- 0x0234
+ when 000565 => D <= "00111010"; -- 0x0235
+ when 000566 => D <= "00000101"; -- 0x0236
+ when 000567 => D <= "00000100"; -- 0x0237
+ when 000568 => D <= "00110011"; -- 0x0238
+ when 000569 => D <= "00111010"; -- 0x0239
+ when 000570 => D <= "00000101"; -- 0x023A
+ when 000571 => D <= "00000100"; -- 0x023B
+ when 000572 => D <= "00110011"; -- 0x023C
+ when 000573 => D <= "00111010"; -- 0x023D
+ when 000574 => D <= "00000101"; -- 0x023E
+ when 000575 => D <= "00000100"; -- 0x023F
+ when 000576 => D <= "01000100"; -- 0x0240
+ when 000577 => D <= "01100010"; -- 0x0241
+ when 000578 => D <= "01000001"; -- 0x0242
+ when others => D <= "--------";
+ end case;
+ end if;
+ end process;
+end;
Index: tags/rel_1_2/syn/t421/ep1c12/t421.qpf
===================================================================
--- tags/rel_1_2/syn/t421/ep1c12/t421.qpf (nonexistent)
+++ tags/rel_1_2/syn/t421/ep1c12/t421.qpf (revision 180)
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "7.0"
+DATE = "20:42:11 April 27, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "t421"
Index: tags/rel_1_2/syn/t421/ep1c12/rom_42x.hex
===================================================================
--- tags/rel_1_2/syn/t421/ep1c12/rom_42x.hex (nonexistent)
+++ tags/rel_1_2/syn/t421/ep1c12/rom_42x.hex (revision 180)
@@ -0,0 +1,38 @@
+:100000004433593356783C333E001250333E00524D
+:1000100050333E77333E50333A0050333A4D333A03
+:1000200047333A4C430550333A1523805F2300068B
+:10003000333A054A0707333E754E5307333A0723D1
+:1000400000333E5406333A00400204230058230094
+:10005000213392333E211F462142214B212300367A
+:10006000239114332A0600302220230006333A005D
+:100070003006333A333C07332C333A25333A3533A1
+:100080003A3106222300102006333A00530622207C
+:1000900006333A322006333A0F1E33A7333A332C55
+:1000A000333A06333A33614F0057330106333A335C
+:1000B0001106333A330306333A331306333A332106
+:1000C00006333A3350332106333A0106333A1106E8
+:1000D000333A0306333A332933282116333A332986
+:1000E0000613333E33513A33504433290601333E2D
+:1000F000444F06333A0F777E757C737A71787F763A
+:100100007D747B7279701F777E757C737A71787FCE
+:10011000767D747B7279702F777E757C737A7178B7
+:100120007F767D747B7279703F777E757C737A7190
+:10013000787F767D747B7279700F333A0504333A99
+:100140000504333A0504333A0504333A0504333AD7
+:100150000504333A0504333A0504333A0504333AC7
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+:100170000504333A0504333A0504441F333A0504B1
+:10018000333A0504333A0504333A0504333A050497
+:10019000333A0504333A0504333A0504333A050487
+:1001A000333A0504333A0504333A0504333A050477
+:1001B000333A0504333A0504333A0504442F333AFD
+:1001C0000504333A0504333A0504333A0504333A57
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+:1001E0000504333A0504333A0504333A0504333A37
+:1001F0000504333A0504333A0504333A0504443F11
+:10020000333A0504333A0504333A0504333A050416
+:10021000333A0504333A0504333A0504333A050406
+:10022000333A0504333A0504333A0504333A0504F6
+:10023000333A0504333A0504333A0504333A0504E6
+:03024000446241D4
+:00000001FF
Index: tags/rel_1_2/KNOWN_BUGS
===================================================================
--- tags/rel_1_2/KNOWN_BUGS (nonexistent)
+++ tags/rel_1_2/KNOWN_BUGS (revision 180)
@@ -0,0 +1,19 @@
+
+Known bugs of the T400 uController core
+=======================================
+Version: $Id$
+
+
+Release 0.1 BETA
+----------------
+
+*******************************************************************************
+Timer skipped in T421 configuration
+
+When the generic opt_type_g is set to t400_opt_type_421_c inside t400_core,
+the timer module is not included in the core. This is wrong because the COP421
+chip contains this timer.
+
+Fixed in:
+t400_core.vhd 1.10
+Fix will be included in next release.
tags/rel_1_2/KNOWN_BUGS
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/README
===================================================================
--- tags/rel_1_2/README (nonexistent)
+++ tags/rel_1_2/README (revision 180)
@@ -0,0 +1,337 @@
+
+README for the T400 uController project
+=======================================
+Version: $Id$
+
+
+Introduction
+------------
+
+The T400 µController is an implementation of National's 4-bit COP400
+microcontroller family architecture. It is intended to be used as a
+replacement for the original chip in SOCs recreating legacy systems.
+Its final target is to provide design variants that are compatible with the
+COP420/421 and COP410L/411L family members. All of them derived from the
+common t400_core design.
+
+
+Download
+--------
+
+Download the latest stable release from the project homepage at OpenCores.org:
+
+ http://www.opencores.org/projects.cgi/web/t400/overview/
+
+You can get the latest version of the design files from CVS:
+
+ http://www.opencores.org/pdownloads.cgi/list/t400
+
+Please keep in mind that this is work in progress and might contain smaller or
+bigger problems.
+You should also check the Tracker for known bugs and see if they affect your
+work.
+
+
+Installation
+------------
+
+Once the directory structure is generated either by check-out from CVS or by
+unpacking the tar-archive, the central project initialization file should be
+set up. A template called init_project.template.sh is located in the sw
+directory where a copy can be edited. Normally, only the definition for the
+variable PROJECT_DIR has to be adjusted to the path where the directory
+structure is located.
+The commands for setting the necessary variables assume a bash/sh-like
+shell. In case you run a different shell like csh or ksh, you should adjust
+these commands as well.
+
+The meaning of the variables is as follows:
+
+ * PROJECT_DIR
+ Points to the root of the project installation. All further references are
+ derived from its setting.
+
+ * MAKEFILES
+ Identifies the global Makefile for compilation of tests.
+
+These variables must be properly set whenever scripts or makefiles of the T400
+project are executed that are related to verification tasks. Otherwise, you
+will most likely encounter error messages.
+
+NOTE: The concepts of the mentioned shells require that the init_project.sh is
+ run in the context of the shell. I.e. you should 'source' the script
+ instead of executing it like a command. This will make sure that the
+ variable settings are really effective in the calling shell instance.
+
+
+Directory Structure
+-------------------
+
+The project's directory structure follows the proposal of OpenCores.org.
+
+t400
+ |
+ \--+-- rtl
+ | |
+ | +-- vhdl : VHDL code containing the RTL description
+ | | | of the core.
+ | | \-- system : RTL VHDL code of sample systems.
+ | |
+ | \-- tech : Technology specific files.
+ | |
+ | +-- cyclone : Cyclone technology flavor.
+ | |
+ | +-- spartan : Spartan technology flavor.
+ | |
+ | \-- generic : Generic RTL designs.
+ |
+ +-- bench
+ | |
+ | \-- vhdl : VHDL testbench code.
+ |
+ +-- sim
+ | |
+ | \-- rtl_sim : Directory for running simulations.
+ |
+ +-- syn
+ | |
+ | \-- t421 : T421 toplevel example synthesis.
+ | |
+ | +-- ep1c12 : for Altera Cyclone.
+ | |
+ | \-- xc3s1000 : for Xilinx Spartan3.
+ |
+ \-- sw : General purpose scripts and files.
+ |
+ \-- verif : The verification suite.
+ |
+ +-- include : Global includes and makefiles.
+ |
+ +-- black_box : Black-box verification tests.
+ |
+ +-- int : Interrupt verification tests.
+ |
+ \-- system : General system level tests.
+
+
+Compiling the VHDL Code
+-----------------------
+
+VHDL compilation and simulation tasks take place inside in sim/rtl_sim
+directory. The project setup supports only the batch mode of certain
+simulators. However, there should be no problems to integrate the testbench
+and RTL code into arbitrary simulation environments.
+
+The main file for compilation is Makefile which contains all information
+regarding the dependencies of the source files and their compilation
+order.
+
+Compilation is based on the make-utility, thus invocation looks like this:
+
+ $ make
+
+This will call ghdl to analzye and elaborate the complete design hierarchy.
+
+ Tristan Gingold's GHDL simulator/compiler, a VHDL front-end for gcc.
+ http://ghdl.free.fr/
+
+Make will analyze all VHDL files (RTL and testbench code) and elaborate all
+testbench top-levels:
+
+ * tb_t410_behav_c0
+ Testbench for the T410 derivative.
+ It instantiates the T410 system toplevel and is intended to exectue all
+ verifcation tests tagged with 't41x'.
+
+ * tb_t411_behav_c0
+ Testbench for the T411 derivative.
+ It instantiates the T411 system toplevel and is intended to exectue all
+ verifcation tests tagged with 't41x'.
+
+ * tb_t420_behav_c0
+ The testbench for the T420 derivative.
+ It instantiates the T420 system toplevel and is intended to execute all
+ verification tests tagged with 't42x' and 't420'.
+
+ * tb_t421_behav_c0
+ The testbench for the T421 derivative.
+ It instantiates the T421 system toplevel and is intended to execute all
+ verification tests tagged with 't42x'.
+
+ * tb_int_behav_c0
+ The testbench for the interrupt verification suite.
+ It instantiates the T420 system topevel and is intended to execute all
+ verification tests tagged with 'int'.
+
+ * tb_microbus_behav_c0
+ The testbench for the microbus verification.
+ It instantiates the T420 system toplevel in microbus configuration and is
+ intended to execute all verifications tests tagged with 'mb'.
+
+ * tb_prod_behav_c0
+ The testbench for the production test.
+ It instantiates the T420 system toplevel an checks D and P output ports
+ for the patterns generated by the software as proposed in
+ "Testing of COP400 Familiy Devices"
+ National Semiconductor
+ COP Note 7
+ April 1991
+
+The Makefile has a 'clean' target to delete all intermediate data:
+
+ $ make clean
+
+The basic simple sequence list can be found in COMPILE_LIST. This can be
+useful to quickly set up the analyze stage of any compiler or
+synthesizer. Especially when synthesizing the code, you want to skip the VHDL
+configurations in *-c.vhd and everything below the bench/ directory.
+
+
+Preparation of the ROM Files
+----------------------------
+
+All testbenches listed above load the internal ROM of the controller from a
+file in hex-format. Its existance is mandatory since it is referenced in the
+VHDL code of the ROM model lpm_rom.vhd. In case it is missing, the
+simulation will stop immediately after elaborating the design.
+
+These files are:
+
+ * rom_41x.hex
+ Program ROM compiled for the T41x derivatives. Maximum size 512 bytes.
+ Referenced by the t410_notri system.
+ Enabled by the 't41x' tag.
+
+ * rom_42x.hex
+ Program ROM compiled for the T42x derivatives. Maximum size 1024 bytes.
+ Referenced by the t420_notri system.
+ Enabled by the 't42x', 't420', 'int', 'mb' and 'prod' tag.
+
+The verification flow for the T400 project generates these two files
+automatically from the assembler source files. Whenever the make process
+locates one or more of the above tags, it assembles and links the source code
+for the repsective derivative.
+
+All regression tests and the general purpose software is organized in a cell
+structure. Currently, this means that the software for a cell is contained in
+a dedicated directory where the assembler run takes place. In the future,
+there will be more aspects to a cell.
+
+Assembling, linking and putting the hex-files in place is under the control of
+the make-mechanism. E.g. to assemble the source code of a cell, issue the
+following command:
+
+ $ make
+
+The above mention environment variable MAKEFILES enables execution of the make
+process from within any subdirectory in the verification tree. This generates
+the linker file (test_41x.p and test_42x.p) and derives hex-files which are
+placed into the simulation directory. So most likely, for running a test case
+or any other software, you will want to issue:
+
+The only supported assembler is Alfred Arnold's macroassembler AS. See
+
+ http://john.ccac.rwth-aachen.de:8000/as/
+
+
+Verification Environment
+------------------------
+
+The verification environment consists of a number of test programs. They are
+all self-checking. I.e. after testing the targeted functionality, they emit a
+pass/fail information. This information is detected by the testbench which
+stops the simulation and prints out the simulation result. This is the default
+mechanism for stopping the VHDL simulation.
+
+Pass/fail is signalled by a certain sequence of the L port contents:
+(R denotes an optional value stored in A when calling the pass or fail
+routines)
+
+ 1) L outputs 0x0R
+ 2) L outputs 0xaR
+ 3) L outputs 0x5R
+ 4) L outputs 0x0R -> Pass
+ L outputs 0xfR -> Fail
+
+The detection is modelled like a state machine and in case the sequence is of
+bytes inside the accumulator does not match, the detection process restarts
+from the beginning. This mechanism is part of all verification tests except
+for the interrupt testbench.
+
+The complete regression suite can be executed with the run_regression.pl
+script. For each test cell, it steps through the sequence
+
+ 1) Assemble the source code
+ 2) Run the compiled VHDL design (currently only GHDL)
+
+It is highly recommended to redirect the output of run_regression.pl into a
+file. Otherwise, analyzing the messages related to each test cell is almost
+impossible.
+
+
+Clocking System
+---------------
+
+The main clock is supplied at input ck_i. To ease system integration, ck_i can
+accept integer multiples of the target clock frequency. Input ck_en_i is used
+to qualify rising edges on ck_i as active clock edges. When ck_i is supplied
+with the target frequency, ck_en_i can be kept high constantly.
+
+
+Generic Parameters
+------------------
+
+Most generic parameters are provided to set the numerous I/O options. Thus
+such options are exhibited on the toplevel designs.
+All generics are implemented with integer types to enable analysis of the RTL
+code without tool restrictions. The related constants are defined in
+t400_opt_pack-p.vhd.
+
+ opt_type_g : Derivative type - T420, T421, T410, T411
+ opt_ck_div_g : Internal divider on CK
+ opt_cko_g : Enable CKO as general purpose input
+ opt_l_out_type_7_g : Output driver type L[7]
+ opt_l_out_type_6_g : Output driver type L[6]
+ opt_l_out_type_5_g : Output driver type L[5]
+ opt_l_out_type_4_g : Output driver type L[4]
+ opt_l_out_type_3_g : Output driver type L[3]
+ opt_l_out_type_2_g : Output driver type L[2]
+ opt_l_out_type_1_g : Output driver type L[1]
+ opt_l_out_type_0_g : Output driver type L[0]
+ opt_microbus_g : Enable MICROBUS interface
+ opt_d_out_type_3_g : Output driver type D[3]
+ opt_d_out_type_2_g : Output driver type D[2]
+ opt_d_out_type_1_g : Output driver type D[1]
+ opt_d_out_type_0_g : Output driver type D[0]
+ opt_g_out_type_3_g : Output driver type G[3]
+ opt_g_out_type_2_g : Output driver type G[2]
+ opt_g_out_type_1_g : Output driver type G[1]
+ opt_g_out_type_0_g : Output driver type G[0]
+ opt_so_output_type_g : Output driver type SO
+ opt_sk_output_type_g : Output driver type SK
+
+
+FPGA Implementation
+-------------------
+
+All of the design files contain pure RTL code. This is true even for the
+technology specific power-on reset module. Two flavors exist, each of them
+implementing the desired behavior in a way that is understood by the design
+tools. The RAM for the data memory is described by generic RTL code as
+well. It should be translated automatically by the tool chain to a technology
+specific RAM macro.
+
+There is a generic method for the program memory ROM as well, although this
+project uses a flow where hex-files are loaded by lpm_rom.vhd as the default
+method. Convert the ROM image to an RTL VHDL file with one of the two
+following commands (either from hex or bin format):
+
+ $ hex2rom -b [rom image file] rom_t41x 9l8s > rom_t41x.vhd
+ $ hex2rom -b [rom image file] rom_t42x 10l8s > rom_t42x.vhd
+
+The option -b specifies that contains binary data. Skip this
+option to process a file in hex format.
+
+These resulting RTL representations are instantiated by t410_rom-struct-a.vhd
+and t420_rom-struct-a.vhd. Altera and Xilinx design tools will detect and
+extract the ROM and turn it into a memory macro.
tags/rel_1_2/README
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: tags/rel_1_2/COMPILE_LIST
===================================================================
--- tags/rel_1_2/COMPILE_LIST (nonexistent)
+++ tags/rel_1_2/COMPILE_LIST (revision 180)
@@ -0,0 +1,91 @@
+rtl/vhdl/t400_opt_pack-p.vhd
+rtl/vhdl/t400_clkgen.vhd
+rtl/vhdl/t400_clkgen-c.vhd
+rtl/vhdl/t400_reset.vhd
+rtl/vhdl/t400_reset-c.vhd
+rtl/vhdl/t400_pack-p.vhd
+bench/vhdl/tb_pack-p.vhd
+rtl/vhdl/t400_pmem_ctrl.vhd
+rtl/vhdl/t400_pmem_ctrl-c.vhd
+rtl/vhdl/t400_dmem_ctrl.vhd
+rtl/vhdl/t400_dmem_ctrl-c.vhd
+rtl/vhdl/t400_comp_pack-p.vhd
+rtl/vhdl/t400_mnemonic_pack-p.vhd
+rtl/vhdl/t400_decoder.vhd
+rtl/vhdl/t400_decoder-c.vhd
+rtl/vhdl/t400_skip.vhd
+rtl/vhdl/t400_skip-c.vhd
+rtl/vhdl/t400_alu.vhd
+rtl/vhdl/t400_alu-c.vhd
+rtl/vhdl/t400_stack.vhd
+rtl/vhdl/t400_stack-c.vhd
+rtl/vhdl/t400_io_pack-p.vhd
+rtl/vhdl/t400_io_l.vhd
+rtl/vhdl/t400_io_l-c.vhd
+rtl/vhdl/t400_io_d.vhd
+rtl/vhdl/t400_io_d-c.vhd
+rtl/vhdl/t400_io_g.vhd
+rtl/vhdl/t400_io_g-c.vhd
+rtl/vhdl/t400_io_in.vhd
+rtl/vhdl/t400_io_in-c.vhd
+rtl/vhdl/t400_sio.vhd
+rtl/vhdl/t400_sio-c.vhd
+rtl/vhdl/t400_timer.vhd
+rtl/vhdl/t400_timer-c.vhd
+rtl/vhdl/t400_core.vhd
+rtl/vhdl/t400_core-c.vhd
+rtl/tech/generic/generic_ram_ena.vhd
+rtl/tech/generic/generic_ram_ena-c.vhd
+bench/vhdl/lpm_rom.vhd
+rtl/vhdl/system/t410_rom-e.vhd
+bench/vhdl/t410_rom-lpm-a.vhd
+bench/vhdl/t410_rom-lpm-c.vhd
+rtl/tech/cyclone/t400_por.vhd
+rtl/tech/cyclone/t400_por-c.vhd
+rtl/vhdl/t400_core_comp_pack-p.vhd
+rtl/tech/t400_tech_comp_pack-p.vhd
+rtl/vhdl/system/t410_notri.vhd
+rtl/vhdl/system/t410_notri-c.vhd
+rtl/vhdl/system/t400_system_comp_pack-p.vhd
+rtl/vhdl/system/t410.vhd
+rtl/vhdl/system/t410-c.vhd
+bench/vhdl/tb_elems.vhd
+bench/vhdl/tb_elems-c.vhd
+bench/vhdl/tb_t410.vhd
+bench/vhdl/tb_t410-c.vhd
+Elaborate toplevel tb_t410_behav_c0.
+
+rtl/vhdl/system/t411.vhd
+rtl/vhdl/system/t411-c.vhd
+bench/vhdl/tb_t411.vhd
+bench/vhdl/tb_t411-c.vhd
+Elaborate toplevel tb_t411_behav_c0.
+
+rtl/vhdl/system/t420_rom-e.vhd
+bench/vhdl/t420_rom-lpm-a.vhd
+bench/vhdl/t420_rom-lpm-c.vhd
+rtl/vhdl/system/t420_notri.vhd
+rtl/vhdl/system/t420_notri-c.vhd
+rtl/vhdl/system/t420.vhd
+rtl/vhdl/system/t420-c.vhd
+bench/vhdl/tb_t420.vhd
+bench/vhdl/tb_t420-c.vhd
+Elaborate toplevel tb_t420_behav_c0.
+
+rtl/vhdl/system/t421.vhd
+rtl/vhdl/system/t421-c.vhd
+bench/vhdl/tb_t421.vhd
+bench/vhdl/tb_t421-c.vhd
+Elaborate toplevel tb_t421_behav_c0.
+
+bench/vhdl/tb_int.vhd
+bench/vhdl/tb_int-c.vhd
+Elaborate toplevel tb_int_behav_c0.
+
+bench/vhdl/tb_microbus.vhd
+bench/vhdl/tb_microbus-c.vhd
+Elaborate toplevel tb_microbus_behav_c0.
+
+bench/vhdl/tb_prod.vhd
+bench/vhdl/tb_prod-c.vhd
+Elaborate toplevel tb_prod_behav_c0.
Index: tags/rel_1_2/COPYING
===================================================================
--- tags/rel_1_2/COPYING (nonexistent)
+++ tags/rel_1_2/COPYING (revision 180)
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
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+
+ Finally, any free program is threatened constantly by software
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+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
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+
+You may charge a fee for the physical act of transferring a copy, and
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+
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+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C) 19yy
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) 19yy name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
Index: tags/rel_1_2
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