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URL https://opencores.org/ocsvn/t48/t48/trunk

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    from Rev 334 to Rev 335
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Rev 334 → Rev 335

/t48/trunk/sw/verif/black_box/upi41/basic_echo/test.asm
2,9 → 2,8
;; Test UPI41 read and write.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8041
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
11,12 → 10,12
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; signal test start
anl P1, #~004H
23,26 → 22,26
 
;; request echo test
mov a, #001H
uout dbb, a
out dbb, a
 
;; read input as data
inp1: ujnibf inp1
inp1: jnibf inp1
jf1 fail
 
uin a, dbb
in a, dbb
 
;; invert and output
cpl a
uout dbb, a
out dbb, a
 
out1: ujobf out1
out1: jobf out1
 
;; read next input as command
inp2: ujnibf inp2
inp2: jnibf inp2
jf1 inp2_2
jmp fail
 
inp2_2: uin a, dbb
inp2_2: in a, dbb
xrl a, #001H
jz pass
 
/t48/trunk/sw/verif/black_box/upi41/basic_echo_int/test.asm
2,9 → 2,8
;; Test UPI41 read and write with IBF interrupt.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8041
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
jmp main
14,7 → 13,7
 
mov r6, a
 
uin a, dbb
in a, dbb
mov r7, a
 
mov a, r6
25,12 → 24,12
main:
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; set up ISR
clr a
42,7 → 41,7
 
;; request echo test
mov a, #001H
uout dbb, a
out dbb, a
 
waitisr:
mov a, r7
53,16 → 52,16
 
;; invert and output
cpl a
uout dbb, a
out dbb, a
 
out1: ujobf out1
out1: jobf out1
 
;; read next input as command
inp2: ujnibf inp2
inp2: jnibf inp2
jf1 inp2_2
jmp fail
 
inp2_2: uin a, dbb
inp2_2: in a, dbb
xrl a, #001H
jz pass
 
/t48/trunk/sw/verif/black_box/upi41/dma/test.asm
2,9 → 2,8
;; Test UPI41A DMA.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8042
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
11,12 → 10,12
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; signal test start
anl P1, #~004H
23,18 → 22,18
 
;; request master interrupt test
mov a, #005H
uout dbb, a
out dbb, a
 
;; setup DMA
;; read input as data
step1: ujnibf step1
step1: jnibf step1
jf1 fail
 
uin a, dbb
in a, dbb
xrl a, #~005H
jnz fail
 
uen_dma
en dma
 
;; Step 2: Request 4 reads via DMA
mov r7, #004H
43,11 → 42,11
dloop2: djnz r0, dloop2
 
mov a, r7
uout dbb, a
out dbb, a
 
orl p2, #040H
 
step2: ujobf step2
step2: jobf step2
djnz r7, read4dma
 
;; Step 3: Request 4 writes via DMA
58,9 → 57,9
 
orl p2, #040H
 
step3: ujnibf step3
step3: jnibf step3
 
uin a, dbb
in a, dbb
xrl a, r7
jnz fail
jf1 fail
69,12 → 68,12
 
 
;; read next input as command
done: ujnibf done
done: jnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
in a, dbb
xrl a, #005H
jz pass
 
/t48/trunk/sw/verif/black_box/upi41/master_int/test.asm
2,9 → 2,8
;; Test UPI41A master interrupts.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8042
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
11,12 → 10,12
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; signal test start
anl P1, #~004H
23,34 → 22,34
 
;; request master interrupt test
mov a, #004H
uout dbb, a
out dbb, a
 
;; read input as data
step1: ujnibf step1
step1: jnibf step1
jf1 fail
 
uin a, dbb
in a, dbb
xrl a, #~004H
jnz fail
 
;; set up master interrupt flags
uen_flags
en flags
orl p2, #00110000B
 
;; read input as command
step2: ujnibf step2
step2: jnibf step2
jf1 step2_goon
jmp fail
step2_goon:
uin a, dbb
in a, dbb
xrl a, #004H
jnz fail
 
;; read turnover byte as data
step3: ujnibf step3
step3: jnibf step3
jf1 fail
 
uin a, dbb
in a, dbb
xrl a, #0AAH
jnz fail
 
59,21 → 58,21
 
;; send step4 indicator
mov a, #040H
uout dbb, a
step4: ujobf step4
out dbb, a
step4: jobf step4
 
;; set step5 indicator
mov a, #050H
uout dbb,a
step5: ujobf step5
out dbb,a
step5: jobf step5
 
;; read next input as command
done: ujnibf done
done: jnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
in a, dbb
xrl a, #004H
jz pass
 
/t48/trunk/sw/verif/black_box/upi41/status41_test/test.asm
2,9 → 2,8
;; Test UPI41 status bits.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8041
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
11,12 → 10,12
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; signal test start
anl P1, #~004H
23,58 → 22,58
 
;; request status41 test
mov a, #002H
uout dbb, a
out dbb, a
 
;; wait for IBF=1 and F1=1
step1: ujnibf step1
step1: jnibf step1
jf1 step1_goon
jmp step1
step1_goon:
 
;; wait for IBF=1 and F1=0
step2: ujnibf step2
step2: jnibf step2
jf1 step2
 
 
;; wait for IBF=1 and F1=1
step3: ujnibf step3
step3: jnibf step3
jf1 step3_goon
jmp step3
step3_goon:
;; read IBF and complement F0
uin a, dbb
in a, dbb
xrl a, #~002H
jnz fail
cpl f0
 
;; wait for IBF=1 and F1=0
step4: ujnibf step4
step4: jnibf step4
jf1 step4
;; read IBF and complement F0
uin a, dbb
in a, dbb
xrl a, #~002H
jnz fail
cpl f0
 
;; wait for IBF=1 and F1=1
step5: ujnibf step5
step5: jnibf step5
jf1 step5_goon
jmp step5
step5_goon:
;; read IBF and complement F0
uin a, dbb
in a, dbb
xrl a, #002H
jnz fail
cpl f0
;; load OBF
mov a, #099H
uout dbb, a
out dbb, a
 
;; wait for IBF=1 and F1=0
step6: ujnibf step6
step6: jnibf step6
jf1 step6
;; read IBF and complement F0
uin a, dbb
in a, dbb
xrl a, #002H
jnz fail
cpl f0
82,15 → 81,15
cpl f1
;; load OBF
mov a, #066H
uout dbb, a
out dbb, a
 
;; read next input as command
done: ujnibf done
done: jnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
in a, dbb
xrl a, #002H
jz pass
 
/t48/trunk/sw/verif/black_box/upi41/status41a_test/test.asm
2,9 → 2,8
;; Test UPI41A extra status bits.
;; *******************************************************************
 
INCLUDE "cpu.inc"
CPU 8042
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
11,12 → 10,12
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
jobf fail
 
;; signal test start
anl P1, #~004H
23,83 → 22,83
 
;; request status41a test
mov a, #003H
uout dbb, a
out dbb, a
 
;; wait for IBF=1 and F1=1
step1: ujnibf step1
step1: jnibf step1
jf1 step1_goon
jmp fail
step1_goon:
uin a, dbb
in a, dbb
xrl a, #003H
jnz fail
 
mov a, #0AAH
umov sts, a
mov sts, a
jf1 step1_f1_ok
jmp fail
step1_f1_ok:
 
mov a, #001H
uout dbb, a
out dbb, a
 
 
;; wait for IBF=1 and F1=0
step2: ujnibf step2
step2: jnibf step2
jf1 fail
 
uin a, dbb
in a, dbb
xrl a, #~003H
jnz fail
 
mov a, #055H
umov sts, a
mov sts, a
jf1 fail
 
mov a, #002H
uout dbb, a
out dbb, a
 
 
;; wait for IBF=1 and F1=1
step3: ujnibf step3
step3: jnibf step3
jf1 step3_goon
jmp fail
step3_goon:
uin a, dbb
in a, dbb
xrl a, #003H
jnz fail
 
mov a, #00AH
umov sts, a
mov sts, a
jf1 step3_f1_ok
jmp fail
step3_f1_ok:
 
mov a, #003H
uout dbb, a
out dbb, a
 
;; wait for IBF=1 and F1=0
step4: ujnibf step4
step4: jnibf step4
jf1 fail
 
uin a, dbb
in a, dbb
xrl a, #~003H
jnz fail
 
mov a, #005H
umov sts, a
mov sts, a
jf1 fail
 
mov a, #004H
uout dbb, a
out dbb, a
 
;; read next input as command
done: ujnibf done
done: jnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
in a, dbb
xrl a, #003H
jz pass
 
/t48/trunk/sw/verif/include/upi41_opcodes.inc File deleted

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