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Rev 329 → Rev 330

/branches/wip_t2x/bench/vhdl/tb_t8021-c.vhd
0,0 → 1,21
-------------------------------------------------------------------------------
--
-- The testbench for t8021.
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
configuration tb_t8021_behav_c0 of tb_t8021 is
 
for behav
 
for t8021_b : t8021
use configuration work.t8021_struct_c0;
end for;
 
end for;
 
end tb_t8021_behav_c0;
/branches/wip_t2x/bench/vhdl/tb_t8021.vhd
0,0 → 1,182
-------------------------------------------------------------------------------
--
-- The testbench for t8021.
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity tb_t8021 is
 
end tb_t8021;
 
 
use work.t48_core_comp_pack.generic_ram_ena;
use work.t48_system_comp_pack.t8021;
 
use work.t48_tb_pack.all;
 
architecture behav of tb_t8021 is
 
-- clock period, 11 MHz
constant period_c : time := 90 ns;
 
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
 
signal xtal_s : std_logic;
signal res_s : std_logic;
signal ale_s : std_logic;
signal prog_n_s : std_logic;
 
signal p0_b : std_logic_vector( 7 downto 0);
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 3 downto 0);
 
signal zero_s : std_logic;
signal one_s : std_logic;
 
begin
 
zero_s <= '0';
one_s <= '1';
 
p2_b <= (others => 'H');
p1_b <= (others => 'H');
p0_b <= (others => 'H');
 
t8021_b : t8021
port map (
xtal_i => xtal_s,
reset_i => res_s,
ale_o => ale_s,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
p0_b => p0_b,
prog_n_o => prog_n_s
);
 
 
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_s <= '1';
wait for 5 * period_c;
res_s <= '0';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
 
 
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
 
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
 
assert false
report "End of simulation reached."
severity failure;
 
end if;
end if;
end loop;
 
end process eos;
--
-----------------------------------------------------------------------------
 
end behav;
/branches/wip_t2x/rtl/vhdl/bus_mux.vhd
48,19 → 48,22
use ieee.std_logic_1164.all;
 
use work.t48_pack.word_t;
use work.t48_pack.bus_idle_level_c;
 
entity t48_bus_mux is
 
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
alu_data_i : in word_t := (others => bus_idle_level_c);
bus_data_i : in word_t := (others => bus_idle_level_c);
dec_data_i : in word_t := (others => bus_idle_level_c);
dm_data_i : in word_t := (others => bus_idle_level_c);
pm_data_i : in word_t := (others => bus_idle_level_c);
p0_data_i : in word_t := (others => bus_idle_level_c);
p1_data_i : in word_t := (others => bus_idle_level_c);
p2_data_i : in word_t := (others => bus_idle_level_c);
psw_data_i : in word_t := (others => bus_idle_level_c);
tim_data_i : in word_t := (others => bus_idle_level_c);
adc_data_i : in word_t := (others => bus_idle_level_c);
data_o : out word_t
);
 
67,8 → 70,6
end t48_bus_mux;
 
 
use work.t48_pack.bus_idle_level_c;
 
architecture rtl of t48_bus_mux is
 
begin
79,10 → 80,12
dec_data_i or
dm_data_i or
pm_data_i or
p0_data_i or
p1_data_i or
p2_data_i or
psw_data_i or
tim_data_i;
tim_data_i or
adc_data_i;
end generate;
 
and_tree: if bus_idle_level_c = '1' generate
91,10 → 94,12
dec_data_i and
dm_data_i and
pm_data_i and
p0_data_i and
p1_data_i and
p2_data_i and
psw_data_i and
tim_data_i;
tim_data_i and
adc_data_i;
end generate;
 
end rtl;
/branches/wip_t2x/rtl/vhdl/decoder.vhd
5,7 → 5,7
--
-- $Id$
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
60,7 → 60,9
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1;
is_upi_g : integer := 0;
is_upi_type_a_g : integer := 0
is_upi_type_a_g : integer := 0;
is_mcs2x_g : integer := 0;
is_mcs2x_type_2_g : integer := 0
);
 
port (
92,6 → 94,8
dm_write_dmem_addr_o : out boolean;
dm_write_dmem_o : out boolean;
dm_read_dmem_o : out boolean;
p0_write_p0_o : out boolean; -- MCS2x
p0_read_p0_o : out boolean; -- MCS2x
p1_write_p1_o : out boolean;
p1_read_p1_o : out boolean;
p2_write_p2_o : out boolean;
162,7 → 166,11
tim_start_t_o : out boolean;
tim_start_cnt_o : out boolean;
tim_stop_tcnt_o : out boolean;
tim_overflow_i : in boolean
tim_overflow_i : in boolean;
-- ADC Interface - MCS22 --------------------------------------------------
adc_sel_an0_o : out boolean;
adc_sel_an1_o : out boolean;
adc_read_adc_o : out boolean
);
 
end t48_decoder;
271,6 → 279,18
report "is_upi_type_a_g must be either 1 or 0!"
severity failure;
 
-- MCS-2x configuration -----------------------------------------------------
assert (is_mcs2x_g = 0) or (is_mcs2x_g = 1)
report "is_mcs2x_g must be either 1 or 0!"
severity failure;
--
assert (is_mcs2x_type_2_g = 0) or (is_mcs2x_type_2_g = 1)
report "is_mcs2x_type_2_g must be either 1 or 0!"
severity failure;
 
assert not ((is_upi_g = 1) and (is_mcs2x_g = 1))
report "is_upi_g and is_mcs2x_g are mutually exclusive!"
severity failure;
-- pragma translate_on
 
 
277,7 → 297,7
-----------------------------------------------------------------------------
-- Opcode Decoder
--
gen_mcs48: if is_upi_g = 0 generate
gen_mcs48: if is_upi_g = 0 and is_mcs2x_g = 0 generate
mnemonic_rec_s <= decode_mcs48_opcode_f (opcode => opc_opcode_q);
end generate;
gen_upi41: if is_upi_g = 1 and is_upi_type_a_g = 0 generate
286,6 → 306,12
gen_upi41a: if is_upi_g = 1 and is_upi_type_a_g = 1 generate
mnemonic_rec_s <= decode_upi41a_opcode_f(opcode => opc_opcode_q);
end generate;
gen_mcs21: if is_mcs2x_g = 1 and is_mcs2x_type_2_g = 0 generate
mnemonic_rec_s <= decode_mcs21_opcode_f(opcode => opc_opcode_q);
end generate;
gen_mcs22: if is_mcs2x_g = 1 and is_mcs2x_type_2_g = 1 generate
mnemonic_rec_s <= decode_mcs22_opcode_f(opcode => opc_opcode_q);
end generate;
--
-----------------------------------------------------------------------------
 
582,6 → 608,8
tim_start_t_o <= false;
tim_start_cnt_o <= false;
tim_stop_tcnt_o <= false;
p0_write_p0_o <= false; -- MCS2x
p0_read_p0_o <= false; -- MCS2x
p1_write_p1_o <= false;
p1_read_p1_o <= false;
p1_read_reg_o <= false;
598,6 → 626,9
psw_write_aux_carry_o <= false;
psw_write_f0_o <= false;
psw_write_bs_o <= false;
adc_sel_an0_o <= false; -- MCS22
adc_sel_an1_o <= false; -- MCS22
adc_read_adc_o <= false; -- MCS22
jtf_executed_s <= false;
en_tcnti_s <= false;
dis_tcnti_s <= false;
808,7 → 839,8
-- injected CALLS are not located in Program Memory,
-- the PC points already to the instruction to be executed
-- after the interrupt
if not int_pending_s then
-- 8021/8022 store unincremented program counter on stack for CALL
if not (int_pending_s or is_mcs2x_g = 1) then
add_inc_pc_s <= true;
end if;
 
1091,6 → 1123,14
add_read_bus_s <= true;
end if;
 
-- Mnemonic IN_P0 - MCS2x -----------------------------------------------
when MN_IN_P0 =>
-- read Port0 and store in Accumulator
if clk_second_cycle_i and clk_mstate_i = MSTATE2 then
alu_write_accu_o <= true;
p0_read_p0_o <= true;
end if;
 
-- Mnemonic INS ---------------------------------------------------------
when MN_INS =>
clk_assert_rd_o <= true;
1793,8 → 1833,23
 
end if;
 
-- Mnemonic OUTL_P0 - MCS2x ---------------------------------------------
when MN_OUTL_P0 =>
-- read Accumulator and store in Port0
if not clk_second_cycle_i and clk_mstate_i = MSTATE4 then
alu_read_alu_o <= true;
p0_write_p0_o <= true;
end if;
 
-- Mnemonic RAD - MCS22 -------------------------------------------------
when MN_RAD =>
if clk_mstate_i = MSTATE3 then
adc_read_adc_o <= true;
alu_write_accu_o <= true;
end if;
 
-- Mnemonic RET ---------------------------------------------------------
when MN_RET =>
when MN_RET | MN_RETR | MN_RETI =>
if not clk_second_cycle_i then
case clk_mstate_i is
-- decrement Stack Pointer
1826,12 → 1881,21
when MSTATE1 =>
dm_read_dmem_o <= true;
pm_write_pch_o <= true;
if opc_opcode_q(4) = '1' then
if opc_mnemonic_s = MN_RETR then
psw_write_psw_o <= true;
retr_executed_s <= true;
elsif opc_mnemonic_s = MN_RETI then
-- no psw in MCS22
retr_executed_s <= true;
end if;
 
when MSTATE2 =>
-- MCS2x require increment of program counter for RET
if is_mcs2x_g = 1 and opc_mnemonic_s = MN_RET then
add_inc_pc_s <= true;
end if;
 
when MSTATE3 =>
add_write_pmem_addr_s <= true;
 
when others =>
1869,6 → 1933,16
end if;
end if;
 
-- Mnemonic SEL_AN - MCS22 ----------------------------------------------
when MN_SEL_AN =>
if clk_mstate_i = MSTATE3 then
if opc_opcode_q(4) = '0' then
adc_sel_an0_o <= true;
else
adc_sel_an1_o <= true;
end if;
end if;
 
-- Mnemonic SEL_MB ------------------------------------------------------
when MN_SEL_MB =>
if clk_mstate_i = MSTATE3 then
/branches/wip_t2x/rtl/vhdl/decoder_pack-p.vhd
2,7 → 2,7
--
-- $Id$
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
66,6 → 66,7
MN_OUTD_PP_A,
MN_OUTL_EXT,
MN_RET,
MN_RETR,
MN_RL,
MN_RR,
MN_SEL_MB,
83,7 → 84,14
MN_JOBF,
-- UPI41A opcodes
MN_EN_DMA_FLAGS,
MN_MOV_STS
MN_MOV_STS,
-- MCS21 opcodes
MN_IN_P0,
MN_OUTL_P0,
-- MCS21 opcodes
MN_RAD,
MN_RETI,
MN_SEL_AN
);
 
type mnemonic_rec_t is
101,6 → 109,12
function decode_upi41a_opcode_f(opcode : in word_t) return
mnemonic_rec_t;
 
function decode_mcs21_opcode_f(opcode : in word_t) return
mnemonic_rec_t;
 
function decode_mcs22_opcode_f(opcode : in word_t) return
mnemonic_rec_t;
 
end t48_decoder_pack;
 
 
107,9 → 121,9
package body t48_decoder_pack is
 
-----------------------------------------------------------------------------
-- Common opcodes of MCS-48 and UPI-41/UPI-41A
-- Basic opcodes shared by all variants.
--
function decode_common_opcode_f(opcode : in word_t) return
function decode_basic_opcode_f(opcode : in word_t) return
mnemonic_rec_t is
variable mnemonic_v : mnemonic_t;
variable multi_cycle_v : boolean;
159,11 → 173,6
when "10010111" => -- CLR C
mnemonic_v := MN_CLR_C;
 
-- Mnemonic CLR_F -------------------------------------------------------
when "10000101" | -- CLR F0
"10100101" =>
mnemonic_v := MN_CLR_F;
 
-- Mnemonic CPL_A -------------------------------------------------------
when "00110111" => -- CPL A
mnemonic_v := MN_CPL_A;
172,31 → 181,14
when "10100111" => -- CPL C
mnemonic_v := MN_CPL_C;
 
-- Mnemonic CPL_F -------------------------------------------------------
when "10010101" | -- CPL F0
"10110101" => -- CPL F1
mnemonic_v := MN_CPL_F;
 
-- Mnemonic DA ----------------------------------------------------------
when "01010111" => -- DA D
mnemonic_v := MN_DA;
 
-- Mnemonic DEC ---------------------------------------------------------
when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr
"11001100" | "11001101" | "11001110" | "11001111" | --
"00000111" => -- DEC A
when "00000111" => -- DEC A
mnemonic_v := MN_DEC;
 
-- Mnemonic DIS_EN_I ----------------------------------------------------
when "00010101" | -- DIS I
"00000101" => -- EN I
mnemonic_v := MN_DIS_EN_I;
 
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when "00110101" | -- DIS TCNTI
"00100101" => -- EN TCNTI
mnemonic_v := MN_DIS_EN_TCNTI;
 
-- Mnemonic DJNZ --------------------------------------------------------
when "11101000" | "11101001" | "11101010" | "11101011" | -- DJNZ Rr, addr
"11101100" | "11101101" | "11101110" | "11101111" => --
215,12 → 207,6
"00010000" | "00010001" => -- INC @ Rr
mnemonic_v := MN_INC;
 
-- Mnemonic JBB ---------------------------------------------------------
when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr
"10010010" | "10110010" | "11010010" | "11110010" => --
mnemonic_v := MN_JBB;
multi_cycle_v := true;
 
-- Mnemonic JC ----------------------------------------------------------
when "11110110" | -- JC addr
"11100110" => -- JNC addr
227,12 → 213,6
mnemonic_v := MN_JC;
multi_cycle_v := true;
 
-- Mnemonic JF ----------------------------------------------------------
when "10110110" | -- JF0 addr
"01110110" => -- JF1 addr
mnemonic_v := MN_JF;
multi_cycle_v := true;
 
-- Mnemonic JMP ---------------------------------------------------------
when "00000100" | "00100100" | "01000100" | "01100100" | -- JMP addr
"10000100" | "10100100" | "11000100" | "11100100" => --
244,14 → 224,6
mnemonic_v := MN_JMPP;
multi_cycle_v := true;
 
-- Mnemonic JT ----------------------------------------------------------
when "00100110" | -- JNT0 addr
"01000110" | -- JNT1 addr
"00110110" | -- JT0 addr
"01010110" => -- JT1 addr
mnemonic_v := MN_JT;
multi_cycle_v := true;
 
-- Mnemonic JTF ---------------------------------------------------------
when "00010110" => -- JTF addr
mnemonic_v := MN_JTF;
268,10 → 240,6
mnemonic_v := MN_MOV_A_DATA;
multi_cycle_v := true;
 
-- Mnemonic MOV_A_PSW ---------------------------------------------------
when "11000111" => -- MOV A, PSW
mnemonic_v := MN_MOV_A_PSW;
 
-- Mnemonic MOV_A_RR ----------------------------------------------------
when "11111000" | "11111001" | "11111010" | "11111011" | -- MOV A, Rr
"11111100" | "11111101" | "11111110" | "11111111" | --
278,10 → 246,6
"11110000" | "11110001" => -- MOV A, @ Rr
mnemonic_v := MN_MOV_A_RR;
 
-- Mnemonic MOV_PSW_A ---------------------------------------------------
when "11010111" => -- MOV PSW, A
mnemonic_v := MN_MOV_PSW_A;
 
-- Mnemonic MOV_RR ------------------------------------------------------
when "10101000" | "10101001" | "10101010" | "10101011" | -- MOV Rr, A
"10101100" | "10101101" | "10101110" | "10101111" | --
306,8 → 270,7
multi_cycle_v := true;
 
-- Mnemonic MOVP --------------------------------------------------------
when "10100011" | -- MOVP A, @ A
"11100011" => -- MOVP3 A, @ A
when "10100011" => -- MOVP A, @ A
mnemonic_v := MN_MOVP;
multi_cycle_v := true;
 
328,14 → 291,18
 
-- Mnemonic OUTD_PP_A ---------------------------------------------------
when "00111100" | "00111101" | "00111110" | "00111111" | -- MOVD Pp, A
"10011100" | "10011101" | "10011110" | "10011111" | -- ANLD PP, A
"10011100" | "10011101" | "10011110" | "10011111" | -- ANLD Pp, A
"10001100" | "10001101" | "10001110" | "10001111" => -- ORLD Pp, A
mnemonic_v := MN_OUTD_PP_A;
multi_cycle_v := true;
 
-- Mnemonic OUTL_EXT ----------------------------------------------------
when "00111001" | "00111010" => -- OUTL Pp, A
mnemonic_v := MN_OUTL_EXT;
multi_cycle_v := true;
 
-- Mnemonic RET ---------------------------------------------------------
when "10000011" | -- RET
"10010011" => -- RETR
when "10000011" => -- RET
mnemonic_v := MN_RET;
multi_cycle_v := true;
 
349,11 → 316,6
"01100111" => -- RRC A
mnemonic_v := MN_RR;
 
-- Mnemonic SEL_RB ------------------------------------------------------
when "11000101" | -- SEL RB0
"11010101" => -- SEL RB1
mnemonic_v := MN_SEL_RB;
 
-- Mnemonic STOP_TCNT ---------------------------------------------------
when "01100101" => -- STOP TCNT
mnemonic_v := MN_STOP_TCNT;
396,7 → 358,113
return result_v;
end;
 
-----------------------------------------------------------------------------
-- Common opcodes of MCS-48 and UPI-41/UPI-41A
--
function decode_common_mcs48_upi41_opcode_f(opcode : in word_t) return
mnemonic_rec_t is
variable mnemonic_v : mnemonic_t;
variable multi_cycle_v : boolean;
variable result_v : mnemonic_rec_t;
begin
-- default assignment
multi_cycle_v := false;
 
case opcode is
-- Mnemonic ANL_EXT -----------------------------------------------------
when "10011001" | "10011010" => -- ANL PP, data
mnemonic_v := MN_ANL_EXT;
multi_cycle_v := true;
 
-- Mnemonic CLR_F -------------------------------------------------------
when "10000101" | -- CLR F0
"10100101" => -- CLR F1
mnemonic_v := MN_CLR_F;
 
-- Mnemonic CPL_F -------------------------------------------------------
when "10010101" | -- CPL F0
"10110101" => -- CPL F1
mnemonic_v := MN_CPL_F;
 
-- Mnemonic DEC - extend basic set --------------------------------------
when "11001000" | "11001001" | "11001010" | "11001011" | -- DEC Rr
"11001100" | "11001101" | "11001110" | "11001111" => --
mnemonic_v := MN_DEC;
 
-- Mnemonic DIS_EN_I ----------------------------------------------------
when "00010101" | -- DIS I
"00000101" => -- EN I
mnemonic_v := MN_DIS_EN_I;
 
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when "00110101" | -- DIS TCNTI
"00100101" => -- EN TCNTI
mnemonic_v := MN_DIS_EN_TCNTI;
 
-- Mnemonic JBB ---------------------------------------------------------
when "00010010" | "00110010" | "01010010" | "01110010" | -- JBb addr
"10010010" | "10110010" | "11010010" | "11110010" => --
mnemonic_v := MN_JBB;
multi_cycle_v := true;
 
-- Mnemonic JF ----------------------------------------------------------
when "10110110" | -- JF0 addr
"01110110" => -- JF1 addr
mnemonic_v := MN_JF;
multi_cycle_v := true;
 
-- Mnemonic JT ----------------------------------------------------------
when "00100110" | -- JNT0 addr
"01000110" | -- JNT1 addr
"00110110" | -- JT0 addr
"01010110" => -- JT1 addr
mnemonic_v := MN_JT;
multi_cycle_v := true;
 
-- Mnemonic MOV_A_PSW ---------------------------------------------------
when "11000111" => -- MOV A, PSW
mnemonic_v := MN_MOV_A_PSW;
 
-- Mnemonic MOV_PSW_A ---------------------------------------------------
when "11010111" => -- MOV PSW, A
mnemonic_v := MN_MOV_PSW_A;
 
-- Mnemonic MOVP - extend basic set -------------------------------------
when "11100011" => -- MOVP3 A, @ A
mnemonic_v := MN_MOVP;
multi_cycle_v := true;
 
-- Mnemonic ORL_EXT -----------------------------------------------------
when "10001001" | "10001010" => -- ORL Pp, data
mnemonic_v := MN_ORL_EXT;
multi_cycle_v := true;
 
-- Mnemonic RETR --------------------------------------------------------
when "10010011" => -- RETR
mnemonic_v := MN_RETR;
multi_cycle_v := true;
 
-- Mnemonic SEL_RB ------------------------------------------------------
when "11000101" | -- SEL RB0
"11010101" => -- SEL RB1
mnemonic_v := MN_SEL_RB;
 
when others =>
mnemonic_v := MN_INVALID;
 
end case;
 
if mnemonic_v = MN_INVALID then
result_v := decode_basic_opcode_f(opcode);
else
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
end if;
 
return result_v;
end;
 
 
-----------------------------------------------------------------------------
-- Specific MCS-48 opcodes
--
410,9 → 478,8
multi_cycle_v := false;
 
case opcode is
-- Mnemonic ANL_EXT -----------------------------------------------------
when "10011000" | -- ANL BUS, data
"10011001" | "10011010" => -- ANL PP, data
-- Mnemonic ANL_EXT - extend common set ---------------------------------
when "10011000" => -- ANL BUS, data
mnemonic_v := MN_ANL_EXT;
multi_cycle_v := true;
 
436,15 → 503,13
mnemonic_v := MN_MOVX;
multi_cycle_v := true;
 
-- Mnemonic ORL_EXT -----------------------------------------------------
when "10001000" | -- ORL BUS, data
"10001001" | "10001010" => -- ORL Pp, data
-- Mnemonic ORL_EXT - extend common set ---------------------------------
when "10001000" => -- ORL BUS, data
mnemonic_v := MN_ORL_EXT;
multi_cycle_v := true;
 
-- Mnemonic OUTL_EXT ----------------------------------------------------
when "00111001" | "00111010" | -- OUTL Pp, A
"00000010" => -- OUTL BUS, A
-- Mnemonic OUTL_EXT - extend basic set ---------------------------------
when "00000010" => -- OUTL BUS, A
mnemonic_v := MN_OUTL_EXT;
multi_cycle_v := true;
 
459,7 → 524,7
end case;
 
if mnemonic_v = MN_INVALID then
result_v := decode_common_opcode_f(opcode);
result_v := decode_common_mcs48_upi41_opcode_f(opcode);
else
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
482,11 → 547,6
multi_cycle_v := false;
 
case opcode is
-- Mnemonic ANL_EXT -----------------------------------------------------
when "10011001" | "10011010" => -- ANL PP, data
mnemonic_v := MN_ANL_EXT;
multi_cycle_v := true;
 
-- Mnemonic IN_DBB ------------------------------------------------------
when "00100010" => -- IN A, DBB
mnemonic_v := MN_IN_DBB;
501,20 → 561,10
mnemonic_v := MN_JOBF;
multi_cycle_v := true;
 
-- Mnemonic ORL_EXT -----------------------------------------------------
when "10001001" | "10001010" => -- ORL Pp, data
mnemonic_v := MN_ORL_EXT;
multi_cycle_v := true;
 
-- Mnemonic OUT_DBB -----------------------------------------------------
when "00000010" => -- OUT DBB, A
mnemonic_v := MN_OUT_DBB;
 
-- Mnemonic OUTL_EXT ----------------------------------------------------
when "00111001" | "00111010" => -- OUTL Pp, A
mnemonic_v := MN_OUTL_EXT;
multi_cycle_v := true;
 
when others =>
mnemonic_v := MN_INVALID;
 
521,7 → 571,7
end case;
 
if mnemonic_v = MN_INVALID then
result_v := decode_common_opcode_f(opcode);
result_v := decode_common_mcs48_upi41_opcode_f(opcode);
else
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
568,4 → 618,108
return result_v;
end;
 
-----------------------------------------------------------------------------
-- Specific MCS-21 opcodes
--
function decode_mcs21_opcode_f(opcode : in word_t) return
mnemonic_rec_t is
variable mnemonic_v : mnemonic_t;
variable multi_cycle_v : boolean;
variable result_v : mnemonic_rec_t;
begin
-- default assignment
multi_cycle_v := false;
 
case opcode is
-- Mnemonic IN_P0 -------------------------------------------------------
when "00001000" => -- IN A, P0
mnemonic_v := MN_IN_P0;
multi_cycle_v := true;
 
-- Mnemonic JT ----------------------------------------------------------
when "01000110" | -- JNT1 addr
"01010110" => -- JT1 addr
mnemonic_v := MN_JT;
multi_cycle_v := true;
 
-- Mnemonic OUTL_P0 -----------------------------------------------------
when "10010000" => -- OUTL P0, A
mnemonic_v := MN_OUTL_P0;
multi_cycle_v := true;
 
when others =>
mnemonic_v := MN_INVALID;
 
end case;
 
if mnemonic_v = MN_INVALID then
result_v := decode_basic_opcode_f(opcode);
else
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
end if;
 
return result_v;
end;
 
-----------------------------------------------------------------------------
-- Specific MCS-22 opcodes
--
function decode_mcs22_opcode_f(opcode : in word_t) return
mnemonic_rec_t is
variable mnemonic_v : mnemonic_t;
variable multi_cycle_v : boolean;
variable result_v : mnemonic_rec_t;
begin
-- default assignment
multi_cycle_v := false;
 
case opcode is
-- Mnemonic DIS_EN_I ----------------------------------------------------
when "00010101" | -- DIS I
"00000101" => -- EN I
mnemonic_v := MN_DIS_EN_I;
 
-- Mnemonic DIS_EN_TCNTI ------------------------------------------------
when "00110101" | -- DIS TCNTI
"00100101" => -- EN TCNTI
mnemonic_v := MN_DIS_EN_TCNTI;
 
-- Mnemonic JT ----------------------------------------------------------
when "00100110" | -- JNT0 addr
"00110110" => -- JT0 addr
mnemonic_v := MN_JT;
multi_cycle_v := true;
 
-- Mnemonic RAD ---------------------------------------------------------
when "10000000" => -- RAD
mnemonic_v := MN_RAD;
multi_cycle_v := true;
 
-- Mnemonic RETI --------------------------------------------------------
when "10010011" => -- RETI
mnemonic_v := MN_RETI;
multi_cycle_v := true;
 
-- Mnemonic SEL_AN ------------------------------------------------------
when "10000101" | -- SEL AN0
"10010101" => -- SEL AN1
mnemonic_v := MN_SEL_AN;
multi_cycle_v := true;
 
when others =>
mnemonic_v := MN_INVALID;
 
end case;
 
if mnemonic_v = MN_INVALID then
result_v := decode_mcs21_opcode_f(opcode);
else
result_v.mnemonic := mnemonic_v;
result_v.multi_cycle := multi_cycle_v;
end if;
 
return result_v;
end;
 
end t48_decoder_pack;
/branches/wip_t2x/rtl/vhdl/system/t48_system_comp_pack-p.vhd
318,4 → 318,38
);
end component;
 
component t8021_notri
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 3 downto 0);
p2_o : out std_logic_vector( 3 downto 0);
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p0_i : in std_logic_vector( 7 downto 0);
p0_o : out std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end component;
 
component t8021
port (
xtal_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_b : inout std_logic_vector( 3 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
p0_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end component;
 
end t48_system_comp_pack;
/branches/wip_t2x/rtl/vhdl/system/t8021-c.vhd
0,0 → 1,21
-------------------------------------------------------------------------------
--
-- T8021 Microcontroller System
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
configuration t8021_struct_c0 of t8021 is
 
for struct
 
for t8021_notri_b : t8021_notri
use configuration work.t8021_notri_struct_c0;
end for;
 
end for;
 
end t8021_struct_c0;
/branches/wip_t2x/rtl/vhdl/system/t8021.vhd
0,0 → 1,147
-------------------------------------------------------------------------------
--
-- T8021 Microcontroller System
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity t8021 is
 
port (
xtal_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_b : inout std_logic_vector( 3 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
p0_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
 
end t8021;
 
 
library ieee;
use ieee.numeric_std.all;
 
use work.t48_system_comp_pack.t8021_notri;
 
architecture struct of t8021 is
 
signal p2_s : std_logic_vector( 3 downto 0);
signal p1_s : std_logic_vector( 7 downto 0);
signal p0_s : std_logic_vector( 7 downto 0);
 
signal vdd_s : std_logic;
 
begin
 
vdd_s <= '1';
 
t8021_notri_b : t8021_notri
generic map (
-- we don't need explicit gating of input ports
-- this is done implicitely by the bidirectional pads
gate_port_input_g => 0
)
 
port map (
xtal_i => xtal_i,
xtal_en_i => vdd_s,
reset_i => reset_i,
ale_o => ale_o,
t1_i => t1_i,
p2_i => p2_b,
p2_o => p2_s,
p1_i => p1_b,
p1_o => p1_s,
p0_i => p0_b,
p0_o => p0_s,
prog_n_o => prog_n_o
);
 
-----------------------------------------------------------------------------
-- Process bidirs
--
-- Purpose:
-- Assign bidirectional signals.
--
bidirs: process (p0_b, p0_s,
p1_b, p1_s,
p2_b, p2_s)
 
function port_bidir_f(port_value : in std_logic_vector;
low_imp : in std_logic) return std_logic_vector is
variable result_v : std_logic_vector(port_value'range);
begin
for idx in port_value'high downto port_value'low loop
if low_imp = '1' then
result_v(idx) := port_value(idx);
elsif port_value(idx) = '0' then
result_v(idx) := '0';
else
result_v(idx) := 'Z';
end if;
end loop;
 
return result_v;
end;
 
begin
-- Port 0 -----------------------------------------------------------------
p0_b <= port_bidir_f(port_value => p0_s,
low_imp => '0');
 
-- Port 1 -----------------------------------------------------------------
p1_b <= port_bidir_f(port_value => p1_s,
low_imp => '0');
 
-- Port 2 -----------------------------------------------------------------
p2_b <= port_bidir_f(port_value => p2_s,
low_imp => '0');
 
end process bidirs;
--
-----------------------------------------------------------------------------
 
 
end struct;
/branches/wip_t2x/rtl/vhdl/system/t8021_notri-c.vhd
0,0 → 1,29
-------------------------------------------------------------------------------
--
-- T8021 Microcontroller System
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
configuration t8021_notri_struct_c0 of t8021_notri is
 
for struct
 
for rom_1k_b : t48_rom
use configuration work.t48_rom_lpm_c0;
end for;
 
for ram_64_b : generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
 
for t21_core_b : t21_core
use configuration work.t21_core_struct_c0;
end for;
 
end for;
 
end t8021_notri_struct_c0;
/branches/wip_t2x/rtl/vhdl/system/t8021_notri.vhd
0,0 → 1,191
-------------------------------------------------------------------------------
--
-- T8021 Microcontroller System
-- 8021 toplevel without tri-states
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity t8021_notri is
 
generic (
gate_port_input_g : integer := 1
);
 
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 3 downto 0);
p2_o : out std_logic_vector( 3 downto 0);
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p0_i : in std_logic_vector( 7 downto 0);
p0_o : out std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
 
end t8021_notri;
 
 
library ieee;
use ieee.numeric_std.all;
 
use work.t48_core_comp_pack.t21_core;
use work.t48_core_comp_pack.t48_rom;
use work.t48_core_comp_pack.generic_ram_ena;
 
architecture struct of t8021_notri is
 
-- Address width of internal ROM
constant rom_addr_width_c : natural := 10;
 
signal reset_s : std_logic;
 
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_addr_s : std_logic_vector(11 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
 
signal p0_in_s,
p0_out_s : std_logic_vector( 7 downto 0);
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 3 downto 0);
 
signal vdd_s : std_logic;
 
begin
 
vdd_s <= '1';
 
reset_s <= not reset_i;
 
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
 
 
t21_core_b : t21_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
reset_i => reset_s,
ale_o => ale_o,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p1_i => p1_in_s,
p1_o => p1_out_s,
p0_i => p0_in_s,
p0_o => p0_out_s,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
 
 
-----------------------------------------------------------------------------
-- Gate port 0, 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p0_in_s <= p0_i and p0_out_s;
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
 
pass_ports: if gate_port_input_g = 0 generate
p0_in_s <= p0_i;
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
 
p0_o <= p0_out_s;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
 
 
rom_1k_b : t48_rom
port map (
clk_i => xtal_i,
rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0),
rom_data_o => pmem_data_s
);
 
ram_64_b : generic_ram_ena
generic map (
addr_width_g => 6,
data_width_g => 8
)
port map (
clk_i => xtal_i,
a_i => dmem_addr_s(5 downto 0),
we_i => dmem_we_s,
ena_i => vdd_s,
d_i => dmem_data_to_s,
d_o => dmem_data_from_s
);
 
end struct;
/branches/wip_t2x/rtl/vhdl/t21_core-c.vhd
0,0 → 1,61
-------------------------------------------------------------------------------
--
-- T21 Microcontroller Core
--
-------------------------------------------------------------------------------
 
configuration t21_core_struct_c0 of t21_core is
 
for struct
 
for alu_b : t48_alu
use configuration work.t48_alu_rtl_c0;
end for;
 
for bus_mux_b : t48_bus_mux
use configuration work.t48_bus_mux_rtl_c0;
end for;
 
for clock_ctrl_b : t48_clock_ctrl
use configuration work.t48_clock_ctrl_rtl_c0;
end for;
 
for cond_branch_b : t48_cond_branch
use configuration work.t48_cond_branch_rtl_c0;
end for;
 
for decoder_b : t48_decoder
use configuration work.t48_decoder_rtl_c0;
end for;
 
for dmem_ctrl_b : t48_dmem_ctrl
use configuration work.t48_dmem_ctrl_rtl_c0;
end for;
 
for timer_b : t48_timer
use configuration work.t48_timer_rtl_c0;
end for;
 
for p0_b : t48_p1
use configuration work.t48_p1_rtl_c0;
end for;
 
for p1_b : t48_p1
use configuration work.t48_p1_rtl_c0;
end for;
 
for p2_b : t48_p2
use configuration work.t48_p2_rtl_c0;
end for;
 
for pmem_ctrl_b : t48_pmem_ctrl
use configuration work.t48_pmem_ctrl_rtl_c0;
end for;
 
for psw_b : t48_psw
use configuration work.t48_psw_rtl_c0;
end for;
 
end for;
 
end t21_core_struct_c0;
/branches/wip_t2x/rtl/vhdl/t21_core.vhd
0,0 → 1,582
-------------------------------------------------------------------------------
--
-- T21 Microcontroller Core
--
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-- Limitations :
-- =============
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity t21_core is
 
generic (
-- divide XTAL1 by 3 to derive Clock States
xtal_div_3_g : integer := 1;
-- store mnemonic in flip-flops (registered-out)
register_mnemonic_g : integer := 1;
-- state in which T1 is sampled (3 or 4)
sample_t1_state_g : integer := 4
);
 
port (
-- T21 Interface ----------------------------------------------------------
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 3 downto 0);
p2_o : out std_logic_vector( 3 downto 0);
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p0_i : in std_logic_vector( 7 downto 0);
p0_o : out std_logic_vector( 7 downto 0);
prog_n_o : out std_logic;
-- Core Interface ---------------------------------------------------------
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
 
end t21_core;
 
 
use work.t48_alu_pack.alu_op_t;
use work.t48_cond_branch_pack.branch_conditions_t;
use work.t48_cond_branch_pack.comp_value_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_comp_pack.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.word_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.to_stdLogic;
use work.t48_pack.to_boolean;
 
architecture struct of t21_core is
 
signal t48_data_s : word_t;
 
signal xtal_en_s : boolean;
signal en_clk_s : boolean;
 
signal t0_s, t1_s : std_logic;
 
-- ALU signals
signal alu_data_s : word_t;
signal alu_write_accu_s : boolean;
signal alu_write_shadow_s : boolean;
signal alu_write_temp_reg_s : boolean;
signal alu_read_alu_s : boolean;
signal alu_carry_s : std_logic;
signal alu_aux_carry_s : std_logic;
signal alu_op_s : alu_op_t;
signal alu_use_carry_s : boolean;
signal alu_da_high_s : boolean;
signal alu_da_overflow_s : boolean;
signal alu_accu_low_s : boolean;
signal alu_p06_temp_reg_s : boolean;
signal alu_p60_temp_reg_s : boolean;
 
-- Clock Controller signals
signal clk_multi_cycle_s : boolean;
signal clk_assert_psen_s : boolean;
signal clk_assert_prog_s : boolean;
signal clk_assert_rd_s : boolean;
signal clk_assert_wr_s : boolean;
signal clk_mstate_s : mstate_t;
signal clk_second_cycle_s : boolean;
signal prog_s : boolean;
signal ale_s : boolean;
signal xtal3_s : boolean;
 
-- Conditional Branch Logic signals
signal cnd_compute_take_s : boolean;
signal cnd_branch_cond_s : branch_conditions_t;
signal cnd_take_branch_s : boolean;
signal cnd_comp_value_s : comp_value_t;
signal cnd_f1_s : std_logic;
signal cnd_tf_s : std_logic;
 
-- Data Memory Controller signals
signal dm_write_dmem_addr_s : boolean;
signal dm_write_dmem_s : boolean;
signal dm_read_dmem_s : boolean;
signal dm_addr_type_s : dmem_addr_ident_t;
signal dm_data_s : word_t;
 
-- Decoder signals
signal dec_data_s : word_t;
 
-- Port 0 signals
signal p0_write_p0_s : boolean;
signal p0_read_p0_s : boolean;
signal p0_data_s : word_t;
 
-- Port 1 signals
signal p1_write_p1_s : boolean;
signal p1_read_p1_s : boolean;
signal p1_data_s : word_t;
 
-- Port 2 signals
signal p2_write_p2_s : boolean;
signal p2_write_exp_s : boolean;
signal p2_read_p2_s : boolean;
signal p2_read_exp_s : boolean;
signal p2_output_pch_s : boolean;
signal p2_data_s : word_t;
signal p2_in_s,
p2_out_s : word_t;
 
-- Program Memory Controller signals
signal pm_write_pcl_s : boolean;
signal pm_read_pcl_s : boolean;
signal pm_write_pch_s : boolean;
signal pm_read_pch_s : boolean;
signal pm_read_pmem_s : boolean;
signal pm_inc_pc_s : boolean;
signal pm_write_pmem_addr_s : boolean;
signal pm_data_s : word_t;
signal pm_addr_type_s : pmem_addr_ident_t;
signal pmem_addr_s : pmem_addr_t;
 
-- PSW signals
signal psw_read_psw_s : boolean;
signal psw_read_sp_s : boolean;
signal psw_write_psw_s : boolean;
signal psw_write_sp_s : boolean;
signal psw_carry_s : std_logic;
signal psw_aux_carry_s : std_logic;
signal psw_f0_s : std_logic;
signal psw_bs_s : std_logic;
signal psw_special_data_s : std_logic;
signal psw_inc_stackp_s : boolean;
signal psw_dec_stackp_s : boolean;
signal psw_write_carry_s : boolean;
signal psw_write_aux_carry_s : boolean;
signal psw_write_f0_s : boolean;
signal psw_write_bs_s : boolean;
signal psw_data_s : word_t;
 
-- Timer signals
signal tim_overflow_s : boolean;
signal tim_of_s : std_logic;
signal tim_read_timer_s : boolean;
signal tim_write_timer_s : boolean;
signal tim_start_t_s : boolean;
signal tim_start_cnt_s : boolean;
signal tim_stop_tcnt_s : boolean;
signal tim_data_s : word_t;
 
signal xtal_mcs2x_q : boolean;
 
signal false_s : boolean;
signal vdd_s : std_logic;
signal gnd_s : std_logic;
 
begin
 
false_s <= false;
vdd_s <= '1';
gnd_s <= '0';
 
en_clk_s <= to_boolean(en_clk_i);
 
t0_s <= '0';
t1_s <=
-- pragma translate_off
To_X01Z
-- pragma translate_on
(t1_i);
 
-----------------------------------------------------------------------------
-- MCS-2x clocking
-- The documents say the MCS-2x has 10 machine cycles instead of 5 in MCS-48.
-- Divide incoming xtal_en_i by 2 for compatibility.
-----------------------------------------------------------------------------
process (reset_i, xtal_i)
begin
if reset_i = res_active_c then
xtal_mcs2x_q <= false;
elsif xtal_i'event and xtal_i = clk_active_c then
if xtal_en_i = '1' then
xtal_mcs2x_q <= not xtal_mcs2x_q;
end if;
end if;
end process;
--
xtal_en_s <= to_boolean(xtal_en_i) and xtal_mcs2x_q;
 
 
alu_b : t48_alu
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => alu_data_s,
write_accu_i => alu_write_accu_s,
write_shadow_i => alu_write_shadow_s,
write_temp_reg_i => alu_write_temp_reg_s,
read_alu_i => alu_read_alu_s,
carry_i => psw_carry_s,
carry_o => alu_carry_s,
aux_carry_o => alu_aux_carry_s,
alu_op_i => alu_op_s,
use_carry_i => alu_use_carry_s,
da_high_i => alu_da_high_s,
da_overflow_o => alu_da_overflow_s,
accu_low_i => alu_accu_low_s,
p06_temp_reg_i => alu_p06_temp_reg_s,
p60_temp_reg_i => alu_p60_temp_reg_s
);
 
bus_mux_b : t48_bus_mux
port map (
alu_data_i => alu_data_s,
dec_data_i => dec_data_s,
dm_data_i => dm_data_s,
pm_data_i => pm_data_s,
p0_data_i => p0_data_s,
p1_data_i => p1_data_s,
p2_data_i => p2_data_s,
psw_data_i => psw_data_s,
tim_data_i => tim_data_s,
data_o => t48_data_s
);
 
clock_ctrl_b : t48_clock_ctrl
generic map (
xtal_div_3_g => xtal_div_3_g
)
port map (
clk_i => clk_i,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal3_o => xtal3_s,
t0_o => open,
multi_cycle_i => clk_multi_cycle_s,
assert_psen_i => clk_assert_psen_s,
assert_prog_i => clk_assert_prog_s,
assert_rd_i => clk_assert_rd_s,
assert_wr_i => clk_assert_wr_s,
mstate_o => clk_mstate_s,
second_cycle_o => clk_second_cycle_s,
ale_o => ale_s,
psen_o => open,
prog_o => prog_s,
rd_o => open,
wr_o => open
);
 
cond_branch_b : t48_cond_branch
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
compute_take_i => cnd_compute_take_s,
branch_cond_i => cnd_branch_cond_s,
take_branch_o => cnd_take_branch_s,
accu_i => alu_data_s,
t0_i => t0_s,
t1_i => t1_s,
int_n_i => vdd_s,
f0_i => psw_f0_s,
f1_i => cnd_f1_s,
tf_i => cnd_tf_s,
carry_i => psw_carry_s,
comp_value_i => cnd_comp_value_s
);
 
decoder_b : t48_decoder
generic map (
register_mnemonic_g => register_mnemonic_g,
is_mcs2x_g => 1,
is_mcs2x_type_2_g => 0
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
ea_i => gnd_s,
ale_i => ale_s,
int_n_i => vdd_s,
t0_dir_o => open,
data_i => t48_data_s,
data_o => dec_data_s,
alu_write_accu_o => alu_write_accu_s,
alu_write_shadow_o => alu_write_shadow_s,
alu_write_temp_reg_o => alu_write_temp_reg_s,
alu_read_alu_o => alu_read_alu_s,
bus_write_bus_o => open,
bus_read_bus_o => open,
dm_write_dmem_addr_o => dm_write_dmem_addr_s,
dm_write_dmem_o => dm_write_dmem_s,
dm_read_dmem_o => dm_read_dmem_s,
p0_write_p0_o => p0_write_p0_s,
p0_read_p0_o => p0_read_p0_s,
p1_write_p1_o => p1_write_p1_s,
p1_read_p1_o => p1_read_p1_s,
pm_write_pcl_o => pm_write_pcl_s,
p2_write_p2_o => p2_write_p2_s,
p2_write_exp_o => p2_write_exp_s,
p2_read_p2_o => p2_read_p2_s,
pm_read_pcl_o => pm_read_pcl_s,
pm_write_pch_o => pm_write_pch_s,
pm_read_pch_o => pm_read_pch_s,
pm_read_pmem_o => pm_read_pmem_s,
psw_read_psw_o => psw_read_psw_s,
psw_read_sp_o => psw_read_sp_s,
psw_write_psw_o => psw_write_psw_s,
psw_write_sp_o => psw_write_sp_s,
alu_carry_i => alu_carry_s,
alu_op_o => alu_op_s,
alu_use_carry_o => alu_use_carry_s,
alu_da_high_o => alu_da_high_s,
alu_da_overflow_i => alu_da_overflow_s,
alu_accu_low_o => alu_accu_low_s,
alu_p06_temp_reg_o => alu_p06_temp_reg_s,
alu_p60_temp_reg_o => alu_p60_temp_reg_s,
bus_output_pcl_o => open,
bus_bidir_bus_o => open,
clk_multi_cycle_o => clk_multi_cycle_s,
clk_assert_psen_o => clk_assert_psen_s,
clk_assert_prog_o => clk_assert_prog_s,
clk_assert_rd_o => clk_assert_rd_s,
clk_assert_wr_o => clk_assert_wr_s,
clk_mstate_i => clk_mstate_s,
clk_second_cycle_i => clk_second_cycle_s,
cnd_compute_take_o => cnd_compute_take_s,
cnd_branch_cond_o => cnd_branch_cond_s,
cnd_take_branch_i => cnd_take_branch_s,
cnd_comp_value_o => cnd_comp_value_s,
cnd_f1_o => cnd_f1_s,
cnd_tf_o => cnd_tf_s,
dm_addr_type_o => dm_addr_type_s,
tim_read_timer_o => tim_read_timer_s,
tim_write_timer_o => tim_write_timer_s,
tim_start_t_o => tim_start_t_s,
tim_start_cnt_o => tim_start_cnt_s,
tim_stop_tcnt_o => tim_stop_tcnt_s,
p1_read_reg_o => open,
p2_read_reg_o => open,
p2_read_exp_o => p2_read_exp_s,
p2_output_pch_o => p2_output_pch_s,
pm_inc_pc_o => pm_inc_pc_s,
pm_write_pmem_addr_o => pm_write_pmem_addr_s,
pm_addr_type_o => pm_addr_type_s,
psw_special_data_o => psw_special_data_s,
psw_carry_i => psw_carry_s,
psw_aux_carry_i => psw_aux_carry_s,
psw_f0_i => psw_f0_s,
psw_inc_stackp_o => psw_inc_stackp_s,
psw_dec_stackp_o => psw_dec_stackp_s,
psw_write_carry_o => psw_write_carry_s,
psw_write_aux_carry_o => psw_write_aux_carry_s,
psw_write_f0_o => psw_write_f0_s,
psw_write_bs_o => psw_write_bs_s,
tim_overflow_i => tim_overflow_s
);
 
dmem_ctrl_b : t48_dmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
write_dmem_addr_i => dm_write_dmem_addr_s,
write_dmem_i => dm_write_dmem_s,
read_dmem_i => dm_read_dmem_s,
addr_type_i => dm_addr_type_s,
bank_select_i => psw_bs_s,
data_o => dm_data_s,
dmem_data_i => dmem_data_i,
dmem_addr_o => dmem_addr_o,
dmem_we_o => dmem_we_o,
dmem_data_o => dmem_data_o
);
 
timer_b : t48_timer
generic map (
sample_t1_state_g => sample_t1_state_g
)
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
t1_i => t1_s,
clk_mstate_i => clk_mstate_s,
data_i => t48_data_s,
data_o => tim_data_s,
read_timer_i => tim_read_timer_s,
write_timer_i => tim_write_timer_s,
start_t_i => tim_start_t_s,
start_cnt_i => tim_start_cnt_s,
stop_tcnt_i => tim_stop_tcnt_s,
overflow_o => tim_of_s
);
 
tim_overflow_s <= to_boolean(tim_of_s);
 
p0_b : t48_p1
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p0_data_s,
write_p1_i => p0_write_p0_s,
read_p1_i => p0_read_p0_s,
read_reg_i => false_s, -- MCS21x always reads pins
p1_i => p0_i,
p1_o => p0_o,
p1_low_imp_o => open
);
 
p1_b : t48_p1
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => p1_data_s,
write_p1_i => p1_write_p1_s,
read_p1_i => p1_read_p1_s,
read_reg_i => false_s, -- MCS21x always reads pins
p1_i => p1_i,
p1_o => p1_o,
p1_low_imp_o => open
);
 
p2_b : t48_p2
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
data_i => t48_data_s,
data_o => p2_data_s,
write_p2_i => p2_write_p2_s,
write_exp_i => p2_write_exp_s,
read_p2_i => p2_read_p2_s,
read_reg_i => false_s, -- MCS21x always reads pins
read_exp_i => p2_read_exp_s,
output_pch_i => p2_output_pch_s,
pch_i => pmem_addr_s(11 downto 8),
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => open,
p2h_low_imp_o => open
);
 
p2_in_s <= "0000" & p2_i;
p2_o <= p2_out_s(3 downto 0);
 
pmem_ctrl_b : t48_pmem_ctrl
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => pm_data_s,
write_pcl_i => pm_write_pcl_s,
read_pcl_i => pm_read_pcl_s,
write_pch_i => pm_write_pch_s,
read_pch_i => pm_read_pch_s,
inc_pc_i => pm_inc_pc_s,
write_pmem_addr_i => pm_write_pmem_addr_s,
addr_type_i => pm_addr_type_s,
read_pmem_i => pm_read_pmem_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_i
);
 
psw_b : t48_psw
port map (
clk_i => clk_i,
res_i => reset_i,
en_clk_i => en_clk_s,
data_i => t48_data_s,
data_o => psw_data_s,
read_psw_i => psw_read_psw_s,
read_sp_i => psw_read_sp_s,
write_psw_i => psw_write_psw_s,
write_sp_i => psw_write_sp_s,
special_data_i => psw_special_data_s,
inc_stackp_i => psw_inc_stackp_s,
dec_stackp_i => psw_dec_stackp_s,
write_carry_i => psw_write_carry_s,
write_aux_carry_i => psw_write_aux_carry_s,
write_f0_i => psw_write_f0_s,
write_bs_i => psw_write_bs_s,
carry_o => psw_carry_s,
aux_carry_i => alu_aux_carry_s,
aux_carry_o => psw_aux_carry_s,
f0_o => psw_f0_s,
bs_o => psw_bs_s
);
 
 
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
ale_o <= to_stdLogic(ale_s);
prog_n_o <= to_stdLogic(not prog_s);
xtal3_o <= to_stdLogic(xtal3_s);
pmem_addr_o <= pmem_addr_s;
 
end struct;
/branches/wip_t2x/rtl/vhdl/t48_comp_pack-p.vhd
22,6 → 22,7
use work.t48_pack.mstate_t;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
use work.t48_pack.bus_idle_level_c;
 
package t48_comp_pack is
 
51,15 → 52,17
 
component t48_bus_mux
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
alu_data_i : in word_t := (others => bus_idle_level_c);
bus_data_i : in word_t := (others => bus_idle_level_c);
dec_data_i : in word_t := (others => bus_idle_level_c);
dm_data_i : in word_t := (others => bus_idle_level_c);
pm_data_i : in word_t := (others => bus_idle_level_c);
p0_data_i : in word_t := (others => bus_idle_level_c);
p1_data_i : in word_t := (others => bus_idle_level_c);
p2_data_i : in word_t := (others => bus_idle_level_c);
psw_data_i : in word_t := (others => bus_idle_level_c);
tim_data_i : in word_t := (others => bus_idle_level_c);
adc_data_i : in word_t := (others => bus_idle_level_c);
data_o : out word_t
);
end component;
66,7 → 69,7
 
component t48_clock_ctrl
generic (
xtal_div_3_g : integer := 1
xtal_div_3_g : integer := 1
);
port (
clk_i : in std_logic;
175,7 → 178,9
generic (
register_mnemonic_g : integer := 1;
is_upi_g : integer := 0;
is_upi_type_a_g : integer := 0
is_upi_type_a_g : integer := 0;
is_mcs2x_g : integer := 0;
is_mcs2x_type_2_g : integer := 0
);
port (
clk_i : in std_logic;
204,6 → 209,8
dm_write_dmem_addr_o : out boolean;
dm_write_dmem_o : out boolean;
dm_read_dmem_o : out boolean;
p0_write_p0_o : out boolean; -- MCS2x
p0_read_p0_o : out boolean; -- MCS2x
p1_write_p1_o : out boolean;
p1_read_p1_o : out boolean;
p2_write_p2_o : out boolean;
264,7 → 271,10
psw_write_aux_carry_o : out boolean;
psw_write_f0_o : out boolean;
psw_write_bs_o : out boolean;
tim_overflow_i : in boolean
tim_overflow_i : in boolean;
adc_sel_an0_o : out boolean;
adc_sel_an1_o : out boolean;
adc_read_adc_o : out boolean
);
end component;
 
/branches/wip_t2x/rtl/vhdl/t48_core_comp_pack-p.vhd
103,6 → 103,38
);
end component;
 
component t21_core
generic (
xtal_div_3_g : integer := 1;
register_mnemonic_g : integer := 1;
sample_t1_state_g : integer := 4
);
 
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_i : in std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 3 downto 0);
p2_o : out std_logic_vector( 3 downto 0);
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p0_i : in std_logic_vector( 7 downto 0);
p0_o : out std_logic_vector( 7 downto 0);
prog_n_o : out std_logic;
clk_i : in std_logic;
en_clk_i : in std_logic;
xtal3_o : out std_logic;
dmem_addr_o : out std_logic_vector( 7 downto 0);
dmem_we_o : out std_logic;
dmem_data_i : in std_logic_vector( 7 downto 0);
dmem_data_o : out std_logic_vector( 7 downto 0);
pmem_addr_o : out std_logic_vector(11 downto 0);
pmem_data_i : in std_logic_vector( 7 downto 0)
);
end component;
 
component generic_ram_ena
generic (
addr_width_g : integer := 10;
/branches/wip_t2x/sim/rtl_sim/Makefile.ghdl
34,6 → 34,15
##############################################################################
# The analyze targets
#
t21_core_struct_c0 = $(LIB_WORK)/t21_core-c.o
t21_core = $(LIB_WORK)/t21_core.o
t8021_notri_struct_c0 = $(LIB_WORK)/t8021_notri-c.o
t8021_notri = $(LIB_WORK)/t8021_notri.o
t8021_struct_c0 = $(LIB_WORK)/t8021-c.o
t8021 = $(LIB_WORK)/t8021.o
tb_t8021_behav_c0 = $(LIB_WORK)/tb_t8021-c.o
tb_t8021 = $(LIB_WORK)/tb_t8021.o
 
upi41_db_bus_rtl_c0 = $(LIB_WORK)/upi41_db_bus-c.o
upi41_db_bus = $(LIB_WORK)/upi41_db_bus.o
upi41_core_struct_c0 = $(LIB_WORK)/upi41_core-c.o
160,6 → 169,7
tb_t8041_elab = tb_t8041_behav_c0
tb_t8041a_elab = tb_t8041a_behav_c0
tb_t8042ah_elab = tb_t8042ah_behav_c0
tb_t8021_elab = tb_t8021_behav_c0
#
##############################################################################
 
191,10 → 201,14
$(tb_t8042ah_elab) : $(tb_t8042ah_behav_c0)
$(ELABORATE) tb_t8042ah_behav_c0
 
$(tb_t8021_elab) : $(tb_t8021_behav_c0)
$(ELABORATE) tb_t8021_behav_c0
 
.PHONY: elaborate
elaborate: $(LIB_WORK) $(tb_elab) $(tb_t8048_elab) $(tb_t8039_elab) \
$(tb_t8048_t8243_elab) $(tb_t8243_elab) \
$(tb_t8041_elab) $(tb_t8041a_elab) $(tb_t8042ah_elab)
$(tb_t8041_elab) $(tb_t8041a_elab) $(tb_t8042ah_elab) \
$(tb_t8021_elab)
#
##############################################################################
 
/branches/wip_t2x/sim/rtl_sim/Makefile.hier
582,3 → 582,69
$(t48_tb_pack) \
$(tb_t8042ah)
$(ANALYZE) $<
 
$(t21_core) : $(RTL_DIR)/t21_core.vhd \
$(decoder_pack) \
$(t48_comp_pack) \
$(pmem_ctrl_pack) \
$(dmem_ctrl_pack) \
$(cond_branch_pack) \
$(t48_pack) \
$(alu_pack)
$(ANALYZE) $<
 
$(t21_core_struct_c0) : $(RTL_DIR)/t21_core-c.vhd \
$(psw_rtl_c0) \
$(pmem_ctrl_rtl_c0) \
$(p2_rtl_c0) \
$(p1_rtl_c0) \
$(timer_rtl_c0) \
$(dmem_ctrl_rtl_c0) \
$(decoder_rtl_c0) \
$(cond_branch_rtl_c0) \
$(clock_ctrl_rtl_c0) \
$(bus_mux_rtl_c0) \
$(alu_rtl_c0) \
$(decoder_pack) \
$(t48_comp_pack) \
$(pmem_ctrl_pack) \
$(dmem_ctrl_pack) \
$(cond_branch_pack) \
$(t48_pack) \
$(alu_pack) \
$(t21_core-struct) \
$(t21_core)
$(ANALYZE) $<
 
$(t8021_notri) : $(RTL_DIR)/system/t8021_notri.vhd \
$(t48_core_comp_pack)
$(ANALYZE) $<
 
$(t8021_notri_struct_c0) : $(RTL_DIR)/system/t8021_notri-c.vhd \
$(t21_core_struct_c0) \
$(generic_ram_ena_rtl_c0) \
$(t48_rom_lpm_c0) \
$(t48_core_comp_pack) \
$(t8021_notri)
$(ANALYZE) $<
 
$(t8021) : $(RTL_DIR)/system/t8021.vhd \
$(t48_system_comp_pack)
$(ANALYZE) $<
 
$(t8021_struct_c0) : $(RTL_DIR)/system/t8021-c.vhd \
$(t8021_notri_struct_c0) \
$(t8021)
$(ANALYZE) $<
 
$(tb_t8021) : $(BENCH_DIR)/tb_t8021.vhd \
$(t48_tb_pack) \
$(t48_core_comp_pack) \
$(t48_system_comp_pack)
$(ANALYZE) $<
 
$(tb_t8021_behav_c0) : $(BENCH_DIR)/tb_t8021-c.vhd \
$(t8021_struct_c0) \
$(t48_tb_pack) \
$(tb_t8021)
$(ANALYZE) $<
/branches/wip_t2x/sw/run_regression.pl
32,6 → 32,7
# no_t41 : don't execute the t8041 testbench tb_t8041_behav_c0
# no_t41a : don't execute the t8041a testbench tb_t8041a_behav_c0
# no_t42ah : don't execute the t8042ah testbench tb_t8042ah_behav_c0
# no_t21 : don't execute the t8021 testbench tb_t8021_behav_c0
# no_dump_compare : don't include testcell when running dump compares
# io_exp : use the testbenches containing the t8243 IO expander
# tb_t8243_behav_c0
72,7 → 73,8
't39' => './tb_t8039_behav_c0',
't41' => './tb_t8041_behav_c0',
't41a' => './tb_t8041a_behav_c0',
't42ah' => './tb_t8042ah_behav_c0');
't42ah' => './tb_t8042ah_behav_c0',
't21' => './tb_t8021_behav_c0');
my %ghdl_io_expanders = ('gen' => './tb_t8243_behav_c0',
't48' => './tb_t8048_t8243_behav_c0');
my $ghdl_simulator_opt = '--assert-level=error --stop-time=20ms';
/branches/wip_t2x/sw/verif/black_box/add/a_data/no_t21
/branches/wip_t2x/sw/verif/black_box/addc/rr/no_t21
/branches/wip_t2x/sw/verif/black_box/anl/pp/no_t21
/branches/wip_t2x/sw/verif/black_box/call/call_ret/no_t21
/branches/wip_t2x/sw/verif/black_box/clr/a/test.asm
16,7 → 16,7
jnz fail
 
inc a
jb0 ok_1
jnz ok_1
jmp fail
 
ok_1: add a, #0FFH
/branches/wip_t2x/sw/verif/black_box/clr/f0/no_t21
/branches/wip_t2x/sw/verif/black_box/cnt/cnt/test.asm
17,7 → 17,8
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf fail
mov a, t
cpl a
26,11 → 27,13
jnz fail
 
;; apply rising edge on T1
orl P1, #002H
mov a, #0FFH
outl P1, a
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf goon
jmp fail
goon: jtf fail
38,11 → 41,13
jnz fail
 
;; apply rising edge on T1
orl P1, #002H
mov a, #0FFH
outl P1, a
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf fail
mov a, t
dec a
54,24 → 59,30
mov t, a
 
;; apply rising edge on T1
orl P1, #002H
mov a, #0FFH
outl P1, a
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf fail
;; apply rising edge on T1
orl P1, #002H
mov a, #0FFH
outl P1, a
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf fail
 
strt cnt
;; apply rising edge on T1
orl P1, #002H
mov a, #0FFH
outl P1, a
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jtf goon2
jmp fail
 
/branches/wip_t2x/sw/verif/black_box/cnt/int/no_t21
/branches/wip_t2x/sw/verif/black_box/cpl/f1/no_t21
/branches/wip_t2x/sw/verif/black_box/dec/a/test.asm
15,7 → 15,7
jnz fail
 
dec a
jb0 ok_0
jnz ok_0
jmp fail
 
ok_0: inc a
/branches/wip_t2x/sw/verif/black_box/dec/rr/no_t21
/branches/wip_t2x/sw/verif/black_box/inc/a/test.asm
16,7 → 16,7
jnz fail
 
inc a
jb0 ok_0
jnz ok_0
jmp fail
 
ok_0: mov a, #0FFH
/branches/wip_t2x/sw/verif/black_box/inc/rr/no_t21
/branches/wip_t2x/sw/verif/black_box/int/jni/no_t21
/branches/wip_t2x/sw/verif/black_box/int/simple_jump_to/no_t21
/branches/wip_t2x/sw/verif/black_box/jbb/jbb_aa/no_t21
/branches/wip_t2x/sw/verif/black_box/jbb/jbb_all_1/no_t21
/branches/wip_t2x/sw/verif/black_box/mb/int/no_t21 --- branches/wip_t2x/sw/verif/black_box/mcs2x/movp/test.asm (nonexistent) +++ branches/wip_t2x/sw/verif/black_box/mcs2x/movp/test.asm (revision 330) @@ -0,0 +1,67 @@ + ;; ******************************************************************* + ;; $Id: test.asm 295 2009-04-01 19:32:48Z arniml $ + ;; + ;; Test MOVP A, @ A + ;; ******************************************************************* + + INCLUDE "cpu.inc" + INCLUDE "pass_fail.inc" + +table MACRO data + DB data & 0FFH + ENDM + + ORG 0 + + ;; Start of test + mov r1, #008H + +loop: mov a, r1 + dec a + call fetch_table1 + mov r0, a + + mov a, r1 + dec a + call fetch_table3 + + add a, r0 + cpl a + jnz fail + + djnz r1, loop + + +pass: PASS + +fail: FAIL + + + ORG 0100H + + db 0AFH + db 033H + db 0C0H + db 012H + db 055H + db 061H + db 02BH + db 0F4H +fetch_table1: + movp a, @a + ret + + + ORG 0300H + + db 050H + db 0CCH + db 03FH + db 0EDH + db 0AAH + db 09EH + db 0D4H + db 00BH +fetch_table3: + movp a, @a + ret
/branches/wip_t2x/sw/verif/black_box/mov/ind_rr/no_t21
/branches/wip_t2x/sw/verif/black_box/movx/no_t21
/branches/wip_t2x/sw/verif/black_box/orl/pp/no_t21
/branches/wip_t2x/sw/verif/black_box/psw/no_t21
/branches/wip_t2x/sw/verif/black_box/rb/misc/no_t21
/branches/wip_t2x/sw/verif/black_box/rl/no_t21
/branches/wip_t2x/sw/verif/black_box/tx/t0/ent0_clk/no_t21
/branches/wip_t2x/sw/verif/black_box/tx/t1/test.asm
11,9 → 11,11
 
;; Start of test
jnt1 fail
anl P1, #0FDH
mov a, #0FDH
outl P1, a
jt1 fail
orl P1, #002H
mov a, #0FFH
outl P1, a
jt1 pass
 
fail: FAIL
/branches/wip_t2x/sw/verif/black_box/upi41/basic_echo/no_t21
/branches/wip_t2x/sw/verif/black_box/upi41/dma/no_t21
/branches/wip_t2x/sw/verif/black_box/upi41/status41_test/no_t21
/branches/wip_t2x/sw/verif/black_box/xch/ind_rr/test.asm
7,6 → 7,14
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
decRx MACRO reg
mov r7, a
mov a, reg
dec a
mov reg, a
mov a, r7
ENDM
 
testR0R1 MACRO pos
inc r0
inc r1
66,37 → 74,37
mov @r0, a
mov @r1, a
 
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
dec r0
decRx r0
xch a, @r0
mov r0, #017H
xch a, @r0
 
mov a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
dec r1
decRx r1
xch a, @r1
mov r1, #027H
xch a, @r1
/branches/wip_t2x/sw/verif/black_box/xch/rr/no_t21 --- branches/wip_t2x/sw/verif/black_box/xchd/test.asm (revision 329) +++ branches/wip_t2x/sw/verif/black_box/xchd/test.asm (revision 330) @@ -7,6 +7,14 @@ INCLUDE "cpu.inc" INCLUDE "pass_fail.inc" +decRx MACRO reg + mov r7, a + mov a, reg + dec a + mov reg, a + mov a, r7 + ENDM + testR0R1 MACRO pos inc r0 inc r1 @@ -66,37 +74,37 @@ mov @r0, a mov @r1, a - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 - dec r0 + decRx r0 xchd a, @r0 mov r0, #017H xchd a, @r0 mov a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 - dec r1 + decRx r1 xchd a, @r1 mov r1, #027H xchd a, @r1
/branches/wip_t2x/sw/verif/black_box/xrl/rr/no_t21
/branches/wip_t2x/sw/verif/white_box/int_on_jmp/no_t21
/branches/wip_t2x/sw/verif/white_box/p1_port_reg_conflict/no_t21
/branches/wip_t2x/sw/verif/white_box/p2_port_reg_conflict/no_t21

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