URL
https://opencores.org/ocsvn/t80/t80/trunk
Subversion Repositories t80
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 42 to Rev 43
- ↔ Reverse comparison
Rev 42 → Rev 43
/trunk/bench/vhdl/SRAM.vhd
1,7 → 1,7
-- |
-- Simple SRAM model without timing |
-- |
-- Version : 0241 |
-- Version : 0247 |
-- |
-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org) |
-- |
73,7 → 73,7
|
begin |
|
Write <= CE_n nor WE_n; |
Write <= '1' when CE_n = '0' and WE_n = '0' else '0'; |
D_del <= D after 1 ns; |
|
process (Write) |
/trunk/sim/rtl_sim/bin/compile.do
7,6 → 7,7
vcom ../../../rtl/vhdl/T80s.vhd |
vcom ../../../rtl/vhdl/T16450.vhd |
vcom ../../../rtl/vhdl/SSRAM2.vhd |
vcom ../../../bench/vhdl/MonZ80.vhd |
vcom ../../../rtl/vhdl/DebugSystem.vhd -93 |
vcom ../../../bench/vhdl/ROM80.vhd |
vcom ../../../bench/vhdl/StimLog.vhd -93 |
14,5 → 15,4
vcom ../../../bench/vhdl/AsyncStim.vhd -93 |
vcom ../../../bench/vhdl/SRAM.vhd -93 |
vcom ../../../bench/vhdl/TestBench.vhd -93 |
vcom ../../../syn/xilinx/src/MonZ80_leo.vhd |
vcom ../../../bench/vhdl/DebugSystem_TB.vhd -93 |
/trunk/syn/xilinx/bin/t80debug.tcl
1,13 → 1,13
set process "5" |
set part "2s200pq208" |
set tristate_map "FALSE" |
set tristate_map "TRUE" |
set opt_auto_mode "TRUE" |
set opt_best_result "29223.458000" |
set dont_lock_lcells "auto" |
set input2output "50.000000" |
set input2register "50.000000" |
set register2output "50.000000" |
set register2register "50.000000" |
set input2output "30.000000" |
set input2register "20.000000" |
set register2output "20.000000" |
set register2register "40.000000" |
set wire_table "xis215-5_avg" |
set encoding "auto" |
set edifin_ground_port_names "GND" |
22,12 → 22,12
../../../rtl/vhdl/T80_Pack.vhd |
../../../rtl/vhdl/T80_MCode.vhd |
../../../rtl/vhdl/T80_ALU.vhd |
../../../rtl/vhdl/T80_Reg.vhd |
../../../rtl/vhdl/T80_RegX.vhd |
../../../rtl/vhdl/T80.vhd |
../../../rtl/vhdl/T80s.vhd |
../../../rtl/vhdl/T16450.vhd |
../src/MonZ80_leo.vhd |
../../../rtl/vhdl/SSRAM2.vhd |
../../../rtl/vhdl/SSRAMX.vhd |
../../../rtl/vhdl/DebugSystem.vhd |
} |
|
/trunk/syn/xilinx/bin/t80.tcl
1,13 → 1,13
set process "5" |
set part "2s200pq208" |
set tristate_map "FALSE" |
set tristate_map "TRUE" |
set opt_auto_mode "TRUE" |
set opt_best_result "29223.458000" |
set dont_lock_lcells "auto" |
set input2output "20.000000" |
set input2output "30.000000" |
set input2register "20.000000" |
set register2output "20.000000" |
set register2register "20.000000" |
set register2register "40.000000" |
set wire_table "xis215-5_avg" |
set encoding "auto" |
set edifin_ground_port_names "GND" |
22,7 → 22,7
../../../rtl/vhdl/T80_Pack.vhd |
../../../rtl/vhdl/T80_MCode.vhd |
../../../rtl/vhdl/T80_ALU.vhd |
../../../rtl/vhdl/T80_Reg.vhd |
../../../rtl/vhdl/T80_RegX.vhd |
../../../rtl/vhdl/T80.vhd |
../../../rtl/vhdl/T80s.vhd |
} |
/trunk/syn/xilinx/bin/t80debugxr.tcl
1,13 → 1,13
set process "5" |
set part "2s200pq208" |
set tristate_map "FALSE" |
set tristate_map "TRUE" |
set opt_auto_mode "TRUE" |
set opt_best_result "29223.458000" |
set dont_lock_lcells "auto" |
set input2output "50.000000" |
set input2output "30.000000" |
set input2register "20.000000" |
set register2output "20.000000" |
set register2register "50.000000" |
set register2register "40.000000" |
set wire_table "xis215-5_avg" |
set encoding "auto" |
set edifin_ground_port_names "GND" |
22,7 → 22,7
../../../rtl/vhdl/T80_Pack.vhd |
../../../rtl/vhdl/T80_MCode.vhd |
../../../rtl/vhdl/T80_ALU.vhd |
../../../rtl/vhdl/T80_Reg.vhd |
../../../rtl/vhdl/T80_RegX.vhd |
../../../rtl/vhdl/T80.vhd |
../../../rtl/vhdl/T80s.vhd |
../../../rtl/vhdl/T16450.vhd |