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URL https://opencores.org/ocsvn/tg68kc/tg68kc/trunk

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    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/tg68kc/trunk/TG68K_ALU.vhd
34,44 → 34,44
DIV_Mode : integer; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter :integer --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
decodeOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_ffo_offset : in std_logic_vector(31 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
decodeOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
non_aligned : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_ffo_offset : in std_logic_vector(31 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
 
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
 
81,143 → 81,140
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : bit;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : bit;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
--BCD
signal bcd_pur : std_logic_vector(9 downto 0);
signal bcd_kor : std_logic_vector(8 downto 0);
signal halve_carry : std_logic;
signal Vflag_a : std_logic;
signal bcd_a_carry : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal result_mulu : std_logic_vector(127 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : bit;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal unshifted_bitmask : std_logic_vector(31 downto 0);
signal bf_set1 : std_logic_vector(39 downto 0);
signal inmux0 : std_logic_vector(39 downto 0);
signal inmux1 : std_logic_vector(39 downto 0);
signal inmux2 : std_logic_vector(39 downto 0);
signal inmux3 : std_logic_vector(31 downto 0);
signal shifted_bitmask : std_logic_vector(39 downto 0);
signal bitmaskmux0 : std_logic_vector(37 downto 0);
signal bitmaskmux1 : std_logic_vector(35 downto 0);
signal bitmaskmux2 : std_logic_vector(31 downto 0);
signal bitmaskmux3 : std_logic_vector(31 downto 0);
signal bf_set2 : std_logic_vector(31 downto 0);
signal shift : std_logic_vector(39 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal mux : std_logic_vector(3 downto 0);
signal bitnr : std_logic_vector(4 downto 0);
signal mask : std_logic_vector(31 downto 0);
signal mask_not_zero : std_logic;
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal bf_s32 : std_logic;
signal index : std_logic_vector(4 downto 0);
-- signal i : integer range 0 to 31;
-- signal i : integer range 0 to 31;
-- signal i : std_logic_vector(5 downto 0);
signal bcd_pur : std_logic_vector(9 downto 0);
signal bcd_kor : std_logic_vector(8 downto 0);
signal halve_carry : std_logic;
signal Vflag_a : std_logic;
signal bcd_a_carry : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal result_mulu : std_logic_vector(127 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : bit;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
 
-- signal hot_bit : std_logic_vector(33 downto 0); simulation error =>
signal hot_bit : std_logic_vector(63 downto 0);
signal hot_msb : std_logic_vector(32 downto 0);
signal vector : std_logic_vector(32 downto 0);
signal result_bs : std_logic_vector(65 downto 0);
signal bit_nr : std_logic_vector(5 downto 0);
signal bit_nr7 : std_logic_vector(6 downto 0);
signal bit_msb : std_logic_vector(5 downto 0);
signal bs_shift : std_logic_vector(5 downto 0);
signal bs_shift_mod : std_logic_vector(5 downto 0);
signal asl_over : std_logic_vector(32 downto 0);
signal asr_sign : std_logic_vector(32 downto 0);
signal msb : std_logic;
signal ring : std_logic_vector(5 downto 0);
signal ALU : std_logic_vector(31 downto 0);
signal BSout : std_logic_vector(31 downto 0);
signal bs_V : std_logic;
signal bs_C : std_logic;
signal bs_X : std_logic;
signal in_offset : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal unshifted_bitmask: std_logic_vector(31 downto 0);
signal bf_set1 : std_logic_vector(39 downto 0);
signal inmux0 : std_logic_vector(39 downto 0);
signal inmux1 : std_logic_vector(39 downto 0);
signal inmux2 : std_logic_vector(39 downto 0);
signal inmux3 : std_logic_vector(31 downto 0);
signal shifted_bitmask : std_logic_vector(39 downto 0);
signal bitmaskmux0 : std_logic_vector(37 downto 0);
signal bitmaskmux1 : std_logic_vector(35 downto 0);
signal bitmaskmux2 : std_logic_vector(31 downto 0);
signal bitmaskmux3 : std_logic_vector(31 downto 0);
signal bf_set2 : std_logic_vector(31 downto 0);
signal shift : std_logic_vector(39 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal mux : std_logic_vector(3 downto 0);
signal bitnr : std_logic_vector(4 downto 0);
signal mask : std_logic_vector(31 downto 0);
signal mask_not_zero : std_logic;
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal bf_s32 : std_logic;
signal index : std_logic_vector(4 downto 0);
-- signal i : integer range 0 to 31;
-- signal i : integer range 0 to 31;
-- signal i : std_logic_vector(5 downto 0);
 
-- signal hot_bit : std_logic_vector(33 downto 0); simulation error =>
signal hot_bit : std_logic_vector(63 downto 0);
signal hot_msb : std_logic_vector(32 downto 0);
signal vector : std_logic_vector(32 downto 0);
signal result_bs : std_logic_vector(65 downto 0);
signal bit_nr : std_logic_vector(5 downto 0);
signal bit_nr7 : std_logic_vector(6 downto 0);
signal bit_msb : std_logic_vector(5 downto 0);
signal bs_shift : std_logic_vector(5 downto 0);
signal bs_shift_mod : std_logic_vector(5 downto 0);
signal asl_over : std_logic_vector(32 downto 0);
signal asl_over_xor : std_logic_vector(32 downto 0);
signal asr_sign : std_logic_vector(32 downto 0);
signal msb : std_logic;
signal ring : std_logic_vector(5 downto 0);
signal ALU : std_logic_vector(31 downto 0);
signal BSout : std_logic_vector(31 downto 0);
signal bs_V : std_logic;
signal bs_C : std_logic;
signal bs_X : std_logic;
 
 
BEGIN
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
bcd_a, result_mulu, result_div, exe_condition, bf_shift, bf_ffo_offset, mulu_reg, BSout,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
bcd_a, result_mulu, result_div, exe_condition, bf_shift, bf_ffo_offset, mulu_reg, BSout,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
BEGIN
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
IF exec(opcBFwb)='1' THEN
ALUout <= result(31 downto 0);
-- ALUout <= bf_datareg(31 downto 0);
IF bf_fffo='1' THEN
-- ALUout <= (OTHERS =>'0');
-- ALUout(5 downto 0) <= bf_firstbit + bf_shift;
-- ALUout(5 downto 0) <= bf_firstbit;
ALUout <= bf_ffo_offset - bf_firstbit;
END IF;
END IF;
393,6 → 390,7
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
END IF;
Vflag_a <= '0'; --nur zum testen
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
END PROCESS;
718,7 → 716,7
-- Barrel Shifter
-----------------------------------------------------------------------------
process (OP1out, OP2out, opcode, bit_nr, bit_nr7, bit_msb, hot_bit, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector,
rot_bits, Flags, msb, hot_msb, asl_over, ALU, asr_sign, exec)
rot_bits, Flags, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec)
begin
ring <= "100000";
IF rot_bits="10" THEN --ROX L/R
780,12 → 778,20
-- calc V-Flag by ASL
hot_msb <= (OTHERS =>'0');
hot_msb(conv_integer(bit_msb)) <= '1';
if bs_shift > ring then
IF bs_shift > ring THEN
bit_msb <= "000000";
else
ELSE
bit_msb <= ring-bs_shift;
end if;
asl_over <= ((('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&'0') - ('0'&hot_msb(31 downto 0));
END IF;
asl_over_xor <= (('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&msb;
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
asl_over_xor(8) <= '0';
WHEN "01"|"11" => --Word
asl_over_xor(16) <= '0';
WHEN OTHERS => NULL;
END CASE;
asl_over <= asl_over_xor - ('0'&hot_msb(31 downto 0));
bs_V <= '0';
IF rot_bits="00" AND exe_opcode(8)='1' THEN --ASL
bs_V <= not asl_over(32);
815,16 → 821,16
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(15 downto 8);
bs_C <= ALU(7);
bs_C <= ALU(7);
WHEN "01"|"11" => --Word
ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(31 downto 16);
bs_C <= ALU(15);
bs_C <= ALU(15);
WHEN "10" => --Long
ALU <= result_bs(31 downto 0) OR result_bs(63 downto 32);
bs_C <= ALU(31);
bs_C <= ALU(31);
WHEN OTHERS => NULL;
END CASE;
IF exe_opcode(0)='1' THEN --left shift
IF exe_opcode(8)='1' THEN --left shift
bs_C <= ALU(0);
END IF;
ELSIF rot_bits="10" THEN --ROX L/R
853,9 → 859,9
IF(bs_shift = "000000") THEN
IF rot_bits="10" THEN --ROX L/R
bs_C <= Flags(4);
bs_C <= Flags(4);
ELSE
bs_C <= '0';
bs_C <= '0';
END IF;
bs_X <= Flags(4);
bs_V <= '0';
865,7 → 871,6
BSout <= ALU;
asr_sign <= (OTHERS =>'0');
asr_sign(32 downto 1) <= asr_sign(31 downto 0) OR hot_msb(31 downto 0);
-- IF opcode(2 downto 0)="000" AND msb='1' THEN --ASR
IF rot_bits="00" AND exe_opcode(8)='0' AND msb='1' THEN --ASR
BSout <= ALU or asr_sign(32 downto 1);
IF bs_shift > ring THEN
953,9 → 958,9
END IF;
IF rising_edge(clk) THEN
IF Reset='1' THEN
IF Reset='1' THEN
Flags(7 downto 0) <= "00000000";
ELSIF clkena_lw = '1' THEN
ELSIF clkena_lw = '1' THEN
IF exec(directSR)='1' OR set_stop='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
/tg68kc/trunk/TG68KdotC_Kernel.vhd
1057,29 → 1057,7
alu_bf_shift <= bf_shift;
alu_bf_loffset <= bf_loffset;
alu_bf_ffo_offset <= bf_full_offset+bf_width+1;
-- ELSIF set_exec(exec_BS)='1' THEN
--
---- IF set_exec(exec_BS)='1' THEN
---- alu_width<="001111";
---- alu_bf_loffset <= "000000";
---- END IF;
--
---- alu_bf_shift <= set_rot_cnt;
-- IF opcode(5)='1' THEN
---- next_micro_state <= rota1;
---- set(ld_rot_cnt) <= '1';
---- setstate <= "01";
-- alu_bf_shift <= OP2out(5 downto 0);
-- ELSE
-- alu_bf_shift(2 downto 0) <= opcode(11 downto 9);
-- IF opcode(11 downto 9)="000" THEN
-- alu_bf_shift(5 downto 3) <="001";
-- ELSE
-- alu_bf_shift(5 downto 3) <="000";
-- END IF;
-- END IF;
END IF;
-- byte <= '0';
memread <= "1111";
FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
1093,9 → 1071,6
state <= "11";
FC(1 downto 0) <= "01";
memmask <= wbmemmask;
-- IF datatype="00" THEN
-- byte <= '1';
-- END IF;
ELSE
state <= setstate;
IF setstate="01" THEN
3016,6 → 2991,9
END IF;
 
WHEN pack1 => -- pack -(Ax),-(Ay)
IF opcode(2 downto 0)="111" THEN
set(use_SP) <= '1';
END IF;
set(hold_ea_data) <= '1';
set(update_ld) <= '1';
setstate <= "10";
3023,6 → 3001,9
next_micro_state <= pack2;
dest_areg <= '1';
WHEN pack2 =>
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
END IF;
set(hold_ea_data) <= '1';
set_direct_data <= '1';
IF opcode(7 downto 6) = "01" THEN --pack

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